Memory access device and method for multiple memory channels and data processing equipment

文档序号：1963510 发布日期：2021-12-14 浏览：23次中文

阅读说明：本技术 多内存通道的内存存取装置、方法和数据处理设备 (Memory access device and method for multiple memory channels and data processing equipment ) 是由不公告发明人于 2021-11-15 设计创作，主要内容包括：本申请公开了一种多内存通道的内存存取装置、方法和数据处理设备,涉及计算机内存访问技术领域,该存取装置通过配置寄存器设置虚拟内存通道和物理内存通道的配置信息,配置信息包括虚拟内存通道索引和物理内存通道索引之间的映射关系；内存管理单元基于内存访问请求的物理内存地址和配置信息计算得到目标虚拟内存通道索引,基于目标虚拟内存通道索引和映射关系计算得到目标虚拟内存通道索引映射的目标物理内存通道索引；存储控制器与物理内存通道对应设置,控制对存储器的存取访问；其中,与目标物理内存通道索引对应的物理内存通道所对应设置的存储控制器根据内存访问请求的物理内存地址对目标存储器中的目标数据进行存取访问。(The application discloses a memory access device, a method and data processing equipment of multiple memory channels, relating to the technical field of computer memory access, wherein the access device sets configuration information of a virtual memory channel and a physical memory channel through a configuration register, and the configuration information comprises a mapping relation between a virtual memory channel index and a physical memory channel index; the memory management unit calculates to obtain a target virtual memory channel index based on the physical memory address and the configuration information of the memory access request, and calculates to obtain a target physical memory channel index mapped by the target virtual memory channel index based on the target virtual memory channel index and the mapping relation; the storage controller is arranged corresponding to the physical memory channel and controls the access to the storage; and the storage controller correspondingly arranged to the physical memory channel corresponding to the target physical memory channel index accesses the target data in the target storage according to the physical memory address of the memory access request.)

1. A multi-channel memory access device, comprising:

the configuration register is used for setting configuration information of a virtual memory channel and a physical memory channel, wherein the configuration information comprises a mapping relation between a virtual memory channel index and a physical memory channel index;

the memory management unit is used for calculating to obtain a target virtual memory channel index based on the physical memory address of the memory access request and the configuration information;

the memory management unit is further configured to calculate a target physical memory channel index mapped by the target virtual memory channel index based on the target virtual memory channel index and the mapping relationship;

the memory controller is arranged corresponding to the physical memory channel and is used for controlling access to the memory;

and the storage controller is further configured to access, according to the physical memory address of the memory access request, the target data in the target storage through the physical memory channel corresponding to the target physical memory channel index.

2. The multi-channel memory access device of claim 1, wherein the configuration information further includes a number of virtual memory channels, a number of available physical memory channels, and a memory channel enable mask, wherein the number of virtual memory channels is not greater than the number of available physical memory channels, and the memory channel enable mask is used to indicate the number of writable and readable physical memory channels corresponding to the number of available physical memory channels.

3. The multi-channel memory access device of claim 2, wherein the configuration information further comprises a number of register banks and a row size in the target memory.

4. The multi-channel memory access device of claim 3, wherein the configuration information further comprises a virtual memory channel enable flag, the virtual memory channel enable flag indicating whether the virtual memory channel is enabled.

5. The multi-channel memory access device of claim 3, wherein the memory management unit is configured to use a modulo result of a quotient obtained by dividing the physical memory address by a product of the number of register banks and the row size and the number of virtual memory channels as the target virtual memory channel index.

6. The multi-channel memory access device of claim 1, wherein the storage controller is further configured to access target data in a target storage via a physical memory channel corresponding to the target physical memory channel index according to a physical memory address of the memory access request, and includes:

the storage controller calculates and obtains a register bank index, a row index and an in-row address offset of a storage area where the target data is located according to the physical memory address;

the storage controller accesses the target data based on the register bank index, the row index and the address offset in the row of the storage area where the target data is located.

7. The multi-channel memory access device of claim 6, wherein the calculating, by the storage controller according to the physical memory address, the register bank index, the row index, and the intra-row address offset of the storage area in which the target data is located comprises:

dividing the physical memory address by the quotient of the row size of the register bank and a register bank mask to perform logical AND operation, wherein the result is used as the register bank index, and the register bank mask is the number of the register banks minus 1;

dividing the physical memory address by the quotient of the product of the row size of the register bank, the number of the register banks and the number of the virtual memory channels to serve as a row index of a storage area where the target data are located;

and performing logical AND operation on the difference between the physical memory address and the row size of the register bank minus 1 to obtain the result, wherein the result is used as the intra-row address offset of the storage area where the target data is located.

8. The multi-channel memory access device of claim 1, further comprising:

and the cache unit is used for forwarding the memory access request to the storage controller.

9. The multi-channel memory access device of claim 8, wherein the cache unit comprises one or both of a level two cache and a level three cache.

10. The multi-channel memory access device of claim 1, wherein the configuration register is further configured to set a plurality of configuration information of the virtual memory channel and the physical memory channel for one or more processing cores, and the plurality of configuration information includes different mapping relationships between the virtual memory channel index and the physical memory channel index.

11. The multi-channel memory access device of claim 10, wherein the configuration information further includes a number of different virtual memory channels, a number of available physical memory channels, and a memory channel enable mask for one or more of the processing cores.

12. A memory access method of multiple memory channels is characterized by comprising the following steps:

setting configuration information of a virtual memory channel and a physical memory channel in a configuration register, wherein the configuration information comprises a mapping relation between a virtual memory channel index and a physical memory channel index;

calculating to obtain a target virtual memory channel index based on the physical memory address of the memory access request and the configuration information;

calculating to obtain a target physical memory channel index mapped by the target virtual memory channel index based on the target virtual memory channel index and the mapping relation;

and according to the physical memory address of the memory access request, accessing and accessing the target data in the target memory through the physical memory channel corresponding to the target physical memory channel index.

13. The method of claim 12, wherein the configuration information further includes a number of virtual memory channels, a number of available physical memory channels, and a memory channel enable mask, wherein the number of virtual memory channels is not greater than the number of available physical memory channels, and wherein the memory channel enable mask is used to indicate the number of writable and readable physical memory channels corresponding to the number of available physical memory channels.

14. The method of claim 13, wherein the configuration information further comprises a number of register banks and a row size in the target memory.

15. The method of claim 14, wherein the configuration information further comprises a virtual memory channel enable flag, the virtual memory channel enable flag indicating whether the virtual memory channel is enabled.

16. The method according to claim 14, wherein the calculating a target virtual memory channel index based on the physical memory address of the memory access request and the configuration information comprises:

and taking the result of the modulo of the quotient of the physical memory address divided by the product of the number of the register banks and the row size and the number of the virtual memory channels as the index of the target virtual memory channel.

17. The method according to claim 12, wherein the accessing target data in a target storage through the physical memory channel corresponding to the target physical memory channel index according to the physical memory address of the memory access request comprises:

calculating to obtain a register bank index, a row index and an in-row address offset of a storage area where the target data is located according to the physical memory address;

and performing access to the target data based on the register bank index, the row index and the address offset in the row of the storage region of the target data.

18. The method according to claim 17, wherein the calculating the bank index, the row index, and the intra-row address offset of the storage area where the target data is located according to the physical memory address comprises:

19. The method of claim 18, wherein the calculating the bank index, the row index, and the intra-row address offset of the storage area in which the target data is located comprises: and calculating to obtain the register bank index, the row index and the in-row address offset of the storage area where the target data is located through a storage controller correspondingly arranged to the physical memory channel corresponding to the target physical memory channel index.

20. The method according to claim 16, wherein said calculating a target physical memory channel index mapped to the target virtual memory channel index based on the target virtual memory channel index and the mapping relationship comprises: and calculating to obtain a target physical memory channel index mapped by the target virtual memory channel index through a memory management unit.

21. The method of claim 12, wherein setting configuration information for the virtual memory channel and the physical memory channel in the configuration register further comprises: setting a plurality of configuration information of a virtual memory channel and a physical memory channel in a configuration register for one or more processing cores, wherein the plurality of configuration information comprises different mapping relations between a virtual memory channel index and a physical memory channel index.

22. The method of claim 21, wherein the configuration information further includes a number of virtual memory channels, a number of available physical memory channels, and a memory channel enable mask, the number of virtual memory channels corresponding to one or more of the processing cores.

23. The method of claim 19, wherein accessing target data in a target storage via a physical memory channel corresponding to the target physical memory channel index according to the physical memory address of the memory access request further comprises: and forwarding the memory access request to a storage controller correspondingly arranged to the physical memory channel corresponding to the target physical memory channel index through a cache unit.

24. A data processing apparatus, characterized by comprising: one or more processing units and a multi-memory channel memory access device as claimed in any one of claims 1 to 11.

25. The data processing device of claim 24, wherein the data processing device comprises one or more of a central processing unit, a graphics processing unit, a digital processing unit, a field programmable gate array, an artificial intelligence chip, a video codec chip.

Technical Field

The present application relates to the field of computer memory access technologies, and in particular, to a memory access device with multiple memory channels, a method and a data processing device.

Background

With the improvement of computing power, more and more memory channels are provided for chips such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an Artificial Intelligence (AI), video coding and decoding, for example, the first 7nm GPU chip AMD Vega20 includes 32 memory channels, and it is a trend that chips including more memory channels will appear in the future.

However, the yield of chips decreases dramatically in the high process below 14 nm. When individual memory channels in the chip are damaged in the manufacturing process, the yield is also reduced sharply, so that the chip cost is greatly improved. In addition, as the service life of the multi-memory channel chip increases, one or more memory channels may be damaged, so that the chip cannot be used continuously, and the reliability of the computing system is reduced. In addition, in many application scenarios, in order to reduce power consumption, the chip needs to operate in a power saving mode, and a conventional multi-memory channel chip cannot use only a part of memory channels. These problems all present challenges to the development of applications for multi-channel memory chips.

Disclosure of Invention

In view of this, the present application provides a multi-memory channel memory access device, a method and a data processing device, which are used to implement flexible configuration during operation of multiple memory channels of a chip, so as to improve the manufacturing yield, physical service life and system reliability of the multi-memory channel chip.

In a first aspect, the present application provides a memory access device with multiple memory channels, including:

the memory management unit is used for calculating to obtain a target virtual memory channel index based on the physical memory address of the memory access request and the configuration information;

the memory controller is arranged corresponding to the physical memory channel and is used for controlling access to the memory;

As a preferred implementation manner of the present application, the configuration information further includes a number of virtual memory channels, a number of available physical memory channels, and a memory channel enable mask, where the number of virtual memory channels is not greater than the number of available physical memory channels, and the memory channel enable mask is used to indicate a readable and writable physical memory channel corresponding to the number of available physical memory channels.

As a preferred embodiment of the present application, the configuration information further includes the number of register banks and the row size in the target memory.

As a preferred embodiment of the present application, the configuration information further includes a virtual memory channel enable identifier, where the virtual memory channel enable identifier is used to indicate whether to enable the virtual memory channel.

As a preferred embodiment of the present application, the memory management unit is configured to use a quotient obtained by dividing the physical memory address by a product of the number of register banks and the row size and a result obtained by modulo the virtual memory channel number as the target virtual memory channel index.

As a preferred embodiment of the present application, the performing, by the storage controller, access to target data in a target storage through a physical memory channel corresponding to the target physical memory channel index according to a physical memory address of the memory access request includes:

the storage controller accesses the target data based on the register bank index, the row index and the address offset in the row of the storage area where the target data is located.

As a preferred embodiment of the present application, the calculating, by the storage controller according to the physical memory address, a register bank index, a row index, and an intra-row address offset of a storage area where the target data is located includes:

As a preferred embodiment of the present application, the access device further includes:

and the cache unit is used for forwarding the memory access request to the storage controller.

As a preferred embodiment of the present application, the cache unit includes one or both of a level two cache and a level three cache.

As a preferred embodiment of the present application, the configuration register is further configured to set multiple pieces of configuration information of a virtual memory channel and a physical memory channel for one or more processing cores, where the multiple pieces of configuration information include different mapping relationships between a virtual memory channel index and a physical memory channel index.

As a preferred embodiment of the present application, the configuration information further includes a number of virtual memory channels, a number of available physical memory channels, and a memory channel enable mask, which correspond to one or more processing cores.

In a second aspect, the present application provides a method for accessing a memory with multiple memory channels, including the following steps:

calculating to obtain a target virtual memory channel index based on the physical memory address of the memory access request and the configuration information;

calculating to obtain a target physical memory channel index mapped by the target virtual memory channel index based on the target virtual memory channel index and the mapping relation;

As a preferred embodiment of the present application, the configuration information further includes the number of register banks and the row size in the target memory.

As a preferred embodiment of the present application, the calculating the target virtual memory channel index based on the physical memory address of the memory access request and the configuration information includes:

As a preferred embodiment of the present application, the performing, according to the physical memory address of the memory access request, an access to target data in a target storage through a physical memory channel corresponding to the target physical memory channel index includes:

calculating to obtain a register bank index, a row index and an in-row address offset of a storage area where the target data is located according to the physical memory address;

and performing access to the target data based on the register bank index, the row index and the address offset in the row of the storage region of the target data.

As a preferred embodiment of the present application, the calculating, according to the physical memory address, a register bank index, a row index, and an intra-row address offset of a storage area where the target data is located includes:

As a preferred embodiment of the present application, the calculating to obtain the register bank index, the row index, and the intra-row address offset of the storage area where the target data is located includes: and calculating to obtain the register bank index, the row index and the in-row address offset of the storage area where the target data is located through a storage controller correspondingly arranged to the physical memory channel corresponding to the target physical memory channel index.

As a preferred embodiment of the present application, the calculating a target physical memory channel index mapped by the target virtual memory channel index based on the target virtual memory channel index and the mapping relationship includes: and calculating to obtain a target physical memory channel index mapped by the target virtual memory channel index through a memory management unit.

As a preferred embodiment of the present application, the setting, in the configuration register, configuration information of the virtual memory channel and the physical memory channel further includes: setting a plurality of configuration information of a virtual memory channel and a physical memory channel in a configuration register for one or more processing cores, wherein the plurality of configuration information comprises different mapping relations between a virtual memory channel index and a physical memory channel index.

As a preferred embodiment of the present application, according to the physical memory address of the memory access request, performing access to the target data in the target storage through the physical memory channel corresponding to the target physical memory channel index further includes: and forwarding the memory access request to a storage controller correspondingly arranged to the physical memory channel corresponding to the target physical memory channel index through a cache unit.

In a third aspect, the present application provides a data processing apparatus, comprising: one or more processing units and the multi-memory channel memory access device of the first aspect.

As a preferred embodiment of the present application, the data processing device includes one or more of a central processing unit, a graphics processing unit, a digital processing unit, a field programmable gate array, an artificial intelligence chip, and a video codec chip.

Compared with the prior art, the method has the following beneficial effects:

(1) even if the chip is damaged, the normal reading and writing of the memory data can be ensured by flexibly configuring the remaining available physical memory channels, so that the yield of chip manufacturing can be improved, and the physical service life of the chip and the reliability of a system can be improved;

(2) the method can realize flexible allocation of resources by a virtualization system, realize random resource division of multi-user virtual machines, achieve optimal resource allocation, realize physical isolation among the virtual machines, and seamlessly switch multi-memory system configuration in a low power consumption state and a high power consumption state of a multi-memory channel system.

Drawings

The features, objects, and advantages of the present application will be more fully understood from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is an exemplary architecture of a conventional GPU chip 100 with multiple memory channels;

FIG. 2 is a diagram of a conventional register bank structure in multiple memory channels;

FIG. 3 is a diagram of an exemplary structure for a 32-bit physical memory address in a multiple memory channel system;

FIG. 4 is a block diagram of a memory access device 400 with multiple memory channels according to an embodiment of the present application;

FIG. 5 is a flow chart illustrating a method for memory access in multiple memory channels according to an embodiment of the present disclosure;

FIG. 6 is a flowchart illustrating specific steps of a method for accessing a memory with multiple memory channels according to an embodiment of the present disclosure;

FIG. 7 is a flowchart illustrating specific steps of a method for accessing a memory with multiple memory channels according to another embodiment of the present application;

FIG. 8 is a block diagram of a data processing apparatus 800 according to an embodiment of the present application;

fig. 9-12 are schematic diagrams of specific applications in 8-memory channel GPU or CPU chips.

Detailed Description

The technical solutions of the present application are clearly and completely described below by way of embodiments and with reference to the accompanying drawings, but the present application is not limited to the embodiments described below. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the following embodiments, fall within the scope of protection of the present application. For the sake of clarity, parts not relevant to the description of the exemplary embodiments have been omitted in the drawings.

It will be understood that terms such as "including" or "having," and the like, in this application are intended to specify the presence of stated features, integers, steps, acts, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, acts, components, or groups thereof. In this application "plurality" may generally be interpreted as meaning two or more.

Fig. 1 shows an exemplary structure of a conventional GPU chip 100 with multiple memory channels. As shown in fig. 1, the GPU chip 100 generally comprises one or more stream processors 110, the stream processors 110 further comprising a scheduler 111, one or more single-instruction multi-threaded processors 112, one or more level one caches 113, a memory management unit 114, and a shared storage 115. The stream processor 110 reads and writes data to and from one or more level two buffers 117 and a PCIE controller 120 through a crossbar or crossbar network 116.

One or more level two caches 117 have read and write access to attached memory 119 through a corresponding attached memory controller 118. Each second level cache 117 and the memory controller 118 and the memory 119 connected to the second level cache constitute a 4-memory channel. In addition, the GPU chip 100 may further include a video codec 121 and/or other processing cores (not shown in the figure).

It should be noted that fig. 1 only exemplarily depicts the GPU chip structure of 4 single-instruction multi-thread processors 112, 4 level-two caches 117, and 4 memory controllers 118, and in fact, the GPU chip 100 may further include a greater number of single-instruction multi-thread processors 112, level-two caches 117, and memory controllers 118, so that a memory structure of a greater number of memory channels may be implemented. In addition, in addition to the GPU chip described in fig. 1, the multi-memory channel chip may further include chips that are not limited to CPU, AI, field programmable gate array, video codec, and the like, and the structures of these chips are similar to the storage structure related to the multi-memory channel, and are not described herein again.

In the embodiment of the present application, the implementation description is only performed by taking a GPU chip with multiple memory channels as an example, but it is not meant that the technical solution of the embodiment of the present application is only applicable to the GPU chip shown in fig. 1, and the GPU structure shown in fig. 1 is not understood to limit the protection scope of the present application.

In FIG. 1, memory management unit 114 typically includes a translation bypass buffer and an address translation unit. The bypass conversion buffer is also called page table buffer and is used for storing a conversion table from a virtual address to a physical memory address, and the address translation component is used for translating the virtual address corresponding to the read-write instruction sent by the chip processing core into the physical memory address based on the bypass conversion buffer. And after the memory management unit translates the virtual address into the physical memory address, the memory management unit informs the corresponding storage controller to read and write data of the corresponding storage unit according to the physical memory address.

A multi-channel memory chip may include 1 or more memory channels, for example, different computing systems may employ various numbers of memory channels, such as 1, 2, 4, 8, 16, 32, etc. groups, as required. As shown in fig. 2, in order to improve the efficiency of memory reading, each chip memory is generally divided into a plurality of register BANKs (referred to as BANKs), each BANK has a plurality of ROWs (referred to as ROWs) inside, and the ROW SIZE ROW _ SIZE of each ROW is generally 64, 128 or 256 bytes. The memory corresponding to each memory channel may include a plurality of BANKs.

For one ROW of each BANK, if the ROW SIZE ROW _ SIZE is 256 bytes, the number of register BANKs NUM _ BANKs is 4, and the number of memory channels NUM _ channels is 4, the space SIZE of one page of the memory is 4KB, i.e., ROW _ SIZE NUM _ BANKs NUM _ channels = 256 × 4 = 4096 bytes.

The number of channels of the memory is actually a bandwidth acceleration technique of the memory, and the bandwidth is multiplied. Most commonly, dual channels are supported by civilian grade computers. The server also has 3 channels and 4 channels. The following multi-channel technique is explained by taking two channels as an example:

the dual channel is that two memory controllers are designed in the north bridge chip level, the two memory controllers can work independently, and each controller controls one memory channel.

FIG. 3 is a diagram of an exemplary structure for a 32-bit physical memory address in a multiple memory channel system. As shown in FIG. 3, such exemplary physical memory addresses generally include a register bank index, a row index, a memory channel index, and an intra-row address offset. The memory channel index refers to a physical memory channel number specified by the read-write instruction, the register bank index refers to a register bank number where read-write target data are located, the row index refers to a row address where the target data are located in a current register bank, and the intra-row address offset refers to an offset address where the target data are located in a current row.

As an example address calculation method, 31-12 bits of the 32-bit address are used as the row index, 11-10 bits are used as the register bank index, 9-8 bits are used as the memory channel index, and 7-0 is used as the address offset in the row in FIG. 3. It should be noted that the present application does not limit the specific encoding manner of the physical memory address.

As described above, once a part of memory channels of the chip with multiple memory channels are damaged and the damaged channels of each chip may be different, the conventional multi-memory channel chip cannot use only a part of the memory channels, and only the memory area is evenly distributed to all the memory channels, so that the damage to the part of the memory channels greatly increases the manufacturing and using cost of the chip, and reduces the reliability of the computing system. Therefore, an improved access method for multiple memory channels is provided in the embodiments of the present application, which achieves flexible allocation of resources by a virtualization system by defining a virtual memory channel and performing run-time programming configuration on the multiple memory channels in a chip, so as to ensure correct memory data reading and writing even if individual channels are damaged.

Fig. 4 is a block diagram of a multi-channel memory access device 400 according to an embodiment of the present application. As shown in fig. 4, the multi-channel memory access device 400 includes:

the configuration register 410 is configured to set configuration information of the virtual memory channel and the physical memory channel, where the configuration information includes a mapping relationship between a virtual memory channel index and a physical memory channel index.

The memory management unit 420 is configured to calculate a target virtual memory channel index based on the physical memory address of the memory access request and the configuration information.

The memory management unit 420 is specifically configured to obtain a target physical memory channel index mapped by the target virtual memory channel index based on the target virtual memory channel index and the mapping relationship calculation.

And the storage controller 430 is arranged corresponding to the physical memory channel and used for controlling access to the storage. The storage controller 430 is specifically configured to access target data in the target storage through a physical memory channel corresponding to the target physical memory channel index according to the physical memory address of the memory access request.

According to the embodiment of the application, the mapping relation between the physical memory channels and the virtual memory channels is defined through the configuration register, so that a plurality of physical memory channels in a chip are mapped to the virtual memory channels, and through the running programming configuration of the plurality of memory channels, the physical memory address of the memory access request from the processing core only needs to be appointed to the virtual memory channels without appointing a specific physical memory channel, so that even if the memory channels are damaged, the normal reading and writing of memory data can be ensured through the configuration of the remaining available physical memory channels, the yield of chip manufacturing can be improved, and the physical service life of the chip and the system reliability are improved. Furthermore, the technical solution of this embodiment can also implement flexible allocation of resources by the virtualization system, implement arbitrary resource division by the multi-user virtual machine, achieve optimal resource allocation, implement physical isolation between the virtual machines, and seamlessly switch the multi-memory system configuration in the low power consumption state and the high power consumption state of the multi-memory channel system.

In this embodiment, the configuration registers 410 may be implemented using one or more general purpose registers or other special purpose registers. The configuration register 410 may also use 16 bits, 32 bits, or 64 bits for the definition of the configuration information described above. It should be noted that fig. 4 only schematically shows an example of 4 memory channels, and actually, the scheme of this embodiment is not limited to the number of memory channels, and may be extended to an implementation of more memory channels.

In this embodiment, the memory management unit 420 may be a software and hardware structure improved based on the existing memory management unit, and may include a bypass conversion buffer and an address translation unit, which are usually included in the existing memory management unit. In some embodiments, the memory management unit 420 may also include one or more units, and may implement configurable memory channel configuration management for each of the plurality of processing cores.

In some embodiments, the configuration information further includes a number of virtual memory channels, a number of available physical memory channels, and a memory channel enable mask, where the number of virtual memory channels is not greater than the number of available physical memory channels, and the memory channel enable mask is used to indicate the number of writable and readable physical memory channels corresponding to the number of available physical memory channels. The number of virtual memory channels is the number of virtual memory channels defined in the current configuration information, and the number of available physical memory channels is only the number of currently enabled physical memory channels, which is consistent with the indication of the memory channel enable mask.

In some embodiments, the configuration information also includes the number of register banks and the row size in the target memory.

In some embodiments, the configuration information further includes a virtual memory channel enable flag indicating whether the virtual memory channel is enabled.

In some embodiments, the memory management unit is configured to modulo a quotient of a physical memory address divided by a product of a number of register banks and a row size and a number of virtual memory channels as the target virtual memory channel index.

In some embodiments, the accessing the target data in the target storage through the physical memory channel corresponding to the target physical memory channel index according to the physical memory address of the memory access request includes:

the memory controller realizes access to the target data based on the register bank index, the row index and the address offset in the row of the memory region where the target data is located.

In some embodiments, the calculating, by the storage controller, the register bank index, the row index, and the intra-row address offset of the storage area where the target data is located according to the physical memory address includes:

dividing the physical memory address by the quotient of the row size of the register bank and the register bank mask to perform logic AND operation, wherein the result is used as the register bank index, and the register bank mask is the number of the register banks minus 1;

In some embodiments, the memory access device 400 may further include (not shown in fig. 4): and a cache unit for forwarding the memory access request to the storage controller 430. In some embodiments, the cache unit may include one or both of a level two cache and a level three cache in the processing chip.

In some embodiments, the configuration register is further configured to set a plurality of configuration information of the virtual memory channel and the physical memory channel for the one or more processing cores, where the plurality of configuration information includes different mapping relationships between the virtual memory channel index and the physical memory channel index.

The following describes a specific implementation of the embodiment of the present application in conjunction with a multi-memory channel configuration register of 8 memory channels.

Memory channel configuration register

Tables 1 and 2 are examples of implementing configuration information for physical and virtual memory channels using 2 32-bit registers. In this example, the memory channel configuration register 1 configures basic configuration information of a virtual memory channel and a physical memory channel, and the memory channel configuration register 2 configures a mapping relationship between a virtual memory channel index and a physical memory channel index.

Table 1 (memory channel configuration register 1)

Table 2 (memory channel configuration register 2)

Based on the above definitions of the configuration registers of tables 1 and 2, if the first memory bank fails (numbering starts from 0), only 7 memory channels are available in the computing system, assuming that the 48bits physical memory address PYH _ ADDR of the target data to be accessed is 0x 00023 BAC 829C.

The configuration information of the memory channel configuration register 1 is:

the number of physical memory channels NUM _ PHY _ MC = 0x 8;

the number of virtual memory channels NUM _ virtual _ MC = 0x 7;

a virtual memory channel ENABLE identification ENABLE _ CONFIG = 0x 1;

reserved bit Reserved = 0x0 (this data field will be ignored);

memory channel ENABLE MASK MC _ ENABLE _ MASK = 0xFD, i.e., 11111101;

the number of register BANKS NUM _ BANKS = 0x 4;

ROW SIZE ROW _ SIZE = 0 (corresponding to 256 BYTES).

The configuration information of the memory channel configuration register 2 is:

virtual memory channel 0: VIRTUAL _0_ MAP _ PHY _ MC = 0x 0;

virtual memory channel 1: VIRTUAL _1_ MAP _ PHY _ MC = 0x 2;

virtual memory channel 2: VIRTUAL _2_ MAP _ PHY _ MC = 0x 3;

virtual memory channel 3: VIRTUAL _3_ MAP _ PHY _ MC = 0x 4;

virtual memory channel 4: VIRTUAL _4_ MAP _ PHY _ MC = 0x 5;

virtual memory channel 5: VIRTUAL _5_ MAP _ PHY _ MC = 0x 6;

virtual memory channel 6: VIRTUAL _6_ MAP _ PHY _ MC = 0x 7;

virtual memory channel 7: VIRTUAL _7_ MAP _ PHY _ MC = 0x0 (this data field will be ignored); reserved bit Reserved = 0x0 (this data field will be ignored).

Computing target virtual memory channel index

The memory management unit calculates the target VIRTUAL memory channel INDEX virtualmc INDEX according to the coding mode of the physical memory address by adopting the following formula:

VIRTUAL_MC_INDEX=PHY_ADDR / (NUM_BANKS * ROW_SIZE_BYTES) % NUM_VIRTURAL_MC。

taking the physical memory address 0x 00023 BAC 829C as an example, according to the relevant configuration information in the memory channel configuration register 1, the number of register BANKS NUM _ BANKS = 0x4, the ROW SIZE ROW _ SIZE = 256 bytes of the register BANKS, and the number of virtual memory channels NUM _ virtual _ MC = 0x7, the above formula is substituted to obtain:

VIRTUAL_MC_INDEX = 0x0002 3BAC 829C / （4 * 256）% 7 = 6

that is, the target virtual memory channel index calculated according to the physical memory address and the configuration information is 6.

Computing target physical memory channel indices

After the memory management unit obtains the target virtual memory channel INDEX corresponding to the physical memory address through calculation, according to the mapping relationship between the virtual memory channel INDEX configured in the memory channel configuration register 2 and the physical memory channel INDEX, the memory management unit may obtain the target physical memory channel INDEX PHY _ MC _ INDEX mapped by the target virtual memory channel INDEX through calculation.

Taking the above physical memory address 0x 00023 BAC 829C as an example, when the VIRTUAL _ MC _ INDEX calculated in the above step is 6, the mapping relationship of the physical memory channel INDEX is VIRTUAL _6_ MAP _ PHY _ MC =7, so the target physical memory channel INDEX PHY _ MC _ INDEX = 7.

Calculating register bank index, row index and inline address offset

After the target physical memory channel index is obtained through calculation, in order to implement access to the target data, the memory management unit needs to send a memory access request including a physical memory address and data to a physical memory channel corresponding to the target physical memory channel index.

In some embodiments, for a CPU chip, the memory management unit may first send a request to the high speed bus; for a GPU chip, the memory management unit may first send a request to the crossbar or crossbar network. The high speed bus or crossbar network then forwards the request to the second level cache or third level cache. And the second-level cache or the third-level cache sends the request to the storage controller mapped corresponding to the target physical memory channel index. The memory controller is responsible for calculating the register bank index, row index and intra-row address offset. The calculation process is as follows:

first, a register BANK MASK BANK _ MASK = register BANK number NUM _ BANKs-1 is defined.

The register BANK INDEX can be calculated by the following formula:

BANK_INDEX=(PYH_ADDR/ROW_SIZE_BYTES)& BANK_MASK；

the ROW INDEX ROW _ INDEX can be calculated by the following formula:

ROW_INDEX = PYH_ADDR/(ROW_SIZE*NUM_BANKS* NUM_VIRTURAL_MC)；

the intra-ROW address OFFSET _ IN _ ROW can be calculated using the following formula:

OFFSET_IN_ROW = PYH_ADDR & (ROW_SIZE-1)。

continuing with the above example of physical memory address 0x 00023 BAC 829C. In this example, NUM _ BANK = 4, BANK _ MASK =3, ROW _ SIZE = 256, and NUM _ virtual _ MC =7, so the following can be calculated:

BANK_INDEX=(0x0002 3BAC 829C /256)&3=2；

ROW _ INDEX = 0x 00023 BAC 829C/(256 × 4 × 7) = 0x51AAE, corresponding to 10, which is 334510 (counting from 0);

OFFSET _ IN _ ROW = 0x 00023 BAC 829C & (256-1) = 0x 00023 BAC 829C & (0 xFF) = 0x9C (counting from 0).

After the calculation result is obtained, the storage controller can realize access to the target data in the corresponding storage unit according to the register bank index, the row index and the address offset in the row.

Fig. 5 is a flowchart illustrating a memory access method for multiple memory channels according to an embodiment of the present application. As shown in fig. 5, the memory access method of the multiple memory channels may include:

step S510, setting configuration information of a virtual memory channel and a physical memory channel in a configuration register, where the configuration information includes a mapping relationship between a virtual memory channel index and a physical memory channel index;

step S520, based on the physical memory address of the memory access request and the configuration information, calculating to obtain a target virtual memory channel index;

step S530, calculating to obtain a target physical memory channel index mapped by the target virtual memory channel index based on the target virtual memory channel index and the mapping relation;

in step S540, according to the physical memory address of the memory access request, the target data in the target memory is accessed through the physical memory channel corresponding to the target physical memory channel index.

In some embodiments, in step S510, the configuration information further includes a number of virtual memory channels, a number of available physical memory channels, and a memory channel enable mask, where the number of virtual memory channels is not greater than the number of available physical memory channels, and the memory channel enable mask is used to indicate the readable and writable physical memory channels corresponding to the number of available physical memory channels.

In some embodiments, the configuration information further includes the bank number and row size of the registers in the target memory in step S510.

In some embodiments, in step S510, the configuration information further includes a virtual memory channel enable flag, where the virtual memory channel enable flag is used to indicate whether to enable the virtual memory channel.

In some embodiments, in step S520, the calculating the target virtual memory channel index based on the physical memory address and the configuration information of the memory access request may include: the result of modulo the physical memory address by the quotient of the product of the number of register banks and the row size and the number of virtual memory channels is taken as the target virtual memory channel index.

In some embodiments, as shown in fig. 6, in step S540, according to the physical memory address of the memory access request, performing access to the target data in the target storage through the physical memory channel corresponding to the target physical memory channel index may include:

step S610, calculating according to the physical memory address to obtain the register bank index, the row index and the in-row address offset of the storage area where the target data is located;

in step S620, based on the register bank index, the row index, and the intra-row address offset, access to the target data is implemented through the storage controller correspondingly configured to the physical memory channel corresponding to the target physical memory channel index.

In some embodiments, as shown in fig. 7, in step S610, calculating the register bank index, the row index, and the intra-row address offset of the storage area where the target data is located according to the physical memory address may include:

step S710, taking the result of the logical AND operation of the quotient of the physical memory address divided by the row size of the register bank and the register bank mask as the register bank index, wherein the register bank mask is the number of the register banks minus 1;

step S720, dividing the physical memory address by the quotient of the product of the row size of the register bank, the number of the register banks and the number of the virtual memory channels, and taking the quotient as the row index of the storage area where the target data is located;

in step S730, the logical and operation result of the difference between the physical memory address and the row size of the register bank minus 1 is used as the intra-row address offset of the storage area where the target data is located.

In some embodiments, the target physical memory channel index mapped by the target virtual memory channel index calculated in steps S520 and S530 is calculated by the memory management unit.

In some embodiments, the register bank index, the row index and the intra-row address offset of the storage area where the target data is located, which are calculated in step S610, are calculated by the storage controller corresponding to the physical memory channel corresponding to the target physical memory channel index.

In some embodiments, setting configuration information of the virtual memory channel and the physical memory channel in the configuration register further comprises: setting a plurality of configuration information of the virtual memory channel and the physical memory channel in a configuration register for one or more processing cores, wherein the plurality of configuration information comprises different mapping relations between the virtual memory channel index and the physical memory channel index.

Therefore, in the multi-memory channel chip with a plurality of processing cores, flexible configuration of various memory channels can be realized aiming at one or a plurality of processing cores, and the flexible configuration requirement of a virtualization system on resources is met.

In some embodiments, according to the physical memory address of the memory access request, accessing the target data in the target storage through the physical memory channel corresponding to the target physical memory channel index may further include: and forwarding the memory access request to a storage controller correspondingly arranged to the physical memory channel corresponding to the target physical memory channel index through a cache unit. The cache unit may include one or both of a level two cache and a level three cache.

Fig. 8 is a schematic structural diagram of a data processing device 800 according to an embodiment of the present application. As shown in fig. 8, the data processing apparatus 800 includes: one or more processing units 810 and a multi-channel memory access device 820 according to any of the embodiments described above.

The one or more processing units 810 may include, but are not limited to, processor cores of various types of processing chips, such as single instruction multi-threaded processors.

In some embodiments, the data processing device may include one or more of a central processing unit, a graphics processing unit, a digital processing unit, a field programmable gate array, an artificial intelligence chip, a video codec chip.

Fig. 9-12 are schematic diagrams of specific applications in 8-memory channel GPU or CPU chips. Fig. 9 illustrates a memory channel access method in the prior art, as shown in fig. 9, 8 memory channels in an original GPU or a CPU chip, all the memory channels 0 to 7 may work normally, and a compute core a and a compute core B may access designated memory cells of all the memory channels.

10-12 illustrate configurable memory channel access using embodiments of the present application. As shown in fig. 10, by using the flexible memory channel configuration of the embodiment of the present application, the configuration register configures the available physical memory channels mapped by the virtual memory channel, so that the computing core a can only read and write the memory channels 0 to 2, and the computing core B can only read and write the memory channels 3 to 7, thereby implementing flexible resource allocation.

As shown in fig. 11, assuming that the memory channels 2 and 7 in the multi-memory channel GPU or the CPU chip are damaged (or the corresponding secondary caches 2 and 7 are damaged), by adopting the flexible memory channel configuration of the embodiment of the present application, the configuration register configures the available physical memory channels mapped by the virtual memory channel, so that the computing core a can only read and write the memory channels 0-1, and the computing core B can only read and write the memory channels 3-6, thereby effectively solving the problem of low chip yield caused by damage to part of the channels, and improving the physical service life and system reliability of the computing system.

As shown in fig. 12, assuming that the memory channel 5 (or the corresponding secondary cache 5) in the multi-memory channel GPU or the CPU chip is damaged, by using the flexible memory channel configuration of the embodiment of the present application, and configuring the available physical memory channel mapped by the virtual memory channel through the configuration register, the computing cores a and B can both read and write the designated storage units of the memory channels 0 to 4 and 6 to 7, and the data of the computing cores a and B cannot be allocated to the memory channel 5.

The multi-memory-channel access device, the multi-memory-channel access method, and the data processing device provided in the embodiments of the present application can define the mapping relationship between the physical memory channel and the virtual memory channel through the configuration register, so as to map the multiple memory channels in the chip to the virtual memory channel, and implement the run-time programmed configuration of the multiple memory channels, so that the physical memory address of the memory access request from the processing core only needs to be assigned to the virtual memory channel, and does not need to assign a specific physical memory channel. Compared with the prior art, the embodiment of the application can ensure normal reading and writing of the memory data through flexible configuration of the remaining available physical memory channels even if the memory channels of the processing chip are damaged, thereby improving the manufacturing yield of the chip and the physical service life of the chip and the reliability of a system.

Furthermore, the embodiment of the application can also realize flexible allocation of resources by a virtualization system, and in a multi-core processing chip, each computing core or application process can be bound with one or more memory channel configurations, so that a multi-user virtual machine can randomly divide resources to achieve optimal resource allocation, physical isolation between virtual machines is realized, and multi-memory system configuration in a low power consumption state and a high power consumption state of the multi-memory channel system can be seamlessly switched.

The steps, units or modules involved in the embodiments of the present application may be implemented by software, hardware or a combination thereof. The described steps, units or modules may also be implemented in a processor of a computing processing device, where the name of a unit or module does not constitute a limitation on the unit or module itself.

The embodiments of the present application are not limited to the above-described examples, and various changes and modifications in form and detail may be made by one skilled in the art without departing from the spirit and scope of the present application, which are considered to fall within the scope of the present application.

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Memory access device and method for multiple memory channels and data processing equipment

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