阅读说明：本技术 对象更新、读取方法及装置 (Object updating and reading method and device ) 是由 洪春涛 于 2021-11-17 设计创作，主要内容包括：本说明书实施例提供一种对象更新、读取方法及装置,在对象更新方法中,任意的第一CPU核的第一线程请求获取写锁,该写锁用于表示对第一对象执行更新的权限。读取第一指针,该第一指针指向第一对象。根据第一指针,读取第一对象并复制,得到第二对象。对第二对象的内容进行调整,得到调整后的第二对象。修改第一指针,以使其指向调整后的第二对象。释放写锁。(In the object updating method, a first thread of an arbitrary first CPU core requests to acquire a write lock, and the write lock is used for expressing the authority of executing updating on a first object. A first pointer is read, the first pointer pointing to a first object. And reading and copying the first object according to the first pointer to obtain a second object. And adjusting the content of the second object to obtain the adjusted second object. The first pointer is modified to point to the adjusted second object. The write lock is released.)

1. An object updating method is applied to a multi-core processing system, wherein the multi-core processing system comprises a plurality of CPUs (central processing units), and each CPU comprises a plurality of CPU cores; the first object to be updated is a shared object of a plurality of threads; the method comprises the following steps:

a first thread of any first CPU core requests to acquire a write lock; the write lock is used for representing the authority of updating the first object;

reading a first pointer, the first pointer pointing to the first object;

reading and copying the first object according to the first pointer to obtain a second object;

adjusting the content of the second object to obtain an adjusted second object;

modifying the first pointer to point to the adjusted second object;

the write lock is released.

2. The method of claim 1, further comprising:

setting a corresponding second zone bit array aiming at the adjusted second object;

allocating each zone bit in the second zone bit array to a thread, and initializing the value of each zone bit; and the value of each initialized flag bit is modified when the corresponding thread starts to access the adjusted second object and is recovered when the access is finished.

3. The method of claim 2, further comprising:

applying for a second memory area;

continuously storing the adjusted second object and the second zone bit array in the second memory area according to the sequence;

said modifying said first pointer comprises:

and modifying the value of the first pointer into the address of the second memory area.

4. The method of claim 1, wherein the reading the first pointer comprises:

reading the first pointer from a local cache of the first CPU core; or the like, or, alternatively,

reading the first pointer from a local cache of a second CPU core; or the like, or, alternatively,

and reading the first pointer from the memory.

5. The method of claim 1, further comprising:

and sending a pointer updating message to other threads of other CPU cores to enable the other threads to update the first pointer before modification stored in local caches of the other CPU cores.

6. The method of claim 1, further comprising:

acquiring a first address of the first object according to the first pointer;

and adding the first address into an address recovery queue, wherein the address recovery queue is used for storing the address of the useless object.

7. The method of claim 6, further comprising:

a recycle thread reads the first address from the recycle queue; the recovery thread is any thread which is responsible for recovering the useless objects;

judging whether the first object corresponding to the first address meets a deleting condition;

deleting the first object in a case where the first object satisfies a deletion condition.

8. The method of claim 7, wherein the determining whether the first object corresponding to the first address meets a deletion condition comprises:

traversing whether the value of each zone bit in the first zone bit array of the first object is an initial value; each flag bit in the first flag bit array corresponds to a thread, and the corresponding value of the flag bit array is an initial value to indicate that the corresponding thread does not access the first object;

and if so, determining that the first object meets the deletion condition.

9. The method of claim 1, wherein the read for the first pointer is an atomic operation.

10. An object reading method is applied to a multi-core processing system, wherein the multi-core processing system comprises a plurality of CPUs (central processing units), and each CPU comprises a plurality of CPU cores; the first object to be read is a shared object of a plurality of threads; the method comprises the following steps:

a first thread of any first CPU core reads a first pointer, wherein the first pointer points to the first object; the first object is provided with a corresponding first flag bit array, wherein each flag bit corresponds to one thread;

reading a first zone bit corresponding to the first thread in the first zone bit array according to the first pointer;

modifying the value of the first zone bit into a preset value; the predetermined value indicates that the first thread is accessing the first object;

reading the first object;

and after the first object is read, restoring the value of the first flag bit to an initial value.

11. The method of claim 10, wherein the first object and the first array of flag bits are stored in a first memory region in a sequential order; the value of the first pointer is the address of the first memory region.

12. The method of claim 11, wherein in the first memory region, the first object is ahead and the first flag bit is behind;

the reading a first flag bit corresponding to the first thread in the first flag bit array according to the first pointer includes:

reading the first flag bit according to the address of the first memory area, the size of the first object, the position index of the first thread and the size of the flag bit;

the reading the first object includes:

and reading the first object according to the address of the first memory area.

13. The method of claim 11, wherein, in the first memory region, the first flag bit array is before and the first object is after;

the reading a first flag bit corresponding to the first thread in the first flag bit array according to the first pointer includes:

reading the first zone bit according to the address of the first memory area, the position index of the first thread and the size of the zone bit;

the reading the first object includes:

and reading the first object according to the address of the first memory area and the size of the first zone bit array.

14. The method of claim 12 or 13, wherein the location index of the first thread is consistent with a unique identification of the first thread.

15. The method of claim 10, wherein the initial value is 0;

modifying the value of the first flag bit into a predetermined value includes:

performing a plus 1 operation on the value of the first zone bit;

the restoring the value of the first flag bit to an initial value includes:

and executing 1 subtracting operation on the value of the first flag bit.

16. An object updating device is arranged in a multi-core processing system, wherein the multi-core processing system comprises a plurality of CPUs (central processing units), and each CPU comprises a plurality of CPU cores; the first object to be updated is a shared object of a plurality of threads; the device comprises:

an acquisition unit, configured to request acquisition of a write lock; the write lock is used for representing the authority of updating the first object;

a reading unit, configured to read a first pointer, where the first pointer points to the first object;

the copying unit is used for reading the first object and copying the first object according to the first pointer to obtain a second object;

the adjusting unit is used for adjusting the content of the second object to obtain an adjusted second object;

a modification unit, configured to modify the first pointer to point to the adjusted second object;

a release unit for releasing the write lock.

17. The apparatus of claim 16, further comprising:

the setting unit is used for setting a corresponding second zone bit array aiming at the adjusted second object;

the distribution unit is used for distributing each zone bit in the second zone bit array to a thread and initializing the value of each zone bit; and the value of each initialized flag bit is modified when the corresponding thread starts to access the adjusted second object and is recovered when the access is finished.

18. The apparatus of claim 16, further comprising: an addition unit;

the obtaining unit is further configured to obtain a first address of the first object according to the first pointer;

the adding unit is used for adding the first address into an address recovery queue, and the address recovery queue is used for storing the address of the useless object.

19. The apparatus of claim 18, further comprising: a judging unit and a deleting unit;

the reading unit is further configured to read the first address from the recycle queue;

the judging unit is used for judging whether the first object corresponding to the first address meets a deleting condition;

the deleting unit is used for deleting the first object under the condition that the first object meets a deleting condition.

20. An object reading device is arranged in a multi-core processing system, wherein the multi-core processing system comprises a plurality of CPUs (central processing units), and each CPU comprises a plurality of CPU cores; the first object to be read is a shared object of a plurality of threads; the device comprises:

a reading unit, configured to read a first pointer, where the first pointer points to the first object; the first object is provided with a corresponding first flag bit array, wherein each flag bit corresponds to one thread;

the reading unit is further configured to read a first flag bit corresponding to the first thread in the first flag bit array according to the first pointer;

a modification unit, configured to modify a value of the first flag bit to a predetermined value; the predetermined value indicates that the first thread is accessing the first object;

the reading unit is further used for reading the first object;

and the recovery unit is used for recovering the value of the first zone bit to an initial value after the first object is read.

21. The apparatus of claim 20, wherein the first object and the first array of flag bits are stored in a first memory region in a sequential order; the value of the first pointer is the address of the first memory region.

22. The apparatus of claim 21, wherein, in the first memory region, the first object is ahead and the first flag bit is behind;

the reading unit is specifically configured to:

reading the first flag bit according to the address of the first memory area, the size of the first object, the position index of the first thread and the size of the flag bit;

the reading unit is further configured to:

and reading the first object according to the address of the first memory area.

23. The apparatus of claim 21, wherein the first flag bit array is preceding and the first object is succeeding in the first memory region;

the reading unit is specifically configured to:

reading the first zone bit according to the address of the first memory area, the position index of the first thread and the size of the zone bit;

the reading is also specifically for:

and reading the first object according to the address of the first memory area and the size of the first zone bit array.

24. A computer-readable storage medium, on which a computer program is stored, wherein the computer program causes a computer to carry out the method of any one of claims 1-15, when the computer program is carried out in the computer.

25. A computing device comprising a memory and a processor, wherein the memory has stored therein executable code that when executed by the processor implements the method of any of claims 1-15.

Technical Field

One or more embodiments of the present disclosure relate to the field of computer technologies, and in particular, to a method and an apparatus for updating and reading an object.

Background

The multi-core processing system can process more tasks in unit time, has stronger processing capacity and wider application. When a multi-threaded task is run with a multi-core processing system, the multiple threads may have shared objects that are all operable between them. And when the shared object is updated, only one thread can be updated at the same time, so that data errors caused by thread conflict are avoided. In the prior art, a Lock (Lock) can be applied between threads, a thread which successfully acquires the Lock can operate the shared object, and a thread which does not acquire the Lock can only wait. It should be noted that the lock is usually a global variable, so that cross-CPU core communication is usually required in the process of applying for the lock by a thread.

Disclosure of Invention

One or more embodiments of the present specification describe an object updating method, an object reading method, and an object updating apparatus, which can ensure the security of a read operation for an original object.

In a first aspect, an object updating method is provided, including:

a first thread of any first CPU core requests to acquire a write lock; the write lock is used for representing the authority of updating the first object;

reading a first pointer, the first pointer pointing to the first object;

reading and copying the first object according to the first pointer to obtain a second object;

adjusting the content of the second object to obtain an adjusted second object;

modifying the first pointer to point to the adjusted second object;

the write lock is released.

In a second aspect, an object reading method is provided, including:

a first thread of any first CPU core reads a first pointer, wherein the first pointer points to the first object; the first object is provided with a corresponding first flag bit array, wherein each flag bit corresponds to one thread;

reading a first zone bit corresponding to the first thread in the first zone bit array according to the first pointer;

modifying the value of the first zone bit into a preset value; the predetermined value indicates that the first thread is accessing the first object;

reading the first object;

and after the first object is read, restoring the value of the first flag bit to an initial value.

In a third aspect, an object updating apparatus is provided, including:

an acquisition unit, configured to request acquisition of a write lock; the write lock is used for representing the authority of updating the first object;

a reading unit, configured to read a first pointer, where the first pointer points to the first object;

the copying unit is used for reading the first object and copying the first object according to the first pointer to obtain a second object;

the adjusting unit is used for adjusting the content of the second object to obtain an adjusted second object;

a modification unit, configured to modify the first pointer to point to the adjusted second object;

a release unit for releasing the write lock.

In a fourth aspect, there is provided an object reading apparatus comprising:

a reading unit, configured to read a first pointer, where the first pointer points to the first object; the first object is provided with a corresponding first flag bit array, wherein each flag bit corresponds to one thread;

the reading unit is further configured to read a first flag bit corresponding to the first thread in the first flag bit array according to the first pointer;

a modification unit, configured to modify a value of the first flag bit to a predetermined value; the predetermined value indicates that the first thread is accessing the first object;

the reading unit is further used for reading the first object;

and the recovery unit is used for recovering the value of the first zone bit to an initial value after the first object is read.

In a fifth aspect, there is provided a computer storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform the method of the first or second aspect.

In a sixth aspect, there is provided a computing device comprising a memory having stored therein executable code, and a processor that when executing the executable code, implements the method of the first or second aspect.

In one or more embodiments of the present disclosure, when an arbitrary first thread updates an object shared by multiple threads, the object updating and reading method and apparatus do not directly update the original object, but update a copy of the original object. The pointer to the original object is then modified to point to the updated copy of the object. Thereby, the security of the read operation for the original object can be ensured. In addition, because the updating operation is not executed for the original object, the locking is not required for the reading operation of the original object, thereby reducing the communication cost and saving the computer resources.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 illustrates a schematic diagram of a multi-core processing system, according to one embodiment;

FIG. 2 illustrates a flow diagram of an object update method according to one embodiment;

FIG. 3a is a schematic diagram of a first memory region;

FIG. 3b is a second schematic diagram of a second memory area;

FIG. 4 illustrates a flow diagram of an object reading method according to one embodiment;

FIG. 5 illustrates a schematic diagram of an object update apparatus, according to one embodiment;

FIG. 6 shows a schematic diagram of an object reading device according to one embodiment.

Detailed Description

The scheme provided by the specification is described below with reference to the accompanying drawings.

FIG. 1 shows a schematic diagram of a multi-core processing system, according to one embodiment. In fig. 1, the multi-core processing system includes a plurality of CPUs, respectively represented as: CPU1, CPU2, …. Each CPU may include several CPU cores, for example, CPU1 may include CPU core 1 and CPU core 2, and CPU2 may include CPU core 3 and CPU core 4. Each CPU core may bind several threads, and in the following description of the present specification, one CPU core binds one thread as an example for explanation. For example, CPU core 1 may bind thread a, CPU core 2 may bind thread B, CPU core 3 may bind thread C and CPU core 4 may bind thread D. And each thread may be assigned a different tid.

In fig. 1, each CPU core may further have a corresponding local Cache (Cache), where the Cache is a Cache layer between the CPU and the memory to reduce access frequency to the memory. For example, when the CPU core 1 reads data from the memory, it first reads the data into the Cache1, and then reads the data from the Cache 1. It should be noted that when the CPU reads data from the memory to the Cache, the CPU reads the data not one byte by one byte, but one block, and the data of the block is called a CPU Line (Cache Line), so the CPU Line is a unit for the CPU to read data from the memory to the Cache.

It should be noted that in the multi-core processing system, threads of different CPU cores may be executed concurrently.

When multiple threads execute concurrently, the same data often needs to be accessed. From the perspective of the data being accessed, the data is shared to different threads. When multiple threads access the shared data, the integrity of the shared data needs to be guaranteed. For example, two threads cannot modify shared data at the same time; one thread cannot read the shared data that is modified in half. The classical approach is to use a locking mechanism. For example, a read lock is added to data during a read operation of the data by a thread. After the read operation, the read lock is released. Similarly, a write lock is applied to data during a write operation to the data by a thread. After the write operation, the write lock is released. Read _ ref is typically used as the reference count for a read thread and the writer _ ID is used to represent the ID of a write thread.

For read operations that are performed on the same data by different threads, multiple read locks may be added. For example, if thread a of CPU core 1 performs a read operation on a certain data, before performing the read operation, a read lock is added to the data, specifically, the value of read _ ref is added to 1 (for example, the data type of read _ ref is a shape, and the initial value is 0), and then the data is read. In the reading process, the thread B of the CPU core 2 also performs a read operation on the same data, and adds 1 to the value of read _ ref and reads the data. It should be understood that the value of read _ ref at this time is 2. After the read operation of thread A is completed, the value of read _ ref is decremented by 1 and the read lock is released. At this time, the value of read _ ref is 1. After that, thread B finishes the read operation of the data, the value of read _ ref is reduced by 1, and the read lock is released. At this time, the value of read _ ref is 0. The read locks for the same data can be duplicated, so that the read locks are shared.

For write operations that are performed on the same data by different threads, a write lock can only be applied once. For example, if a thread A is going to write certain data, before the write operation is performed, the data is locked by writing, specifically, the value of the writer _ ID is updated to the ID of the thread A (for example, the data type of the writer _ ID is a shape and the initial value is 0; the ID of any thread is not 0), and then the data is written. In the process of writing, the thread B also performs writing operation on the same data, but since the value of the writer _ ID is not 0 in this case, the thread B cannot add a write lock and cannot perform writing operation on the data. After the write operation of thread A is completed, the write lock is released, i.e., the value of the writer _ ID is updated to 0. After thread B fails the previous write lock and waits for a period of time, it knows that the value of writer _ ID is 0 at this time, and can add the write lock. Thereafter, the value of the writer _ ID is updated to the ID of the thread B, and then the data is written. After the write operation of thread B is completed, the write lock is released, i.e., the value of the writer _ ID is updated to 0. As can be seen, write locks on the same data cannot be duplicated, and thus, there is mutual exclusivity between write locks.

In addition, the write lock and the read lock are mutually exclusive, namely, at any time, the write lock cannot be added again when the read lock is added to the same data, and the write lock cannot be added when the write lock is added. Thus, before a thread reads data, it needs to check whether the writer _ ID value of the data is 0. If 0, the read operation can be performed; if not 0, it is necessary to wait for the writer _ ID value to become 0. Similarly, before writing a data, a thread needs to check whether the read _ ref value of the data is 0. If the value is 0, the write operation can be carried out; if not 0, it is necessary to wait for the read _ ref value to become 0. In fact, for the add-read lock, in order to further avoid the add-write lock operation performed by another thread for a write operation simultaneously between the operation of checking the writer _ ID value and the corresponding read operation, i.e. to avoid the collision detection failure caused in this case, after adding 1 to the value of read _ ref, it is checked again whether the writer _ ID value at this time is 0. If 0, then a read operation is performed. Similarly, for write-lock, in order to further avoid a read-lock operation performed by another thread for a read operation between the operation of checking the read _ ref value and the corresponding write operation, i.e. to avoid failure of collision detection caused in this case, after updating the writer _ ID value to the ID of the write thread, it is checked again whether the read _ ref value at this time is 0. If 0, the write operation is performed.

The change of the read _ ref value and the writer _ ID value by the thread belongs to the atomic operation. Atomic operations are typically instructions provided by the CPU with atomicity. When one thread executes an atomic operation, the thread is not interrupted by other threads and is not switched to other threads. In other words, such an atomic operation, once started, runs until the operation ends.

The above is the conventional method of ensuring the integrity of shared data for multiple threads. The inventors of the present application have found, through research, that the above method has the following problems: first, the read/write operation of data can only be selected one by one, which greatly reduces the read/write efficiency. In addition, in the case where threads of different CPU cores perform a large number of read operations on the same data over a period of time without write operations, a read _ ref value is maintained in the local cache corresponding to each CPU core. And according to the implementation manner in the prior art, the read _ ref value in the local cache corresponding to each CPU core needs to be kept consistent. Thus, for the multi-core processing system, once the read _ ref value in the local cache corresponding to one CPU core changes, the read _ ref value is communicated with other CPU cores to inform the change. And after receiving the notification, other CPU cores update the read _ ref value in the respective local caches. That is, in this case, multiple communications across the CPU cores are required, which would greatly consume communication resources.

For this reason, the present specification will provide an object updating and reading method. In the object updating method, the original object is not updated directly, but a copy of the original object is updated. The pointer to the original object is then modified to point to the updated copy of the object. Thereby, the security of the read operation for the original object can be ensured. In addition, because the updating operation is not executed for the original object, the locking is not required for the reading operation of the original object, thereby reducing the communication cost and saving the computer resources.

In the object reading method, before a reading operation is executed on an object, a flag bit corresponding to a current thread is read from a flag bit array corresponding to the object, and then only the flag bit is modified so as to realize the reference counting of the object. That is to say, in the process of reading the object, each thread only modifies the corresponding flag bit, and locking is not needed, so that cross-CPU core communication is not needed, and therefore, the object reading efficiency can be improved.

This scheme will be described in detail below.

FIG. 2 illustrates a flow diagram of an object update method according to one embodiment. It is to be appreciated that the method can be performed by any apparatus, device, platform, cluster of devices having computing and processing capabilities. Such as the multi-core processing system of fig. 1. As shown in fig. 2, the method includes at least the following steps.

At step 202, a first thread of any first CPU core requests acquisition of a write lock indicating permission to perform an update on a first object.

The first object (also called data object, denoted obj1) may be, for example, a data table, a notepad, or a word document. The first object may also have a first array of flag bits, represented as: flags1[ ], where each flag bit corresponds to a thread (the establishment of the correspondence is described below) and has a corresponding initial value (e.g., 0). The initial value is modified (e.g., to 1) when the corresponding thread begins accessing the first object and is restored when access is terminated. It should be noted that the length of each flag bit may be one cache line, for example, may be 64 bytes. Therefore, the modification of a certain thread for the corresponding flag bit can be ensured, and the failure of the local cache result of other threads can not be caused. In addition, each flag bit also has a corresponding position index, and the position index of each flag bit may be: 0,1,2, …, n-1, wherein n is the number of the flag bits. For example, assuming that the number of flag bits in the first flag bit array may be 256, the position index of each flag bit is: 0,1,2, …, 255.

In this embodiment of the present specification, based on the first object and the first flag bit array, a step of instantiating a predefined class, which may include two variables, may also be performed. Specifically, during instantiation, obj1 may be assigned to a first variable as one class parameter and flags1[ ] may be assigned to a second variable as another class parameter. The result of the above instantiation (also called a class object) can be expressed as: refcountobj 1.

By instantiating the predefined class, the first memory area can be applied from the memory, and the first object and the corresponding first flag bit array are continuously stored in the first memory area according to the sequence.

Fig. 3a and 3b show schematic diagrams of a first memory area. In fig. 3a, the first object is in front and the first flag bit is in back. It should be understood that in this case, the address of the first memory area is the location of the first object in the first memory area. In fig. 3b, the first flag bit array is first and the first object is second. It should be understood that in this case, the location of the first object in the first memory region needs to be determined according to the address of the first memory region and the size of the first flag bit array.

Referring back to fig. 2, the first CPU core may be any one of the CPU cores 1,2, 3, and 4 in fig. 1, for example. The first CPU core may be bound to a plurality of threads, and in the following description of the present specification, the binding of the first CPU core to one thread will be described as an example.

In this specification, for each thread bound to each CPU core, a corresponding tid may be assigned to it. The tid of each thread may be consistent with the position index of the flag bit, that is, the tid of each thread may be an integer value starting from 0, so that a correspondence between the thread and the flag bit may be established, that is, each flag bit may be assigned to one thread. For example, assuming there are 256 threads, the tids of the 256 threads may be: 0,1,2, …, 255.

In addition, there is a one-to-one correspondence between the write locks and the objects, that is, a corresponding write lock is set for each object. Therefore, the request for acquiring the write lock refers to a request for acquiring a write lock corresponding to the first object, and the acquiring process is the same as that in the prior art. Judging whether the value of the writer _ ID is an initial value or not, and if not, failing the request; if so, the request is successful, and then the value of the writer _ ID is modified to the tid of the first thread, thus completing the acquisition of the write lock for the first object.

In this embodiment, the initial value of the writer _ ID may be set to any integer value other than 0 to 255.

At step 204, the first thread reads a first pointer, the first pointer pointing to a first object.

The first pointer (denoted ptr) here may be maintained in memory. It should be noted that the reading of this first pointer belongs to an atomic operation, so that no lock is required. For an explanation of the atomic operations, see above.

When the first thread reads the first pointer for the first time, it is usually determined whether the first pointer is stored in the local caches of the other CPU cores, if so, the first pointer is read from the local caches of the other CPU cores, otherwise, the first pointer is read from the memory. It should be appreciated that after the first read, when the first thread reads the first pointer again, it may read the first pointer directly from the first CPU core's local cache.

It should be noted that, the above-mentioned first pointer pointing to the first object may be understood that the value of the first pointer is the first address of the first object.

It should be understood that when the step of instantiating the predefined class described above is also performed, the value of the first pointer described above may point to refcountobj 1, i.e., the value of the first pointer is the address (typically the first address) of the first memory region.

In addition, the first thread may also record a value of the first pointer, i.e. record a first address of the first object or an address of the first memory area.

In step 206, the first thread reads and copies the first object according to the first pointer to obtain a second object.

Specifically, the first object is preferentially read from the local cache of the first CPU core, and if the first object is read, the process is ended; otherwise, reading the first object from the local caches of other CPU cores, if so, ending, otherwise, reading the first object from the memory.

For example, taking the value of the first pointer as the address of the first memory area, the process of reading the first object from the memory may be: if the first object is in front of the first memory area and the first flag bit is behind the first memory area, the first object can be read directly according to the address of the first memory area. Otherwise, if the first flag bit array is in front of the first object and the first object is behind the first object in the memory area, the first object may be read according to the address of the first memory area and the size of the first flag bit array. For example, the location of the first object in the first memory area may be determined by the following formula: ptr +256 × 64, where ptr is the address (typically the first address) of the first memory region, 256 is the number of flag bits, 64 is the size of the flag bits (i.e., the length of the flag bits), and 256 × 64 is the size of the first flag bit array.

The second object obtained by the replication may be represented as: obj 2.

And step 208, the first thread adjusts the content of the second object to obtain an adjusted second object.

Taking the first object and the second object as data tables as an example, the adjusted second object, denoted obj2, can be obtained by modifying the field values in the data tables.

For the adjusted second object, a corresponding second flag bit array, denoted as flags2[ ], may also be set. It should be understood that each flag bit in the second flag bit array also has a corresponding position index, which is: 0,1,2, …, n-1, wherein n is the number of the flag bits. That is, the position index of each flag bit in the second flag bit array is consistent with the tid of each thread, so that the corresponding relationship between each flag bit in the second flag bit array and a thread can be established, that is, each flag bit can be allocated to one thread.

For the second flag bit array, the value of each flag bit may be initialized, for example, to 0. In one example, each flag bit may have a length of one cache line, for example, 64 bytes. Therefore, the modification of a certain thread for the corresponding flag bit can be ensured, and the failure of the local cache result of other threads can not be caused.

It should be noted that the initial value of each flag bit in the second flag bit array is modified (for example, modified to 1) when the corresponding thread starts accessing the adjusted second object, and is restored when the access is finished.

Optionally, the predefined class may be instantiated again after the adjusted second object is obtained. As described above, the predefined class may include two variables. Specifically, during the instantiation process, obj2 can be assigned to a first variable as a class parameter, and flags2[ ] can be assigned to a second variable as another class parameter. The result of the above instantiation (also called a class object) can be expressed as: refcountobj 2.

By instantiating the predefined class, the second memory area can be applied from the memory, and the adjusted second object and the second flag bit array are continuously stored in the second memory area according to the sequence.

In step 210, the first thread modifies the first pointer to point to the adjusted second object.

Here, the first pointer may be modified by an atomic operation. That is, in the present specification embodiment, both the read and write operations with respect to the first pointer are atomic operations, and therefore dirty data is not read when data is read according to the pointer.

The modified value of the first pointer is the adjusted second address of the second object.

When the above step of instantiating the predefined class is also performed, the modified first pointer points to refcountobj 2, i.e. the value of the modified first pointer is the address (typically the first address) of the second memory area.

It should be appreciated that the above-described operation of modifying the first pointer is performed after the adjusted second object is obtained, so that the first pointer can always point to a valid object.

At step 212, the first thread releases the write lock.

The step of releasing the write lock may include: the value of the writer _ ID is restored to the initial value, and the update for the first object is completed.

It is noted that after the first thread modifies the value of the first pointer, it may send a pointer update message to other threads of other CPU cores to cause the other threads to update the pre-modified first pointer stored in the local caches of the other CPU cores. For example, when the first thread is thread a of CPU core 1, then a pointer update message may be sent to thread B, thread C, and thread D corresponding to CPU core 2, CPU core 3, and CPU core 4, respectively. Thread B, thread C, and thread D, upon receiving the pointer update message, may update the first pointer before modification stored in the local cache of the corresponding CPU core.

That is, after the value of the first pointer is modified, communication across the CPU cores needs to be performed once, and then each thread may directly read from the local cache of the corresponding CPU core.

It should be further noted that the first thread may also put the recorded first address of the first object or the address of the first memory area into an address recycling queue. The address reclaim queue is used to store addresses for garbage objects.

After the first address or the address of the first memory area is put into a recycle queue, a recycle thread reads the first address or the address of the first memory area from the recycle queue, wherein the recycle thread is any thread which is responsible for recycling the useless object. If the reading fails, waiting; if the reading is successful, whether the first address or the first object corresponding to the address of the first memory area meets the deletion condition is judged, and under the condition that the first object meets the deletion condition, the first object or the instantiated result (including the first object and the first flag bit array) is deleted to release the memory resources. Otherwise, waiting for a period of time and judging whether the deletion condition is met again until the deletion condition is met.

In one example, the determining whether the deletion condition is satisfied may include: and judging whether the modified time length aiming at the first pointer reaches a preset time length, if so, meeting, otherwise, not meeting.

In another example, determining whether the deletion condition is satisfied may include: traversing whether the value of each zone bit in a first zone bit array of the first object is an initial value; wherein, the corresponding value of each flag bit in the first flag bit array is an initial value to indicate that the corresponding thread does not access the first object; if so, determining that the first object meets the deletion condition, otherwise, not meeting the deletion condition.

In summary, according to the object updating method provided in the embodiments of the present specification, when any first thread updates an object shared by multiple threads, the first thread does not directly update the original object, but updates a copy of the original object. The pointer to the original object is then modified to point to the updated copy of the object. Therefore, the safety of the reading operation aiming at the original object can be ensured, namely, dirty data can not be read at any time. In addition, the updating operation is not executed for the original object, so that the locking is not required for the reading operation of the original object, and therefore, communication between the threads does not need to be carried out across CPU cores, the communication cost can be reduced, and the computer resources are saved.

FIG. 4 illustrates a flow diagram of an object reading method according to one embodiment. The method may be performed by any apparatus, device, platform, cluster of devices having computing, processing capabilities. Such as the multi-core processing system of fig. 1. As shown in fig. 4, the method includes at least the following steps.

At step 402, a first thread of any first CPU core reads a first pointer.

Where the first pointer points to a first object having a corresponding first array of flag bits, where each flag bit corresponds to a thread. The first pointer, the first object, the first flag bit array and the related description of the flag bits may be referred to above, and the description of the present specification is not repeated herein.

The above-described reading of the first pointer belongs to an atomic operation, so that no lock is required. For an explanation of the atomic operations, see above.

Specifically, the first object may be preferentially read from the local cache of the first CPU core, and if the first object is read, the process is ended; otherwise, reading the first object from the local caches of other CPU cores, if so, ending, otherwise, reading the first object from the memory.

In addition, as described above, the first object and the corresponding first flag bit array may be stored in the first memory area sequentially, so that the value of the first pointer may be the address of the first memory area.

In step 404, the first thread reads a first flag bit corresponding to the first thread from the first flag bit array according to the first pointer.

As described above, in this specification, for each thread bound to each CPU core, a corresponding tid may be assigned thereto. The tid of each thread may be consistent with the position index of the flag bit, that is, the tid of each thread may be an integer value starting from 0, so that a correspondence between the thread and the flag bit may be established, that is, each flag bit may be assigned to one thread.

The above-described procedure for reading the first flag bit is explained below in two cases.

First, in the first memory area, the first object is in front, and the first flag bit is behind, then reading the first flag bit may include: and reading the first flag bit according to the address of the first memory area, the size of the first object, the position index of the first thread and the size of the flag bit.

In one example, the location of the first flag bit in the first memory region may be determined according to the following formula: ptr + S (obj1) + n × 64, where ptr is the address (usually the first address) of the first memory area, S (obj1) is the size of the first object, 64 is the size of the flag bit (i.e. the length of the flag bit), and n is the position index of the first thread, and its value range is: [0,255]. As described above, the tid of the first thread is consistent with its position index, so that n can also be understood as the unique identification tid of the first thread.

Second, reading the first flag bit in the first memory area with the first flag bit array ahead and the first object behind may include: and reading the first zone bit according to the address of the first memory area, the position index of the first thread and the size of the zone bit.

In one example, the location of the first flag bit in the first memory region may be determined according to the following formula: ptr + n × 64, where ptr is an address (generally, a first address) of the first memory area, 64 is a size of a flag bit (i.e., a value length of the flag bit), n is a position index of the first thread, and a value range thereof is: [0,255].

It should be understood that the above is the process of reading the first flag bit for the first time by the first thread, i.e. the process of reading the first flag bit from the memory. After the first flag bit is read once, the first flag bit is stored in a local cache of the first CPU core, so that when the first thread needs to read the first flag bit again, the first thread only needs to read the first flag bit from the local cache, and cross-CPU core communication does not need to be executed.

In step 406, the first thread modifies the value of the first flag bit to a predetermined value.

The predetermined value indicates that the first thread is accessing the first object. In one example, the predetermined value may be 1.

Taking the initial value of the first flag bit as 0 as an example, the modifying the value of the first flag bit to the predetermined value may include: and performing 1 addition operation on the value of the first flag bit.

At step 408, the first thread reads the first object.

Specifically, the first object is preferentially read from the local cache of the first CPU core, and if the first object is read, the process is ended; otherwise, reading the first object from the local caches of other CPU cores, if so, ending, otherwise, reading the first object from the memory.

For example, taking the value of the first pointer as the address of the first memory area, the process of reading the first object from the memory may be: if the first object is in front of the first memory area and the first flag bit is behind the first memory area, the first object can be read directly according to the address of the first memory area. Otherwise, if the first flag bit array is in front of the first object and the first object is behind the first object in the memory area, the first object may be read according to the address of the first memory area and the size of the first flag bit array. For example, the location of the first object in the first memory area may be determined by the following formula: ptr +256 × 64, where ptr is the address (typically the first address) of the first memory region, 256 is the number of flag bits, 64 is the size of the flag bits (i.e., the length of the flag bits), and 256 × 64 is the size of the first flag bit array.

In step 410, the first thread restores the value of the first flag bit to the initial value after reading the first object.

Taking the initial value of the first flag bit as 0 as an example, the restoring the value of the first flag bit to the initial value may include: and performing 1 subtraction operation on the value of the first flag bit.

It should be noted that, in the embodiment of this specification, only the corresponding thread will execute for modification and recovery of the flag bit, and other threads will not execute, so that locking is not required. In addition, when the value length of each flag bit is one cache line, the modification or recovery of each thread for each flag bit does not cause the failure of the local cache result of other threads.

In summary, the object reading method provided in the embodiments of the present specification is a read-only operation for the object reading operation, does not need to be locked, and does not cause communication across CPU cores, thereby greatly saving computer resources.

Corresponding to the object updating method, an embodiment of the present specification further provides an object updating apparatus. The device is arranged in a multi-core processing system, the multi-core processing system comprises a plurality of CPUs, and each CPU comprises a plurality of CPU cores. As shown in fig. 5, the apparatus may include:

an obtaining unit 502 is configured to request to obtain a write lock, where the write lock is used to indicate a right to perform an update on a first object.

A reading unit 504 is configured to read a first pointer, where the first pointer points to a first object.

Wherein the reading for the first pointer is an atomic operation.

The reading unit 504 is specifically configured to:

reading a first pointer from a local cache of a first CPU core; or the like, or, alternatively,

reading a first pointer from a local cache of a second CPU core; or the like, or, alternatively,

and reading the first pointer from the memory.

And the copying unit 506 is configured to read the first object and copy the first object according to the first pointer to obtain a second object.

An adjusting unit 508, configured to adjust the content of the second object to obtain an adjusted second object.

A modifying unit 510, configured to modify the first pointer to point to the adjusted second object.

A release unit 512 for releasing the write lock.

Optionally, the apparatus further comprises:

a setting unit 514, configured to set a corresponding second flag bit array for the adjusted second object.

And an allocating unit 516, configured to allocate each flag bit in the second flag bit array to a thread, and initialize a value of each flag bit. And the value of each initialized flag bit is modified when the corresponding thread starts to access the adjusted second object and is recovered when the access is finished.

Optionally, the apparatus further comprises:

and the application unit is used for applying for the second memory area.

And the storage unit is used for continuously storing the adjusted second object and the second flag bit array in the second memory area according to the sequence.

The modifying unit 510 is specifically configured to:

and modifying the value of the first pointer into the address of the second memory area.

Optionally, the apparatus further comprises: a transmitting unit;

and the sending unit is used for sending the pointer updating message to other threads of other CPU cores so that the other threads update the first pointers before modification stored in the local caches of the other CPU cores.

Optionally, the apparatus further comprises: a unit 518 is added.

The obtaining unit 502 is further configured to obtain a first address of the first object according to the first pointer.

An adding unit 518 is configured to add the first address to an address de-allocation queue, where the address de-allocation queue is configured to store addresses of the garbage objects.

Optionally, the apparatus further comprises: a judging unit 520 and a deleting unit 522.

The reading unit 504 is further configured to read the first address from a recycle queue, where the recycle thread is any thread responsible for recycling the garbage object.

The determining unit 520 is configured to determine whether the first object corresponding to the first address satisfies the deletion condition.

The determining unit 520 is specifically configured to:

traversing whether the value of each zone bit in a first zone bit array of the first object is an initial value; each zone bit in the first zone bit array corresponds to one thread, and the corresponding value of the zone bit array is an initial value to indicate that the corresponding thread does not access the first object;

if so, determining that the first object meets the deletion condition.

A deleting unit 522 for deleting the first object in case the first object satisfies the deletion condition.

The functions of each functional module of the device in the above embodiments of the present description may be implemented through each step of the above method embodiments, and therefore, a specific working process of the device provided in one embodiment of the present description is not repeated herein.

The object updating method provided by one embodiment of the present specification can ensure the security of the read operation for the original object.

Corresponding to the object reading method, an embodiment of the specification further provides an object reading device. The device is arranged in a multi-core processing system, the multi-core processing system comprises a plurality of CPUs, and each CPU comprises a plurality of CPU cores. As shown in fig. 6, the apparatus may include:

a reading unit 602, configured to read a first pointer, where the first pointer points to a first object. The first object has a corresponding first array of flag bits, each flag bit corresponding to a thread.

The first object and the first zone bit array are stored in the first memory area according to the sequence, and the value of the first pointer is the address of the first memory area.

The reading unit 602 is further configured to read a first flag bit corresponding to the first thread in the first flag bit array according to the first pointer.

A modifying unit 604, configured to modify a value of the first flag bit to a predetermined value, where the predetermined value indicates that the first thread is accessing the first object.

Wherein the initial value is 0, and the modifying unit 604 is specifically configured to:

and performing 1 addition operation on the value of the first flag bit.

The reading unit 602 is further configured to read the first object.

A restoring unit 606, configured to restore the value of the first flag bit to the initial value after reading the first object.

The recovery unit 606 is specifically configured to:

and performing 1 subtraction operation on the value of the first flag bit.

Wherein, in the first memory area, the first object is in front and the first flag bit is in back;

the reading unit 602 is specifically configured to:

reading a first zone bit according to the address of the first memory area, the size of the first object, the position index of the first thread and the size of the zone bit;

the reading unit 602 is further specifically configured to:

and reading the first object according to the address of the first memory area.

Wherein, in the first memory region, the first flag bit array is in front of the first object;

the reading unit 602 is specifically configured to:

reading a first zone bit according to the address of the first memory area, the position index of the first thread and the size of the zone bit;

the reading unit 602 is further specifically configured to:

and reading the first object according to the address of the first memory area and the size of the first zone bit array.

Wherein the position index of the first thread is determined according to the unique identifier of the first thread.

The functions of each functional module of the device in the above embodiments of the present description may be implemented through each step of the above method embodiments, and therefore, a specific working process of the device provided in one embodiment of the present description is not repeated herein.

The object reading method provided by one embodiment of the specification can save communication resources.

According to an embodiment of another aspect, there is also provided a computer-readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform the method described in connection with fig. 2 or fig. 4.

According to an embodiment of yet another aspect, there is also provided a computing device comprising a memory having stored therein executable code, and a processor that, when executing the executable code, implements the method described in connection with fig. 2 or fig. 4.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied in hardware or may be embodied in software instructions executed by a processor. The software instructions may consist of corresponding software modules that may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. Additionally, the ASIC may reside in a server. Of course, the processor and the storage medium may reside as discrete components in a server.

Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in this invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

The above-mentioned embodiments, objects, technical solutions and advantages of the present specification are further described in detail, it should be understood that the above-mentioned embodiments are only specific embodiments of the present specification, and are not intended to limit the scope of the present specification, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present specification should be included in the scope of the present specification.