阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 驹井尚纪 佐佐木直人 小川尚纪 井上孝史 岩元勇人 大冈豊 长田昌也 于 2014-12-12 设计创作，主要内容包括：本发明涉及半导体器件。该半导体器件可包括：第一半导体基板和第二半导体基板,在所述第一半导体基板中形成有像素区域,在所述像素区域内二维布置有进行光电转换的像素部,在所述第二半导体基板中形成有用于处理从所述像素部输出的像素信号的逻辑电路,所述第一半导体基板与所述第二半导体基板被层叠,其中,在所述第一半导体基板的所述像素区域内的片上透镜上布置有用于保护所述片上透镜的保护基板,在所述保护基板与所述片上透镜之间设置有密封树脂。(The present invention relates to a semiconductor device. The semiconductor device may include: a first semiconductor substrate in which a pixel region in which a pixel portion performing photoelectric conversion is two-dimensionally arranged and a second semiconductor substrate in which a logic circuit for processing a pixel signal output from the pixel portion is formed are laminated, wherein a protective substrate for protecting an on-chip lens is arranged on the on-chip lens in the pixel region of the first semiconductor substrate, and a sealing resin is provided between the protective substrate and the on-chip lens.)

1. A semiconductor device, comprising:

a first semiconductor substrate in which a pixel region in which pixel portions that perform photoelectric conversion are two-dimensionally arranged and a second semiconductor substrate in which a logic circuit for processing pixel signals output from the pixel portions are formed, the first semiconductor substrate and the second semiconductor substrate being laminated,

wherein a protective substrate for protecting the on-chip lenses is disposed on the on-chip lenses in the pixel region of the first semiconductor substrate, and a sealing resin is disposed between the protective substrate and the on-chip lenses.

2. The semiconductor device according to claim 1, wherein the laminated structure of the first semiconductor substrate and the second semiconductor substrate includes a wiring layer of the first semiconductor substrate and a wiring layer of the second semiconductor substrate which are in contact with each other.

3. The semiconductor device of claim 2, further comprising:

a first through electrode that penetrates the first semiconductor substrate and is electrically connected to the wiring layer of the first semiconductor substrate;

a second through electrode penetrating the first semiconductor substrate and the wiring layer of the first semiconductor substrate and electrically connected to the wiring layer of the second semiconductor substrate;

a connection wiring electrically connecting the first through electrode to the second through electrode; and

a third through electrode penetrating the second semiconductor substrate and electrically connecting an electrode section to a wiring layer of the second semiconductor substrate, the electrode section outputting the pixel signal to an outside of the semiconductor device.

4. The semiconductor device according to claim 3, wherein a solder mask is formed on a surface on which the electrode portion of the second semiconductor substrate is formed, and the solder mask is not formed in a region in which the electrode portion is formed.

5. The semiconductor device according to claim 3, wherein an insulating film is formed on a surface on which the electrode portion of the second semiconductor substrate is formed, and the insulating film is not formed in a region in which the electrode portion is formed.

6. The semiconductor device of claim 2, further comprising:

a first through electrode that penetrates the second semiconductor substrate and is electrically connected to the wiring layer of the second semiconductor substrate;

a second through electrode penetrating the second semiconductor substrate and the wiring layer of the second semiconductor substrate and electrically connected to the wiring layer of the first semiconductor substrate;

a connection wiring electrically connecting the first through electrode to the second through electrode; and

a rewiring that electrically connects an electrode portion, which outputs the pixel signal to the outside of the semiconductor device, to the connection wiring.

7. The semiconductor device of claim 2, further comprising:

a through electrode penetrating the second semiconductor substrate and electrically connecting an electrode section to a wiring layer of the second semiconductor substrate, the electrode section outputting the pixel signal to an outside of the semiconductor device; and

a rewiring that electrically connects the through electrode to the electrode section,

wherein the wiring layer of the first semiconductor substrate and the wiring layer of the second semiconductor substrate are connected by metal bonding of one or more of the wiring layers.

8. The semiconductor device of claim 7, further comprising:

a dummy wiring that is not electrically connected to any wiring layer in the same layer as the rewiring.

9. The semiconductor device of claim 2, further comprising:

a first through electrode that penetrates the second semiconductor substrate and is electrically connected to the wiring layer of the second semiconductor substrate;

a second through electrode penetrating the second semiconductor substrate and the wiring layer of the second semiconductor substrate and electrically connected to the wiring layer of the first semiconductor substrate;

a connection wiring electrically connecting the first through electrode to the second through electrode;

a rewiring electrically connected to an electrode section that outputs the pixel signal to an outside of the semiconductor device; and

a connection conductor connecting the rewiring to the connection wiring.

10. The semiconductor device of claim 2, further comprising:

a first through electrode that penetrates the first semiconductor substrate and is electrically connected to the wiring layer of the first semiconductor substrate;

a second through electrode penetrating the first semiconductor substrate and the wiring layer of the first semiconductor substrate and electrically connected to the wiring layer of the second semiconductor substrate;

a connection wiring electrically connecting the first through electrode to the second through electrode; and

a third through electrode penetrating the first and second semiconductor substrates and electrically connected to an electrode portion that outputs the pixel signal to an outside of the semiconductor device.

Technical Field

The present invention relates to a semiconductor device and a manufacturing method thereof, and an electronic apparatus, and more particularly, to a semiconductor device configured to be further miniaturized and a manufacturing method thereof, and an electronic apparatus.

< cross reference to related applications >

This application claims priority to japanese priority patent applications JP2013-262099 filed on 12/19/2013 and japanese priority patent application JP2014-100182 filed on 5/14/2014, and the entire contents of these japanese priority applications are incorporated herein by reference.

Background

In response to the demand for miniaturization of semiconductor devices, wafer-level CSPs (Chip Size packages) have been realized, for which semiconductor devices are miniaturized to Chip sizes.

As a wafer-level CSP of the solid-state imaging device, such a structure has been proposed: among them, a surface-type solid-state imaging device in which a color filter or an on-chip lens is formed is pasted to glass having a cavity structure, a through hole and a rewiring (rewiring) are formed from one side of a silicon substrate, and a solder ball is mounted (for example, see PTL 1).

Reference list

Patent document

PTL 1: japanese unexamined patent application publication No. 2009-158862

Disclosure of Invention

Technical problem

The surface type solid-state imaging device has a structure in which: in which a pixel region in which pixel portions for performing photoelectric conversion are arrayed and a peripheral circuit for performing control are arranged in a planar direction. In some cases, in addition to the peripheral circuits, an image processing unit or the like that performs pixel signal processing is also arranged in the planar direction. Even when the surface-type solid-state imaging device has a wafer-level CSP structure, there is a limit to the reduction of the area due to the fact that the solid-state imaging device has a package size of a planar area containing at least peripheral circuits.

In view of such circumstances, the present invention has been devised and further miniaturization of a semiconductor device is desired.

Solution to the problem

According to a first embodiment of the present invention, there is provided a semiconductor device including a first semiconductor substrate in which a pixel region in which pixel portions that perform photoelectric conversion are two-dimensionally arranged and a second semiconductor substrate in which a logic circuit that processes pixel signals output from the pixel portions is formed, the first and second semiconductor substrates being laminated. A protective substrate for protecting the on-chip lens is provided on the on-chip lens in the pixel region of the first semiconductor substrate, and a sealing resin is interposed between the on-chip lens and the protective substrate.

According to a second embodiment of the present invention, there is provided a method of manufacturing a semiconductor device. The method comprises the following steps: connecting a first semiconductor substrate formed with a first wiring layer and a second semiconductor substrate formed with a second wiring layer so that the wiring layers of the two face each other; forming through electrodes electrically connected to the first wiring layer and the second wiring layer; forming a color filter and an on-chip lens; and a protective substrate that protects the on-chip lens is attached to the on-chip lens by a sealing resin.

In the second embodiment of the present invention, a first semiconductor substrate formed with a first wiring layer and a second semiconductor substrate formed with a second wiring layer are connected so that the wiring layers thereof face each other, through electrodes electrically connected to the first wiring layer and the second wiring layer are formed, a color filter and an on-chip lens are formed, and a protective substrate protecting the on-chip lens is connected to the on-chip lens through a sealing resin.

According to a third embodiment of the present invention, there is provided a method of manufacturing a semiconductor device. The method comprises the following steps: forming a color filter and an on-chip lens on a surface opposite to a side of a first wiring layer on which the first semiconductor substrate is formed, on the first semiconductor substrate; forming a through electrode penetrating the second semiconductor substrate formed with the second wiring layer; and connecting the first semiconductor substrate on which the color filters and the on-chip lenses are formed and the second semiconductor substrate on which the through electrodes are formed so that wiring layers of the two face each other.

In a third embodiment according to the present invention, in a first semiconductor substrate formed with a first wiring layer, a color filter and an on-chip lens are formed on a surface opposite to a side of the first wiring layer formed with the first semiconductor substrate; a through electrode formed in the second semiconductor substrate having the second wiring layer and penetrating the second semiconductor substrate; and the first semiconductor substrate formed with the color filters and the on-chip lenses and the second semiconductor substrate formed with the through electrodes are connected such that wiring layers thereof face each other.

According to a fourth embodiment of the present invention, there is provided an electronic device including a first semiconductor substrate in which a pixel region in which pixel sections that perform photoelectric conversion are two-dimensionally arranged and a second semiconductor substrate in which a logic circuit that processes pixel signals output from the pixel sections is formed, the first semiconductor substrate and the second semiconductor substrate being laminated. A protective substrate that protects the on-chip lens is disposed on the on-chip lens in the pixel region of the first semiconductor substrate, and a sealing resin is interposed between the on-chip lens and the protective substrate.

In the first to fourth embodiments of the present invention, a first semiconductor substrate formed with a pixel region in which pixel portions performing photoelectric conversion are two-dimensionally arranged and a second semiconductor substrate formed with a logic circuit that processes pixel signals output from the pixel portions are configured to be laminated. A protective substrate that protects the on-chip lens is disposed on the on-chip lens in the pixel region of the first semiconductor substrate, and a sealing resin is interposed between the on-chip lens and the protective substrate.

The semiconductor device and the electronic apparatus may be separate devices or may be modules embedded in other devices.

The invention has the advantages of

According to the first to fourth embodiments of the present invention, the semiconductor device can be further miniaturized.

It is not necessary to limit the advantageous effects described herein but any advantageous effects described in the present specification may be obtained.

Drawings

Fig. 1 is a schematic diagram illustrating an appearance of a solid-state imaging device as a semiconductor device according to an embodiment of the present invention.

Fig. 2 is an explanatory diagram illustrating a substrate of the solid-state imaging device.

Fig. 3 illustrates a circuit configuration example of the laminated substrate.

Fig. 4 illustrates an equivalent circuit of a pixel.

Fig. 5 illustrates a detailed structure of the laminated substrate.

Fig. 6 is an explanatory diagram illustrating a detailed structure of the laminated substrate according to the first modification.

Fig. 7 is an explanatory diagram illustrating a detailed structure of a laminated substrate according to a second modification.

Fig. 8 is an explanatory diagram illustrating a detailed structure of a laminated substrate according to a third modification.

Fig. 9 is an explanatory diagram illustrating a detailed structure of a laminated substrate according to a fourth modification.

Fig. 10 is an explanatory diagram illustrating a detailed structure of a laminated substrate according to a fifth modification.

Fig. 11 is an explanatory diagram illustrating a detailed structure of a laminated substrate according to a sixth modification.

Fig. 12 is an explanatory diagram illustrating a detailed structure of a laminated substrate according to a seventh modification.

Fig. 13 is an explanatory diagram illustrating a detailed structure of a laminated substrate according to an eighth modification.

Fig. 14 is an explanatory diagram illustrating a detailed structure of a laminated substrate according to a ninth modification.

Fig. 15 is a sectional view illustrating a back-facing structure of the solid-state imaging device.

Fig. 16 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 17 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 18 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 19 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 20 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 21 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 22 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 23 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 24 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 25 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 26 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 27 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 28 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 29 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 30 is an explanatory diagram illustrating a first manufacturing method of the solid-state imaging device of fig. 15.

Fig. 31 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 32 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 33 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 34 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 35 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 36 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 37 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 38 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 39 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 40 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 41 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 42 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 43 is an explanatory diagram illustrating a second manufacturing method of the solid-state imaging device of fig. 15.

Fig. 44 is an explanatory diagram illustrating a third manufacturing method of the solid-state imaging device of fig. 15.

Fig. 45 is an explanatory diagram illustrating a third manufacturing method of the solid-state imaging device of fig. 15.

Fig. 46 is an explanatory diagram illustrating a third manufacturing method of the solid-state imaging device of fig. 15.

Fig. 47 is an explanatory diagram illustrating a third manufacturing method of the solid-state imaging device of fig. 15.

Fig. 48 is an explanatory diagram illustrating a third manufacturing method of the solid-state imaging device of fig. 15.

Fig. 49 is an explanatory diagram illustrating a third manufacturing method of the solid-state imaging device of fig. 15.

Fig. 50 is an explanatory diagram illustrating rewiring according to a modification.

Fig. 51A is an explanatory diagram illustrating rewiring according to a modification.

Fig. 51B is an explanatory diagram illustrating rewiring according to a modification.

Fig. 51C is an explanatory diagram illustrating rewiring according to a modification.

Fig. 52A is an explanatory diagram illustrating rewiring according to a modification.

Fig. 52B is an explanatory diagram illustrating rewiring according to a modification.

Fig. 52C is an explanatory diagram illustrating rewiring according to a modification.

Fig. 52D is an explanatory diagram illustrating rewiring according to a modification.

Fig. 53 is an explanatory diagram illustrating rewiring according to a modification.

Fig. 54A is an explanatory diagram illustrating rewiring according to a modification.

Fig. 54B is an explanatory diagram illustrating rewiring according to a modification.

Fig. 54C is an explanatory diagram illustrating rewiring according to a modification.

Fig. 54D is an explanatory diagram illustrating rewiring according to a modification.

Fig. 54E is an explanatory diagram illustrating rewiring according to a modification.

Fig. 55 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 56 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 57 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 58 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 59 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 60 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 61 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 62 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 63 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 64 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 65 is an explanatory diagram illustrating a manufacturing method of the solid-state imaging device of fig. 5.

Fig. 66A is an explanatory diagram illustrating a first manufacturing method of the first modification of fig. 6.

Fig. 66B is an explanatory diagram illustrating a first manufacturing method of the first modification of fig. 6.

Fig. 66C is an explanatory diagram illustrating a first manufacturing method of the first modification of fig. 6.

Fig. 66D is an explanatory diagram illustrating a first manufacturing method of the first modification of fig. 6.

Fig. 67A is an explanatory diagram illustrating a first manufacturing method of the first modification of fig. 6.

Fig. 67B is an explanatory diagram illustrating a first manufacturing method of the first modification of fig. 6.

Fig. 67C is an explanatory diagram illustrating a first manufacturing method of the first modification of fig. 6.

Fig. 68A is an explanatory diagram illustrating a second manufacturing method of the first modification of fig. 6.

Fig. 68B is an explanatory diagram illustrating a second manufacturing method of the first modification of fig. 6.

Fig. 68C is an explanatory diagram illustrating a second manufacturing method of the first modification of fig. 6.

Fig. 68D is an explanatory diagram illustrating a second manufacturing method of the first modification of fig. 6.

Fig. 69A is an explanatory diagram illustrating a second manufacturing method of the first modification of fig. 6.

Fig. 69B is an explanatory diagram illustrating a second manufacturing method of the first modification of fig. 6.

Fig. 69C is an explanatory diagram illustrating a second manufacturing method of the first modification of fig. 6.

Fig. 70A is an explanatory diagram illustrating a second manufacturing method of the first modification of fig. 6.

Fig. 70B is an explanatory diagram illustrating a second manufacturing method of the first modification of fig. 6.

Fig. 70C is an explanatory diagram illustrating a second manufacturing method of the first modification of fig. 6.

Fig. 71A is an explanatory diagram illustrating a modification of the second manufacturing method of the first modification of fig. 6.

Fig. 71B is an explanatory diagram illustrating a modification of the second manufacturing method of the first modification of fig. 6.

Fig. 72A is an explanatory diagram illustrating a third manufacturing method of the first modification of fig. 6.

Fig. 72B is an explanatory diagram illustrating a third manufacturing method of the first modification of fig. 6.

Fig. 72C is an explanatory diagram illustrating a third manufacturing method of the first modification of fig. 6.

Fig. 72D is an explanatory diagram illustrating a third manufacturing method of the first modification of fig. 6.

Fig. 73A is an explanatory diagram illustrating a third manufacturing method of the first modification of fig. 6.

Fig. 73B is an explanatory diagram illustrating a third manufacturing method of the first modification of fig. 6.

Fig. 73C is an explanatory diagram illustrating a third manufacturing method of the first modification of fig. 6.

Fig. 73D is an explanatory diagram illustrating a third manufacturing method of the first modification of fig. 6.

Fig. 74A is an explanatory diagram illustrating a fourth manufacturing method of the first modification of fig. 6.

Fig. 74B is an explanatory diagram illustrating a fourth manufacturing method of the first modification of fig. 6.

Fig. 74C is an explanatory diagram illustrating a fourth manufacturing method of the first modification of fig. 6.

Fig. 74D is an explanatory diagram illustrating a fourth manufacturing method of the first modification of fig. 6.

Fig. 75A is an explanatory diagram illustrating a fourth manufacturing method of the first modification of fig. 6.

Fig. 75B is an explanatory diagram illustrating a fourth manufacturing method of the first modification of fig. 6.

Fig. 75C is an explanatory diagram illustrating a fourth manufacturing method of the first modification of fig. 6.

Fig. 75D is an explanatory diagram illustrating a fourth manufacturing method of the first modification of fig. 6.

Fig. 76A is an explanatory diagram illustrating a fifth manufacturing method of the first modification of fig. 6.

Fig. 76B is an explanatory diagram illustrating a fifth manufacturing method of the first modification of fig. 6.

Fig. 76C is an explanatory diagram illustrating a fifth manufacturing method of the first modification of fig. 6.

Fig. 76D is an explanatory diagram illustrating a fifth manufacturing method of the first modification of fig. 6.

Fig. 77A is an explanatory diagram illustrating a fifth manufacturing method of the first modification of fig. 6.

Fig. 77B is an explanatory diagram illustrating a fifth manufacturing method of the first modification of fig. 6.

Fig. 77C is an explanatory diagram illustrating a fifth manufacturing method of the first modification of fig. 6.

Fig. 78A is an explanatory diagram illustrating a sixth manufacturing method of the first modification of fig. 6.

Fig. 78B is an explanatory diagram illustrating a sixth manufacturing method of the first modification of fig. 6.

Fig. 78C is an explanatory diagram illustrating a sixth manufacturing method of the first modification of fig. 6.

Fig. 78D is an explanatory diagram illustrating a sixth manufacturing method of the first modification of fig. 6.

Fig. 79A is an explanatory diagram illustrating a sixth manufacturing method of the first modification of fig. 6.

Fig. 79B is an explanatory diagram illustrating a sixth manufacturing method of the first modification of fig. 6.

Fig. 79C is an explanatory diagram illustrating a sixth manufacturing method of the first modification of fig. 6.

Fig. 80A is an explanatory diagram illustrating a sixth manufacturing method of the first modification of fig. 6.

Fig. 80B is an explanatory diagram illustrating a sixth manufacturing method of the first modification of fig. 6.

Fig. 80C is an explanatory diagram illustrating a sixth manufacturing method of the first modification of fig. 6.

Fig. 81A is an explanatory diagram illustrating a first manufacturing method of the second modification of fig. 7.

Fig. 81B is an explanatory diagram illustrating a first manufacturing method of the second modification of fig. 7.

Fig. 81C is an explanatory diagram illustrating a first manufacturing method of the second modification of fig. 7.

Fig. 81D is an explanatory diagram illustrating a first manufacturing method of the second modification of fig. 7.

Fig. 82A is an explanatory diagram illustrating a first manufacturing method of the second modification of fig. 7.

Fig. 82B is an explanatory diagram illustrating a first manufacturing method of the second modification of fig. 7.

Fig. 82C is an explanatory diagram illustrating a first manufacturing method of the second modification of fig. 7.

Fig. 82D is an explanatory diagram illustrating a first manufacturing method of the second modification of fig. 7.

Fig. 83A is an explanatory diagram illustrating a second manufacturing method of the second modification of fig. 7.

Fig. 83B is an explanatory diagram illustrating a second manufacturing method of the second modification of fig. 7.

Fig. 83C is an explanatory diagram illustrating a second manufacturing method of the second modification of fig. 7.

Fig. 83D is an explanatory diagram illustrating a second manufacturing method of the second modification of fig. 7.

Fig. 84A is an explanatory diagram illustrating a second manufacturing method of the second modification of fig. 7.

Fig. 84B is an explanatory diagram illustrating a second manufacturing method of the second modification of fig. 7.

Fig. 84C is an explanatory diagram illustrating a second manufacturing method of the second modification of fig. 7.

Fig. 85A is an explanatory diagram illustrating a second manufacturing method of the second modification of fig. 7.

Fig. 85B is an explanatory diagram illustrating a second manufacturing method of the second modification of fig. 7.

Fig. 85C is an explanatory diagram illustrating a second manufacturing method of the second modification of fig. 7.

Fig. 86A is an explanatory diagram illustrating a manufacturing method of the third modification of fig. 8.

Fig. 86B is an explanatory diagram illustrating a manufacturing method of the third modification of fig. 8.

Fig. 86C is an explanatory diagram illustrating a manufacturing method of the third modification of fig. 8.

Fig. 86D is an explanatory diagram illustrating a manufacturing method of the third modification of fig. 8.

Fig. 87A is an explanatory diagram illustrating a manufacturing method of the third modification of fig. 8.

Fig. 87B is an explanatory diagram illustrating a manufacturing method of the third modification of fig. 8.

Fig. 87C is an explanatory diagram illustrating a manufacturing method of the third modification of fig. 8.

Fig. 87D is an explanatory diagram illustrating a manufacturing method of the third modification of fig. 8.

Fig. 88A is an explanatory diagram illustrating a manufacturing method of the fourth modification of fig. 9.

Fig. 88B is an explanatory diagram illustrating a manufacturing method of the fourth modification of fig. 9.

Fig. 88C is an explanatory diagram illustrating a manufacturing method of the fourth modification of fig. 9.

Fig. 88D is an explanatory diagram illustrating a manufacturing method of the fourth modification of fig. 9.

Fig. 89A is an explanatory diagram illustrating a manufacturing method of the fourth modification of fig. 9.

Fig. 89B is an explanatory diagram illustrating a manufacturing method of the fourth modification of fig. 9.

Fig. 89C is an explanatory diagram illustrating a manufacturing method of the fourth modification of fig. 9.

Fig. 89D is an explanatory diagram illustrating a manufacturing method of the fourth modification of fig. 9.

Fig. 90A is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 90B is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 90C is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 90D is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 91A is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 91B is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 91C is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 91D is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 92A is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 92B is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 92C is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 92D is an explanatory diagram illustrating a manufacturing method of the fifth modification of fig. 10.

Fig. 93A is an explanatory diagram illustrating a manufacturing method of the sixth modification of fig. 11.

Fig. 93B is an explanatory diagram illustrating a manufacturing method of the sixth modification of fig. 11.

Fig. 93C is an explanatory diagram illustrating a manufacturing method of the sixth modification of fig. 11.

Fig. 94A is an explanatory diagram illustrating a manufacturing method of the sixth modification of fig. 11.

Fig. 94B is an explanatory diagram illustrating a manufacturing method of the sixth modification of fig. 11.

Fig. 94C is an explanatory diagram illustrating a manufacturing method of the sixth modification of fig. 11.

Fig. 95A is an explanatory diagram illustrating a manufacturing method of the seventh modification of fig. 12.

Fig. 95B is an explanatory diagram illustrating a manufacturing method of the seventh modification of fig. 12.

Fig. 95C is an explanatory diagram illustrating a manufacturing method of the seventh modification of fig. 12.

Fig. 96A is an explanatory diagram illustrating a manufacturing method of the seventh modification of fig. 12.

Fig. 96B is an explanatory diagram illustrating a manufacturing method of the seventh modification of fig. 12.

Fig. 96C is an explanatory diagram illustrating a manufacturing method of the seventh modification of fig. 12.

Fig. 97A is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 97B is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 97C is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 98A is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 98B is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 98C is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 99A is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 99B is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 99C is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 100A is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 100B is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 100C is an explanatory diagram illustrating a manufacturing method of the eighth modification of fig. 13.

Fig. 101A is an explanatory diagram illustrating a manufacturing method of the ninth modification of fig. 14.

Fig. 101B is an explanatory diagram illustrating a manufacturing method of the ninth modification of fig. 14.

Fig. 101C is an explanatory diagram illustrating a manufacturing method of the ninth modification of fig. 14.

Fig. 102A is an explanatory diagram illustrating a manufacturing method of the ninth modification of fig. 14.

Fig. 102B is an explanatory diagram illustrating a manufacturing method of the ninth modification of fig. 14.

Fig. 102C is an explanatory diagram illustrating a manufacturing method of the ninth modification of fig. 14.

Fig. 102D is an explanatory diagram illustrating a manufacturing method of the ninth modification of fig. 14.

Fig. 103A is an explanatory diagram illustrating a manufacturing method of the ninth modification of fig. 14.

Fig. 103B is an explanatory diagram illustrating a manufacturing method of the ninth modification of fig. 14.

Fig. 103C is an explanatory diagram illustrating a manufacturing method of the ninth modification of fig. 14.

Fig. 104 is an explanatory diagram illustrating a detailed structure of a laminated substrate according to a tenth modification.

Fig. 105A is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 105B is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 105C is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 105D is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 105E is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 106A is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 106B is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 106C is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 106D is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 106E is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 107A is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 107B is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 107C is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 107D is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 107E is an explanatory diagram illustrating a first manufacturing method of the tenth modification of fig. 15.

Fig. 108A is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 108B is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 108C is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 108D is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 108E is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 109A is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 109B is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 109C is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 109D is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 109E is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 110A is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 110B is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 110C is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 110D is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 110E is an explanatory diagram illustrating a second manufacturing method of the tenth modification of fig. 15.

Fig. 111A is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 111B is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 111C is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 111D is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 111E is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 112A is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 112B is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 112C is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 112D is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 112E is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 113A is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 113B is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 113C is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 113D is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 113E is an explanatory diagram illustrating a manufacturing method of a solid-state imaging device having a conventional back-side illumination type structure.

Fig. 114A illustrates the overall configuration of a three-layer laminated substrate of a solid-state imaging device.

Fig. 114B illustrates the overall configuration of a three-layer laminated substrate of a solid-state imaging device.

Fig. 115A is an explanatory diagram illustrating a structure of a three-layer laminated substrate.

Fig. 115B is an explanatory diagram illustrating a structure of a three-layer laminated substrate.

Fig. 115C is an explanatory diagram illustrating a structure of a three-layer laminated substrate.

Fig. 116A is an explanatory view illustrating a structure of a three-layer laminated substrate.

Fig. 116B is an explanatory diagram illustrating a structure of a three-layer laminated substrate.

Fig. 116C is an explanatory view illustrating a structure of a three-layer laminated substrate.

Fig. 117A is an explanatory diagram illustrating a structure of a three-layer laminated substrate.

Fig. 117B is an explanatory diagram illustrating a structure of a three-layer laminated substrate.

Fig. 117C is an explanatory diagram illustrating a structure of a three-layer laminated substrate.

Fig. 118 is an explanatory view illustrating a structure of a three-layer laminated substrate.

Fig. 119 is a block diagram illustrating a configuration example of an imaging device as an electronic device according to an embodiment of the present invention.

Detailed Description

Hereinafter, embodiments for implementing the present invention (hereinafter referred to as examples) will be described. The description will be made in the following order.

1. General structure of solid-state imaging device

2. First basic structure example of solid-state imaging device

3. First to ninth modified structural examples of solid-state imaging device

4. Second basic structure example of solid-state imaging device

5. Method for producing a second basic structure

6. Method for producing a first basic structure

7. Tenth modification

8. Manufacturing method of tenth modification

9. Construction example of three-layer laminated substrate

10. Application example applied to electronic device

<1. general construction of solid-state imaging device >

< schematic drawing of appearance >

Fig. 1 is a schematic diagram illustrating an appearance of a solid-state imaging device as a semiconductor device according to an embodiment of the present invention.

The solid-state imaging device 1 shown in fig. 1 is a semiconductor package in which a laminated substrate 13 is packaged, the laminated substrate 13 being constituted by laminating a lower substrate 11 and an upper substrate 12.

A plurality of solder balls 14, which are rear electrodes electrically connected to an external substrate (not shown), are formed on the lower substrate 11.

An R (red), G (green), or B (blue) color filter 15 and an on-chip lens 16 are formed on the upper surface of the upper substrate 12. The upper substrate 12 is connected to a glass protective substrate 18 that protects the on-chip lens 16, and a glass sealing resin 17 having a cavity-free structure is provided between the upper substrate 12 and the glass protective substrate 18.

For example, as shown in fig. 2A, a pixel region 21 in which pixel portions for performing photoelectric conversion are two-dimensionally arranged and a control circuit 22 for controlling the pixel portions are formed on the upper substrate 12. A logic circuit 23 (such as a signal processing circuit that processes pixel signals output from the pixel portion) is formed on the lower substrate 11.

Alternatively, as shown in fig. 2B, a configuration may be realized in which: only the pixel region 21 is formed on the upper substrate 12, and the control circuit 22 and the logic circuit 23 are formed on the lower substrate 11.

As described above, by forming one of the logic circuits 23 or both of the control circuit 22 and the logic circuit 23 and laminating on the lower substrate 11 different from the upper substrate 12 of the pixel region 21, the size of the solid-state imaging device 1 can be miniaturized, as compared with the case where the pixel region 21, the control circuit 22, and the logic circuit 23 are arranged in the planar direction of one semiconductor substrate.

Hereinafter, in the description, the upper substrate 12 on which at least the pixel region 21 is formed is referred to as a pixel sensor substrate 12, and the lower substrate 11 on which at least the logic circuit 23 is formed is referred to as a logic substrate 11.

< example of laminated substrate construction >

Fig. 3 illustrates a circuit configuration example of the laminated substrate 13.

The laminated substrate 13 includes a pixel array unit 33 in which pixels 32 are arranged in a two-dimensional array, a vertical drive circuit 34, a column signal processing circuit 35, a horizontal drive circuit 36, an output circuit 37, a control circuit 38, and an input/output terminal 39.

The pixel 32 includes a photodiode serving as a photoelectric conversion element and a plurality of pixel transistors. A circuit configuration example of the pixel 32 will be explained below with reference to fig. 4.

The pixels 32 can also have a pixel-sharing structure. The pixel sharing structure is formed of a plurality of photodiodes, a plurality of transfer transistors, one common floating diffusion (floating diffusion region), and pixel transistors shared with each other. That is, the common pixel is configured such that the photodiode and the transfer transistor forming the plurality of unit pixels share the pixel transistor with each other.

The control circuit 38 receives an input clock and data indicating an operation mode and the like, and outputs data such as internal data of the laminated substrate 13. That is, the control circuit 38 generates a clock signal or a control signal serving as an operation reference of the vertical drive circuit 34, the column signal processing circuit 35, the horizontal drive circuit 36, and the like, in accordance with the vertical synchronization signal, the horizontal synchronization signal, and the master clock. Then, the control circuit 38 outputs the generated clock signal or control signal to the vertical drive circuit 34, the column signal processing circuit 35, the horizontal drive circuit 36, and the like.

The vertical drive circuit 34 includes, for example, a shift register, selects a predetermined pixel drive wiring 40, supplies a pulse for driving the pixels 32 to the selected pixel drive wiring 40, and drives the pixels 32 in units of rows. That is, the vertical drive circuit 34 selectively scans the pixels 32 of the pixel array unit 33 in the vertical direction in a row unit in sequence, and supplies pixel signals based on signal charges generated according to the amount of light received by the photoelectric conversion portion of each pixel 32 to the column signal processing circuit 35 via the vertical signal line 41.

The column signal processing circuit 35 is arranged at each column of the pixels 32, and performs signal processing such as noise removal for each pixel column on signals output from the pixels 32 corresponding to one row. For example, the column signal processing circuit 35 performs signal processing such as Correlated Double Sampling (CDS) and AD conversion to remove fixed pattern noise unique to the pixel.

The horizontal drive circuit 36 includes, for example, a shift register or the like, sequentially selects the column signal processing circuits 35 by sequentially outputting horizontal scan pulses, and outputs pixel signals from the respective column signal processing circuits 35 to the horizontal signal line 42.

The output circuit 37 performs signal processing on signals sequentially supplied from the column signal processing circuit 35 via the horizontal signal line 42 and outputs the processed signals. For example, the output circuit 37 performs only buffering in some cases or performs black level adjustment, column change correction, various types of digital signal processing, and the like in some cases. The input/output terminal 39 transmits a signal to the outside and receives a signal from the outside.

The laminated substrate 13 having the above-described configuration is a CMOS image sensor called a column AD type in which a column signal processing circuit 35 that performs CDS processing and AD conversion processing is arranged in each pixel column.

< example of Circuit configuration of Pixel >

Fig. 4 illustrates an equivalent circuit of the pixel 32.

The pixel 32 shown in fig. 4 has a configuration to realize an electronic global shutter function.

The pixel 32 includes a photodiode 51 as a photoelectric conversion element, a first transfer transistor 52, a memory portion (MEM)53, a second transfer transistor 54, an FD (floating diffusion region) 55, a reset transistor 56, an amplification transistor 57, a selection transistor 58, and a discharge transistor 59.

The photodiode 51 is a photoelectric conversion portion that generates and accumulates electric charges (signal charges) according to the amount of received light. The anode terminal of the photodiode 51 is grounded and the cathode terminal thereof is connected to the storage section 53 via the first transfer transistor 52. The cathode terminal of the photodiode 51 is also connected to a discharge transistor 59 for discharging unnecessary electric charges.

When the transfer signal TRX turns on the power supply, the first transfer transistor 52 reads the electric charge generated by the photodiode 51 and transfers the electric charge to the storage section 53. The storage section 53 is a charge holding section: the charge is temporarily held until the charge is transferred to the FD 55.

When the transfer signal TRG turns on the power supply, the second transfer transistor 54 reads the electric charge held in the storage section 53 and transfers the electric charge to the FD 55.

FD 55 is a charge holding part: which holds the electric charges read from the memory section 53 to read the electric charges as signals. When the reset signal RST turns on the power supply, the reset transistor 56 resets the potential of the FD 55 by discharging the electric charges held in the FD 55 to the constant voltage source VDD.

The amplification transistor 57 outputs a pixel signal according to the potential of the FD 55. That is, the amplifying transistor 57 forms a load MOS 60 serving as a constant current source and a source follower circuit. A pixel signal indicating a level according to the electric charge held in the FD 55 is output from the amplifying transistor 57 to the column signal processing circuit 35 via the selection transistor 58 (see fig. 3). For example, the load MOS 60 is arranged within the column signal processing circuit 35.

When the pixel 32 is selected by the selection signal SEL, the selection transistor 58 is turned on and outputs a pixel signal of the pixel 32 to the column signal processing circuit 35 via the vertical signal line 41.

When the discharge signal OFG turns on the power supply, the discharge transistor 59 discharges unnecessary electric charges stored in the photodiode 51 to the constant voltage source VDD.

The transfer signals TRX and TRG, the reset signal RST, the discharge signal OFG, and the selection signal SEL are supplied from the vertical drive circuit 34 via the pixel drive wiring 40.

The operation of the pixel 32 will be briefly explained.

First, when the discharge signal OFG having a high level before the start of exposure is supplied to the discharge transistor 59, the discharge transistor 59 is turned on, the electric charges accumulated in the photodiode 51 are discharged to the constant voltage source VDD and the photodiodes 51 of all the pixels are reset.

When the discharge transistor 59 is turned off by the discharge signal OFG having a low level after the reset of the photodiode 51, the exposure of all the pixels of the pixel array unit 33 starts.

When a predetermined exposure time determined in advance has elapsed, the transfer signal TRX turns on the first transfer transistor 52 in all the pixels of the pixel array unit 33, and the electric charges accumulated in the photodiode 51 are transferred to the storage section 53.

After the first transfer transistor 52 is turned off, the electric charges held in the storage section 53 of the pixel 32 are sequentially read to the column signal processing circuit 35 in units of rows. In the reading operation, the transfer signal TRG turns on the second transfer transistors 54 of the pixels 32 of the row being read, and the electric charges held in the storage sections 53 are transferred to the FD 55. Then, when the selection transistor 58 is turned on by the selection signal SEL, a signal indicating a level according to the electric charge accumulated in the FD 55 is output from the amplification transistor 57 to the column signal processing circuit 35 via the selection transistor 58.

As described above, the pixel 32 including the pixel circuit in fig. 4 is capable of performing an operation (imaging) according to the global shutter scheme (i.e., setting the same exposure time in all pixels of the pixel array unit 33, temporarily holding charges in the storage section 53 after the end of exposure, and sequentially reading the charges from the storage section 53 in units of rows).

The circuit configuration of the pixel 32 is not limited to the configuration shown in fig. 4. For example, a circuit configuration that does not include the storage section 53 and operates according to a so-called rolling shutter scheme can also be employed.

<2. first basic structure example of solid-state imaging device >

Next, a detailed configuration of the laminated substrate 13 will be described with reference to fig. 5. Fig. 5 is a sectional view of a part of the solid-state imaging device 1 enlarged.

In the logic substrate 11, the multilayer wiring layer 82 is formed on the upper side (pixel sensor substrate 12 side) of a semiconductor substrate 81 (hereinafter referred to as a silicon substrate 81) formed of, for example, silicon (Si). The multilayer wiring layer 82 forms the control circuit 22 and the logic circuit 23 in fig. 2.

The multilayer wiring layer 82 includes a plurality of wiring layers 83 and an interlayer insulating film 84 formed between the wiring layers 83, and the plurality of wiring layers 83 include an uppermost wiring layer 83a closest to the pixel sensor substrate 12, an intermediate wiring layer 83b, and a lowermost wiring layer 83c closest to the silicon substrate 81.

The plurality of wiring layers 83 are formed of, for example, copper (Cu), aluminum (Al), or tungsten (W), and the interlayer insulating film 84 is formed of, for example, a silicon oxide film or a silicon nitride film. In the plurality of wiring layers 83 and the interlayer insulating films 84, the same material may be used for all wiring layers or all interlayer insulating films or two or more materials may be used.

At a predetermined position of the Silicon substrate 81, a Through-Silicon Via 85 penetrating the Silicon substrate 81 and a Through-Silicon Via (TSV: Through Silicon Via) formed by fitting a connection conductor 87 on an inner wall of the Through-Silicon Via 85 are formedThrough-silicon via) 88, and an insulating film 86 is formed between the through-silicon via 85 and the through-silicon via electrode 88. The insulating film 86 can be made of, for example, SiO₂The film or the SiN film is formed.

The insulating film 86 and the connection conductor 87 are formed along the inner wall surface of the through-silicon via electrode 88 shown in fig. 5 so that the inside of the through-silicon via 85 is hollow. However, the entire inside of the through-silicon via 85 is embedded to the connection conductor 87 according to the inner diameter. In other words, the inside of the through hole may be embedded with a conductor or a part of the inside of the through hole may be hollow. The same applies to a Through Chip Via (TCV) 105 and the like which will be described below.

The connection conductor 87 of the through-silicon electrode 88 is connected to the re-wiring 90 formed on the lower surface side of the silicon substrate 81, and the re-wiring 90 is connected to the solder ball 14. The connection conductor 87 and the rewiring 90 can be formed of, for example, copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium tungsten alloy (TiW), or polysilicon.

On the lower surface side of the silicon substrate 81, a solder mask (solder resist) 91 is formed to cover the rewiring 90 and the insulating film 86 except for the region where the solder ball 14 is formed.

On the other hand, in the pixel sensor substrate 12, the multilayer wiring layer 102 is formed on the lower side (logic substrate 11 side) of a semiconductor substrate 101 (hereinafter referred to as a silicon substrate 101) formed of silicon (Si). The multilayer wiring layer 102 forms a pixel circuit of the pixel region 21 in fig. 2.

The multilayer wiring layer 102 includes a plurality of wiring layers 103 and an interlayer insulating film 104 formed between the wiring layers 103, and the wiring layers 103 include an uppermost wiring layer 103a closest to the silicon substrate 101, an intermediate wiring layer 103b, and a lowermost wiring layer 103c closest to the logic substrate 11.

The same material as that of the wiring layer 83 and the interlayer insulating film 84 described above can be used as the material used for the plurality of wiring layers 103 and the interlayer insulating film 104. One material or two or more materials may be used to form the plurality of wiring layers 103 or the interlayer insulating films 104, which are the same as the wiring layers 83 and the interlayer insulating films 84 described above.

In the example of fig. 5, the multilayer wiring layer 102 of the pixel sensor substrate 12 includes three wiring layers 103 and the multilayer wiring layer 82 of the logic substrate 11 includes four wiring layers 83. However, the number of wiring layers is not limited thereto. Any number of layers can be formed.

In the silicon substrate 101, the photodiode 51 formed of a PN junction is formed in each pixel 32.

Although not shown, a plurality of pixel transistors (such as the first transfer transistor 52 and the second transfer transistor 54) or a memory portion (MEM)53 and the like are formed in the multilayered wiring layer 102 and the silicon substrate 101.

A through-silicon via electrode 109 connected to the wiring layer 103a of the pixel sensor substrate 12 and a through-chip via electrode 105 connected to the wiring layer 83a of the logic substrate 11 are formed at a predetermined position of the silicon substrate 101 where the color filter 15 and the on-chip lens 16 are not formed.

The through-chip electrodes 105 and the through-silicon via electrodes 109 are connected to connection wirings 106 formed on the upper surface of the silicon substrate 101. An insulating film 107 is formed between the silicon substrate 101 and the through-silicon via electrode 109 and between the silicon substrate 101 and the through-chip via electrode 105. The color filter 15 or the on-chip lens 16 is formed on the upper surface of the silicon substrate 101, and an insulating film (planarizing film) 108 is provided between the color filter 15 or the on-chip lens 16 and the upper surface of the silicon substrate 101.

As described above, the laminated substrate 13 of the solid-state imaging device 1 shown in fig. 1 has a laminated structure in which: wherein the multilayer wiring layer 82 side of the logic substrate 11 and the multilayer wiring layer 102 side of the pixel sensor substrate 12 are bonded to each other. In fig. 5, the adhesion surface between the multilayer wiring layer 82 of the logic substrate 11 and the multilayer wiring layer 102 of the pixel sensor substrate 12 is indicated by a broken line.

In the laminated substrate 13 of the solid-state imaging device 1, the wiring layer 103 of the pixel sensor substrate 12 and the wiring layer 83 of the logic substrate 11 are connected by two through-silicon electrodes (i.e., the through-silicon electrode 109 and the through-chip electrode 105), and the wiring layer 83 of the logic substrate 11 and the solder ball (back electrode) 14 are connected by the through-silicon electrode 88 and the rewiring 90. Therefore, the planar area of the solid-state imaging device 1 can be reduced to the minimum.

The laminate substrate 13 and the glass protective substrate 18 are bonded to each other by the glass sealing resin 17 to thereby form a cavity-less structure, and therefore the height of the solid-state imaging device can also be reduced.

Therefore, the solid-state imaging device 1 shown in fig. 1, i.e., a further miniaturized semiconductor device (semiconductor package) can be realized.

<3. first to ninth modified structure examples of solid-state imaging device >

Next, other examples of the internal structure of the laminated substrate 13 of the solid-state imaging device 1 will be explained with reference to fig. 6 to 14.

In fig. 6 to 14, portions corresponding to those in the structure shown in fig. 5 are denoted by the same reference numerals, and their description will be omitted as appropriate. A part different from the part in the structure shown in fig. 5 will be described by comparison with the above-described structure. Hereinafter, the structure shown in fig. 5 is referred to as a basic structure. In fig. 6 to 14, for example, a part of the structure shown in fig. 5, such as the insulating film 86, the insulating film 107, the insulating film 108, and the like, is not illustrated in some cases for simplifying the explanation.

< first modification >

Fig. 6 illustrates a laminated substrate 13 of the solid-state imaging device 1 according to the first modification.

In the basic structure of fig. 5, the logic substrate 11 and the pixel sensor substrate 12 are connected on the upper side of the pixel sensor substrate 12 side using two through-electrodes (i.e., the through-silicon via electrode 109 and the through-chip via electrode 105).

In contrast, in the first modification of fig. 6, the logic substrate 11 and the pixel sensor substrate 12 are connected on the lower logic substrate 11 side using two through-electrodes (i.e., the silicon through-electrode 151 and the chip through-electrode 152).

More specifically, a silicon through-electrode 151 connected to the wiring layer 83c of the logic substrate 11 and a chip through-electrode 152 connected to the wiring layer 103c of the pixel sensor substrate 12 are formed at a predetermined position of the silicon substrate 81 on the logic substrate 11 side. The through-silicon via electrodes 151 and the chip via electrodes 152 (not shown) are insulated from the substrate 81 by an insulating film.

The through-silicon via electrodes 151 and the chip via electrodes 152 are connected to connection wirings 153 formed on the lower surface of the silicon substrate 81. The connection wiring 153 is also connected to the rewiring 154 connected to the solder ball 14.

In the first modification described above, since the stacked structure of the logic substrate 11 and the pixel sensor substrate 12 is adopted, the package size of the solid-state imaging device 1 can be miniaturized.

In the first modification, the connection wiring 153 that electrically connects the logic substrate 11 with the pixel sensor substrate 12 is formed not on the upper side of the silicon substrate 101 of the pixel sensor substrate 12 but on the lower side of the silicon substrate 81 of the logic substrate 11. Therefore, since the space (thickness) having the cavity-less structure between the glass protective substrate 18 and the laminated substrate 13 can be minimized, a low backside of the solid-state imaging device 1 can be realized.

< second modification >

Fig. 7 illustrates a laminated substrate 13 of the solid-state imaging device 1 according to a second modification.

In the second modification, the logic substrate 11 and the pixel sensor substrate 12 are connected by metal bonding of the wiring layer.

More specifically, the uppermost wiring layer 83a in the multilayer wiring layer 82 of the logic substrate 11 and the lowermost wiring layer 103c in the multilayer wiring layer 102 of the pixel sensor substrate 12 are connected by metal bonding. For example, copper (Cu) is suitable for the material of the wiring layer 83a and the wiring layer 103 c. In the example of fig. 7, the wiring layer 83a and the wiring layer 103c are formed only in a part of the bonding surface of the logic substrate 11 and the pixel sensor substrate 12. However, a metal (copper) layer may be formed on the entire surface of the bonding surface as a bonding wiring layer.

In fig. 7, the schematic diagram is simply illustrated for comparison with fig. 5. However, as with the basic structure of fig. 5, the wiring layer 83 and the solder ball 14 in the logic substrate 11 are connected by the through-silicon via electrode 88 and the rewiring 90.

< third modification >

Fig. 8 illustrates a laminated substrate 13 of the solid-state imaging device 1 according to a third modification.

In the third modification, the connection method of the logic substrate 11 and the pixel sensor substrate 12 is the same as that in the first modification illustrated in fig. 6. That is, the logic substrate 11 and the pixel sensor substrate 12 are connected by the through-silicon via electrode 151, the through-chip via electrode 152, and the connection wiring 153.

The third modification differs from the first modification in that: a connection conductor 171 is formed in the depth direction between the rewiring 154 connected to the solder ball 14 and the connection wiring 153 connecting the through-silicon via electrode 151 and the through-chip via electrode 152. The linking conductor 171 connects the linking wiring 153 to the rewiring 154.

< fourth modification >

Fig. 9 illustrates a laminated substrate 13 of the solid-state imaging device 1 according to a fourth modification.

In the fourth modification, the connection method of the logic substrate 11 and the pixel sensor substrate 12 is the same as that in the basic structure shown in fig. 5. That is, the logic substrate 11 and the pixel sensor substrate 12 are connected to the upper side of the pixel sensor substrate 12 by using the connection wiring 106 and the two through-electrodes (i.e., the through-silicon electrode 109 and the through-chip electrode 105).

The solder balls 14 on the lower side of the solid-state imaging device 1 are connected to the plurality of wiring layers 83 of the logic substrate 11 and the plurality of wiring layers 103 of the pixel sensor substrate 12 via through-chip electrodes 181 penetrating the logic substrate 11 and the pixel sensor substrate 12.

More specifically, the chip through-electrode 181 penetrating the logic substrate 11 and the pixel sensor substrate 12 is formed at a predetermined position of the laminate substrate 13. The chip through-electrode 181 is connected to the wiring layer 103 of the pixel sensor substrate 12 via a connection wiring 182, and the connection wiring 182 is formed on the upper surface of the silicon substrate 101 of the pixel sensor substrate 12. Further, the through-chip electrodes 181 are also connected to the rewirings 183 formed on the lower surface of the silicon substrate 81 of the lower logic substrate 11, and are thus connected to the solder balls 14 via the rewirings 183.

< fifth modification >

Fig. 10 illustrates a laminated substrate 13 of a solid-state imaging device 1 according to a fifth modification.

In the fifth modification of fig. 10, the connection method of the logic substrate 11 and the pixel sensor substrate 12 and the connection method of the underside of the solid-state imaging device 1 and the solder ball 14 are the same as those in the fourth modification described in fig. 9.

However, in the fifth modification, the structure of the lower side of the silicon substrate 81 of the logic substrate 11 is different from that of the fourth modification of fig. 9.

Specifically, in the fourth modification illustrated in fig. 9, the lower surface of the silicon substrate 81 of the logic substrate 11 is covered with an insulating film 86, and then a solder mask (solder resist) 91 is formed.

However, in the fifth modification of fig. 10, the lower surface of the silicon substrate 81 of the logic substrate 11 is covered with only the thick insulating film 86. The insulating film 86 can include SiO formed by, for example, a plasma Chemical Vapor Deposition (CVD) method₂Films and SiN films.

< sixth modification >

Fig. 11 illustrates a laminated substrate 13 of the solid-state imaging device 1 according to a sixth modification.

In the sixth modification of fig. 11, the connection method of the solder ball 14 is the same as that in the fourth modification (fig. 9) and the fifth modification (fig. 10) described above. That is, the solder balls 14 are connected to the wiring layer 83 of the logic substrate 11 and the wiring layer 103 of the pixel sensor substrate 12 by penetrating the chip through electrodes 181 of the logic substrate 11 and the pixel sensor substrate 12.

However, in the sixth modification, the connection method of the logic substrate 11 and the pixel sensor substrate 12 is different from those in the fourth modification (fig. 9) and the fifth modification (fig. 10).

Specifically, in the sixth modification, one chip through electrode 191 is formed from the connection wiring 192 formed on the upper side of the silicon substrate 101 of the pixel sensor substrate 12 to the wiring layer 83a of the logic substrate 11 so as to penetrate the pixel sensor substrate 12. The chip through electrode 191 is also connected to the wiring layer 103b of the pixel sensor substrate 12.

Therefore, in the sixth modification, one chip through electrode 191 is configured to share the connection with the wiring layer 83 of the logic substrate 11 and the connection with the wiring layer 103 of the pixel sensor substrate 12.

< seventh modification >

Fig. 12 illustrates a laminated substrate 13 of the solid-state imaging device 1 according to a seventh modification.

In the seventh modification of fig. 12, the connection method of the solder ball 14 located on the lower side of the solid-state imaging device 1 is the same as that in the fourth to sixth modifications (fig. 9 to 11). That is, the solder ball 14 on the lower side of the solid-state imaging device 1 is connected to the wiring layer 83 of the logic substrate 11 and the wiring layer 103 of the pixel sensor substrate 12 via the through-chip electrode 181 penetrating the logic substrate 11 and the pixel sensor substrate 12.

However, in the seventh modification, the connection method of the logic substrate 11 and the pixel sensor substrate 12 is different from that in the fourth to sixth modifications (fig. 9 to 11).

More specifically, in the seventh modification, the uppermost wiring layer 83a of the logic substrate 11 and the lowermost wiring layer 103c of the pixel sensor substrate 12 are connected by metal bonding. For example, copper (Cu) is used as a material of the wiring layer 83a and the wiring layer 103 c. In the example of fig. 12, the wiring layer 83a and the wiring layer 103c are formed only in a part of the bonding surface of the logic substrate 11 and the pixel sensor substrate 12. However, a metal (copper) layer may be formed on the entire surface of the bonding surface as a bonding wiring layer.

< eighth modification >

Fig. 13 illustrates a laminated substrate 13 of the solid-state imaging device 1 according to an eighth modification.

In the eighth modification, compared with the basic structure of fig. 5, the insulating film 201 formed on the lower surface of the silicon substrate 81 of the logic substrate 11 is different.

In the eighth modification, an inorganic film formed at a high temperature equal to or more than 250 degrees and equal to or less than 400 degrees that does not affect the wiring layer 83 and the like is formed as the insulating film 201 on the lower surface of the silicon substrate 81 of the logic substrate 11. For example, plasma TEOS film, plasma SiN film, plasma SiO₂Film, CVD-SiN film or CVD-SiO₂The membrane canFormed as an insulating film 201.

For example, when the insulating film 201 is formed using an organic material and a low-temperature insulating film is used, there is a problem in that: reliability degradation due to poor moisture resistance, corrosion, or ion migration may occur. However, the inorganic film has good moisture resistance. Therefore, in the structure of the eighth modification, wiring reliability can be improved by employing an inorganic film formed as the insulating film 201 at a temperature equal to or less than 400 degrees.

< ninth modification >

Fig. 14 illustrates a laminated substrate 13 of the solid-state imaging device 1 according to a ninth modification.

In the ninth modification of fig. 14, the connection method of the logic substrate 11 and the pixel sensor substrate 12 is different from that in the basic structure of fig. 5.

That is, in the basic structure of fig. 5, the logic substrate 11 and the pixel sensor substrate 12 are connected by two through electrodes (i.e., the through silicon electrode 151 and the through chip electrode 152). However, in the ninth modification, the uppermost wiring layer 83a in the multilayer-type wiring layer 82 of the logic substrate 11 and the lowermost wiring layer 103c in the multilayer-type wiring layer 102 of the pixel sensor substrate 12 are connected by metal bonding (Cu — Cu bonding).

In the ninth modification, the connection method of the solder balls 14 on the lower side of the solid-state imaging device 1 is the same as that in the basic structure of fig. 5. That is, by connecting the through-silicon via electrode 88 to the lowermost wiring layer 83c of the logic substrate 11, the solder balls 14 are connected to the wiring layer 83 and the wiring layer 103 in the laminate substrate 13.

However, the structure in the ninth modification differs from the basic structure of fig. 5 in that: on the lower surface side of the silicon substrate 81, dummy wirings 211 which are not electrically connected to any portion are formed of the same wiring material as the rewiring 90 in the same layer as the rewiring 90 connected to the solder ball 14.

The dummy wiring 211 is formed to reduce the influence of unevenness when the uppermost wiring layer 83a on the logic substrate 11 side and the lowermost wiring layer 103c on the pixel sensor substrate 12 side are connected by metal bonding (Cu — Cu bonding). That is, when the re-wiring 90 is formed only in a partial area of the lower surface of the silicon substrate 81 at the time of Cu-Cu bonding, unevenness is caused by a difference in thickness due to the presence or absence of the re-wiring 90. Therefore, by providing the dummy wirings 211, the influence of unevenness can be reduced.

<4. second basic structure example of solid-state imaging device >

In the basic structure and the modification of the solid-state imaging device 1 described above, the laminated substrate 13 has a laminated structure of: wherein the multilayer wiring layer 82 side of the logic substrate 11 and the multilayer wiring layer 102 side of the pixel sensor substrate 12 are bonded so as to face each other. In this specification, a structure in which wiring layers of two substrates face each other is referred to as a face-to-face (face-to-face) structure.

Next, as another configuration example of the solid-state imaging device 1, a stacked structure will be described below: the surface of the logic substrate 11 opposite to the multilayer wiring layer 82 side is bonded to the multilayer wiring layer 102 side of the pixel sensor substrate 12, thereby forming the laminate substrate 13. In this specification, a structure in which the wiring layer side of one substrate is joined to the surface of the other substrate opposite to the wiring layer side is referred to as a face-to-back (face-to-back) structure.

Fig. 15 is a cross-sectional view of a part of the solid-state imaging device 1 of fig. 5 enlarged when the solid-state imaging device 1 is configured to have a face-to-back structure.

Basically, the difference between the back-to-back configuration shown in fig. 15 and the face-to-face configuration shown in fig. 5 is that: the multilayer wiring layer 82 side of the logic substrate 11 is bonded to the multilayer wiring layer 102 side of the pixel sensor substrate 12, or is not bonded to the multilayer wiring layer 82 but is bonded to the opposite side of the multilayer wiring layer 82.

Therefore, in fig. 15, portions corresponding to those in fig. 5 are denoted by the same reference numerals, and detailed configurations will not be described again but will be described only roughly.

In the solid-state imaging device 1 of fig. 15, the interlayer insulating film 104 of the multilayer wiring layer 102 of the pixel sensor substrate 12 and the insulating film 86 of the logic substrate 11 are bonded to each other. In fig. 15, the adhesion surface between the insulating film 86 of the logic substrate 11 and the multilayer wiring layer 102 of the pixel sensor substrate 12 is indicated by a broken line.

In the logic substrate 11, the multilayer wiring layer 82 is formed on the side (lower side in the figure) opposite to the surface on which the insulating film 86 of the silicon substrate 81 is formed, and is formed with, for example, a rewiring 90 (formed of copper (Cu)), solder balls 14, and a solder mask (solder resist) 91.

On the other hand, in the pixel sensor substrate 12, the multilayer wiring layer 102 is formed on the lower side (logic substrate 11 side) of the silicon substrate 101 in the drawing, and the color filter 15, the on-chip lens 16, and the like are formed on the upper side of the silicon substrate 101, which is the opposite side of the surface on which the multilayer wiring layer 102 is formed.

In the silicon substrate 101, a photodiode 51 is formed in each pixel.

The wiring layer 103 of the pixel sensor substrate 12 and the wiring layer 83 of the logic substrate 11 are connected by two through electrodes (i.e., the silicon through electrode 109 and the chip through electrode 105).

Fig. 15 differs from fig. 5 in that: a high-dielectric film 401 that suppresses dark current is illustrated on the upper surface of the silicon substrate 101, and a cap film 402 formed of a nitride film (SiN) or the like is illustrated on the upper surface of the connection wiring 106 that connects the chip through-electrode 105 to the silicon through-electrode 109. Even in the face-to-face structure of fig. 5, the high dielectric film 401 and the cap film 402 can be formed in this way. Alternatively, in the face-to-back structure of fig. 15, the upper dielectric film 401 and the cap film 402 may be omitted as in the face-to-face structure of fig. 5.

In the laminated substrate 13 of the solid-state imaging device 1, the wiring layer 103 of the pixel sensor substrate 12 and the wiring layer 83 of the logic substrate 11 are connected by two through electrodes (i.e., the through-silicon electrode 109 and the through-chip electrode 105) and a connection wire 106 connecting the two through electrodes to each other. The wiring layer 83 of the logic substrate 11 and the solder ball (back electrode) 14 are connected by the rewiring 90. Therefore, the planar area of the solid-state imaging device 1 can be reduced to the minimum.

The laminate substrate 13 and the glass protective substrate 18 are bonded to each other by the glass sealing resin 17 to thereby form a cavity-less structure, and therefore the height of the solid-state imaging device can also be reduced.

Therefore, the solid-state imaging device 1 having the face-to-back structure, i.e., a further miniaturized semiconductor device (semiconductor package) can be realized.

<5. method for producing second basic Structure >

< first manufacturing method of solid-state imaging device of FIG. 15 >

Next, a first manufacturing method of the solid-state imaging device 1 having the face-to-back structure shown in fig. 15 will be described with reference to fig. 16 to 30.

First, the semi-finished logic substrate 11 and the semi-finished pixel sensor substrate 12 are manufactured separately.

In the logic substrate 11, a multilayer wiring layer 82 to be the control circuit 22 or the logic circuit 23 is formed in a region to be each chip section of a silicon substrate (silicon wafer) 81. At this time, the silicon substrate 81 is not yet thinned and has a thickness of, for example, about 600 μm.

On the other hand, in the pixel sensor substrate 12, the photodiode 51 and the source/drain regions of the pixel transistors of each pixel 32 are formed in a region of the silicon substrate (silicon wafer) 101 to be each chip section. A multilayer wiring layer 102 forming a part of the control circuit 22 and the like is formed on the surface of the silicon substrate 101 where the source/drain regions of the pixel transistors are formed.

Thereafter, as shown in fig. 16, a temporary bonding substrate (silicon substrate) 411 as a support substrate is stuck to the multilayer wiring layer 82 side of the semi-finished logic substrate 11.

Examples of the pasting include plasma bonding and adhesive bonding. In the present embodiment, it is assumed that plasma bonding is performed. In the case of plasma bonding, the logic substrate 11 and the temporary bonding substrate 411 are bonded by: a plasma TEOS film, a plasma SiN film, a SiON film (barrier film), a SiC film, or the like is formed on the bonding surface of the logic substrate 11 and the temporary bonding substrate 411, plasma treatment is performed on the bonding surface, and the two substrates are stacked and then annealing treatment is performed.

As shown in fig. 17, after thinning the silicon substrate 81 of the logic substrate 11 to a degree having a thickness that does not affect the device characteristics (for example, to a degree of about 20 micrometers to about 100 micrometers), an insulating film 86 for insulating from the silicon substrate 81 is formed on the surface of the silicon substrate 81 by a plasma CVD method.

Here, as shown in fig. 18, in order to avoid the influence of hot electrons caused by heating of the logic substrate 11, a light shielding film 416 formed of a metal such as tantalum (Ta), copper (Cu), or titanium (Ti) may be formed on the insulating film 86 and a SiO light shielding film 416 may be formed on the light shielding film 416₂Etc. is formed on the protective film 417. The region on the surface of the silicon substrate 81 where the light shielding film 416 is not formed is a region where the through-silicon via electrode 109 and the through-chip via electrode 105 are to be formed. After the protective film 417 is formed by a plasma CVD method or the like, it is necessary to planarize it by a Chemical Mechanical Polishing (CMP) method.

A description will be made without forming the light shielding film 416 and the protective film 417. As shown in fig. 19, the insulating film 86 of the logic substrate 11 and the multilayer wiring layer 102 of the partially fabricated semi-finished pixel sensor substrate 12 are pasted so as to face each other. Fig. 20 illustrates the attached state, and the attachment surface is indicated by a dotted line. Examples of the pasting include plasma bonding and adhesive bonding. In the present embodiment, it is assumed that plasma bonding is performed. In the case of plasma bonding, the logic substrate 11 and the pixel sensor substrate 12 are bonded by: a plasma TEOS film, a plasma SiN film, a SiON film (barrier film), a SiC film, or the like is formed on the bonding surface of the logic substrate 11 and the pixel sensor substrate 12, plasma treatment is performed on the bonding surface, and the two substrates are stacked and then annealing treatment is performed.

After the logic substrate 11 and the pixel sensor substrate 12 are pasted to each other, as shown in fig. 21, the silicon substrate 101 of the pixel sensor substrate 12 is thinned to the extent of about 1 micrometer to about 10 micrometers. A high dielectric film 401 and an insulating film 108 serving as a sacrificial layer are formed. For example, SiO can be used₂A film or the like is used as the insulating film 108.

As shown in fig. 22, a resist 412 is applied on the insulating film 108, the resist 412 is patterned in accordance with the region where the through-silicon via electrode 109 and the through-silicon via electrode 105 are formed, and openings 413 and 414 corresponding to the through-silicon via electrode 105 and the through-silicon via electrode 109 are formed. After the openings 413 and 414 are formed, the resist 412 is stripped.

Thereafter, as shown in fig. 23, after the insulating film 107 is formed on the inner walls of the openings 413 and 414 by the plasma CVD method, the insulating film 107 at the bottoms of the openings 413 and 414 is removed by the etch-back method. Therefore, the wiring layer 83a of the logic substrate 11 is exposed in the opening 413 and the wiring layer 103a of the pixel sensor substrate 12 is exposed in the opening 414. A part of the insulating film 108 between the opening 413 and the opening 414 is also removed in the etch-back process.

As shown in fig. 24, copper (Cu) is inserted between the openings 413 and 414, thereby forming the through-chip electrodes 105, the through-silicon via electrodes 109, and the connection wires 106 connecting the through-chip electrodes 105 and the through-silicon via electrodes 109. As the copper (Cu) embedding method, for example, the following method can be adopted. First, if necessary, a barrier metal film for electric field plating and a Cu seed layer are formed by a sputtering method and the Cu seed layer is strengthened by an electroless plating method or the like. Thereafter, after the openings are filled with copper by using a plating method, excess copper is removed by a CMP method to form the chip through-electrode 105, the through-silicon-via-electrode 109, and the connection wiring 106. As a material of the barrier metal film, for example, tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), a nitride film thereof, or a carbide film thereof can be used. In this embodiment, a titanium film is used as the barrier metal film.

As shown in fig. 25, a cap film 402 formed of a nitride film (SiN) or the like is formed on the surfaces of the connection wiring 106 and the insulating film 108, and then the cap film 402 is covered with the insulating film 108.

Thereafter, as shown in fig. 26, a cavity 415 is formed by etching the cover film 402 and the insulating film 108 in the pixel region 21 where the photodiode 51 is formed.

As shown in fig. 27, a color filter 15 and an on-chip lens 16 are formed in the formed cavity 415.

Next, as shown in fig. 28, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is connected to the cavity-less structure. After the glass protective substrate 18 is attached, the temporary bonding substrate 411 is separated (peeled).

Next, as shown in fig. 29, the logic substrate 11 and the pixel sensor substrate 12 are turned upside down so that the glass protective substrate 18 is used as a supporting substrate, a part of the wiring layer 83c closest to the outside of the logic substrate 11 is exposed and a rewiring 90 is formed by a semi-additive method.

Thereafter, as shown in fig. 30, after the solder mask 91 is formed to protect the re-wiring 90, only the solder mask 91 in the region where the solder ball 14 is to be mounted is removed, and then the solder ball 14 is formed by a solder ball mounting method or the like.

The solid-state imaging device 1 in fig. 15 can be manufactured by the manufacturing method described above.

< second manufacturing method of solid-state imaging device of FIG. 15 >

Next, a second manufacturing method of the solid-state imaging device 1 having the face-to-back structure shown in fig. 15 will be described with reference to fig. 31 to 43.

First, as shown in fig. 31, a semi-finished logic substrate 11 is manufactured in which a multilayer wiring layer 82 to be a control circuit 22 or a logic circuit 23 is formed in a region to be each chip section of a silicon substrate 81. At this time, the silicon substrate 81 has not yet been thinned and has a thickness of, for example, about 600 μm.

As shown in fig. 32, the rewiring 90 connected to the uppermost wiring layer 83c of the multilayer wiring layer 82 is formed by a damascene method using, for example, Cu as a wiring material. A cap film 421 using a nitride film (SiN) or the like is formed on the upper surfaces of the formed rewiring 90 and the interlayer insulating film 84, and then, for example, SiO is used₂The cap film 421 is covered with the insulating film 422. In fig. 15, the cap film 421 and the insulating film 422 are not illustrated. The cap film 421 and the insulating film 422 can be formed by, for example, a plasma CVD method.

Thereafter, as shown in fig. 33, a temporary bonding substrate (silicon substrate) 423 as a support substrate is stuck to the multilayer wiring layer 82 side of the logic substrate 11 by plasma bonding or adhesive bonding.

As shown in fig. 34, after thinning the silicon substrate 81 of the logic substrate 11 to such an extent as to have a thickness that does not affect the device characteristics (for example, to such an extent as to be about 20 micrometers to about 100 micrometers), an insulating film 86 for insulating from the silicon substrate 81 is formed on the surface of the silicon substrate 81 by a plasma CVD method or the like. The manufacturing method is the same as the first manufacturing method described above in that: a light shielding film 416 and a protective film 417 may be formed on the upper surface of the insulating film 86 to avoid the influence of hot electrons (refer to fig. 18).

As shown in fig. 35, the multilayered wiring layer 102 side of the separately manufactured semi-finished pixel sensor substrate 12 is pasted to the thinned logic substrate 11.

After the logic substrate 11 and the pixel sensor substrate 12 are pasted to each other, as shown in fig. 36, the silicon substrate 101 of the pixel sensor substrate 12 is thinned to the extent of about 1 micrometer to about 10 micrometers. A high dielectric film 401 and an insulating film 108 serving as a sacrificial layer are formed. For example, SiO can be used₂A film or the like is used as the insulating film 108.

Thereafter, the chip through-hole electrodes 105, the through-silicon-via electrodes 109, the connection wires 106 connecting the chip through-hole electrodes 105 and the through-silicon-via electrodes 109, and the color filters 15 and the on-chip lenses 16 are formed by the method described with reference to fig. 22 to 27 in the first manufacturing method described above. Then, as shown in fig. 37, the glass protective substrate 18 is attached via the glass sealing resin 17, and then the temporary bonding substrate 423 is separated.

As shown in fig. 38, the logic substrate 11 and the pixel sensor substrate 12 are turned upside down. As shown in fig. 39, the glass protective substrate 18 is used as a support substrate to expose a part of the rewiring 90, and the solder ball 14 is formed by a solder ball mounting method or the like. The upper surface of the insulating film 422 except for the region where the solder ball 14 is mounted is covered with a solder mask 91.

< first modification of solder ball mounting portion >

Fig. 40 illustrates a first modification of the solder ball mounting portion as an area where the solder ball 14 is mounted.

In the first modification, as shown in fig. 40, a pad 431 is formed on the rewiring 90 from the same material (e.g., Cu) as the rewiring 90. Then, the solder ball 14 is attached to the pad 431.

The upper surface of the pad 431 other than the solder ball 14 is covered with a cover film 441 and an insulating film 442. Therefore, a 4-layer structure of the cap film 421, the insulating film 422, the cap film 441, and the insulating film 442 is formed on the upper surface of the rewiring 90.

When the solder ball mounting portion has the structure shown in fig. 40, the pad 431, the cover film 441, and the insulating film 442 may be further formed as shown in fig. 41, in addition to the manufacturing steps of the rewiring 90, the cover film 421, and the insulating film 422 described with reference to fig. 32. The remaining manufacturing method is the same as the second manufacturing method described above.

< second modification of solder ball mounting portion >

Fig. 42 illustrates a second modification of the solder ball mounting portion.

In the second modification, as shown in fig. 42, the rewiring 90 and the pad 431 are not directly connected as in the first modification but connected through a via (connection conductor) 443. A 4-layer structure of a cap film 421, an insulating film 422, a cap film 441, and an insulating film 442 is formed on the upper surface of the rewiring 90.

Therefore, since wiring is easy by forming a plurality of layers using the via 443, an advantage in layout can be obtained.

When the solder ball mounting portion has the structure shown in fig. 42, the pad 431, the via 443, and the cover film 441 and the insulating film 442 may be formed as shown in fig. 43 in addition to the manufacturing process of the rewiring 90, the cover film 421, and the insulating film 422 described with reference to fig. 32. The remaining manufacturing method is the same as the second manufacturing method described above.

< third manufacturing method of solid-state imaging device of FIG. 15 >

Next, a third manufacturing method of the solid-state imaging device 1 having the face-to-back structure shown in fig. 15 will be described with reference to fig. 44 to 49.

First, as shown in fig. 44, a semi-finished logic substrate 11 is manufactured in which a multilayer wiring layer 82 to be a control circuit 22 or a logic circuit 23 is formed in a region to be each chip section of a silicon substrate 81. At this time, the silicon substrate 81 has not yet been thinned and has a thickness of, for example, about 600 μm.

As shown in fig. 45, the rewiring 90 connected to the uppermost wiring layer 83c of the multilayer wiring layer 82 is formed by a damascene method using, for example, Cu as a wiring material. A cap film 421 using a nitride film (SiN) or the like is formed on the upper surface of the formed rewiring 90 and the interlayer insulating film 84, and then, for example, SiO is used₂The cap film 421 is covered with the insulating film 422.

These steps are the same as those of the second manufacturing method described above.

Next, as shown in fig. 46, a solder mask 91 is formed, and an opening 451 is formed by etching the solder mask 91, the cap film 421, and the insulating film 422 in a region where the solder ball 14 is to be mounted. The opening 451 may be formed by coating a photoresist in a region where the solder ball 14 is to be mounted and performing dry etching.

Then, as shown in fig. 47, the solder ball 14 is formed in the opening 451 by, for example, a solder ball mounting method.

Next, as shown in fig. 48 and 49, the solder ball 14 side of the logic substrate 11 and a temporary bonding substrate (silicon substrate) 453 are pasted together using an adhesive 452 having a thickness capable of burying the solder ball 14.

The manufacturing process after bonding the logic substrate 11 and the temporary bonding substrate 453 using the adhesive 452 is the same as the manufacturing process of the second manufacturing method described above, and therefore, a description thereof will be omitted.

< modification of rewiring >

Regarding the thickness of the re-wiring 90 connected to the solder ball 14 or the wiring layer with the pad 431, it is necessary to ensure that the remaining thickness does not react with copper because tin in the solder and copper in the metal wiring react with each other and form an intermetallic compound (IMC) during soldering.

Alternatively, as shown in fig. 50, a barrier metal 461 can be formed outside the rewiring 90. Therefore, even when all the copper of the rewiring 90 reacts, the reaction can be stopped by the barrier metal 461. As a material of the barrier metal 461, Ta, TaN, Ti, Co (cobalt), Cr (chromium), or the like can be used. When Ta or TaN is used as the material of the barrier metal 461, the thickness of the barrier metal 461 can be set to about 30 nm. On the other hand, when Ti is used as the material of the barrier metal 461, the thickness of the barrier metal 461 can be set to about 200 nm. The barrier metal 461 may have a stacked structure of Ta (lower layer)/Ti (upper layer) or TaN/Ta/Ti.

Fig. 51A to 51C illustrate the post-reaction state in which an intermetallic compound (IMC) is formed in the re-wiring 90 when soldering is performed using Ta or TaN as the barrier metal 461. The barrier metal 461A in fig. 51A to 51C indicates a barrier metal 461 formed using Ta or TaN.

Fig. 51A illustrates such a state: only the upper portion of the rewiring 90 near the solder ball 14 is converted into imc (cusn) 462.

Fig. 51B illustrates such a state: the re-wiring 90 is formed thinner than that in fig. 51A, all Cu of the re-wiring 90 becomes IMC 462 and the reaction is terminated by the barrier metal 461A.

Fig. 51C illustrates such a state: the re-wiring 90 is formed thinner than that of fig. 51A, all Cu of the re-wiring 90 becomes IMC 462 and the reaction is terminated by the barrier metal 461A. In fig. 51C, the IMC 462 is diffused into the interior of the solder ball 14.

Fig. 52A to 52D illustrate a post-reaction state in which an intermetallic compound (IMC) is formed in the rewiring 90 when soldering is performed using Ti as the barrier metal 461. The barrier metal 461B in fig. 52A to 52D represents a barrier metal 461 formed using Ti.

As with fig. 51A, fig. 52A illustrates such a state: only the upper portion of the rewiring 90 near the solder ball 14 is converted into imc (cusn) 462.

As with fig. 51B, fig. 52B illustrates such a state: the re-wiring 90 is formed thinner than that of fig. 52A, all Cu of the re-wiring 90 becomes IMC 462 and the reaction is terminated by the barrier metal 461B.

Fig. 52C illustrates such a state: the rewiring 90 is formed thinner than that of fig. 52A, all Cu of the rewiring 90 is reacted and becomes IMC 462 made of CuSn, a part of the barrier metal 461B is also reacted and thus formed with IMC 463 made of TiSn.

Fig. 52D illustrates such a state: the re-wiring 90 is formed thinner than that of fig. 52A, all Cu of the re-wiring 90 is reacted, the IMC 462 composed of CuSn is diffused to the inside of the solder ball 14, a part of the barrier metal 461B is also reacted and thus the IMC 463 composed of TiSn is formed.

Therefore, by forming the barrier metal 461 below the rewiring 90, soldering defects can be suppressed. When Ti is used as the material of the barrier metal 461, it can also be expected to suppress the growth of Kirkendall void (Kirkendall void) occurring due to the difference in the interdiffusion rate between Cu and Sn in the reliability test after soldering.

< example of case where bonding pad exists >

Even when the pad 431 is formed over the rewiring 90 (as shown in fig. 40 or 42), the barrier metal 461 can be formed in this way.

Fig. 53 illustrates such a structure example: here, barrier metals 461 are formed on the lower layer of the rewiring 90 and the lower layer of the pad 431, respectively. Therefore, a structure in which the barrier metal 461 is disposed under the solder ball 14 is referred to as an Under Bump Metallurgy (UBM) structure.

A process of forming the barrier metal 461 when the pad 431 is present as shown in fig. 53 will be described with reference to fig. 54A to 54E.

First, as shown in fig. 54A, after a barrier metal 461 is formed by a sputtering method, a rewiring 90 is formed by a damascene method. After the redistribution lines 90 are formed, a cap film 421 and an insulating film 422 are stacked.

Next, after exposing the region where the pad 431 is to be formed as shown in fig. 54B, a barrier metal 461 and a wiring material 431A for the pad 431 are formed as shown in fig. 54C. Here, by setting the thickness of the barrier metal 461 to be as thick as, for example, about 500nm, the connection reliability of the solder ball 14 can be improved.

Then, as shown in fig. 54D, the surface is planarized by a CMP method to remove the excess wiring material 431A and the excess barrier metal 461, thereby forming the pad 431.

Finally, as shown in fig. 54E, a cap film 441 and an insulating film 442 are formed on the uppermost surface, the solder ball 14 is formed over the pad 431, and a solder mask 91 is formed elsewhere.

As described above, by forming the re-wiring 90 and the pad 431 by the damascene method, the barrier metal 461 can be formed at the wiring side wall, and therefore the risk of inter-wiring leakage or the like can be reduced. Since the UBM structure of the solder ball mounting portion is formed by the damascene method, it is possible to remove the undercut of the barrier metal 461 and thus easily thicken the barrier metal 461 or form a laminated film.

According to the first to third manufacturing methods of the solid-state imaging device 1 having the above-described face-to-back structure, the two through-electrodes (i.e., the chip through-electrodes 105 and the through-silicon-via-electrodes 109) are formed before the color filters 15 or the on-chip lenses 16 are formed. Therefore, before the color filter 15 or the on-chip lens 16 is formed, the insulating film 107 or the insulating film 108 serving as a barrier film can also be formed. Therefore, the insulating film 107 or the insulating film 108 having good film quality can be formed, and therefore, characteristics such as pressure resistance or adhesiveness can be improved. That is, the reliability of the insulating film 107 or the insulating film 108 which can secure high reliability can be improved.

<6. method for producing first basic Structure >

Next, a method of manufacturing the solid-state imaging device 1 having the face-to-face structure (in which the wiring layer of the logic substrate 11 and the wiring layer of the pixel sensor substrate 12 face each other) as shown in fig. 5 to 14 will be explained.

< method for producing basic Structure of FIG. 5 >

A method of manufacturing the solid-state imaging device 1 having the basic structure shown in fig. 5 will be first explained with reference to fig. 55 to 65.

First, the semi-finished logic substrate 11 and the semi-finished pixel sensor substrate 12 are manufactured separately.

In the logic substrate 11, a multilayer wiring layer 82 to be the control circuit 22 or the logic circuit 23 is formed in a region to be each chip section of a silicon substrate (silicon wafer) 81. At this time, the silicon substrate 81 has not yet been thinned and has a thickness of, for example, about 600 μm.

On the other hand, in the pixel sensor substrate 12, the photodiode 51 and the source/drain regions of the pixel transistors of each pixel 32 are formed in a region to be each chip section of the silicon substrate (silicon wafer) 101. A multilayer wiring layer 102 for forming a part of a control circuit and the like is formed on one surface of a silicon substrate 101, and a color filter 15 and an on-chip lens 16 are formed on the other surface of the silicon substrate 101.

As shown in fig. 55, the multilayer wiring layer 82 side of the manufactured logic substrate 11 and the multilayer wiring layer 102 side of the pixel sensor substrate 12 are pasted so as to face each other. Examples of the pasting include plasma bonding and adhesive bonding. In the present embodiment, it is assumed that plasma bonding is performed. In the case of plasma bonding, the logic substrate 11 and the pixel sensor substrate 12 are bonded by: a plasma TEOS film, a plasma SiN film, a SiON film (barrier film), a SiC film, or the like is formed on the bonding surface of the logic substrate 11 and the pixel sensor substrate 12, plasma treatment is performed on the bonding surface, and the two substrates are stacked and then annealing treatment is performed.

After the logic substrate 11 and the pixel sensor substrate 12 are bonded together, the through-silicon via electrode 109, the through-chip electrode 105, and the connection wiring 106 for connecting the through-silicon via electrode 105 and the through-silicon via electrode 109 are formed by a damascene method or the like.

As shown in fig. 55, a glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 formed with the pixel sensor substrate 12 bonded to the logic substrate 11. As shown in fig. 56, the glass protective substrate 18 is connected to a cavity-less structure.

Next, as shown in fig. 57, after the laminated substrate 13 where the logic substrate 11 and the pixel sensor substrate 12 are pasted together is turned upside down, the silicon substrate 81 of the logic substrate 11 is thinned to a degree having a thickness that does not affect the device characteristics (for example, to a degree of about 30 micrometers to about 100 micrometers).

Next, as shown in fig. 58, after patterning the photoresist 221 so as to expose the thinned silicon substrate 81 at the position where the through-silicon via electrode 88 (not shown) is disposed, the silicon substrate 81 and a part of the interlayer insulating film 84 under the silicon substrate 81 are removed by dry etching to form an opening 222.

Next, as shown in FIG. 59, the resist is removed by, for example, a plasma CVD methodAn insulating film (isolation film) 86 is formed on the entire upper surface (including the opening 222) of the silicon substrate 81. As described above, for example, SiO can be used₂The film or SiN film is formed as the insulating film 86.

Next, as shown in fig. 60, the insulating film 86 on the bottom surface of the opening 222 is removed by etching back to expose the wiring layer 83c closest to the silicon substrate 81.

Next, as shown in fig. 61, a barrier metal film (not shown) and a Cu seed layer 231 are formed by a sputtering method. When the connection conductor 87 is embedded by the electroplating method, the barrier metal film prevents the connection conductor 87(Cu) from diffusing, and the Cu seed layer 231 becomes an electrode. As a material of the barrier metal film, for example, tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), and a nitride film or a carbide film thereof can be used. In this embodiment, a titanium film is used as the barrier metal film.

Next, as shown in fig. 62, after a resist pattern 241 is formed in a necessary region on the Cu seed layer 231, copper (Cu) serving as the connection conductor 87 is electroplated by an electroplating method. Therefore, the through-silicon via electrode 88 is formed and the rewiring 90 is also formed on the upper side of the silicon substrate 81.

Next, as shown in fig. 63, after the resist pattern 241 is removed, the barrier metal film (not shown) and the Cu seed layer 231 under the resist pattern 241 are removed by wet etching.

Next, as shown in fig. 64, after the solder mask 91 is formed to protect the rewiring 90, the solder mask opening 242 is formed by removing only the solder mask 91 in the solder ball 14 mounting area.

Then, as shown in fig. 65, the solder balls 14 are formed in the solder mask openings 242 by a solder ball mounting method or the like.

The solid-state imaging device 1 having the basic structure shown in fig. 5 can be manufactured by the manufacturing method described above.

According to the manufacturing method described above, after the color filter 15 is formed, the through-silicon via electrode 88 is formed. In this case, in the formation process of the through-silicon via electrode 88, it is particularly necessary to form the insulating film 86 insulating the silicon substrate 81 and the connection conductor 87 by a low-temperature plasma CVD method at about 200 to about 220 degrees in order to prevent the color filter 15, the on-chip lens 16, and the like from being damaged.

However, when the insulating film 86 is formed at a low temperature, the interatomic bonding may be insufficient and the film quality may be deteriorated in some cases. Further, when the film quality deteriorates, peeling or cracking may occur, and thus a silicon withstand voltage failure or metal wiring leakage or the like may occur in some cases.

Therefore, a manufacturing method that ensures the reliability of the insulating film 86 while preventing the color filter 15 or the on-chip lens 16 and the like from being damaged will be described below.

< first manufacturing method of first modification >

A first manufacturing method of the solid-state imaging device 1 having the structure according to the first modification shown in fig. 6 will be described with reference to fig. 66A to 67C.

First, the semi-finished logic substrate 11 and the semi-finished pixel sensor substrate 12 are manufactured separately.

In the logic substrate 11, a multilayer wiring layer 82 to be the control circuit 22 or the logic circuit 23 is formed in a region to be each chip section of a silicon substrate (silicon wafer) 81. At this time, the silicon substrate 81 has not yet been thinned and has a thickness of, for example, about 600 μm.

On the other hand, in the pixel sensor substrate 12, the photodiode 51 of each pixel 32 and the source/drain regions of the pixel transistors are formed in a region to be each chip section of a silicon substrate (silicon wafer) 101. A multilayer wiring layer 102 for forming a part of the control circuit 22 and the like is formed on the surface of the silicon substrate 101 where the source/drain regions of the pixel transistors are formed. Some figures subsequent to fig. 66A to 66D do not illustrate the photodiode 51 formed in the silicon substrate 101 as a figure of the semi-finished pixel sensor substrate 12.

Thereafter, as shown in fig. 66A, the semi-finished logic substrate 11 and the semi-finished pixel sensor substrate 12 are pasted by plasma bonding or adhesive so that the multilayer wiring layer 82 side of the logic substrate 11 and the multilayer wiring layer 102 side of the pixel sensor substrate 12 face each other.

As shown in fig. 66B, after the silicon substrate 81 of the logic substrate 11 is thinned to a degree having a thickness that does not affect the device characteristics (for example, to a degree of about 20 micrometers to about 100 micrometers), an insulating film 86 for insulating from the silicon substrate 81 is formed on the surface of the silicon substrate 81 by a plasma CVD method or the like.

Next, as shown in fig. 66C, through-silicon via electrodes 151 connected to the wiring layer 83C of the logic substrate 11, chip through-electrodes 152 connected to the wiring layer 103C of the pixel sensor substrate 12, and connection wires 153 connecting the through-silicon via electrodes 151 and the chip through-electrodes 152 are formed at predetermined positions on the silicon substrate 81 on the logic substrate 11 side. Through-silicon via electrodes 151, chip via electrodes 152, and connection wiring 153 can be formed by the same steps as those described with reference to fig. 22 to 24.

A rewiring 154 is also formed, and solder balls 14 are to be mounted on the rewiring 154. The re-wiring 154 is formed by, for example, a damascene method.

In fig. 6, 66A to 66D, and 67A to 67C, an insulating film 86 is formed as one layer. Actually, as in the face-to-back structure, a cap film 421, an insulating film 422, or the like is stacked. As described above, the rewiring 154 can have a structure in which: wherein the remaining thickness does not react with copper or the reaction is stopped using the barrier metal 461. Further, for example, a structure with a pad 431 added as shown in fig. 40 and 42 or a UBM structure shown in fig. 52A to 53 can also be used.

Next, as shown in fig. 66D, a temporary bonding substrate (silicon substrate) 471 as a support substrate is pasted to the insulating film 86 side of the logic substrate 11.

As shown in fig. 67A, all the substrates to which the temporary bonding substrate 471 is bonded are turned upside down. After thinning the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns, the color filter 15 and the on-chip lens 16 are formed. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 67B, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is connected to the cavity-less structure. After the glass protective substrate 18 is attached, the temporary bonding substrate 471 is separated.

As shown in fig. 67C, the solder mask 91 is formed on the entire surface, the solder mask 91 is removed only in the region where the solder ball 14 is to be mounted, and then the solder ball 14 is formed by a solder ball mounting method or the like.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the first modification shown in fig. 6 is completed.

< second production method of first modification >

Next, a second manufacturing method of the solid-state imaging device 1 having the structure according to the first modification shown in fig. 6 will be described with reference to fig. 68A to 70C.

First, as shown in fig. 68A, the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are bonded so that their wiring layers face each other.

As shown in fig. 68B, the silicon substrate 101 of the pixel sensor substrate 12 is thinned to about 1 micrometer to about 10 micrometers using the silicon substrate 81 of the logic substrate 11 as a support substrate.

Next, as shown in fig. 68C, a temporary bonding substrate (silicon substrate) 472 is attached to the thinned silicon substrate 101 of the pixel sensor substrate 12. At this time, as shown in fig. 68D, the temporary bonding substrate 472 is used as a support substrate to thin the silicon substrate 81 of the logic substrate 11 to 20 micrometers to about 100 micrometers.

Next, as shown in fig. 69A, through-silicon via electrodes 151 connected to the wiring layer 83c of the logic substrate 11, chip through-electrodes 152 connected to the wiring layer 103c of the pixel sensor substrate 12, and connection wires 153 connecting the through-silicon via electrodes 151 and the chip through-electrodes 152 are formed at predetermined positions on the silicon substrate 81 on the logic substrate 11 side. Through-silicon via electrodes 151, chip via electrodes 152, and connection wiring 153 can be formed by the same steps as those described with reference to fig. 22 to 24.

A rewiring 154 is also formed, and solder balls 14 are to be mounted on the rewiring 154. The re-wiring 154 is formed by, for example, a damascene method.

Next, after the temporary bonding substrate 473 is pasted to the insulating film 86 side of the logic substrate 11 as shown in fig. 69B, the temporary bonding substrate 472 on the pixel sensor substrate 12 side is separated as shown in fig. 69C.

Next, as shown in fig. 70A, all the substrates to which the temporary bonding substrate 473 is bonded are turned upside down, and the color filter 15 and the on-chip lens 16 are formed on the silicon substrate 101 of the pixel sensor substrate 12. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 70B, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is connected to the cavity-less structure. After the glass protective substrate 18 is attached, the temporary bonding substrate 473 is separated.

Finally, as shown in fig. 70C, a solder mask 91 is formed on the entire surface, the solder mask 91 is removed only in the region where the solder ball 14 is to be mounted, and then the solder ball 14 is formed by a solder ball mounting method or the like.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the first modification shown in fig. 6 is completed.

In the face-to-face structure shown in fig. 6, the connection wiring 153 for connecting the through-silicon via electrode 151 to the through-chip via electrode 152 is configured to be formed on the upper surface of the silicon substrate 81.

However, as shown in fig. 71A, at least a part of the connection wiring 153 formed by the damascene method may be formed in a portion formed by etching the silicon substrate 81.

Fig. 71B illustrates such a structure example: the rewiring 154 connected to the solder ball 14 is omitted, and the connection wiring 153 formed by a damascene method is formed in a portion formed by etching the silicon substrate 81.

Therefore, by forming the connection wiring 153 in a portion formed by etching the silicon substrate 81, the insulating film (oxide film) 86 can be thin. Therefore, since the number of processes for forming the insulating film can be reduced, productivity is improved.

< third production method of first modification >

Next, a third manufacturing method of the solid-state imaging device 1 having the structure according to the first modification shown in fig. 6 will be described with reference to fig. 72A to 73D.

First, as shown in fig. 72A, the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are bonded so that their wiring layers face each other.

As shown in fig. 72B, after the silicon substrate 81 of the logic substrate 11 is thinned to a degree having a thickness that does not affect the device characteristics (for example, to a degree of about 20 micrometers to about 100 micrometers), an insulating film 86 for insulating from the silicon substrate 81 is formed on the surface of the silicon substrate 81 by a plasma CVD method or the like.

Next, as shown in fig. 72C, the through-silicon via electrodes 151, the chip via electrodes 152, the connection wirings 153, and the rewirings 154 are formed at predetermined positions on the silicon substrate 81 on the logic substrate 11 side. The formation method is the same as the above-described method.

Next, the surface of the insulating film 86 of the logic substrate 11 is planarized by the CMP method. Thereafter, as shown in fig. 72D, a temporary bonded substrate 481 is pasted by plasma bonding, and the temporary bonded substrate 481 includes a peeling layer 481A such as a porous layer. Since the temporary bonding substrate 481 can be temporarily attached by plasma bonding with the flatness of the entire thickness set to vary by about 0.5 μm, the film thickness is easily controlled when the silicon substrate 101 of the pixel sensor substrate 12 is thinned in the subsequent process.

Next, as shown in fig. 73A, all the substrates to which the temporary bonding substrate 481 is bonded are turned upside down. After thinning the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns, the color filter 15 and the on-chip lens 16 are formed. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 73B, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is connected to the cavity-less structure.

After the glass protective substrate 18 is attached, the temporary bonding substrate 481 is peeled off with the peeling layer 481A remaining. Then, as shown in fig. 73C, the peeling layer 481A is removed by grinding, polishing, or the like.

Finally, as shown in fig. 73D, a solder mask 91 is formed on the entire surface, the solder mask 91 is removed only in the region where the solder ball 14 is to be mounted, and then the solder ball 14 is formed by a solder ball mounting method or the like.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the first modification shown in fig. 6 is completed.

< fourth production method of first modification >

Next, a fourth manufacturing method of the solid-state imaging device 1 having the structure according to the first modification shown in fig. 6 will be described with reference to fig. 74A to 75D.

First, as shown in fig. 74A, the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are attached so that their wiring layers face each other.

As shown in fig. 74B, after the silicon substrate 81 of the logic substrate 11 is thinned to a degree having a thickness that does not affect the device characteristics (for example, to a degree of about 20 micrometers to about 100 micrometers), an insulating film 86 for insulating from the silicon substrate 81 is formed on the surface of the silicon substrate 81 by a plasma CVD method or the like.

Next, as shown in fig. 74C, through-silicon via electrodes 151, chip via electrodes 152, connection wirings 153, and rewirings 154 are formed at predetermined positions on the silicon substrate 81 on the logic substrate 11 side. The formation method is the same as the above-described method.

Next, the surface of the insulating film 86 of the logic substrate 11 is planarized by the CMP method. Thereafter, as shown in fig. 74D, a temporary bonding substrate 481 as a support substrate is attached by plasma bonding. In the temporary bonding substrate 481, a reliable insulating film 482 made of SiN or the like is formed in advance on a bonding surface having the release layer 481A such as a porous layer, and the insulating film 482 of the temporary bonding substrate 481 and the insulating film 86 of the logic substrate 11 are bonded to each other. Since the temporary bonding substrate 481 can be temporarily bonded by plasma bonding with the flatness of the entire thickness being changed by about 0.5 μm, the film thickness can be easily controlled when the silicon substrate 101 of the pixel sensor substrate 12 is thinned in the subsequent process.

Next, as shown in fig. 75A, all the substrates to which the temporary bonding substrate 481 is bonded are turned upside down. After thinning the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns, the color filter 15 and the on-chip lens 16 are formed. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 75B, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is connected to the cavity-less structure.

After the glass protective substrate 18 is attached, the temporary bonding substrate 481 is peeled off with the peeling layer 481A remaining. Then, the peeling layer 481A is removed by grinding, polishing, or the like to expose the reliable insulating film 482.

Finally, as shown in fig. 75D, a solder mask 91 is formed on the entire surface, the solder mask 91 is removed only in the region where the solder ball 14 is to be mounted, and then the solder ball 14 is formed by a solder ball mounting method or the like.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the first modification shown in fig. 6 is completed.

According to the third and fourth manufacturing methods of the first modification described above, the temporary bonding substrate 481 can be reused, and the manufacturing cost can be reduced.

< fifth production method of first modification >

Next, a fifth manufacturing method of the solid-state imaging device 1 having the structure according to the first modification shown in fig. 6 will be described with reference to fig. 76A to 77C.

First, as shown in fig. 76A, the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are attached so that their wiring layers face each other.

As shown in fig. 76B, after thinning the silicon substrate 81 of the logic substrate 11 to such an extent as to have a thickness that does not affect the device characteristics (for example, to such an extent as to about 20 micrometers to about 100 micrometers), an insulating film 86 for insulating from the silicon substrate 81 is formed on the surface of the silicon substrate 81 by a plasma CVD method or the like.

Next, as shown in fig. 76C, through-silicon via electrodes 151, chip via electrodes 152, connection wirings 153, and rewirings 154 are formed at predetermined positions on the silicon substrate 81 on the logic substrate 11 side. The formation method is the same as the above-described method.

Further, the solder mask 91 is formed on the entire surface, the solder mask 91 is removed only in the region where the solder ball 14 is to be mounted, and then the solder ball 14 is formed by a solder ball mounting method or the like.

Next, as shown in fig. 76D, the temporary bonding substrate 491 is pasted with an adhesive 490 having a thickness capable of burying the solder ball 14.

Next, as shown in fig. 77A, all the substrates to which the temporarily bonded substrate 491 is bonded are turned upside down. After thinning the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns, the color filter 15 and the on-chip lens 16 are formed. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 77B, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is connected to the cavity-less structure. After the glass protective substrate 18 is attached, the temporary bonding substrate 491 is separated.

As shown in fig. 77C, the adhesive 490 for adhering the temporary bonding substrate 491 is removed.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the first modification shown in fig. 6 is completed.

< sixth production method of first modification >

Next, a sixth manufacturing method of the solid-state imaging device 1 having the structure according to the first modification shown in fig. 6 will be described with reference to fig. 78A to 80C.

First, as shown in fig. 78A, the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are bonded so that their wiring layers face each other.

As shown in fig. 78B, the silicon substrate 81 of the logic substrate 11 is used as a support substrate to thin the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns.

Next, as shown in fig. 78C, a temporary bonding substrate (silicon substrate) 492 is bonded to the thinned silicon substrate 101 of the pixel sensor substrate 12. At this time, as shown in fig. 78D, the temporary bonding substrate 492 is used as a support substrate to thin the silicon substrate 81 of the logic substrate 11 to 20 micrometers to about 100 micrometers.

Next, as shown in fig. 79A, the through-silicon via electrodes 151, the chip via electrodes 152, the connection wirings 153, and the rewirings 154 are formed at predetermined positions on the silicon substrate 81 on the logic substrate 11 side. The formation method is the same as the above-described method.

Further, the solder mask 91 is formed on the entire surface, the solder mask 91 is removed only in the region where the solder ball 14 is to be mounted, and then the solder ball 14 is formed by a solder ball mounting method or the like.

Next, as shown in fig. 79B, a temporary bonding substrate 493 is pasted using an adhesive 490 having a thickness capable of burying the solder balls 14.

Next, as shown in fig. 79C, the temporary bonding substrate 492 on the pixel sensor substrate 12 side is separated.

Next, as shown in fig. 80A, all the substrates to which the temporary bonding substrate 492 is bonded are turned upside down. After thinning the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns, the color filter 15 and the on-chip lens 16 are formed. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 80B, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is connected to the cavity-less structure. After the glass protective substrate 18 is attached, the temporary bonding substrate 492 is separated.

As shown in fig. 80C, the adhesive 490 for attaching the temporary bonding substrate 492 is removed.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the first modification shown in fig. 6 is completed.

< first manufacturing method of second modification >

Next, a first manufacturing method of the solid-state imaging device 1 having the structure according to the second modification shown in fig. 7 will be described with reference to fig. 81A to 82D. The structure according to the second modification shown in fig. 7 is a face-to-face structure using metal bonding (Cu-Cu bonding).

First, as shown in fig. 81A, the wiring layer 83a of the multilayer wiring layer 82 of the semi-finished logic substrate 11 and the wiring layer 103c of the multilayer wiring layer 102 of the semi-finished pixel sensor substrate 12, which are separately manufactured, are bonded by metal bonding (Cu — Cu).

As shown in fig. 81B, after thinning the silicon substrate 81 of the logic substrate 11 to a degree having a thickness that does not affect the device characteristics (for example, to a degree of about 20 micrometers to about 100 micrometers), an insulating film 86 for insulating from the silicon substrate 81 is formed on the surface of the silicon substrate 81 by a plasma CVD method or the like.

Next, as shown in fig. 81C, through-silicon via electrodes 88 and rewirings 90 are formed at predetermined positions on the silicon substrate 81 on the logic substrate 11 side. The formation method is the same as the formation method of the through-silicon via 151 and the rewiring 154 described above.

As shown in fig. 81D, a solder mask 91 and solder balls 14 can be formed after this step, as in the step shown in fig. 76C.

Next, as shown in fig. 82A, a temporary bonding substrate (silicon substrate) 493 as a supporting substrate is pasted to the insulating film 86 side of the logic substrate 11.

Next, as shown in fig. 82B, all the substrates to which the temporary bonding substrate 493 is bonded are turned upside down. After thinning the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns, the color filter 15 and the on-chip lens 16 are formed. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 82C, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is connected to the cavity-less structure. After the glass protective substrate 18 is attached, the temporary bonding substrate 493 is separated.

As shown in fig. 82D, the solder mask 91 is formed on the entire surface, the solder mask 91 is removed only in the region where the solder ball 14 is to be mounted, and then the solder ball 14 is formed by a solder ball mounting method or the like.

As shown in fig. 81D, when until the solder mask 91 and the solder ball 14 are formed on the insulating film 86 and then the temporary bonding substrate 493 is bonded, the temporary bonding substrate 493 may be separated and then only the adhesive may be removed.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the second modification shown in fig. 7 is completed.

< second manufacturing method of second modification >

Next, a second manufacturing method of the solid-state imaging device 1 having the structure according to the second modification shown in fig. 7 will be described with reference to fig. 83A to 85C.

First, as shown in fig. 83A, the wiring layer 83A of the multilayer wiring layer 82 of the separately manufactured semi-finished logic substrate 11 and the wiring layer 103c of the multilayer wiring layer 102 of the semi-finished pixel sensor substrate 12 are pasted together by metal bonding (Cu — Cu).

As shown in fig. 83B, the silicon substrate 101 of the pixel sensor substrate 12 is thinned to about 1 micron to about 10 microns using the silicon substrate 81 of the logic substrate 11 as a support substrate.

Next, as shown in fig. 83C, a temporary bonding substrate (silicon substrate) 494 is pasted to the thinned silicon substrate 101 of the pixel sensor substrate 12. At this time, as shown in fig. 83D, the temporary bonding substrate 494 is used as a support substrate to thin the silicon substrate 81 of the logic substrate 11 to 20 micrometers to about 100 micrometers.

Next, as shown in fig. 84A, an insulating film 86 is formed on the surface of the silicon substrate 81 by a plasma CVD method or the like, and then a through-silicon via electrode 88 and a rewiring 90 are formed at predetermined positions of the silicon substrate 81 on the logic substrate 11 side. The formation method is the same as the formation method of the through-silicon via 151 and the rewiring 154 described above.

Next, as shown in fig. 84B, a temporary bonding substrate (silicon substrate) 495 as a support substrate is pasted to the insulating film 86 side of the logic substrate 11. As shown in fig. 84C, the temporary bonding substrate 494 on the pixel sensor substrate 12 side is separated.

Next, as shown in fig. 85A, all the substrates to which the temporary bonding substrate 495 is bonded are turned upside down. After thinning the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns, the color filter 15 and the on-chip lens 16 are formed. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 85B, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is connected to the cavity-less structure. After the glass protective substrate 18 is attached, the temporary bonding substrate 495 is separated.

As shown in fig. 85C, the solder mask 91 is formed on the entire surface, the solder mask 91 is removed only in the region where the solder ball 14 is to be mounted, and then the solder ball 14 is formed by a solder ball mounting method or the like.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the second modification shown in fig. 7 is completed.

Further, in fig. 84A, the solder mask 91 and the solder ball 14 are first formed on the insulating film 86, and then the temporary bonding substrate 495 is pasted. In this case, in fig. 85B, after the temporary bonding substrate 495 is separated, only the adhesive agent adhering to the temporary bonding substrate 495 is removed.

< manufacturing method of third modification >

Next, a method of manufacturing the solid-state imaging device 1 having the structure according to the third modification shown in fig. 8 will be described with reference to fig. 86A to 87D. The structure according to the third modification shown in fig. 8 is a face-to-face structure: among them, the linking wiring 153 and the rewiring 154 are connected to a linking conductor (through hole) 171.

First, as shown in fig. 86A, the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are pasted such that their wiring layers face each other.

As shown in fig. 86B, after the silicon substrate 81 of the logic substrate 11 is thinned to a degree having a thickness that does not affect the device characteristics (for example, to a degree of about 20 micrometers to about 100 micrometers), an insulating film 86 for insulating from the silicon substrate 81 is formed on the surface of the silicon substrate 81 by a plasma CVD method or the like.

Next, as shown in fig. 86C, the through-silicon via electrodes 151, the chip via electrodes 152, and the connection wirings 153 are formed at predetermined positions on the silicon substrate 81 on the logic substrate 11 side. The formation method is the same as the above-described method.

Next, as shown in fig. 86D, a temporary bonding substrate (silicon substrate) 496 as a support substrate is attached to the insulating film 86 side of the logic substrate 11.

Next, as shown in fig. 87A, all the substrates to which the temporarily bonded substrates 496 are bonded are turned upside down. After thinning the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns, the color filter 15 and the on-chip lens 16 are formed. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 87B, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is connected to the cavity-less structure. After the glass protective substrate 18 is attached, the temporary bonding substrate 496 is separated.

As shown in fig. 87C, a part of the insulating film 86 on the connection wiring 153 is opened by etching, and then a connection conductor (via hole) 171 and a rewiring 154 are formed by a semi-additive method.

As shown in fig. 87D, after the solder mask 91 is formed to cover the insulating film 86 and the rewiring 154, the solder mask 91 is opened only in the region where the solder ball 14 is to be mounted.

Finally, the solder balls 14 are formed in the solder mask opening areas by a solder ball mounting method or the like.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the third modification shown in fig. 8 is completed.

As described in the above first modification, in the structures according to the above first to third modifications, the connection wiring 153 that electrically connects the logic substrate 11 to the pixel sensor substrate 12 is formed not on the upper side of the silicon substrate 101 of the pixel sensor substrate 12 but on the lower side of the silicon substrate 81 of the logic substrate 11. Therefore, since the space (thickness) having a cavity-free structure between the glass protective substrate 18 and the laminated substrate 13 can be minimized, a low backside of the solid-state imaging device 1 can be achieved, and thus the pixel characteristics can be improved.

< manufacturing method of fourth modification >

Next, a method of manufacturing the solid-state imaging device 1 having the structure according to the fourth modification shown in fig. 9 will be described with reference to fig. 88A to 89D.

The structure according to the fourth modification shown in fig. 9 is a face-to-face structure: the solder balls 14, the wiring layers 83 of the logic substrate 11, and the wiring layers 103 of the pixel sensor substrate 12 are connected to each other by one through-chip electrode 181 penetrating the logic substrate 11 and the pixel sensor substrate 12.

First, as shown in fig. 88A, the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are bonded so that their wiring layers face each other. Then, the through-silicon via electrode 109, the chip through-electrode 105, the connection wiring 106 connecting the through-silicon via electrode 109 to the chip through-electrode 105, the chip through-electrode 181, and the connection wiring 182 are formed. The upper surface of the silicon substrate 101 including the through-silicon via electrode 109, the chip through-electrode 105, the connection wiring 106, the chip through-electrode 181, and the connection wiring 182 is covered with an insulating film 108. As with the other embodiments described above, the insulating film 108 may be configured to include a plurality of layers (i.e., the cap film and the insulating film).

In the first to third modifications described above, the through-silicon via electrode 109, the chip through-electrode 105, and the connection wiring 106 connecting the chip through-electrode 105 to the through-silicon via electrode 109 are formed on the logic substrate 11 side. However, in the fourth modification, as shown in fig. 88A, the through-silicon via electrode 109, the chip via electrode 105, and the connection wiring 106 are formed on the pixel sensor substrate 12 side. However, the forming method is the same as the forming method according to the first to third modifications described above. The through-silicon via electrodes 181 and the connection wires 182 may be formed simultaneously with the through-silicon via electrodes 109, the through-chip via electrodes 105, and the connection wires 106.

Next, as shown in fig. 88B, a necessary region including the pixel region 21 is etched in a portion where the insulating film 108 is formed. Alternatively or additionally, a necessary region including the pixel region 21 is formed in the groove portion formed with the insulating film 108. As shown in fig. 88C, the color filter 15 and the on-chip lens 16 are formed in the cutout of the pixel region 21. Alternatively or additionally, the color filter 15 and the on-chip lens 16 are formed in a groove portion of the pixel region 21.

As shown in fig. 88D, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is attached to the cavity-less structure.

Next, as shown in fig. 89A, the silicon substrate 81 of the logic substrate 11 is subjected to back grinding (polishing) to be thinned using the glass protective substrate 18 as a support substrate. In the back grinding, the through-chip electrodes 181 slightly protrude from the silicon substrate 81 by the difference in polishing rate. After the thinning, the surface of the polished silicon substrate 81 is planarized by the CMP method.

Thereafter, after a TEOS film serving as the insulating film 86 is formed by a plasma CVD method, the formed TEOS film is planarized by a CMP method and wet-etched using hydrofluoric acid (HF). Then, as shown in fig. 89B, the surface of the silicon substrate 81 except for the upper surface of the through-chip electrode 181 is covered with an insulating film 86.

After the re-wiring 183 is formed by the semi-addition method as shown in fig. 89C, a solder mask 91 and solder balls 14 are formed as shown in fig. 89D.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the fourth modification shown in fig. 9 is completed.

< manufacturing method of fifth modification >

Next, a method of manufacturing the solid-state imaging device 1 having the structure of the fifth modification shown in fig. 10 will be described with reference to fig. 90A to 92C.

The steps shown in fig. 90A to 90C are the same as those of the manufacturing method of the fourth modification shown in fig. 88A to 88C.

That is, after the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are bonded so that their wiring layers face each other, connection conductors such as the through-chip via electrodes 105, the through-silicon via electrodes 109, and the through-chip via electrodes 181 are formed. Then, the color filter 15 and the on-chip lens 16 are formed on the back side of the pixel sensor substrate 12.

Thereafter, as shown in fig. 90D, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, a temporary bonding substrate 521 using a silicon substrate is pasted to the cavity-less structure.

In the manufacturing method of the fourth modification shown in fig. 88D, the glass protective substrate 18 is pasted in this step. However, in the manufacturing method of the fifth modification, the temporary bonding substrate 521 is pasted. By doing so, the advantage of utilizing previously processed equipment can be obtained.

As shown in fig. 91A, as in fig. 89A, the temporary bonding substrate 521 is used as a support substrate to thin the silicon substrate 81 of the logic substrate 11.

As shown in fig. 91B, an insulating film 86A such as a TEOS film is formed in the same step as the step of the method described with reference to fig. 89B. Thereafter, as shown in fig. 91C, the rewiring 183 and the insulating film 86B are formed on the upper surface of the insulating film 86A.

Therefore, the insulating film 86 in the fifth modification is configured to include two layers, i.e., the insulating film 86A before formation of the re-wiring 183 and the insulating film 86B after formation of the re-wiring 183. The rewiring 183 can be formed by a semi-additive method and the insulating film 86B can be formed by a plasma CVD method.

Next, as shown in fig. 91D, an area on the re-wiring 183 where the solder ball 14 is to be formed is opened, and, for example, an embedding material 522 having etching selectivity to the insulating film 86, such as a resist or SOG (spin on glass) is embedded in the opening. Then, the temporary bonding substrate 523 is pasted to the upper surface of the insulating film 86 of the logic substrate 11 in which the embedding material 522 is embedded.

As shown in fig. 92A, the temporary bonding substrate 521 attached to the on-chip lens 16 side is separated. Thereafter, as shown in fig. 92B, the glass protective substrate 18 is attached to the on-chip lens 16 side.

Next, as shown in fig. 92C, the temporary bonding substrate 523 on the insulating film 86 side of the logic substrate 11 is separated and the embedding material 522 is removed. Then, the solder ball 14 is formed on the portion where the embedding material 522 is removed by a solder ball mounting method or the like.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the fifth modification shown in fig. 10 is completed.

< manufacturing method of sixth modification >

Next, a method of manufacturing the solid-state imaging device 1 having the structure according to the sixth modification shown in fig. 11 will be described with reference to fig. 93A to 94C.

First, as shown in fig. 93A, after the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are bonded so that their wiring layers face each other, the chip through-electrodes 191, the connection wirings 192, the chip through-electrodes 181, and the connection wirings 182 are formed. Then, the upper surface of the silicon substrate 101 including the chip through-electrode 191, the connection wiring 192, the chip through-electrode 181, and the connection wiring 182 is covered with an insulating film 108. The method of forming the through-chip electrodes 191, the connection wires 192, and the like is the same as the method of forming the first to fifth modifications described above. As with the other embodiments described above, the insulating film 108 can be configured to include a plurality of layers (i.e., the cap film and the insulating film).

Next, as shown in fig. 93B, a necessary region including the pixel region 21 is etched in a portion where the insulating film 108 is formed. Alternatively or additionally, a necessary region including the pixel region 21 is formed in the groove portion where the insulating film 108 is formed. As shown in fig. 93C, the color filter 15 and the on-chip lens 16 are formed in the cutouts of the pixel region 21. Alternatively or additionally, the color filter 15 and the on-chip lens 16 are formed at the groove portion of the pixel region 21.

As shown in fig. 94A, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is attached to the cavity-less structure.

Next, as shown in fig. 94B, the silicon substrate 81 of the logic substrate 11 is thinned by subjecting it to back grinding (polishing) using the glass protective substrate 18 as a support substrate, and thus the silicon substrate 81 is thinned so that the chip through-electrodes 181 slightly protrude from the silicon substrate 81.

As shown in fig. 94C, after the re-wiring 183 is formed by the semi-additive method, a solder mask 91 and solder balls 14 are formed.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the sixth modification shown in fig. 11 is completed.

The structure according to the sixth modification can also be manufactured by using the method of temporarily bonding the substrates 521 and 523 described with reference to fig. 90A to 92D, which is two substrates.

< manufacturing method of seventh modification >

Next, a method of manufacturing the solid-state imaging device 1 having the structure according to the seventh modification shown in fig. 12 will be described with reference to fig. 95A to 96C.

First, as shown in fig. 95A, after the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are bonded so that their wiring layers face each other, the chip through-electrodes 181 and the connection wirings 182 are formed. Then, the upper surface of the silicon substrate 101 including the chip through-electrodes 181 and the connection wirings 182 is covered with an insulating film 108.

The structure of the solid-state imaging device 1 according to the seventh modification shown in fig. 12 is a structure in which: the logic substrate 11 and the pixel sensor substrate 12 are connected by metal bonding. Thus, in fig. 95A, the wiring layer 83a of the multilayer wiring layer 82 of the separately manufactured semi-finished logic substrate 11 and the wiring layer 103c of the multilayer wiring layer 102 of the semi-finished pixel sensor substrate 12 are bonded together by Cu — Cu metal bonding.

The method of forming the through-chip electrodes 181 and the connection wirings 182 is the same as that of the first to sixth modifications described above. As with the other embodiments described above, the insulating film 108 can be configured to include a plurality of layers (i.e., the cap film and the insulating film).

Next, as shown in fig. 95B, a necessary region including the pixel region 21 is etched in a portion where the insulating film 108 is formed. Alternatively or additionally, a necessary region including the pixel region 21 is formed in the groove portion where the insulating film 108 is formed. As shown in fig. 95C, the color filter 15 and the on-chip lens 16 are formed in the cutouts of the pixel region 21. Alternatively or additionally, the color filter 15 and the on-chip lens 16 are formed at the groove portion of the pixel region 21.

As shown in fig. 96A, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is attached to the cavity-less structure.

Next, as shown in fig. 96B, the silicon substrate 81 of the logic substrate 11 is thinned by subjecting it to back grinding (polishing) using the glass protective substrate 18 as a support substrate, and thus the silicon substrate 81 is thinned so that the chip through-electrodes 181 slightly protrude from the silicon substrate 81.

As shown in fig. 96C, after the re-wiring 183 is formed by the semi-additive method, a solder mask 91 and solder balls 14 are formed.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the seventh modification shown in fig. 12 is completed.

The structure according to the seventh modification can also be manufactured by using the method of temporarily bonding the substrates 521 and 523 described with reference to fig. 90A to 92D, which is two substrates.

< manufacturing method of eighth modification >

Next, a method of manufacturing the solid-state imaging device 1 having the structure according to the eighth modification shown in fig. 13 will be described with reference to fig. 97A to 100C.

First, as shown in fig. 97A, the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are bonded so that their wiring layers face each other.

As shown in fig. 97B, both the attached logic substrate 11 and pixel sensor substrate 12 are turned upside down. After thinning the silicon substrate 81 of the logic substrate 11, the through-silicon via electrode 88 and the rewiring 90 are formed. The formation method of the through-silicon via electrode 88 and the rewiring 90 is the same as that of the first to seventh modifications described above.

Next, as shown in fig. 97C, the insulating film 201 is formed on the upper surface of the silicon substrate 81 of the logic substrate 11 on which the rewiring 90 is formed at a temperature equal to or greater than 250 degrees and equal to or less than 400 degrees without affecting the wiring layer 83 and the like. For example, as described with reference to fig. 13, for example, a plasma TEOS film, a plasma SiN film, a plasma SiO film, or the like can be used₂Film, CVD-SiN film or CVD-SiO₂The film is formed as an insulating film 201.

After the insulating film 201 formed by the CMP method is planarized as shown in fig. 98A, a temporary bonding substrate 541 is attached to the upper surface of the planarized insulating film 201 as shown in fig. 98B.

As shown in fig. 98C, the logic substrate 11 and the pixel sensor substrate 12 are turned upside down again, and the silicon substrate 101 of the pixel sensor substrate 12 is thinned using the temporary bonding substrate 541 as a supporting substrate.

As shown in fig. 99A, the through-chip via electrode 105, the through-silicon via electrode 109, and the connection wiring 106 connecting the through-chip via electrode 105 and the through-silicon via electrode 109 are formed. An upper surface of the silicon substrate 101 including the chip through-electrode 105, the through-silicon via electrode 109, and the connection wiring 106 is covered with an insulating film 108. As with the other embodiments described above, the insulating film 108 can be configured to include a plurality of layers (i.e., the cap film and the insulating film). The insulating film 108 can be formed in two or more steps as with the insulating films 86A and 86B in fig. 91C.

Next, as shown in fig. 99B, necessary regions including the pixel region 21 are etched in the region where the insulating film 108 is formed, and the color filter 15 and the on-chip lens 16 are formed in the etched portion of the pixel region 21. Alternatively or additionally, necessary areas including the pixel area 21 are formed in the groove portion where the insulating film 108 is formed, and the color filter 15 and the on-chip lens 16 are formed in the groove portion of the pixel area 21.

As shown in fig. 99C, after the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, the glass protective substrate 18 is attached to the cavity-less structure.

Thereafter, as shown in fig. 100A, the temporarily bonded substrate 541 is separated with both the attached logic substrate 11 and pixel sensor substrate 12 turned upside down.

The insulating film 201 of the region where the solder ball 14 is to be mounted is etched as shown in fig. 100B, so that the insulating film 201 is removed as shown in fig. 100C. Then, the solder ball 14 is formed on the exposed rewiring 90 by a solder ball mounting method or the like.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the eighth modification shown in fig. 13 is completed.

< summary of manufacturing methods of first to eighth modifications >

A method of manufacturing the solid-state imaging device 1 having the structure according to the first to eighth modifications will be briefly described.

In the structures according to the first to eighth modifications, the silicon substrate 81 on the logic substrate 11 side where the multilayer type wiring layer 82 is formed and the silicon substrate 101 on the pixel sensor substrate 12 side where the multilayer type wiring layer 102 is formed are pasted so that the wiring layers face each other.

Next, a through hole connecting the wiring layer 83 of the logic substrate 11 to the wiring layer 103 of the pixel sensor substrate 12 is formed, and a through hole and a rewiring connecting the solder ball 14 as a back surface electrode to the wiring layer 83 of the logic substrate 11 are formed.

The through-holes and the rewires correspond to the through-silicon-via electrodes 151, the chip through-electrodes 152, and the rewires 154 in the first and third modifications, correspond to the through-silicon-via electrodes 88 and the rewires 90 in the second modification, and correspond to the through-chip-via electrodes 105, the through-silicon-via electrodes 109, the through-chip-via electrodes 181, and the rewires 183 in the fourth, fifth, and eighth modifications. The through-holes and the rewires correspond to the chip through-electrodes 181, the chip through-electrodes 191, and the rewires 183 in the sixth and seventh modifications.

The step of forming the through hole or the rewiring also includes forming the insulating film 86.

After the through-holes and the rewirings are formed, the color filters 15 and the on-chip lenses 16 are formed. Finally, the glass protective substrate 18 is connected with the cavity-less structure using the glass sealing resin 17 to complete the solid-state imaging device 1.

Therefore, before forming the color filters 15 and the on-chip lenses 16, through holes that connect the wiring layer 83 of the logic substrate 11 to the wiring layer 103 of the pixel sensor substrate 12 are formed and through holes and rewires that connect the solder balls 14 as the rear surface electrodes to the wiring layer 83 of the logic substrate 11 are formed. Therefore, the insulating film 86 can be formed at a high temperature equal to or higher than 250 degrees. Therefore, the insulating film 86 ensuring high reliability can be formed. In other words, the mechanical characteristics or insulation resistance of the insulating film 86 can be improved to the same level as that of the signal processing wiring.

< manufacturing method of ninth modification >

Next, a method of manufacturing the solid-state imaging device 1 having the structure according to the ninth modification shown in fig. 14 will be described with reference to fig. 101A to 103C.

First, as shown in fig. 101A, for example, after a multilayer wiring layer 102 forming a part of a control circuit 22 and the like is formed in a region to be each chip section of a silicon substrate (silicon wafer) 101 having a thickness of about 600 μm, a temporary bonding substrate 251 is attached to an upper surface of the multilayer wiring layer 102.

Next, as shown in fig. 101B, after the silicon substrate 101 is thinned, the photodiode 51 of each pixel 32 is formed in a predetermined region within the silicon substrate 101. A color filter 15 and an on-chip lens 16 are formed on the upper side of the photodiode 51.

Next, as shown in fig. 101C, a glass protective substrate 18 is connected to the cavity-less structure using a glass sealing resin 17 on the upper surface of the silicon substrate 101 on which the on-chip lenses 16 are formed. Then, after the glass surface protective film 252 is formed on the upper surface of the glass protective substrate 18, the temporary bonding substrate 251 is peeled off. For example, a SiN film or SiO can be used₂The film serves as a glass surface protective film 252.

The semi-finished pixel sensor substrate 12 is completed through the aforementioned processes.

On the other hand, on the logic substrate 11 side, as shown in fig. 102A, for example, after a multilayer wiring layer 82 for forming a logic circuit 23 is formed in a region to be each chip section of a silicon substrate (silicon wafer) 81 having a thickness of about 600 μm, a temporary bonding substrate 261 is attached to the upper surface of the multilayer wiring layer 82.

Next, as shown in fig. 102B, after thinning the silicon substrate 81, an opening 262 is formed at a position where a through-silicon via electrode 88 (not shown) is to be arranged and an insulating film (isolation film) 86 is formed on an inner wall surface of the opening 262 and an upper surface of the silicon substrate 81. The insulating film 86 is formed at a high temperature equal to or greater than 250 degrees in order to ensure high reliability.

After forming a barrier metal film and a Cu seed layer (not shown), the connection conductor 87 and the rewiring 90 are formed, as in the above-described manufacturing method of the basic structure.

In the ninth modification, dummy wirings 211 are also formed at predetermined positions on the insulating film 86 formed on the silicon substrate 81 to reduce the influence of unevenness at the time of Cu — Cu bonding.

As shown in fig. 102C, the temporary bonding substrate 261 is peeled off. Thereafter, as shown in fig. 102D, at this time, an adhesive 263 is applied to the rewiring 90 side of the silicon substrate 81 and the temporary bonding substrate 264 is pasted to the side.

The semi-finished logic substrate 11 is completed through the aforementioned processes.

As shown in fig. 103A, the semi-finished logic substrate 11 and the semi-finished pixel sensor substrate 12 are pasted together by metal bonding (Cu — Cu bonding) of the wiring layer 83A of the uppermost layer of the logic substrate 11 and the wiring layer 103c of the lowermost layer of the pixel sensor substrate 12.

Thereafter, as shown in fig. 103B, the temporary bonding substrate 264 temporarily stuck to the logic substrate 11 is peeled off and the adhesive 263 is also removed.

Finally, as shown in fig. 103C, after the solder mask 91 and the solder ball 14 are formed by the process described with reference to fig. 64 and 65, the glass surface protective film 252 is removed.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the ninth modification shown in fig. 14 is completed.

According to the manufacturing method of the ninth modification described above, the through-silicon via electrode 88 is formed in the process of the separate logic substrate 11 before the logic substrate 11 and the pixel sensor substrate 12 are pasted together. Therefore, when the through-silicon via electrode 88 is formed, the color filter 15 and the on-chip lens 16 having low heat resistance do not exist. Therefore, the insulating film 86 can be formed at a high temperature equal to or higher than 250 degrees. Therefore, the insulating film 86 ensuring high reliability can be formed.

According to the manufacturing method of the ninth modification, before the logic substrate 11 and the pixel sensor substrate 12 are pasted together, the color filter 15 and the on-chip lens 16 are formed when the deformation of the individual pixel sensor substrate 12 is small. Therefore, since misalignment (misalignment) between the color filter 15 and the on-chip lens 16 and the photodiode 51 can be made small, the percentage of defects caused by the misalignment can be reduced. Since the misalignment is small, the pixel size can be miniaturized.

According to the manufacturing method of the ninth modification, the dummy wirings 211 which are not related to transmission and reception of electric signals are formed in the same layer as the layer where the re-wirings 90 are formed. Therefore, the influence of unevenness due to the presence or absence of the rewiring 90 when Cu — Cu bonding is performed can be reduced.

<7 > tenth modification

Fig. 104 illustrates a detailed structure of the laminated substrate 13 of the solid-state imaging device 1 according to the tenth modification.

In a tenth modification shown in fig. 104, a part of the structure of the first modification shown in fig. 6 is modified.

In fig. 104, portions corresponding to those of the first modification shown in fig. 6 are denoted by the same reference numerals, and their description will be omitted.

In the first modification of fig. 6, two through-electrodes (i.e., the through-silicon via electrode 151 and the chip through-electrode 152) penetrate the silicon substrate 81. A connection wiring 153 for connecting the through-silicon via electrode 151 and the through-chip via electrode 152 is formed on the silicon substrate 81.

In contrast to this, in the tenth modification, as shown in fig. 104, the connection wiring 153 is formed to be embedded in the silicon substrate 81. The re-wiring 154 is omitted (or the connection wiring 153 and the re-wiring 154 are integrated), the solder ball 14 is formed on the connection wiring 153, and the upper surface of the silicon substrate 81 other than the solder ball 14 is covered with the insulating film 86. The rest of the structure is the same as that of the first modification shown in fig. 6.

In the tenth modification of fig. 104, the structure according to the first modification shown in fig. 6 is modified such that the connection wiring 153 is embedded in the silicon substrate 81. The same modification can also be applied to the structures according to the second to ninth modifications shown in fig. 7 to 14. For example, the connection wiring 106 or 182 may be configured to be embedded in the silicon substrate 101, or the rewiring 90 may be configured to be embedded in the silicon substrate 81.

<8 > manufacturing method of tenth modification

< first manufacturing method of tenth modification >

Next, a first manufacturing method of the solid-state imaging device 1 having the structure according to the tenth modification shown in fig. 104 will be described with reference to fig. 105A to 107E.

First, as shown in fig. 105A, the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are pasted so that their wiring layers face each other.

Next, as shown in fig. 105B, the silicon substrate 81 of the logic substrate 11 is thinned to a degree having a thickness that does not affect the device characteristics (for example, to a degree of about 20 micrometers to about 100 micrometers).

Next, as shown in fig. 105C, through-silicon via electrodes 151 connected to the wiring layer 83C of the logic substrate 11, chip through-electrodes 152 connected to the wiring layer 103C of the pixel sensor substrate 12, and connection wires 153 connecting the through-silicon via electrodes 151 and the chip through-electrodes 152 are formed at predetermined positions on the silicon substrate 81 on the logic substrate 11 side. The through-silicon via 151, the chip via 152, and the connection wiring 153 can be formed in the same steps as those described with reference to fig. 22 to 24.

Next, as shown in fig. 105D, the insulating film 86 is formed on the entire upper surfaces of the silicon substrate 81 and the connection wiring 153 of the logic substrate 11. The insulating film 86 includes, for example, a single-layer cic n layer, a stack of SiN and SiO, or a stack of SiCN and SiO, and functions as a passivation film that prevents diffusion of the material (e.g., Cu) of the connection wiring 153. The insulating film 86 can be formed at a high temperature of 250 degrees or more and 400 degrees or less. Therefore, an insulating film having good moisture resistance and good film quality can be formed, and thus corrosion and wiring reliability can be improved.

Next, as shown in fig. 105E, in the insulating film 86 formed on the entire upper surface of the silicon substrate 81 of the logic substrate 11 and the connection wiring 153, the region where the solder ball 14 is to be formed is opened, and thus the pad portion 600 is formed. Here, as shown in fig. 105E, in the pad portion 600, the thin insulating film 86 remains.

Next, as shown in fig. 106A, an insert material film 601 is formed in the pad portion 600 of the opening. In addition to the pad portion 600, the insertion material film 601 is also formed on the upper surface of the insulating film 86, and the formed insertion material film 601 is planarized by the CMP method. The insertion material film 601 may contain a material having etching selectivity to the insulating film 86. For example, an organic insulating film having a low dielectric constant, an SiO film, or an SiOC film can be used.

The insertion material film 601 can be formed by rotating and applying a resist. In this case, the planarization process by the CMP method is not necessary.

Next, after the temporary bonding substrate 602 is pasted to the insertion material film 601 side of the logic substrate 11 as shown in fig. 106B, all the substrates are turned upside down as shown in fig. 106C.

After thinning the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns as shown in fig. 106D, the color filter 15 and the on-chip lens 16 are formed on the thinned silicon substrate 101 as shown in fig. 106E. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 107A, after a glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, a glass protective substrate 18 is attached to the cavity-less structure.

After the glass protective substrate 18 is attached, the temporary bonding substrate 602 is separated as shown in fig. 107B.

Next, after all the substrates are turned upside down again as shown in fig. 107C, the embedding material film 601 is removed by, for example, wet etching using hydrofluoric acid (HF) as shown in fig. 107D. The thin insulating film 86 remaining in the pad portion 600 is removed by etching back the entire surface on which the insulating film 86 is formed, so that the connection wiring 153 is exposed.

When the insertion material film 601 is formed by spin-coating a resist in the process described with reference to fig. 106A, O can be passed₂The film 601 of insert material is removed (ashed) by plasma.

Finally, as shown in fig. 107E, the solder ball 14 is formed on the exposed portion of the connection wiring 153 by a solder ball mounting method or the like.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the tenth modification shown in fig. 104 is completed.

< second manufacturing method of tenth modification >

Next, a second manufacturing method of the solid-state imaging device 1 having the structure according to the tenth modification shown in fig. 104 will be described with reference to fig. 108A to 110E.

First, as shown in fig. 108A, the separately manufactured semi-finished logic substrate 11 and the pixel sensor substrate 12 are attached so that their wiring layers face each other.

Next, as shown in fig. 108B, the silicon substrate 81 of the logic substrate 11 is thinned to a degree having a thickness that does not affect the device characteristics (for example, to a degree of about 20 micrometers to about 100 micrometers).

Next, as shown in fig. 108C, through-silicon via electrodes 151 connected to the wiring layer 83C of the logic substrate 11, chip through-hole electrodes 152 connected to the wiring layer 103C of the pixel sensor substrate 12, and connection wires 153 connecting the through-silicon via electrodes 151 and the chip through-hole electrodes 152 are formed at predetermined positions on the silicon substrate 81 on the logic substrate 11 side. Through-silicon via 151, through-chip via 152, and connection wiring 153 can be formed in the same steps as those described with reference to fig. 22 to 24.

Next, as shown in fig. 108D, the insulating film 86 is formed on the entire upper surfaces of the silicon substrate 81 and the connection wiring 153 of the logic substrate 11. The insulating film 86 includes, for example, a single-layer cic n layer, a stack of SiN and SiO, or a stack of SiCN and SiO, and functions as a passivation film that prevents diffusion of the material (e.g., Cu) of the connection wiring 153. The insulating film 86 can be formed at a high temperature of 250 degrees or more and 400 degrees or less. Therefore, an insulating film having good moisture resistance and good film quality can be formed, and thus corrosion and wiring reliability can be improved.

Next, as shown in fig. 108E, in the insulating film 86 formed on the entire upper surface of the silicon substrate 81 of the logic substrate 11 and the connection wiring 153, an opening is formed in a region where the solder ball 14 is to be formed, and thus a pad portion 611 is formed. Here, in the second manufacturing method, as shown in fig. 108E, the insulating film 86 is removed in the pad portion 611 until the connection wiring 153 is exposed.

Next, as shown in fig. 109A, an insert material film 601 is formed in the pad portion 611 of the opening. The insertion material film 601 is formed on the upper surface of the insulating film 86 in addition to the pad portion 611, and the formed insertion material film 601 is planarized by the CMP method. The insertion material film 601 may contain a material having etching selectivity to the insulating film 86. For example, an organic insulating film having a low dielectric constant, an SiO film, or an SiOC film can be used.

Next, after the temporary bonding substrate 602 is pasted to the insertion material film 601 side of the logic substrate 11 as shown in fig. 109B, all the substrates are turned upside down as shown in fig. 109C.

After thinning the silicon substrate 101 of the pixel sensor substrate 12 to about 1 micron to about 10 microns as shown in fig. 109D, the color filter 15 and the on-chip lens 16 are formed on the thinned silicon substrate 101 as shown in fig. 109E. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 101 to suppress dark current.

Next, as shown in fig. 110A, after a glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the pixel sensor substrate 12 is formed, a pasted glass protective substrate 18 is bonded to the cavity-less structure.

After the glass protective substrate 18 is bonded, the temporary bonding substrate 602 is separated as shown in fig. 110B.

Next, after all the substrates are turned upside down again as shown in fig. 110C, the embedding material film 601 is removed by, for example, wet etching using hydrofluoric acid (HF) as shown in fig. 110D. Therefore, the connection wiring 153 is exposed in the pad portion 611.

Finally, as shown in fig. 110E, the solder ball 14 is formed on the exposed portion of the connection wiring 153 by a solder ball mounting method or the like.

According to the foregoing manufacturing method, the solid-state imaging device 1 in fig. 1 having the structure according to the tenth modification shown in fig. 104 is completed.

Even in the first and second manufacturing methods of the tenth modification described with reference to fig. 105A to 110E, the two through-electrodes (i.e., the through-silicon via electrode 151 and the through-chip via electrode 152) and the connection wiring 153 connecting the two through-electrodes to each other are formed before the color filter 15 and the on-chip lens 16 are formed. Therefore, the insulating film 86 can be formed at a high temperature equal to or higher than 250 degrees. Therefore, the insulating film 86 ensuring high reliability can be formed. In other words, the mechanical characteristics or insulation resistance of the insulating film 86 can be improved to the same level as that of the signal processing wiring.

Even in the solid-state imaging device 1 having the face-to-face structure of the first to tenth modifications described above, a structure in which the pads 431 are formed on the rewiring 90 as described with reference to fig. 40 to 42 can be employed. At this time, as shown in fig. 50, a barrier metal 461 for preventing a reaction with copper in the metal wiring can be formed below the rewiring 90.

< method for manufacturing conventional backside illumination type Structure >

Next, a method of manufacturing a solid-state imaging device having a conventional back surface irradiation type structure will be described with reference to fig. 111A to 113E.

First, as shown in fig. 111A, a photodiode (not shown) is formed in each pixel in a silicon substrate 701, which is a first semiconductor substrate, and pixel circuits of a control circuit, a logic circuit, and a pixel transistor (such as a first transfer transistor or an amplification transistor) are formed in the silicon substrate 701 and a multilayer wiring layer 704. The multilayer wiring layer 704 includes a plurality of wiring layers 702 and an interlayer insulating film 703 formed between the wiring layers 702.

Next, as shown in fig. 111B, a silicon substrate 705 (which is a second semiconductor substrate) is attached to an upper portion of the multilayered wiring layer 704 of the silicon substrate 701. Unlike the structure of the laminated substrate 13 described above, the wiring layer is not formed in the silicon substrate 705 (which is a second semiconductor substrate) as in the other manufacturing methods described above.

Next, as shown in fig. 111C, a rewiring 707 and a through-silicon via electrode 706 connected to the uppermost wiring layer 702 are formed at a predetermined position of the silicon substrate 705. Through-silicon via 706 and rewiring 707 can be formed in the same steps as those described with reference to fig. 22 to 24.

Next, as shown in fig. 111D, an insulating film 708 is formed on the entire upper surfaces of the silicon substrate 705 and the rewiring 707. The insulating film 708 includes, for example, a single-layer cic n layer, a stack of SiN and SiO, or a stack of SiCN and SiO, and functions as a passivation film for preventing diffusion of a material (e.g., Cu) of the rewiring 707. The insulating film 708 can be formed at a high temperature of 250 degrees or more and 400 degrees or less. Therefore, an insulating film having good moisture resistance and good film quality can be formed, and thus corrosion and wiring reliability can be improved.

Next, as shown in fig. 111E, in the insulating film 708 formed over the entire upper face of the silicon substrate 705 and the rewiring 707, an opening is formed in a region where a solder ball 716 (see fig. 113E) is to be formed, and thus a pad portion 709 is formed. Here, as shown in fig. 111E, a thin insulating film 708 remains in the pad portion 709.

Next, as shown in fig. 112A, a material film 710 is embedded in the pad portion 709 of the opening. In addition to the pad portion 709, an insertion material film 710 is also formed on the upper surface of the insulating film 708, and the formed insertion material film 710 is planarized by a CMP method. The material film for embedding 710 may contain a material having etching selectivity to the insulating film 708. For example, an organic insulating film having a low dielectric constant, an SiO film, or an SiOC film can be used.

The insertion material film 710 can be formed by rotating and coating a resist. In this case, the planarization process by the CMP method is not necessary.

Next, after the temporary bonding substrate 711 is attached to the insertion material film 710 side of the silicon substrate 705 as shown in fig. 112B, all the substrates are turned upside down as shown in fig. 112C.

After thinning the silicon substrate 701 to about 1 micron to about 10 microns as shown in fig. 112D, a color filter 712 and an on-chip lens 713 are formed on the thinned silicon substrate 701 as shown in fig. 112E. Further, a high dielectric film such as the high dielectric film 401 of fig. 15 may be formed on the upper surface of the thinned silicon substrate 701 to suppress dark current.

Next, as shown in fig. 113A, after a glass sealing resin 714 is applied to the entire surface of the on-chip lens 713 formed with the silicon substrate 701, a glass protective substrate 715 is bonded to the cavity-less structure.

After the glass protective substrate 715 is bonded, the temporary bonding substrate 711 is separated as shown in fig. 113B.

Next, after all the substrates are turned upside down again as shown in fig. 113C, the embedding material film 710 is removed by, for example, wet etching using hydrofluoric acid (HF) as shown in fig. 113D. The thin insulating film 708 remaining in the pad section 709 is removed by etching back the entire surface on which the insulating film 708 is formed, so that the rewiring 707 is exposed.

When the insertion material film 710 is formed by rotating and applying a resist in the process described with reference to fig. 112A, O can be passed₂The plasma removes (ashs) the film 710 of intercalation material.

Finally, as shown in fig. 113E, a solder ball 716 is formed at a portion where the redistribution lines 707 are exposed by a solder ball mounting method or the like.

As described above, when bonding a silicon substrate on which a wiring layer is not formed, instead of bonding a semiconductor substrate on which a wiring layer is formed in advance, the through-silicon via electrode 706 and the rewiring 707 can be formed before forming the color filter 712 and the on-chip lens 713, as in the other manufacturing methods described above. Therefore, since the insulating film 708 can be formed at a high temperature of 250 degrees or more, the insulating film 708 which ensures high reliability can be formed. In other words, the mechanical characteristics or insulation resistance of the insulating film 708 can be improved to the same level as that of the signal processing wiring.

<9. construction example of three-layer laminated substrate >

In each of the embodiments described above, the laminated substrate 13 of the solid-state imaging device 1 is configured to include two layers, i.e., the logic substrate 11 and the pixel sensor substrate 12.

However, as shown in fig. 114A and 114B, the laminated substrate 13 can also have a three-layer configuration in which a memory substrate 801 as a third semiconductor substrate is provided between the logic substrate 11 and the pixel sensor substrate 12.

A memory circuit 802 is formed in the memory substrate 801, and the memory circuit 802 stores data such as a signal generated in the pixel region 21 and a result of signal processing in the logic circuit 23.

Fig. 115A to 118 illustrate specific configuration examples when the laminated substrate 13 of the solid-state imaging device 1 is configured to include three layers.

Since the detailed configuration of each substrate of fig. 115A to 118 is the same as that described for the logic substrate 11 and the pixel sensor substrate 12 described above, their description will be omitted.

First, the configuration of the solid-state imaging device 1 having the three-layer structure shown in fig. 115A to 115C will be explained.

In all the solid-state imaging devices 1 shown in fig. 115A to 115C, the logic substrate 11 and the pixel sensor substrate 12 are laminated in a face-to-face structure. The storage substrate 801 interposed between the logic substrate 11 and the pixel sensor substrate 12 is laminated with the pixel sensor substrate 12 in a face-to-face structure.

The solid-state imaging device 1 shown in fig. 115A is manufactured in the following order.

First, the separately fabricated semi-finished pixel sensor substrate 12 and the storage substrate 801 are bonded so that their wiring layers face each other. Next, after the silicon substrate 812 of the memory substrate 801 is thinned, a through-silicon via electrode 813 penetrating the silicon substrate 812 of the memory substrate 801 and the multilayer wiring layer 811, a through-silicon via electrode 814 penetrating the silicon substrate 812, and a rewiring 821 connecting the through-silicon via electrode 813 and the through-silicon via electrode 814 are formed. Therefore, the multilayer wiring layer 102 of the pixel sensor substrate 12 is connected to the multilayer wiring layer 811 of the storage substrate 801 using the through-chip via electrode 813, the through-silicon via electrode 814, and the rewiring 821.

Next, the memory substrate 801 and the semi-finished logic substrate 11 are bonded together, and the chip through-electrodes 815 penetrating the silicon substrate 81 of the logic substrate 11 and the multilayer wiring layer 82, the through-silicon via electrodes 816 penetrating the silicon substrate 81, and the connection wirings 153 are formed. Therefore, the multilayer wiring layer 82 of the logic substrate 11 is connected to the multilayer wiring layer 811 of the memory substrate 801 using the through-chip via electrode 815, the through-silicon via electrode 816, and the connection wiring 153.

After the rewiring 154 and the insulating film 86 are formed on the upper portion of the connection wiring 153 of the logic substrate 11, the logic substrate 11 and a temporary bonding substrate (not shown) are bonded together.

A temporary bonding substrate (not shown) is used as a support substrate to thin the silicon substrate 101 of the pixel sensor substrate 12, and a color filter 15 and an on-chip lens 16 are formed on the upper surface of the thinned silicon substrate 101. Then, after the color filter 15 and the on-chip lens 16 are formed, the glass sealing resin 17 is stuck to the glass protective substrate 18.

Finally, the temporary bonding substrate bonded to the logic substrate 11 is separated and the solder mask 91 and the solder balls 14 are formed to complete the solid-state imaging device 1 shown in fig. 115A.

Next, the solid-state imaging device 1 shown in fig. 115B is manufactured in the following order

First, the separately manufactured semi-finished pixel sensor substrate 12 and the storage substrate 801 are pasted such that their wiring layers face each other. Next, after the silicon substrate 812 of the memory substrate 801 is thinned, a through-silicon via electrode 813 penetrating the silicon substrate 812 of the memory substrate 801 and the multilayer wiring layer 811, a through-silicon via electrode 814 penetrating the silicon substrate 812, and a rewiring 821 connecting the through-silicon via electrode 813 and the through-silicon via electrode 814 are formed. Therefore, the multilayer wiring layer 102 of the pixel sensor substrate 12 is connected to the multilayer wiring layer 811 of the storage substrate 801 using the through-chip via electrode 813, the through-silicon via electrode 814, and the rewiring 821.

Next, the memory substrate 801 and the semi-finished logic substrate 11 are bonded together by metal bonding (Cu — Cu) of the rewiring 821 of the memory substrate 801 and the wiring layer 83 of the multilayer wiring layer 82 of the logic substrate 11.

After the silicon substrate 81 of the logic substrate 11 is thinned, the through-silicon via electrode 816, the connection wiring 153, the rewiring 154, and the insulating film 86 penetrating the silicon substrate 81 are formed. Thereafter, a temporary bonding substrate (not shown) is attached to the insulating film 86 side of the logic substrate 11.

The silicon substrate 101 of the pixel sensor substrate 12 is thinned using a temporary bonding substrate (not shown) as a support substrate, and a color filter 15 and an on-chip lens 16 are formed on the upper surface of the thinned silicon substrate 101. Then, after the color filter 15 and the on-chip lens 16 are formed, the glass sealing resin 17 is stuck to the glass protective substrate 18.

Finally, the temporary bonding substrate bonded to the logic substrate 11 is separated and the solder mask 91 and the solder balls 14 are formed to complete the solid-state imaging device 1 shown in fig. 115B.

Next, the solid-state imaging device 1 illustrated in fig. 115C is manufactured in the following order.

First, the separately manufactured semi-finished pixel sensor substrate 12 and the storage substrate 801 are pasted so that their wiring layers face each other. The pixel sensor substrate 12 and the storage substrate 801 are bonded together by metal bonding (Cu — Cu) of the multilayer wiring layer 102 of the pixel sensor substrate 12 and the multilayer wiring layer 811 of the storage substrate 801.

Next, after the silicon substrate 812 of the memory substrate 801 is thinned, the through-silicon via electrode 814 penetrating the silicon substrate 812 of the memory substrate 801 and the rewiring 821 connected to the through-silicon via electrode 814 are formed.

Next, the semi-finished logic substrate 11 and the memory substrate 801 are bonded together by metal bonding (Cu — Cu) of the rewiring 821 of the memory substrate 801 and the wiring layer 83 of the multilayered wiring layer 82 of the logic substrate 11.

After the silicon substrate 81 of the logic substrate 11 is thinned, the through-silicon via electrode 816, the connection wiring 153, the rewiring 154, and the insulating film 86 penetrating the silicon substrate 81 are formed. Thereafter, a temporary bonding substrate (not shown) is attached to the insulating film 86 side of the logic substrate 11.

Next, a temporary bonding substrate (not shown) is used as a support substrate to thin the silicon substrate 101 of the pixel sensor substrate 12, and the color filter 15 and the on-chip lens 16 are formed on the upper surface of the thinned silicon substrate 101. Then, after the color filter 15 and the on-chip lens 16 are formed, the glass sealing resin 17 is stuck to the glass protective substrate 18.

Finally, the temporary bonding substrate bonded to the logic substrate 11 is separated and the solder mask 91 and the solder balls 14 are formed to complete the solid-state imaging device 1 shown in fig. 115C.

Next, the solid-state imaging device 1 having the three-layer structure shown in fig. 116A to 116C will be described in the following order.

In all the solid-state imaging devices 1 shown in fig. 116A to 116C, the storage substrate 801 and the logic substrate 11 are laminated in a face-to-face structure. The pixel sensor substrate 12 is also laminated to the logic substrate 11 in a face-to-face configuration.

The solid-state imaging device 1 shown in fig. 116A is manufactured in the following order.

First, the separately manufactured semi-finished logic substrate 11 and the storage substrate 801 are bonded so that their wiring layers face each other.

Next, after the silicon substrate 81 of the logic substrate 11 is thinned, the through-silicon via 816, the connection wiring 153, the rewiring 154, and the insulating film 86 are formed, and the logic substrate 11 and a temporary bonding substrate (not shown) are bonded together.

Next, after the silicon substrate 812 of the storage substrate 801 is thinned using a temporary bonding substrate (not shown) as a support substrate, the through-chip electrodes 813, the through-silicon electrodes 814, and the rewirings 821 are formed.

Next, after the pixel sensor substrate 12 is bonded to the upper side of the memory substrate 801 and the silicon substrate 101 of the pixel sensor substrate 12 is thinned, the chip through-electrode 842 penetrating the silicon substrate 101 of the pixel sensor substrate 12 and the multilayer wiring layer 102, the through-silicon via electrode 843 penetrating the silicon substrate 101, and the rewiring 844 connecting the chip through-silicon via electrode 842 with the through-silicon via electrode 843 are formed. Therefore, the multilayer wiring layer 102 of the pixel sensor substrate 12 is connected to the multilayer wiring layer 811 of the memory substrate 801 using the chip through-electrode 842, the through-silicon-via-electrode 843, and the rewiring 844. Thereafter, the color filter 15 and the on-chip lens 16 are formed and the glass protective substrate 18 is bonded by the glass sealing resin 17.

Finally, the temporary bonding substrate bonded to the logic substrate 11 is separated and the solder mask 91 and the solder balls 14 are formed to complete the solid-state imaging device 1 shown in fig. 116A.

Next, the solid-state imaging device 1 shown in fig. 116B is manufactured in the following order.

First, the separately manufactured semi-finished logic substrate 11 and the storage substrate 801 are bonded so that their wiring layers face each other.

Next, after thinning the silicon substrate 81 of the logic substrate 11 manufactured up to the half-finished state, the through-chip electrodes 815, the through-silicon via electrodes 816, the connection wirings 153, the rewirings 154, and the insulating film 86 are formed. Therefore, the multilayer wiring layer 82 of the logic substrate 11 is connected to the multilayer wiring layer 811 of the memory substrate 801 using the through-chip via electrode 815, the through-silicon via electrode 816, and the connection wiring 153. Thereafter, the logic substrate 11 is bonded to a temporary bonding substrate (not shown).

Next, after the silicon substrate 812 of the storage substrate 801 is thinned, the pixel sensor substrate 12 is bonded to the upper side of the thinned silicon substrate 812.

Next, a through-chip electrode 852 penetrating the entire pixel sensor substrate 12 and the silicon substrate 812 of the memory substrate 801, a through-silicon electrode 843 penetrating the silicon substrate 101 of the pixel sensor substrate 12, and a rewiring 844 connecting the through-chip electrode 852 and the through-silicon electrode 843 are formed. Therefore, the multilayer wiring layer 102 of the pixel sensor substrate 12 is connected to the multilayer wiring layer 811 of the memory substrate 801 using the chip through-electrode 852, the through-silicon-via electrode 843, and the rewiring 844. Thereafter, after the color filter 15 and the on-chip lens 16 are formed, the glass sealing resin 17 is attached to the glass protective substrate 18.

Finally, the temporary bonding substrate bonded to the logic substrate 11 is separated and the solder mask 91 and the solder balls 14 are formed to complete the solid-state imaging device 1 shown in fig. 116B.

Next, the solid-state imaging device 1 shown in fig. 116C is manufactured in the following order.

First, a first temporary bonding substrate (not shown) is pasted to the multilayer wiring layer 811 side of the semi-finished storage substrate 801, and the silicon substrate 812 of the storage substrate 801 is thinned using the first temporary bonding substrate as a support substrate.

Next, the pixel sensor substrate 12 manufactured up to a half-finished state is pasted to the storage substrate 801, the first temporary bonding substrate pasted to the other side of the storage substrate 801 is separated, and the through-chip electrode 813, the through-silicon electrode 814, and the rewiring 821 are formed. Therefore, the multilayer wiring layer 102 of the pixel sensor substrate 12 is connected to the multilayer wiring layer 811 of the storage substrate 801 using the through-chip via electrode 813, the through-silicon via electrode 814, and the rewiring 821.

Next, the logic substrate 11 manufactured up to a half-finished state is pasted to the storage substrate 801 on the rewiring 821 side, and the through-chip electrode 815, the through-silicon electrode 816, the connection wiring 153, the rewiring 154, and the insulating film 86 are formed. Therefore, the multilayer wiring layer 82 of the logic substrate 11 is connected to the multilayer wiring layer 811 of the memory substrate 801 using the through-chip via electrode 815, the through-silicon via electrode 816, and the connection wiring 153. Thereafter, the logic substrate 11 is pasted to a second temporary bonding substrate (not shown).

After thinning the silicon substrate 101 of the pixel sensor substrate 12, the color filter 15 and the on-chip lens 16 are formed and the glass protective substrate 18 is attached by the glass sealing resin 17.

Finally, the second temporary bonding substrate bonded to the logic substrate 11 is separated and the solder mask 91 and the solder balls 14 are formed to complete the solid-state imaging device 1 shown in fig. 116C.

Next, the solid-state imaging device 1 having the three-layer structure shown in fig. 117A to 117C will be described in the following order.

In the solid-state imaging device 1 shown in fig. 117A to 117C, the storage substrate 801 and the logic substrate 11 are also laminated in a face-to-face structure, and the pixel sensor substrate 12 is also laminated to the logic substrate 11 in a face-to-face structure.

The solid-state imaging device 1 shown in fig. 117A is manufactured in the following order.

First, the separately fabricated semi-finished logic substrate 11 and the storage substrate 801 are bonded so that their wiring layers face each other by metal bonding (Cu — Cu) of the multilayer wiring layer 82 of the logic substrate 11 and the multilayer wiring layer 811 of the storage substrate 801.

Next, after the silicon substrate 81 of the logic substrate 11 is thinned, the through silicon via 816, the connection wiring 153, the rewiring 154, and the insulating film 86 are formed. Thereafter, the logic substrate 11 is attached to a temporary bonding substrate (not shown).

Next, after the silicon substrate 812 of the memory substrate 801 is thinned using a temporary bonding substrate (not shown) as a supporting substrate, the through-silicon via electrode 814 and the rewiring 821 are formed.

Next, after the pixel sensor substrate 12 is bonded to the upper side of the memory substrate 801 and the silicon substrate 101 of the pixel sensor substrate 12 is thinned, the chip through-electrode 842 penetrating the silicon substrate 101 of the pixel sensor substrate 12 and the multilayer wiring layer 102, the through-silicon via electrode 843 penetrating the silicon substrate 101, and the rewiring 844 connecting the chip through-silicon via electrode 842 with the through-silicon via electrode 843 are formed. Therefore, the multilayer wiring layer 102 of the pixel sensor substrate 12 is connected to the multilayer wiring layer 811 of the memory substrate 801 using the chip through-electrode 842, the through-silicon-via-electrode 843, and the rewiring 844. Thereafter, the color filter 15 and the on-chip lens 16 are formed and the glass protective substrate 18 is attached using the glass sealing resin 17.

Finally, the temporary bonding substrate bonded to the logic substrate 11 is separated and the solder mask 91 and the solder balls 14 are formed to complete the solid-state imaging device 1 shown in fig. 117A.

Next, the solid-state imaging device 1 shown in fig. 117B is manufactured in the following order.

First, a first temporary bonding substrate (not shown) is pasted to the multilayer wiring layer 811 side of the semi-finished storage substrate 801, and the silicon substrate 812 of the storage substrate 801 is thinned using the first temporary bonding substrate as a support substrate.

Next, the pixel sensor substrate 12 manufactured up to a half-finished state is pasted to the storage substrate 801, the first temporary bonding substrate pasted to the other side of the storage substrate 801 is separated, and the through-chip electrode 813, the through-silicon electrode 814, and the rewiring 821 are formed. Therefore, the multilayer wiring layer 102 of the pixel sensor substrate 12 is connected to the multilayer wiring layer 811 of the storage substrate 801 using the through-chip via electrode 813, the through-silicon via electrode 814, and the rewiring 821.

Next, the logic substrate 11 of the semi-finished product and the storage substrate 801 are bonded so that their wiring layers face each other by metal bonding (Cu — Cu) of the multilayer wiring layer 82 of the logic substrate 11 and the multilayer wiring layer 811 of the storage substrate 801.

Next, after the silicon substrate 81 of the logic substrate 11 is thinned, the through silicon via 816, the connection wiring 153, the rewiring 154, and the insulating film 86 are formed. Thereafter, the logic substrate 11 is attached to a second temporary bonding substrate (not shown).

Then, the silicon substrate 101 of the pixel sensor substrate 12 is thinned using the second temporary bonding substrate as a support substrate. Thereafter, the color filter 15 and the on-chip lens 16 are formed and the glass protective substrate 18 is bonded using the glass sealing resin 17.

Finally, the second temporary bonding substrate bonded to the logic substrate 11 is detached and the solder mask 91 and the solder balls 14 are formed to complete the solid-state imaging device 1 shown in fig. 117B.

Next, the solid-state imaging device 1 illustrated in fig. 117C is manufactured in the following order.

First, the separately fabricated semi-finished logic substrate 11 and the storage substrate 801 are bonded so that their wiring layers face each other by metal bonding (Cu — Cu) of the multilayer wiring layer 82 of the logic substrate 11 and the multilayer wiring layer 811 of the storage substrate 801.

Next, after the silicon substrate 81 of the logic substrate 11 is thinned, the through silicon via 816, the connection wiring 153, the rewiring 154, and the insulating film 86 are formed. Thereafter, the logic substrate 11 is attached to a temporary bonding substrate (not shown).

Next, after the silicon substrate 812 of the memory substrate 801 is thinned, the through-silicon via electrode 814 and the rewiring 821 are formed.

Next, the pixel sensor substrate 12 is attached to the upper side of the storage substrate 801. That is, the storage substrate 801 is bonded to the pixel sensor substrate 12 by metal bonding (Cu — Cu) of the rewiring 821 of the storage substrate 801 to the multilayer wiring layer 102 of the pixel sensor substrate 12.

Thereafter, a color filter 15 and an on-chip lens 16 are formed on the upper surface of the silicon substrate 101 of the pixel sensor substrate 12, and a glass protective substrate 18 is bonded using a glass sealing resin 17.

Finally, the temporary bonding substrate bonded to the logic substrate 11 is separated and the solder mask 91 and the solder balls 14 are formed to complete the solid-state imaging device 1 shown in fig. 117C.

As described above with reference to fig. 115A to 117C, the solid-state imaging device 1 having a three-layer structure can be constructed by interposing the storage substrate 801 between the logic substrate 11 and the pixel sensor substrate 12 having an arrangement relationship of a face-to-face structure. In this case, as described above, the direction of the storage substrate 801 can be made to face either one of the face-to-face structure and the face-to-back structure with respect to the logic substrate 11.

Each structure shown in fig. 115A to 117C is configured as a structure in which: in which signals of the pixel sensor substrate 12 almost separated from the solder balls 14 are transferred to the logic substrate 11 via the storage substrate 801.

However, for example, as shown in fig. 118, it is also possible to form a through-chip electrode 861 that penetrates through the three semiconductor substrates (i.e., the logic substrate 11, the memory substrate 801, and the pixel sensor substrate 12). The signal of the pixel sensor substrate 12 can be transmitted to the logic substrate 11 side via the through-chip electrode 861. Similarly, a signal of the memory substrate 801 can be transmitted to the logic substrate 11 side through the through-chip electrode 861.

The number of stacked semiconductor substrates included in the solid-state imaging device 1 is not limited to two or three semiconductor substrates as described above, and four, five, or more semiconductor substrates may be stacked.

<10. application example to electronic apparatus >

The technique of the present invention is not limited to application to solid-state imaging devices. That is, the technique of the present invention can be applied to a general-purpose electronic apparatus using a solid-state imaging device for an image pickup unit (photoelectric conversion unit), such as an imaging apparatus (such as a digital still camera or a video camera), a portable terminal apparatus having an imaging function, or a copying machine using a solid-state imaging device for an image reading unit, or the like.

Fig. 119 is a block diagram illustrating a configuration example of an imaging device as an electronic device according to an embodiment of the present invention.

The imaging apparatus 300 of fig. 119 includes a solid-state imaging device 302 employing the configuration of the solid-state imaging device 1 of fig. 1 and a Digital Signal Processor (DSP) circuit 303 as a camera signal processing circuit. The imaging apparatus 300 further includes a frame memory 304, a display unit 305, a recording unit 306, an operation unit 307, and a power supply unit 308. The DSP circuit 303, the frame memory 304, the display unit 305, the recording unit 306, the operation unit 307, and the power supply unit 308 are connected to each other via a bus 309.

The solid-state imaging device 302 captures incident light (image light) of a subject, converts the light amount of the incident light formed as an image on an imaging surface into an electric signal in units of pixels, and outputs the electric signal as a pixel signal. The solid-state imaging device 1 of fig. 1 (i.e., a semiconductor package miniaturized by stacking a pixel sensor substrate 12 containing a pixel region 21 and a logic substrate 11 containing at least a logic circuit 23) can be used as the solid-state imaging device 302.

The display unit 305 is configured of, for example, a panel-type display device such as a liquid crystal panel or an organic EL (electroluminescence) panel, and displays a moving image or a still image taken by the solid-state imaging device 302. The recording unit 306 records a moving image or a still image captured by the solid-state imaging device 302 in a recording medium such as a hard disk or a semiconductor memory.

The operation unit 307 issues operation instructions related to various functions of the image forming apparatus 300 under the operation of the user. The power supply unit 308 appropriately supplies various amounts of power as operation power of the DSP circuit 303, the frame memory 304, the display unit 305, the recording unit 306, and the operation unit 307 to supply targets.

As described above, by using the solid-state imaging device 1 having any of the above-described structures as the solid-state imaging device 302, miniaturization can be achieved while enlarging the area of the photodiode PD and achieving high sensitivity. Therefore, even in the imaging device 300 such as a video camera, a digital camera, or a camera module for a mobile device such as a portable telephone, or the like, the miniaturization of the semiconductor package and the high-quality compatibility of the taken image can be achieved.

In the above-described example, the configuration of the CMOS solid-state imaging device has been described as an example of a semiconductor device in which the laminated substrate 13 configured by laminating the lower substrate 11 and the upper substrate 12 is packaged. However, the technique of the present invention is not limited to the solid-state imaging device, but can also be applied to a semiconductor device packaged for other usage purposes.

For example, the technique of the present invention is not limited to a solid-state imaging device that detects the light quantity distribution of incident light in visible light and images the light quantity distribution of the incident light as an image, but can also be generally applied to a solid-state imaging device that images incident infrared rays, X-rays, or photons as an image, or to a solid-state imaging device (physical quantity distribution detecting device) that detects the distribution of other physical quantities such as pressure or electrostatic capacity, such as a fingerprint detection sensor, and images the distribution as an image in a broad sense.

The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention without departing from the gist of the present invention.

For example, all of the above-described embodiments or a combination of some of the above-described embodiments may be employed.

The benefits described herein are merely exemplary and not limiting, and other benefits not described herein can also be obtained.

Embodiments of the present invention can be configured as follows.

(1)

A semiconductor device includes a first semiconductor substrate in which a pixel region in which pixel portions that perform photoelectric conversion are two-dimensionally arranged and a second semiconductor substrate in which a logic circuit for processing pixel signals output from the pixel portions is formed, the first semiconductor substrate and the second semiconductor substrate being laminated. A protective substrate for protecting the on-chip lenses is disposed on the on-chip lenses in the pixel region of the first semiconductor substrate, and a sealing resin is disposed between the protective substrate and the on-chip lenses.

(2)

In the semiconductor device described in (1) above, the laminated structure of the first semiconductor substrate and the second semiconductor substrate may be constructed by connecting the first semiconductor substrate and the second semiconductor substrate after forming wiring layers, respectively.

(3)

The semiconductor device described in (2) above may further include: a first through electrode that penetrates the first semiconductor substrate and is electrically connected to the wiring layer of the first semiconductor substrate; a second through electrode penetrating the first semiconductor substrate and the wiring layer of the first semiconductor substrate and electrically connected to the wiring layer of the second semiconductor substrate; a connection wiring electrically connecting the first through electrode to the second through electrode; and a third through electrode penetrating the second semiconductor substrate and electrically connecting an electrode section to a wiring layer of the second semiconductor substrate, the electrode section outputting the pixel signal to an outside of the semiconductor device.

(4)

In the semiconductor device described in (3) above, a solder mask may be formed on a surface where the electrode portion of the second semiconductor substrate is formed, and the solder mask is not formed in a region where the electrode portion is formed.

(5)

In the semiconductor device described in (3) above, an insulating film may be formed on a surface where the electrode portion of the second semiconductor substrate is formed, and the insulating film is not formed in a region where the electrode portion is formed.

(6)

The semiconductor device described in (2) above may further include: a first through electrode that penetrates the second semiconductor substrate and is electrically connected to the wiring layer of the second semiconductor substrate; a second through electrode penetrating the second semiconductor substrate and the wiring layer of the second semiconductor substrate and electrically connected to the wiring layer of the first semiconductor substrate; a connection wiring electrically connecting the first through electrode to the second through electrode; and a rewiring that electrically connects an electrode portion to the connection wiring, the electrode portion outputting the pixel signal to the outside of the semiconductor device.

(7)

The semiconductor device described in (2) above may further include: a through electrode penetrating the second semiconductor substrate and electrically connecting an electrode section to a wiring layer of the second semiconductor substrate, the electrode section outputting the pixel signal to an outside of the semiconductor device; and a rewiring that electrically connects the through electrode to the electrode portion. The wiring layer of the first semiconductor substrate and the wiring layer of the second semiconductor substrate may be connected by metal bonding of one or more of the wiring layers.

(8)

The semiconductor device described in (7) above may further include: a dummy wiring that is not electrically connected to any wiring layer in the same layer as the rewiring.

(9)

The semiconductor device described in (2) above may further include: a first through electrode that penetrates the second semiconductor substrate and is electrically connected to the wiring layer of the second semiconductor substrate; a second through electrode penetrating the second semiconductor substrate and the wiring layer of the second semiconductor substrate and electrically connected to the wiring layer of the first semiconductor substrate; a connection wiring electrically connecting the first through electrode to the second through electrode; a rewiring electrically connected to an electrode section that outputs the pixel signal to an outside of the semiconductor device; and a connection conductor connecting the rewiring to the connection wiring.

(10)

The semiconductor device described in (2) above may further include: a first through electrode that penetrates the first semiconductor substrate and is electrically connected to the wiring layer of the first semiconductor substrate; a second through electrode penetrating the first semiconductor substrate and the wiring layer of the first semiconductor substrate and electrically connected to the wiring layer of the second semiconductor substrate; a connection wiring electrically connecting the first through electrode to the second through electrode; and a third through electrode penetrating the first semiconductor substrate and the second semiconductor substrate and electrically connected to an electrode portion that outputs the pixel signal to an outside of the semiconductor device.

(11)

In the semiconductor device described in (10) above, a solder mask may be formed on a surface on which the electrode portion of the second semiconductor substrate is formed, and the solder mask is not formed in a region in which the electrode portion is formed.

(12)

In the semiconductor device described in (10) above, an insulating film may be formed on a surface where the electrode portion of the second semiconductor substrate is formed, and the insulating film is not formed in a region where the electrode portion is formed.

(13)

The semiconductor device described in (2) above may further include: a first through electrode that penetrates the first semiconductor substrate and is electrically connected to the wiring layer of the first semiconductor substrate and the wiring layer of the second semiconductor substrate; and a second through electrode penetrating the first and second semiconductor substrates and electrically connected to an electrode portion that outputs the pixel signal to an outside of the semiconductor device.

(14)

The semiconductor device described in (2) above may further include: a through electrode penetrating the first and second semiconductor substrates and electrically connected to an electrode portion that outputs the pixel signal to an outside of the semiconductor device. The wiring layer of the first semiconductor substrate and the wiring layer of the second semiconductor substrate may be connected by metal bonding of one or more of the wiring layers.

(15)

In the semiconductor device described in (1) above, the first semiconductor substrate and the second semiconductor substrate may be configured such that wiring layers thereof face each other.

(16)

In the semiconductor device described in (1) above, the first semiconductor substrate and the second semiconductor substrate may be configured such that a wiring layer side of the first semiconductor substrate faces a surface of the second semiconductor substrate opposite to a wiring layer side.

(17)

The semiconductor device described in (1) above may further include: an electrode section that outputs the pixel signal to an outside of the semiconductor device; and a rewiring that transfers the pixel signal from the second semiconductor substrate to the electrode portion.

(18)

In the semiconductor device described in (17) above, the electrode portion may be mounted on a pad portion formed on the re-wiring.

(19)

In the semiconductor device described in the above (17) or (18), a barrier metal film that reduces a reaction with a material of the electrode portion may be formed outside the re-wiring.

(20)

In the semiconductor device described in any one of (17) to (19) above, at least a part of the rewiring may be formed in a groove of the second semiconductor substrate.

(21)

In the semiconductor device described in (1) above, a third semiconductor substrate formed with a wiring layer may be interposed between the first semiconductor substrate and the second semiconductor substrate so that the semiconductor device includes three layers of semiconductor substrates.

(22)

In the semiconductor device described in the above (21), the third semiconductor substrate may be interposed between the first semiconductor substrate and the second semiconductor substrate so that a wiring layer formed in the third semiconductor substrate faces the wiring layer of the first semiconductor substrate.

(23)

In the semiconductor device described in the above (21), the third semiconductor substrate may be interposed between the first semiconductor substrate and the second semiconductor substrate so that a wiring layer formed on the third semiconductor substrate faces a wiring layer of the second semiconductor substrate.

(24)

In the semiconductor device described in (21) above, the third semiconductor substrate may include a memory circuit.

(25)

In the semiconductor device described in (24) above, the storage circuit may store at least one of a signal generated in the pixel region and data representing a pixel signal processed by the logic circuit.

(26)

A method of manufacturing a semiconductor device, the method comprising: connecting a first semiconductor substrate formed with a first wiring layer and a second semiconductor substrate formed with a second wiring layer so that the wiring layers of the two face each other; forming through electrodes electrically connected to the first wiring layer and the second wiring layer; forming a color filter and an on-chip lens; and a protective substrate that protects the on-chip lens is attached to the on-chip lens by a sealing resin.

(27)

A method of manufacturing a semiconductor device, the method comprising: forming a color filter and an on-chip lens on a surface opposite to a side of a first wiring layer on which the first semiconductor substrate is formed, on the first semiconductor substrate on which the first wiring layer is formed; forming a through electrode penetrating the second semiconductor substrate formed with the second wiring layer; and connecting the first semiconductor substrate on which the color filters and the on-chip lenses are formed to the second semiconductor substrate on which the through electrodes are formed such that wiring layers thereof face each other.

(28)

An electronic device, comprising: the photoelectric conversion device includes a first semiconductor substrate in which a pixel region in which pixel portions performing photoelectric conversion are two-dimensionally arranged and a second semiconductor substrate in which a logic circuit processing pixel signals output from the pixel portions is formed, the first semiconductor substrate and the second semiconductor substrate being laminated. A protective substrate for protecting the on-chip lens is disposed on the on-chip lens in the pixel region of the first semiconductor substrate, and a sealing resin is disposed between the on-chip lens and the protective substrate.

(A1)

A method of manufacturing a semiconductor device, the method comprising: bonding a first semiconductor substrate formed with a first wiring layer and a second semiconductor substrate formed with a second wiring layer so that the wiring layers of the two face each other; forming through electrodes electrically connected to the first wiring layer and the second wiring layer, and then forming color filters and on-chip lenses; and a protective substrate for protecting the on-chip lens is attached to the on-chip lens by a sealing resin.

(A2)

In the method of manufacturing a semiconductor device according to the above (a1), after the first semiconductor substrate and the second semiconductor substrate are bonded, a first through electrode and a second through electrode may be formed as the through electrodes. The first through electrode may penetrate the second semiconductor substrate and may be electrically connected to a wiring layer of the second semiconductor substrate. The second through electrode may penetrate the second semiconductor substrate and the wiring layer of the second semiconductor substrate and may be electrically connected to the wiring layer of the first semiconductor substrate.

(A3)

The method of manufacturing a semiconductor device described in (a2) above may further include: forming a connection wiring electrically connecting the first through electrode to the second through electrode; and forming a rewiring that electrically connects an electrode portion, which outputs a signal to the outside of the semiconductor device, to the connection wiring.

(A4)

In the manufacturing method of a semiconductor device recited in the above (a3), after the connection wiring and the rewiring are formed, a temporary bonding substrate may be attached to the connection wiring and the rewiring. The electrode portion may be formed after peeling the temporary bonding substrate.

(A5)

In the method of manufacturing a semiconductor device recited in (a4) above, the first semiconductor substrate may be thinned after the connection wiring and the rewiring are formed.

(A6)

In the method of manufacturing a semiconductor device of the above (a4) or (a5), the temporary bonding substrate may include a peeling layer, and a surface of the peeling layer of the temporary bonding substrate may be pasted. When the temporary bonding substrate is peeled, the peeled layer may remain after the peeling.

(A7)

In the manufacturing method of a semiconductor device of the above (a4) or (a5), the temporary bonding substrate may include a peeling layer and an insulating film, and a surface of the insulating film of the temporary bonding substrate may be pasted. When the temporary bonding substrate is peeled, the peeling layer and the insulating film may remain in the peeling.

(A8)

In the manufacturing method of the semiconductor device of any one of (a4) to (a7) above, the first semiconductor substrate may be thinned before the connection wiring and the rewiring are formed.

(A9)

In the method for manufacturing a semiconductor device according to (a4) above, at least a part of the connection wiring or the rewiring may be formed in an engraved portion of the first semiconductor substrate.

(A10)

In the manufacturing method of a semiconductor device recited in (a3) above, after the connection wiring and the re-wiring are formed, the electrode portion may be formed on the connection wiring and the re-wiring and a temporary bonding substrate may be attached to the electrode portion.

(A11)

In the method of manufacturing a semiconductor device recited in (a10) above, the first semiconductor substrate may be thinned after the connection wiring and the rewiring are formed.

(A12)

In the manufacturing method of a semiconductor device recited in the above (a10), the first semiconductor substrate may be thinned before the connection wiring and the rewiring are formed.

(A13)

In the method of manufacturing a semiconductor device recited in (a2) above, after a connection wiring electrically connecting the first through electrode to the second through electrode is formed simultaneously with the first through electrode and the second through electrode, a temporary bonding substrate may be bonded to the connection wiring. After peeling the temporary bonding substrate, a rewiring may be formed that electrically connects an electrode portion, which outputs a signal to the outside of the semiconductor device, to the connection wiring.

(A14)

In the method of manufacturing a semiconductor device recited in the above (a13), after the temporary bonding substrate is peeled off, a connection conductor that connects the connection wiring to the rewiring may be further formed.

(A15)

In the method of manufacturing a semiconductor device described in (a2) above, a rewiring connected to an electrode portion that outputs a signal to the outside of the semiconductor device may be formed together with the first through electrode and the second through electrode.

(A16)

In the manufacturing method of a semiconductor device described in the above (a15), after the rewiring is formed, an insulating film may be formed on the rewiring.

(A17)

In the method of manufacturing a semiconductor device recited in (a16) above, a portion of the insulating film in a region where the electrode portion on the rewiring is formed may be removed.

(A18)

In the method of manufacturing a semiconductor device recited in (a16) above, the insulating film in the region where the electrode portion on the rewiring is formed may be removed until the rewiring is exposed.

(A19)

In the method of manufacturing a semiconductor device recited in the above (a1), the first semiconductor substrate and the second semiconductor substrate may be bonded by metal bonding of the wiring layer, and a through electrode penetrating the second semiconductor substrate may be formed.

(A20)

In the manufacturing method of the semiconductor device described in the above (a19), the rewiring connected to the electrode portion that outputs a signal to the outside of the semiconductor device may be formed together with the through electrode, and then the first semiconductor substrate may be thinned.

(A21)

In the method of manufacturing a semiconductor device described in (a19) above, the first semiconductor substrate may be thinned before forming the rewiring connected to an electrode portion that outputs a signal to the outside of the semiconductor device together with the through electrode.

(A22)

In the method of manufacturing a semiconductor device according to the above (a1), after the first semiconductor substrate and the second semiconductor substrate are bonded, a first through electrode and a second through electrode may be formed as the through electrode. The first through electrode may penetrate the first semiconductor substrate and may be electrically connected to a wiring layer of the first semiconductor substrate. The second through electrode may penetrate the first semiconductor substrate and the wiring layer of the first semiconductor substrate and may be electrically connected to the wiring layer of the second semiconductor substrate.

(A23)

In the method of manufacturing a semiconductor device according to the above (a22), a third through-electrode that penetrates the first semiconductor substrate and the second semiconductor substrate and is electrically connected to an electrode portion that outputs a signal to the outside of the semiconductor device may be formed simultaneously with the first through-electrode and the second through-electrode.

(A24)

In the method of manufacturing a semiconductor device of the above (a22) or (a23), after the on-chip lens is formed, a temporary bonding substrate may be stuck to the on-chip lens. After peeling the temporary bonding substrate, the protective substrate may be connected by the sealing resin.

(A25)

In the method of manufacturing a semiconductor device recited in (a2) above, a third through-electrode may be formed before the first semiconductor substrate and the second semiconductor substrate are bonded and then the first through-electrode and the second through-electrode are formed as the through-electrodes. The first through electrode may penetrate the first semiconductor substrate and may be electrically connected to a wiring layer of the first semiconductor substrate. The second through electrode may penetrate the first semiconductor substrate and the wiring layer of the first semiconductor substrate and may be electrically connected to the wiring layer of the second semiconductor substrate. The third through electrode may penetrate the second semiconductor substrate and may be electrically connected to a wiring layer of the second semiconductor substrate.

(A26)

In the method of manufacturing a semiconductor device according to the above (a1), after the first semiconductor substrate and the second semiconductor substrate are bonded, a first through electrode and a second through electrode may be formed as the through electrodes. The first through electrode may penetrate the first semiconductor substrate and may be electrically connected to a wiring layer of the first semiconductor substrate and a wiring layer of the second semiconductor substrate. The second through electrode may penetrate the first semiconductor substrate and the second semiconductor substrate and may be electrically connected to an electrode portion that outputs a signal to the outside of the semiconductor device.

(A27)

In the manufacturing method of the semiconductor device recited in the above (a1), the first semiconductor substrate and the second semiconductor substrate may be bonded by metal bonding of the wiring layer. The through electrode may be formed to penetrate the first semiconductor substrate and the second semiconductor substrate and electrically connected to an electrode portion that outputs a signal to the outside of the semiconductor device.

(A28)

In the manufacturing method of the semiconductor device described in the above (a1), the rewiring connected to the electrode portion that outputs a signal to the outside of the semiconductor device may be formed by a damascene method.

(A29)

In the method of manufacturing a semiconductor device described in (a1) above, the rewiring connected to the electrode portion that outputs a signal to the outside of the semiconductor device may be formed by a semi-additive method.

(B1)

A method of manufacturing a semiconductor device, the method comprising: bonding a first semiconductor substrate formed with a first wiring layer and a second semiconductor substrate formed with a second wiring layer so that the first wiring layer of the first semiconductor substrate faces a surface of the second semiconductor substrate opposite to the second wiring layer side; forming through electrodes electrically connected to the first wiring layer and the second wiring layer, and then forming color filters and on-chip lenses; and a protective substrate that protects the on-chip lens is attached to the on-chip lens by a sealing resin.

(B2)

In the method of manufacturing a semiconductor device according to the above (B1), after the first semiconductor substrate and the second semiconductor substrate are bonded, a first through electrode and a second through electrode may be formed as the through electrodes. The first through electrode may penetrate the first semiconductor substrate and may be electrically connected to a wiring layer of the first semiconductor substrate. The second through electrode may penetrate the second semiconductor substrate and the wiring layer of the second semiconductor substrate and may be electrically connected to the wiring layer of the first semiconductor substrate.

(B3)

The method of manufacturing a semiconductor device described in (B1) or (B2) above may further include: after the protective substrate is connected to the sealing resin, a rewiring connected to an electrode portion that outputs a signal to the outside of the semiconductor device is formed.

(B4)

In the method of manufacturing a semiconductor device described in (B3) above, after the second semiconductor substrate is thinned, a light-shielding film may be formed on a bonding surface with the first semiconductor substrate.

(B5)

The method of manufacturing a semiconductor device described in (B2) above may further include: forming a rewiring connected to an electrode portion that outputs a signal to the outside of the semiconductor device before the first semiconductor substrate and the second semiconductor substrate are bonded.

(B6)

In the manufacturing method of the semiconductor device described in the above (B5), a pad portion that is formed of a predetermined connection conductor and that is connected to the electrode portion that outputs a signal to the outside of the semiconductor device is formed on the rewiring.

(B7)

In the manufacturing method of a semiconductor device described in the above (B6), the pad portion and the rewiring may be connected by a via hole.

(B8)

The method of manufacturing a semiconductor device described in (B1) above may further include: forming an electrode portion that outputs a signal to the outside of the semiconductor device and a rewiring connected to the electrode portion before bonding the first semiconductor substrate and the second semiconductor substrate.

(B9)

In the manufacturing method of the semiconductor device described in the above (B1), the rewiring connected to the electrode portion that outputs a signal to the outside of the semiconductor device may be formed by a damascene method.

(B10)

In the method of manufacturing a semiconductor device described in (B1) above, the rewiring connected to the electrode portion that outputs a signal to the outside of the semiconductor device may be formed by a semi-additive method.

(C1)

A method of manufacturing a semiconductor device, the method comprising: forming a color filter and an on-chip lens on a surface opposite to a first wiring side on which a first semiconductor substrate is formed, in the first semiconductor substrate on which a first wiring layer is formed; forming a through electrode penetrating a second semiconductor substrate in the second semiconductor substrate on which a second wiring layer is formed; and bonding the first semiconductor substrate on which the color filters and the on-chip lenses are formed and the second semiconductor substrate on which the through electrodes are formed such that wiring layers thereof face each other.

(C2)

In the manufacturing method of the semiconductor device recited in the above (C1), the first semiconductor substrate and the second semiconductor substrate may be bonded by metal bonding of the first wiring layer and the second wiring layer.

(C3)

In the manufacturing method of the semiconductor device recited in the above (C2), after the color filter and the on-chip lens are formed on the surface opposite to the side where the first wiring layer of the first semiconductor substrate is formed, a protective substrate that protects the on-chip lens may be connected to the on-chip lens by a sealing resin.

(C4)

The method of manufacturing a semiconductor device described in (C3) above may further include: forming a protective film on a surface of the protective substrate.

(C5)

In the method of manufacturing a semiconductor device recited in (C1) above, when the through electrode penetrating the second semiconductor substrate is formed in the second semiconductor substrate, a rewiring electrically connected to an electrode portion that outputs a signal to the outside of the semiconductor device may also be formed.

(C6)

In the method of manufacturing a semiconductor device recited in the above (C5), a dummy wiring that is not electrically connected to any wiring layer and is located in the same layer as the rewiring may also be formed.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and changes may be made within the scope of the appended claims or their equivalents depending on design requirements and other factors.

REFERENCE SIGNS LIST

1 solid-state imaging device

11 lower substrate (logic substrate)

12 Upper substrate (Pixel sensor substrate)

13 laminated substrate

15 color filter

16 on-chip lens

17 glass sealing resin

18 glass protective substrate

21 pixel region

22 control circuit

23 logic circuit

32 pixels

51 photodiode

81 silicon substrate

83 wiring layer

86 insulating film

88 through-silicon via

91 welding mask

101 silicon substrate

103 wiring layer

105 chip through electrode

106 connecting wiring

109 through-silicon via

151 silicon through electrode

152 chip through electrode

153 connecting wiring

154 rewiring

171 connecting conductor

181 chip through electrode

191 chip through electrode

211 dummy wiring

300 image forming apparatus

302 solid-state imaging device

421 cover film

431 pad

441 insulating film

443 through hole

801 storage substrate