阅读说明：本技术 面板和拼接屏 (Panel and spliced screen ) 是由 刘超 冯莎 王莉莉 汪楚航 王静 贾明明 翟明 孙海威 时凌云 于 2021-09-15 设计创作，主要内容包括：本公开提供一种面板和拼接屏,属于显示技术领域。本公开的面板包括阵列基板、连接基板和驱动电路板。阵列基板包括第一基底、多条信号线和设置在所述周边区的多条侧边走线,侧边走线沿所述多个侧表面中的至少一个弯折设置,侧边走线和所述信号线一一对应,每条侧边走线的一端和一条信号线连接,每条侧边走线的另一端位于第二表面。连接基板包括第二基底,多个连接垫和多个焊盘,每个连接垫的一端通过连接线与一个焊盘连接,每个连接垫的另一端与一条侧边走线的另一端连接。驱动电路板设置在阵列基板与连接基板之间,驱动电路板与焊盘连接。(The utility model provides a panel and concatenation screen belongs to and shows technical field. The panel of the present disclosure includes an array substrate, a connection substrate, and a driving circuit board. The array substrate comprises a first substrate, a plurality of signal wires and a plurality of side wires arranged on the peripheral area, wherein the side wires are arranged along at least one of the side surfaces in a bending mode, the side wires correspond to the signal wires one to one, one end of each side wire is connected with one signal wire, and the other end of each side wire is located on the second surface. The connecting substrate comprises a second substrate, a plurality of connecting pads and a plurality of bonding pads, one end of each connecting pad is connected with one bonding pad through a connecting line, and the other end of each connecting pad is connected with the other end of one side routing line. The driving circuit board is arranged between the array substrate and the connecting substrate and connected with the welding plate.)

1. A panel is characterized by comprising an array substrate, a connecting substrate and a driving circuit board; the array substrate comprises a first surface, a second surface and a plurality of side surfaces, wherein the first surface and the second surface are oppositely arranged, the side surfaces are connected with the first surface and the second surface, and the first surface comprises a functional element area and a peripheral area which is arranged around the functional element area; the array substrate comprises a first substrate, a plurality of signal lines and a plurality of side wires arranged on the peripheral area, wherein the side wires are arranged along at least one of the side surfaces in a bending mode, the side wires correspond to the signal lines one to one, one end of each side wire is connected with one signal line, and the other end of each side wire is located on the second surface;

the connecting substrate comprises a second substrate, a plurality of connecting pads and a plurality of bonding pads; one end of each connecting pad is connected with one bonding pad through a connecting line, and the other end of each connecting pad is connected with the other end of one side routing line;

the driving circuit board is arranged between the array substrate and the connecting substrate, and the driving circuit board is connected with the welding plate.

2. The panel of claim 1, wherein the material of the second substrate is a flexible material.

3. The panel of claim 2, wherein the material of the second substrate comprises polyimide or poly terephthalic acid.

4. The panel of claim 3, wherein the connection substrate further comprises a first buffer layer on a side of the second substrate adjacent to the array substrate.

5. The panel according to claim 4, wherein the connection substrate further comprises a support pad located between the first buffer layer and the connection pad, and an orthographic projection of the support pad on the second substrate covers an orthographic projection of the connection pad on the connection substrate.

6. The panel according to claim 5, wherein the thickness of the supporting pad is equal to 0.3-0.8 times the thickness of the driving circuit board.

7. Panel according to claim 5, characterized in that the material of the support pad is epoxy.

8. The panel of claim 5, wherein the connection substrate further comprises a second buffer layer covering the first buffer layer, the second buffer layer and the support pad at least partially overlapping in an orthographic projection of the first buffer layer, the second buffer layer comprising a material comprising silicon nitride, silicon oxide, or silicon oxynitride.

9. The panel according to claim 4, wherein the connection substrate further comprises an insulating layer on a side of the first buffer layer away from the second substrate, and an orthographic projection of the insulating layer, the connection pad, and the pad on the second substrate overlap.

10. The panel according to claim 8, wherein the connection substrate further comprises an insulating layer on a side of the second buffer layer away from the second substrate, and an orthographic projection of the insulating layer, the connection pad, and the pad on the second substrate overlap.

11. The panel of claim 1, wherein the panel comprises a protective layer, and the protective layer comprises a first protective layer covering the first surface of the array substrate, a second protective layer covering the connection substrate, and a third protective layer covering the side traces.

12. The panel according to any one of claims 1 to 11, wherein the connection substrate includes a stiffening layer on a side of the second base away from the array substrate.

13. The panel according to claim 12, wherein the stiffening layer has an opening between the connection pad and the pad in an orthographic projection of the second substrate.

14. The panel of claim 1, wherein the functional element region comprises a plurality of light emitting devices arranged in an array, and the light emitting devices are millimeter light emitting diodes Mini LEDs or Micro diodes Micro LEDs.

15. A tiled screen comprising a plurality of panels according to claims 1-14.

Technical Field

The utility model belongs to the technical field of show, concretely relates to panel and concatenation screen.

Background

At present, Micro Light Emitting Diode (Micro LED) display technology is being developed day by day, due to its outstanding advantages: the volume is miniature, the power consumption is low, the color saturation is high, the reaction speed is high, the service life is long, and the like, so that the investment research of the majority of scientific and technological workers is attracted. However, the development of Micro LED displays in high resolution and large size is hindered because the massive transfer technology has not been developed. The capacity of the existing mass transfer technology corresponds to television-level and large screen display, and the seamless splicing display technology can make up the defects of the existing mass transfer technology to realize large screen display. In order to realize true seamless splicing in a Micro LED spliced display screen, front signals, such as data voltage signals, of a display panel and end connection pads of a source driver are LED to the back of the display panel through a Side wiring (Side wiring) technology to perform chip bonding (IC bonding) and the like.

Disclosure of Invention

The present disclosure is directed to at least one of the problems of the prior art, and provides a panel and a tiled screen.

In a first aspect, an embodiment of the present disclosure provides a panel, including an array substrate, a connection substrate, and a driving circuit board; the array substrate comprises a first surface, a second surface and a plurality of side surfaces, wherein the first surface and the second surface are oppositely arranged, the side surfaces are connected with the first surface and the second surface, and the first surface comprises a functional element area and a peripheral area which is arranged around the functional element area; the array substrate comprises a first substrate, a plurality of signal lines and a plurality of side wires arranged on the peripheral area, wherein the side wires are arranged along at least one of the side surfaces in a bending mode, the side wires correspond to the signal lines one to one, one end of each side wire is connected with one signal line, and the other end of each side wire is located on the second surface;

the connecting substrate comprises a second substrate, a plurality of connecting pads and a plurality of bonding pads; one end of each connecting pad is connected with one bonding pad through a connecting line, and the other end of each connecting pad is connected with the other end of one side routing line;

the driving circuit board is arranged between the array substrate and the connecting substrate, and the driving circuit board is connected with the welding plate.

Optionally, the material of the second substrate is a flexible material.

Optionally, the material of the second substrate comprises polyimide, poly terephthalic acid.

Optionally, the connection substrate further includes a first buffer layer, and the first buffer layer is located on one side of the second substrate close to the array substrate.

Optionally, the connection substrate further includes a support pad, the support pad is located between the first buffer layer and the connection pad, and an orthographic projection of the support pad on the second substrate covers an orthographic projection of the connection pad on the connection substrate.

Optionally, the thickness of the supporting pad is equal to 0.3-0.8 times the thickness of the driving circuit board.

Optionally, the material of the support pad is epoxy resin.

Optionally, the connection substrate further includes a second buffer layer covering the first buffer layer, the second buffer layer and the support pad at least partially overlap in an orthographic projection of the first buffer layer, and a material of the second buffer layer includes silicon nitride, silicon oxide, or silicon oxynitride.

Optionally, the connection substrate further includes an insulating layer, the insulating layer is located on a side of the first buffer layer away from the second substrate, and the insulating layer, the connection pad, and an orthographic projection portion of the pad on the second substrate overlap.

Optionally, the connection substrate further includes an insulating layer, the insulating layer is located on a side of the second buffer layer away from the second substrate, and the insulating layer, the connection pad, and an orthographic projection portion of the pad on the second substrate overlap.

Optionally, the panel includes a protection layer, where the protection layer includes a first protection layer covering the first surface of the array substrate, a second protection layer covering the connection substrate, and a third protection layer covering the side traces.

Optionally, the connection substrate includes a stiffening layer, and the stiffening layer is located on a side of the second substrate away from the array substrate.

Optionally, the stiffening layer has an opening in an orthogonal projection of the second substrate, between the connection pad and the pad in the orthogonal projection of the second substrate.

Optionally, the functional element region includes a plurality of light emitting devices arranged in an array, and the light emitting devices are millimeter light emitting diodes Mini LEDs or Micro diodes Micro LEDs.

In a second aspect, the embodiment of the present disclosure provides a spliced screen, which is formed by splicing the panels.

Drawings

FIG. 1 is a schematic illustration of an area of an exemplary panel;

FIG. 2 is a schematic diagram of an exemplary panel construction;

FIG. 3 is a schematic diagram of a pixel circuit in an exemplary panel;

FIG. 4 is a top view of a panel provided by embodiments of the present disclosure;

FIG. 5 is a cross-sectional view of the faceplate of FIG. 4 taken along the line A-A';

FIG. 6 is a top view of the structure of the connection substrate in the panel shown in FIG. 5;

FIG. 7 is a flow chart of a method for manufacturing a panel according to an embodiment of the present disclosure;

fig. 8 to 23 are schematic structural views of a panel corresponding to steps in another panel manufacturing method according to an embodiment of the present disclosure.

Detailed Description

For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In order to clarify the specific structure of the display panel in the embodiment of the present invention, first, as shown in fig. 1, a schematic diagram of distribution of each part area of an exemplary display panel is provided, where the display panel includes a display area AA and a side routing connection area BA, where the side routing connection area BA is located at least one side of the display panel, the display area AA of the display panel in the schematic diagram in fig. 1 is located in a middle area, and the side routing connection area BA is located at upper and lower sides of the display panel; the side routing connection area BA on the upper side of the display panel is used for providing a first bonding pad and a second bonding pad of a data voltage signal for a pixel unit arranged in the display AA area; the first pads are located on a first surface of a substrate 10 of the display panel, and the second pads are located on a second surface of the substrate. The side trace connection area BA located on the lower side of the display panel is provided with a first pad and a second pad for providing power voltage signals for the shift register in the display area AA, where the power voltage signals include VDD high power voltage and VSS low power voltage, the first pad is located on the first surface of the substrate of the display panel, and the second pad is located on the second surface of the substrate. The structure of the side trace connection region BA for providing the data voltage signal to the pixel unit disposed in the display area AA is illustrated in the following embodiments of the present disclosure. The connection relationship between the first pad and the second pad is described below.

As shown in fig. 2, an exemplary structure of the display panel is given to facilitate better understanding of the display panel in the embodiment of the present invention. It should be understood that the display panel is not intended to limit the scope of the embodiments of the invention. The display panel is divided into a display area AA and a side routing connection area BA; the side-trace connection area BA is located on one side of the display area AA, for example: as shown in fig. 1, the side-trace connection area BA is located at the left side of the display area AA; wherein, a pixel circuit is disposed on the substrate 10 in the display area AA; the side surface wiring connection area BA is located, a first connection pad 91 is arranged on the substrate 10, a second connection pad 92 is arranged on one side of the substrate away from the first connection pad, the first connection pad 91 and the second connection pad 92 are connected through a side wiring 11 located on the side surface of the substrate 10, a third connection pad (not shown) which is on the same layer with the two connection pads is further arranged on the substrate 10, the third connection pad and the second connection pad 92 are connected through a flexible printed circuit board, and a driving chip IC (not shown) is bound on the third connection pad. The first connection pad 91 is connected to the pixel circuit through a signal introduction line to transmit an external signal supplied from the driving chip IC to the pixel circuit. Among them, the pixel circuit generally includes a pixel driving circuit and a light emitting device; as for the pixel driving circuit, it includes at least a switching transistor and a driving transistor, and of course, it may also include a threshold compensation transistor, a storage capacitor, and so on, as shown in fig. 3, which gives an exemplary pixel circuit. The pixel circuit specifically includes: it includes: a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a switching transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7, a first storage capacitor C1, and a light emitting device D; a first pole of the first transistor T1 is connected to the initial voltage signal terminal Vint, a second pole of the first Reset transistor T1 is connected to the second end of the first storage capacitor C1, the first pole of the threshold compensation transistor T2 and the control pole of the driving transistor T3, and the control pole of the first Reset transistor T1 is connected to the Reset signal terminal Reset; a second pole of the threshold compensating transistor T2 is connected to the second pole of the driving transistor T3 and the first pole of the second light emission controlling transistor T6, and a control pole of the threshold compensating transistor T2 is connected to the Gate line Gate; a first pole of the driving transistor T3 is connected to the first power voltage terminal VD; a first pole of the switching transistor T4 is connected to the Data line Data, and a second pole of the switching transistor T4 is connected to the second pole of the first light emission controlling transistor T5, the second pole of the second reset transistor T7, and the first pole of the first storage capacitor C1; a control electrode of the switching transistor T4 is connected to the gate line; a first electrode of the first light-emitting control transistor T5 is connected to a reference voltage signal terminal Vref, and a control electrode of the first light-emitting control transistor T5 is connected to a light-emitting control line EM; a second electrode of the second emission control transistor T6 is connected to the first electrode of the light emitting device D, and a control electrode of the second emission control transistor T6 is connected to the emission control line EM; a first pole of the second Reset transistor T7 is connected to the reference voltage signal terminal Vref, a control pole of the second Reset transistor T7 is connected to the Reset signal terminal Reset, and a second pole of the light emitting device is connected to the second power supply voltage terminal VSS.

The transistors used in the above description may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the transistors used are symmetrical, there is no difference between the source and the drain. In the embodiment of the present invention, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a control pole. In addition, the transistors can be divided into an N type and a P type according to the characteristic distinction of the transistors, when the P type transistors are adopted, the first pole is the source electrode of the P type transistor, the second pole is the drain electrode of the P type transistor, and when the grid electrode inputs a low level, the source electrode and the drain electrode are conducted; when an N-type transistor is adopted, the first electrode is the source electrode of the N-type transistor, the second electrode is the drain electrode of the N-type transistor, and when the grid electrode inputs a high level, the source electrode and the drain electrode are conducted. The transistors in the pixel circuit are all illustrated as N-type transistors, and it is conceivable that the implementation of P-type transistors is easily conceivable by those skilled in the art without creative efforts, and therefore, the present invention is also within the protection scope of the embodiments of the present invention.

The positional relationship of the respective film layers shown in the cross-sectional view of the display panel shown in fig. 2 is explained below, in which only a part of the devices, for example: the switching transistor T4, the driving transistor T3, and the like are explained, taking the switching transistor T4 and the driving transistor T3 as top gate thin film transistors as an example.

The display panel includes: a substrate 10, a buffer layer 1 located on the substrate 10; an active layer of the switching transistor T4 and an active layer of the driving transistor T3 on the same layer above the buffer layer 1; a gate insulating layer 2 on the active layer of the switching transistor T4 and the active layer of the driving transistor T3, the gate insulating layer 2 covering the display area AA and the side trace connection area BA; a gate of the switching transistor T4 and a gate of the driving transistor T3 located on the same layer above the gate insulating layer 2; a first insulating layer 3 on the layer where the gate of the switching transistor T4 and the gate of the driving transistor T3 are located, the first insulating layer 3 covering the display area AA and the side trace connection area BA; a source and a drain of the switching transistor T4, a source and a drain of the driving transistor T3, and a data line connected to the source of the switching transistor T4, which are located on the same layer and are located on the first insulating layer 3; a first planarization layer 61 on a layer on which the source and drain of the switching transistor T4, the source and drain of the driving transistor T3, and the data line connected to the source of the switching transistor T4 are located, the first planarization layer 61 being located only in the display area AA; a first passivation layer 62 on the first planarization layer 61, wherein the first passivation layer 62 covers the display area AA and the side trace connection area BA; the second sub-signal introducing line 502 and the first connecting electrode 8 which are positioned on the first planarizing layer 61 and are disposed at the same layer; the second sub signal introduction line 502 is connected to the data line through a first via hole penetrating the first planarization layer 61 and the first passivation layer 62, and the first connection electrode 8 is connected to the drain electrode of the driving transistor T3 through a third via hole penetrating the first planarization layer 61 and the first passivation layer 62; a second planarization layer 63 on the layer where the second sub-signal introduction line 502 and the first connection electrode 8 are located, the second planarization layer 63 being located only in the display area AA; a second passivation layer 64 on the second planarization layer 63, wherein the second passivation layer 64 covers the display area AA and the side trace connection area BA; a first sub-signal lead-in 501, a first pad 71, and a second pad 72, which are disposed on the same layer and on the second passivation layer 64; the first sub-signal lead-in 501 extends from the display area AA to the side trace connection area BA, and is connected to the second sub-signal lead-in 502 through a second via hole penetrating through the second planarization layer 63 and the second passivation layer 64; the first pad 71 is connected to the first connection electrode 8 through a fourth via hole penetrating the second planarization layer 63 and the second passivation layer 64; a third passivation layer 12 on the first sub-signal lead-in 501, the first pad 71 and the second pad 72, wherein the third passivation layer 12 covers the display area AA and the side trace connection area BA; a first connection pad 91 located on the side trace connection area BA and above the third passivation layer 12, wherein the first connection pad 91 is connected to the first sub-signal lead-in 501 through a fifth via penetrating through the third passivation layer 12; a first pole of the light emitting device D is connected to the first pad 71 through a sixth via hole penetrating the third passivation layer 12, and a second pole of the light emitting device D is connected to the second pad 72 through a seventh via hole penetrating the third passivation layer 12.

The Light Emitting device D may be a Micro inorganic Light Emitting Diode, and further may be a current type Light Emitting Diode, such as a Micro Light Emitting Diode (Micro LED) or a Mini Light Emitting Diode (Mini LED), and of course, the Light Emitting device D in the embodiment of the present disclosure may also be an Organic Light Emitting Diode (OLED). One of the first and second electrodes of the light emitting device D is an anode and the other is a cathode; in the embodiment of the present invention, the first electrode of the light emitting device D is taken as an anode, and the second electrode is taken as a cathode.

In the manufacturing process of the display panel shown in fig. 2, the first connection pad 91 on the front side of the display panel is electrically connected with the second connection pad 92 on the back side of the glass substrate 10 through the side routing 11, so that the binding region can be eliminated, and a frameless design is realized. In addition, the third connection pad bound with the driver chip IC is connected with the second connection pad 92 through a Flexible Printed Circuit (FPC), so that the problem that the FPC cannot be directly bonded on the back due to large manufacturing tolerance of the FPC exists.

Based on this, in order to solve at least one of the above technical problems, embodiments of the present disclosure provide a panel and a tiled screen, and the panel and the tiled screen of the display panel provided by embodiments of the present disclosure will be described in further detail with reference to the accompanying drawings and detailed description.

In a first aspect, the present general embodiment provides a panel, fig. 4 is a top view of a panel provided in an embodiment of the present disclosure, fig. 5 is a cross-sectional view of the panel shown in fig. 4 along a direction a-a', and fig. 6 is a structural top view of a connection substrate in the panel shown in fig. 5. As shown in fig. 4 to 6, the panel includes an array substrate 41, a connection substrate 42, and a driving circuit board 43. The array substrate 41 includes a first surface and a second surface disposed opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, where the first surface includes a functional element region a1 and a peripheral region B1 disposed around the functional element region a 1.

Specifically, the array substrate 41 includes the first substrate 411, a plurality of signal lines, and a plurality of side traces 45 disposed in the peripheral region B1, the side traces 45 are bent along at least one of the side surfaces, the side traces 45 are in one-to-one correspondence with the signal lines, one end of each side trace 45 is connected to one signal line, and the other end of each side trace 45 is located on the second surface of the array substrate 41.

The connection substrate 42 includes a second substrate 422, a plurality of connection pads 46 and a plurality of bonding pads 47, wherein one end of each connection pad 46 is connected to one bonding pad 47 through a connection line 461, and the other end of each connection pad 46 is connected to the other end of one side trace 45. The driving circuit board 43 is disposed between the array substrate 41 and the connection substrate 42, and the driving circuit board 43 is connected to the pad 47.

The signal line may be driven passively or actively. The functional element area a1 includes a plurality of light emitting devices 4131 arranged in an array, and the light emitting devices 4131 are millimeter light emitting diodes Mini LEDs or Micro diodes Micro LEDs.

The material of the first substrate 411 may be glass, resin, sapphire, quartz, or the like, the material of the second substrate 422 may be the same as or different from the material of the first substrate 411, and this embodiment is described by taking as an example the material of the first substrate 411 and the material of the second substrate 422 are different, in this embodiment, the material of the second substrate 422 is a flexible material, for example: polyimide, poly (terephthalic acid).

The manner of "connection" in the present embodiment includes contact connection, non-contact connection, electrical connection, and the like.

In the present embodiment, the number of the connection pads 46 is the same as that of the pads 47. The shape of the pad may be selected according to circumstances, for example, the shape of the pad 47 may be rectangular, quadrangular, circular, elliptical, or the like, and the present embodiment will be described by taking the shape of the pad 47 as a rectangular example.

In this embodiment, the side trace 45 is bent along at least one of the side surfaces, the side trace 45 corresponds to the signal lines one to one, one end of each side trace 45 is connected to one signal line, the other end of each side trace 45 is located on the second surface of the array substrate 41, one end of each connection pad 46 is connected to one pad 47 through a connection line 461, the other end of each connection pad 46 is connected to the other end of one side trace 45, and the driving circuit board 43 disposed between the array substrate 41 and the connection substrate 42 is connected to the pad 47, so that the problem of scratches caused by the turn-over operation in the existing side line process on the lines and the protective layer is effectively avoided. In addition, the cutting precision and the total spacing precision of the connecting substrate 42 can reach the um level, so that the problem of large tolerance of an FPC (flexible printed circuit) manufacturing process in a back surface Bonding process is solved, the reliability of a product is improved, and the connecting substrate can be applied to splicing application products at lower cost.

In some embodiments, as shown in fig. 5, the connection substrate 42 further includes a first buffer layer 423, and the first buffer layer 423 is located on one side of the second base 422 close to the array substrate 41. The material of the first buffer layer 423 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, and the like. In this embodiment, the first buffer layer 423 functions to isolate water and oxygen and increase adhesion.

In some embodiments, as shown in fig. 5, the connection substrate 42 further includes a support pad 48, the support pad 48 is located between the first buffer layer 423 and the connection pad 46, and an orthographic projection of the support pad 48 on the second substrate 422 covers an orthographic projection of the connection pad 46 on the connection substrate 42. In some embodiments, the thickness of support pad 48 is equal to 0.3-0.8 times the thickness of the drive circuit board. For example, the thickness of the driving circuit board is 10um, and the thickness of the support pad 48 is 5 um. In some embodiments, the material of support pad 48 includes, but is not limited to, epoxy, and the like. In this embodiment, the supporting pads 48 are arranged to provide an effective pressing height for the binding connection of the subsequent connecting pads 46, so as to eliminate the step difference. It should be noted that in some embodiments, the support pads 48 may not be provided, and may be connected by conductive balls in ACF conductive paste.

In some embodiments, as shown in fig. 5, the connection substrate 42 further includes a second buffer layer 424, the second buffer layer 424 covers the first buffer layer 423, the second buffer layer 424 and the support pad 48 at least partially overlap in an orthographic projection of the first buffer layer 423, and a material of the second buffer layer 424 includes, but is not limited to, silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the second buffer layer 424 is disposed to increase the adhesion between the bonding pads 46 and the supporting pads 48, so that the bonding pads 46 are more firmly fixed and the water and oxygen isolation capability is further enhanced.

In some embodiments, the connection substrate further includes an insulating layer on a side of the first buffer layer away from the second substrate, and the insulating layer, the connection pad, and an orthographic projection of the pad on the second substrate overlap. In some embodiments, as shown in fig. 5, the connection substrate 42 further includes an insulating layer 425, the insulating layer 425 is located on a side of the second buffer layer 424 away from the second substrate 422, and the orthogonal projections of the insulating layer 423, the connection pads 46 and the pads 47 on the second substrate 422 overlap. In the present embodiment, by providing the insulating layer 425, the corrosion of the connection substrate 42 by water oxygen can be prevented.

In some implementations, as shown in fig. 5, the connection substrate 42 includes a stiffening layer 421, and the stiffening layer 421 is located on a side of the second base 422 away from the array substrate 41. The stiffening layer 421 has an opening 49, and the opening 49 is located between the connecting pad 16 and the pad 47 in the orthographic projection of the second substrate 42. The material of the stiffening layer 421 includes, but is not limited to, glass or other toughened materials. In this embodiment, the third opening 49 is disposed on the connection substrate 42 including the stiffening layer 421, so that the height of the driving circuit board 43 can be prevented from interfering with the bonding connection between the connection pads 46 and the side traces 45.

In some embodiments, as shown in fig. 22, the panel further includes a protection layer, which includes a first protection layer 414 covering the first surface of the array substrate 41, a second protection layer 51 covering the connection substrate 42, and a third protection layer 50 covering the side traces 45. The material of the protective layer includes, but is not limited to, a black resin material, etc. In this embodiment, the second protective layer 51 covering the connection substrate 42 and the third protective layer 50 covering the side traces are provided to prevent the connection substrate 42 and the side traces 45 from being corroded by water and oxygen. By providing the first protective layer 414 covering the first surface of the array substrate 41, the display device 4131 can be prevented from being corroded by water oxygen, which delays the lifetime of the device.

In a second aspect, the present disclosure provides a tiled screen formed by splicing the panels.

In a third aspect, an embodiment of the present disclosure provides a method for manufacturing a panel, and fig. 7 is a flowchart of the method for manufacturing the panel, as shown in fig. 7, the method for manufacturing the panel includes:

s101, a display device layer 413 is formed on the first substrate 411.

S102, forming a plurality of side traces 45 in the peripheral region B1 of the panel, where the side traces 45 are bent along at least one of the side surfaces, the side traces 45 are in one-to-one correspondence with each other, one end of each side trace 45 is connected to one signal line, and the other end of each side trace 45 is located on the second surface of the array substrate 41.

S103, forming a plurality of connection pads 46 and a plurality of pads 47 on the second substrate 422, wherein the connection pads 46 are connected to the third connection pads 47 by fan-out connection lines.

S104, the side trace 45 is bound and connected through the connecting pad 46, and the driving circuit board 43 is bound and connected through the bonding pad 47.

In this embodiment, the side traces 45 are bent along at least one of the side surfaces, the side traces 45 correspond to the signal lines one to one, one end of each side trace 45 is connected to one signal line, the other end of each side trace 45 is located on the second surface of the array substrate 41, one end of each connection pad 46 is connected to one pad 47 through a connection line 461, the other end of each connection pad 46 is connected to the other end of one side trace 45, and the driving circuit board 43 disposed between the array substrate 41 and the connection substrate 42 is connected to the pad 47, so that the problem of scratches caused by the turn-over operation in the original side surface circuit process on the circuit and the protection layer is effectively avoided. In addition, the cutting precision and the TP precision of the connecting substrate 42 can reach the um level, so that the problem of large tolerance of an FPC (flexible printed circuit) manufacturing process in a back surface Bonding process is solved, the reliability of a product is improved, and the connecting substrate can be applied to splicing application products at lower cost.

In some implementations, before forming the plurality of connection pads 46 and the plurality of pads 47 on the second substrate 421, further comprising: support pads 48 are formed on second substrate 422, support pads 48 being disposed between connection pads 46 and second substrate 422. In the present embodiment, the supporting pad 48 formed on the second substrate 422 serves as a pad-up to provide an effective pressing height for the bonding connection of the subsequent bonding pad 47.

In some implementations, after forming support pad 48 on second substrate 422 further includes: a second buffer layer 424 is formed on a side of back-up pad 48 facing away from second substrate 422, and an orthographic projection of second buffer layer 424 on second substrate 421 covers an orthographic projection of back-up pad 48 on second substrate 422.

In the present embodiment, by forming the second buffer layer 424 on the side of the supporting pad 48 away from the second substrate 422, the adhesion between the connecting pad 46 and the supporting pad 48 can be increased, so that the connecting pad 46 is fixed more firmly.

In some embodiments, after forming the plurality of connection pads 46 and the plurality of pads 47 on the second substrate 422, further comprising: an insulating layer 425 is formed on the side of the layer where the connection pads 46 and the bonding pads 47 are located facing away from the second substrate 422.

In the present embodiment, by forming the insulating layer 425 on the side of the layer where the connection pads 46 and the pads 47 are located away from the second substrate 422, the connection substrate 42 can be prevented from being corroded by water and oxygen.

The following description will be given by way of example of a panel manufacturing method:

step 1, sequentially forming a display device layer 413 on a first glass substrate 411, and forming a connection pad 44 and a side trace 45 in a peripheral region B1 of a panel 41, wherein the side trace 45 is bent along at least one of a plurality of side surfaces, the connection pad 44 is arranged in one-to-one correspondence with a signal line, the side trace 45 is connected with the connection pad 44 in one-to-one correspondence, one end of each side trace 45 is connected with one connection pad 44, the other end of each side trace 45 is located on a second surface of the array substrate 41, and then covering the side trace 45 with a side protective OC glue 50. The LED is then soldered and coated with a black glue 414 (see fig. 8-10, where fig. 9 is a cross-sectional view of the structure shown in fig. 8). Wherein, the width of the OC glue 50 coated on the back of the first glass substrate 411 is about 0.2-1 mm. The lead-out length of the side trace 45 on the second surface of the array substrate 41 is 1mm to 4 mm.

Step 2, forming a second substrate 422 on the stiffening layer 421, forming a first buffer layer 423 on a side of the second substrate 422 away from the stiffening layer 421, where the second substrate 422 is made of a flexible material including but not limited to Polyimide (PI), and the first buffer layer 423 is made of SiN, SiO, or SiON. Thereafter, a support pad layer is formed on the first buffer layer 423, and the support pad 48 is formed through a patterning process (as shown in fig. 11 and 12, where fig. 12 is a top view of the structure shown in fig. 11). Wherein, the material of supporting pad layer can select for use epoxy resin class material, and the thickness of supporting pad 48 is about 5 ~ 10 um. It should be noted that the "patterning process" refers to a step of forming a structure having a specific pattern, and may be a photolithography process, where the photolithography process includes one or more steps of forming a material layer, coating a photoresist, exposing, developing, etching, and stripping the photoresist; of course, the "patterning process" may also be an imprinting process, an inkjet printing process, or other processes.

Step 3, forming a second buffer layer 424 on a side of the support pad 48 facing away from the second glass substrate 421 (as shown in fig. 13 and 14, fig. 14 is a top view of the structure shown in fig. 13), where the material of the second buffer layer 424 includes, but is not limited to, SiN, SiO, or SiON.

Step 4, forming a first metal layer on one side of the second buffer layer 424, which is far away from the second substrate 422, and forming a connecting pad 46 and a bonding pad 47 through a patterning process; then, a second metal layer is formed on the side of the layer where the connection pads 46 and the pads 47 are located away from the second substrate 422, and fan-out connection lines 461 connecting the connection pads and the pads 47 are formed through a patterning process (as shown in fig. 15 and 16, fig. 16 is a top view of the structure shown in fig. 15). The first metal layer and the second metal layer are made of Cu, Ti, Al or Mo, and the thicknesses of the connecting pad 46 and the bonding pad 47 are 0.6 um-2 um.

And 5, forming an insulating layer 425 on the side, away from the second substrate 422, of the layer where the connecting pads 46 and the bonding pads 47 are located (as shown in fig. 17), wherein the insulating layer 425 is made of SiN, and the thickness of the insulating layer 425 is 0.6-1 um.

Step 6, bonding the pad 47 and the driving circuit board 43 by using an anisotropic conductive film 80(ACF) (as shown in fig. 18 and fig. 6, fig. 6 is a top view of the structure shown in fig. 18), wherein the driving circuit board 43 may be a driver IC + FPC design, a COF + FPC design, or a single FPC design.

Step 7, forming a third opening 49 on the stiffening layer 421 by using a laser cutting process, wherein an orthographic projection of the third opening 49 on the second substrate 422 is located between the connection pad 46 and the bonding pad 47, and the second substrate 422 is exposed at the third opening 49 (as shown in fig. 19 and 20, fig. 20 is a schematic back view of the structure shown in fig. 19).

Step 8, bonding the connection substrate 42 to the back surface of the array substrate 41 with anisotropic conductive adhesive 80(ACF), wherein the connection pads 46 are bonded to the side traces 45 through the anisotropic conductive adhesive (as shown in fig. 21 and 22).

Step 9, spraying or depositing a water-oxygen-resistant material 51 on the panel for protection (see fig. 22 and 23, fig. 23 is a schematic view of the back side of the structure shown in fig. 22), such as a fluorinating agent or an ultra-low viscosity underfill epoxy glue.

It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.