阅读说明：本技术 显示基板及其制备方法、显示面板 (Display substrate, preparation method thereof and display panel ) 是由 卢辉 刘珂 张振华 石领 刘畅畅 刘烺 谢帅 于 2021-09-16 设计创作，主要内容包括：一种显示基板及其制备方法、显示面板,显示基板包括第一显示区,所述第一显示区包括多个第一子像素以及位于所述多个第一子像素之间的透光区域,所述第一子像素包括像素电路,所述像素电路包括多条信号线；在所述第一显示区的透光区域中,至少部分信号线的材料采用透明走线；在所述第一显示区的透光区域以外的区域,至少部分信号线的材料采用金属走线。本公开能够更好地实现高频显示。(A display substrate comprises a first display area, wherein the first display area comprises a plurality of first sub-pixels and light-transmitting areas positioned among the first sub-pixels, the first sub-pixels comprise pixel circuits, and the pixel circuits comprise a plurality of signal lines; in the light transmission area of the first display area, at least part of the signal wires are made of transparent wires; and in the area outside the light transmission area of the first display area, at least part of the signal wires are made of metal wires. The present disclosure enables better high frequency display.)

1. A display substrate is characterized by comprising a first display area, a second display area and a third display area, wherein the first display area comprises a plurality of first sub-pixels and light-transmitting areas positioned among the first sub-pixels;

the first sub-pixel includes a pixel circuit including a plurality of signal lines;

in the light transmission area of the first display area, at least part of the signal lines are made of transparent wires, and in the area outside the light transmission area of the first display area, at least part of the signal lines are made of metal wires.

2. The display substrate according to claim 1, wherein the plurality of signal lines include a scanning signal line, a data signal line, a first power supply line, an initial signal line, and a light-emitting signal line, wherein:

the scanning signal line, the data signal line, the first power line and the initial signal line are all metal wires, and the light-emitting signal line is a transparent wire.

3. The display substrate according to claim 2, wherein the display substrate comprises a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate;

in the first display area, the first power line and the data signal line are located on different conductive layers, and an overlapping area exists between an orthographic projection of the first power line on the substrate and an orthographic projection of the data signal line on the substrate.

4. The display substrate according to claim 2, wherein the display substrate comprises a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate; the scanning signal lines comprise a first scanning signal line and a second scanning signal line, and the first scanning signal line and the second scanning signal line are positioned on different conducting layers;

the pixel circuit includes a driving sub-circuit configured to generate a driving current between a second node and a third node under control of a first node, a data writing sub-circuit, and a first resetting sub-circuit; the data writing sub-circuit is configured to write a data signal to a second node under control of the first scanning signal line; the first reset sub-circuit is configured to reset the first node under control of the second scan signal line;

in the first display area, an overlapping area exists between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate.

5. The display substrate according to claim 4, wherein in the first display region, the second scan signal lines extend along a first direction, the second scan signal lines comprise bent portions arranged at intervals, the bent portions extend along a second direction, and the first direction and the second direction are orthogonal.

6. The display substrate according to claim 4, wherein in the first display region, there is a region where an orthogonal projection of the first scanning signal line on a base, an orthogonal projection of the initial signal line on a base, and an orthogonal projection of the second scanning signal line on a base overlap each other.

7. The display substrate according to claim 4, wherein on a plane perpendicular to the display substrate, the display substrate comprises a substrate, and a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a first transparent conductive layer and a second source-drain metal layer which are sequentially arranged on the substrate;

the semiconductor layer includes active layers of a plurality of transistors, at least one of the first gate metal layer and the second gate metal layer includes the second scanning signal line, the first source-drain metal layer includes the initial signal line and a first power line, the first transparent conductive layer includes the light emitting signal line, and the second source-drain metal layer includes the first scanning signal line and a data signal line.

8. The display substrate of claim 7, wherein the first display region comprises a plurality of columns of the first sub-pixels, and the semiconductor layers in the first sub-pixels of each column are staggered with the semiconductor layers in the first sub-pixels of adjacent columns in the row direction.

9. The display substrate according to claim 7, wherein in the first display region, the first scan signal line includes a plurality of branches, the first transparent conductive layer includes a fourteenth connection electrode and a fifteenth connection electrode, the first source-drain metal layer includes a sixth connection electrode and a seventh connection electrode, and the first gate metal layer includes a first connection electrode;

the sixth connecting electrode and the seventh connecting electrode are electrically connected with two ends of the first connecting electrode through via holes respectively, the fourteenth connecting electrode is electrically connected with the seventh connecting electrode through a via hole, and the fifteenth connecting electrode is electrically connected with the sixth connecting electrode through a via hole;

each branch of the first scanning signal line is electrically connected with the fourteenth connecting electrode and the fifteenth connecting electrode in two adjacent first sub-pixels in the same row through via holes.

10. The display substrate according to claim 7, wherein in the first display region, the initial signal line includes a plurality of branches, and the second gate metal layer includes a third connection electrode;

and each branch of the initial signal line is electrically connected with the third connecting electrodes in two adjacent first sub-pixels in the same row through a via hole.

11. The display substrate according to claim 7, wherein in the first display region, the first power line includes a plurality of branches, the first transparent conductive layer includes an eleventh connection electrode and a twelfth connection electrode, and the second source-drain metal layer includes a seventeenth connection electrode;

the seventeenth connecting electrode is electrically connected with the eleventh connecting electrode and the twelfth connecting electrode through via holes respectively, and each branch of the first power line is electrically connected with the eleventh connecting electrode and the twelfth connecting electrode in two adjacent first sub-pixels in the same column through via holes respectively.

12. A display panel, comprising: a display substrate as claimed in any one of claims 1 to 11.

13. A method for manufacturing a display substrate, the display substrate comprising a first display region, the first display region comprising a plurality of first sub-pixels and a light-transmissive region between the plurality of first sub-pixels, the first sub-pixels comprising a pixel circuit, the pixel circuit comprising a plurality of signal lines, the method comprising:

forming a semiconductor layer on a substrate;

forming a first gate metal layer on the semiconductor layer;

forming a second gate metal layer on the first gate metal layer;

forming a first source drain metal layer on the second gate metal layer;

forming a first transparent conducting layer on the first source drain metal layer;

forming a second source drain metal layer on the first transparent conductive layer; in the light-transmitting area of the first display area, the first transparent conductive layer is used for running at least part of signal lines; and in the region outside the light-transmitting region of the first display region, at least one of the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer is used for running at least part of signal lines.

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, and particularly relates to a display substrate, a preparation method thereof and a display panel.

Background

With the development of technology, the appearance of a mobile terminal is receiving more and more attention, wherein a large screen terminal with a relatively large screen is gradually one of the mainstream designs of the mobile terminal. The large screen terminal can promote the game entertainment experience of the user, is favorable for split screen display, and the science and technology of the whole machine is felt to be higher, so that stronger visual impact can be brought to the user.

At present, full-screen display has become the mainstream trend of mobile phone display. The design space of devices such as a camera, an infrared sensor, a receiver and the like is compressed by the full-face screen, and the devices such as the camera, the infrared sensor and the like are arranged below the display screen, so that the design of the display device with the current potential is formed.

Disclosure of Invention

The embodiment of the disclosure provides a display substrate, a preparation method thereof and a display panel, which can better realize high-frequency display.

The embodiment of the present disclosure provides a display substrate, including a first display area, where the first display area includes a plurality of first sub-pixels and a light-transmitting area located between the plurality of first sub-pixels, the first sub-pixels include a pixel circuit, and the pixel circuit includes a plurality of signal lines; in the light transmission area of the first display area, at least part of the signal lines are made of transparent wires, and in the area outside the light transmission area of the first display area, at least part of the signal lines are made of metal wires.

In some exemplary embodiments, the plurality of signal lines include a scan signal line, a data signal line, a first power supply line, an initial signal line, and a light emitting signal line, wherein:

the scanning signal line, the data signal line, the first power line and the initial signal line are all metal wires, and the light-emitting signal line is a transparent wire.

In some exemplary embodiments, the display substrate includes a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate;

in the first display area, the first power line and the data signal line are located on different conductive layers, and an overlapping area exists between an orthographic projection of the first power line on the substrate and an orthographic projection of the data signal line on the substrate.

In some exemplary embodiments, the display substrate includes a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate; the scanning signal lines comprise a first scanning signal line and a second scanning signal line, and the first scanning signal line and the second scanning signal line are positioned on different conducting layers;

the pixel circuit includes a driving sub-circuit configured to generate a driving current between a second node and a third node under control of a first node, a data writing sub-circuit, and a first resetting sub-circuit; the data writing sub-circuit is configured to write a data signal to a second node under control of the first scanning signal line; the first reset sub-circuit is configured to reset the first node under control of the second scan signal line;

in the first display area, an overlapping area exists between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate.

In some exemplary embodiments, in the first display region, the second scan signal line extends along a first direction, the second scan signal line includes bent portions arranged at intervals, the bent portions extend along a second direction, and the first direction and the second direction are orthogonal.

In some exemplary embodiments, in the first display area, there is a region where an orthogonal projection of the first scanning signal line on the substrate, an orthogonal projection of the initial signal line on the substrate, and an orthogonal projection of the second scanning signal line on the substrate overlap each other.

In some exemplary embodiments, on a plane perpendicular to the display substrate, the display substrate includes a substrate, and a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a first transparent conductive layer, and a second source-drain metal layer sequentially disposed on the substrate;

the semiconductor layer includes active layers of a plurality of transistors, at least one of the first gate metal layer and the second gate metal layer includes the second scanning signal line, the first source-drain metal layer includes the initial signal line and a first power line, the first transparent conductive layer includes the light emitting signal line, and the second source-drain metal layer includes the first scanning signal line and a data signal line.

In some exemplary embodiments, the first display region includes a plurality of columns of the first sub-pixels, and the semiconductor layer in the first sub-pixel of each column is staggered with the semiconductor layer in the first sub-pixel of an adjacent column in a row direction.

In some exemplary embodiments, in the first display region, the first scan signal line includes a plurality of branches, the first transparent conductive layer includes a fourteenth connection electrode and a fifteenth connection electrode, the first source-drain metal layer includes a sixth connection electrode and a seventh connection electrode, and the first gate metal layer includes a first connection electrode;

the sixth connecting electrode and the seventh connecting electrode are electrically connected with two ends of the first connecting electrode through via holes respectively, the fourteenth connecting electrode is electrically connected with the seventh connecting electrode through a via hole, and the fifteenth connecting electrode is electrically connected with the sixth connecting electrode through a via hole;

each branch of the first scanning signal line is electrically connected with the fourteenth connecting electrode and the fifteenth connecting electrode in two adjacent first sub-pixels in the same row through via holes.

In some exemplary embodiments, in the first display region, the preliminary signal line includes a plurality of branches, and the second gate metal layer includes a third connection electrode;

and each branch of the initial signal line is electrically connected with the third connecting electrodes in two adjacent first sub-pixels in the same row through a via hole.

In some exemplary embodiments, in the first display region, the first power line includes a plurality of branches, the first transparent conductive layer includes an eleventh connection electrode and a twelfth connection electrode, and the second source-drain metal layer includes a seventeenth connection electrode;

the seventeenth connecting electrode is electrically connected with the eleventh connecting electrode and the twelfth connecting electrode through via holes respectively, and each branch of the first power line is electrically connected with the eleventh connecting electrode and the twelfth connecting electrode in two adjacent first sub-pixels in the same column through via holes respectively.

The embodiment of the present disclosure also provides a display panel, including: the display substrate comprises the display substrate, the polarizer arranged on the light emergent side of the display substrate, the cover plate, the supporting layer arranged on the backlight side of the display substrate, the heat dissipation layer and the like.

The embodiment of the present disclosure also provides a method for manufacturing a display substrate, where the display substrate includes a first display area, the first display area includes a plurality of first sub-pixels and a light-transmitting area located between the plurality of first sub-pixels, the first sub-pixels include a pixel circuit, the pixel circuit includes a plurality of signal lines, and the method includes:

forming a semiconductor layer on a substrate;

forming a first gate metal layer on the semiconductor layer;

forming a second gate metal layer on the first gate metal layer;

forming a first source drain metal layer on the second gate metal layer; forming a first transparent conducting layer on the first source drain metal layer;

forming a second source drain metal layer on the first transparent conductive layer;

in the light-transmitting area of the first display area, the first transparent conductive layer is used for running at least part of signal lines; and in the region outside the light-transmitting region of the first display region, at least one of the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer is used for running at least part of signal lines.

According to the display substrate, the manufacturing method of the display substrate and the display panel, the high-frequency display is better realized by enabling part of signal wires in the first display area to be made of metal materials, in addition, the wires are overlapped through multiple signal wires, the occupied area of the metal wires in the first display area is effectively reduced, the light transmittance of the first display area is increased, and the camera shooting functions of self-shooting, face recognition and the like of the front camera are improved. In addition, the preparation process disclosed by the invention can be well compatible with the existing preparation process, and is simple in process implementation, easy to implement, high in production efficiency, low in production cost and high in yield.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not limit the disclosure.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a pixel arrangement structure of the display panel shown in FIG. 2;

fig. 4 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 5 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 4;

fig. 6a is a schematic plan view illustrating a display substrate according to an embodiment of the disclosure;

FIG. 6b is a cross-sectional view taken along line A-A of FIG. 6 a;

fig. 7 is a schematic structural diagram of a semiconductor layer of a display substrate according to an embodiment of the disclosure;

fig. 8 is a schematic structural diagram of a first conductive layer of a display substrate according to an embodiment of the disclosure;

fig. 9 is a schematic structural diagram of a second conductive layer of a display substrate according to an embodiment of the disclosure;

fig. 10 is a schematic structural diagram of a fourth insulating layer of a display substrate according to an embodiment of the disclosure;

fig. 11 is a schematic structural diagram of a third conductive layer of a display substrate according to an embodiment of the disclosure;

fig. 12 is a schematic structural diagram of a fifth insulating layer of a display substrate according to an embodiment of the disclosure;

fig. 13 is a schematic structural diagram of a fourth conductive layer of a display substrate according to an embodiment of the disclosure;

fig. 14 is a schematic structural diagram of a first planarization layer of a display substrate according to an embodiment of the disclosure;

fig. 15 is a schematic structural diagram of a fifth conductive layer of a display substrate according to an embodiment of the disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

Fig. 1 is a schematic structural diagram of a display panel. As shown in fig. 1, the OLED display panel may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emission signal lines (E1 to Eo), and a plurality of subpixels Pxij. In some exemplary embodiments, the timing controller may supply a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, may supply a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver, and may supply a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, n may be a natural number. The scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number. The light emitting signal driver may generate emission signals to be supplied to the light emitting signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emitting signal driver may sequentially supply the emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting signal driver may be configured in the form of a shift register, and may generate the light emitting signal in such a manner that the light emitting stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, and o may be a natural number. The pixel array may include a plurality of subpixels Pxij, each of which may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line, and i and j may be natural numbers. The subpixel Pxij may refer to a subpixel in which a transistor is connected to an ith scan signal line and to a jth data signal line.

Fig. 2 is a schematic plan view of a display panel according to an exemplary embodiment of the disclosure. As shown in fig. 2, the display panel according to the embodiment of the present invention includes a first display area 100 and a second display area 200, the first display area 100 includes a plurality of first sub-pixels and a plurality of light-transmitting regions, the second display area 200 includes a plurality of second sub-pixels, and the first sub-pixels satisfy at least one of the following conditions: the distribution density of the first sub-pixels is smaller than that of the second sub-pixels, and the area occupied by the first sub-pixels is smaller than that occupied by the second sub-pixels. Through the distribution density that reduces first sub-pixel in first display area 100 or reduce the shared area of first sub-pixel, increase the area of the light transmission region in first display area 100 to can set up the structure of imaging in the light transmission region, make first display area 100 both can be used for showing, improve the screen of display area and account for the ratio, also can image through the light transmission region, satisfy user's multiple demand.

In some exemplary embodiments, the relative positional relationship between the first display area 100 and the second display area 200 may be such that at least a part of the edge of the first display area 100 coincides with at least a part of the edge of the second display area 200, and the remaining part of the first display area 100 is surrounded by the second display area 200, and thus, the first display area 100 may be disposed at the edge of the display panel display area. In other exemplary embodiments, the relative position relationship between the second display area 200 and the first display area 100 may also be that the second display area 200 surrounds the first display area 100, so that the first display area 100 may be disposed inside the display panel display area, as shown in fig. 2. For example, the first display area 100 may be disposed at the upper left corner of the second display area 200. As another example, the first display area 100 may be disposed at the upper right corner of the second display area 200. For another example, the first display area 100 may be disposed at the left side of the second display area 200. For another example, the first display area 100 may be disposed at an upper side of the second display area 200. Of course, in practical applications, the specific position of the first display area 100 may be determined according to practical application environments, and is not limited herein.

In practical implementation, the shape of the first display area 100 may be a regular shape, such as a rectangle, and the top corner of the rectangle may be a right angle, or the top corner of the rectangle may also be an arc-shaped corner. For another example, the shape of the first display area 20 may be a trapezoid, which may be a regular trapezoid or an inverted trapezoid. In addition, the top angle of the trapezoid can be a regular included angle or can also be an arc-shaped angle. For another example, the shape of the first display area 100 may be set to an irregular shape. For example, the first display area 100 may be shaped in a droplet shape. Of course, in practical applications, the shape of the first display area 100 may be designed according to the shape of the elements disposed in the first display area 100, and is not limited herein.

In some exemplary embodiments, the area of the first display region 100 is smaller than the area of the second display region 200. Of course, in practical applications, the design may be performed according to the elements disposed in the first display area 100, and is not limited herein.

Fig. 3 is a schematic layout structure of a pixel array according to an exemplary embodiment of the disclosure. As shown in fig. 3, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first light emitting unit P1 emitting light of a first color, a second light emitting unit P2 emitting light of a second color, and a third light emitting unit P3 emitting light of a third color, and each of the first light emitting unit P1, the second light emitting unit P2, and the third light emitting unit P3 includes a pixel driving circuit and a light emitting element. The pixel driving circuits in the first, second, and third light emitting units P1, P2, and P3 are connected to the scan signal line, the data signal line, and the light emitting signal line, respectively, and the pixel driving circuits are configured to receive the data voltage transmitted from the data signal line and output corresponding currents to the light emitting elements under the control of the scan signal line and the light emitting signal line. The light emitting elements in the first, second, and third light emitting cells P1, P2, and P3 are respectively connected to the pixel driving circuit of the corresponding light emitting cell, and the light emitting elements are configured to emit light of corresponding brightness in response to a current output from the pixel driving circuit of the corresponding light emitting cell.

In an exemplary embodiment, the pixel unit P may include a red (R) light emitting unit, a green (G) light emitting unit, and a blue (B) light emitting unit therein, or may include a red light emitting unit, a green light emitting unit, a blue light emitting unit, and a white light emitting unit therein, and the disclosure is not limited thereto. In an exemplary embodiment, the shape of the light emitting unit in the pixel unit may be a rectangular shape, a diamond shape, a pentagon shape, or a hexagon shape. When the pixel unit includes three light emitting units, the three light emitting units may be arranged in a horizontal parallel, vertical parallel or delta-shaped manner, and when the pixel unit includes four light emitting units, the four light emitting units may be arranged in a horizontal parallel, vertical parallel or Square (Square) manner, which is not limited in this disclosure.

In some exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Fig. 4 is an equivalent circuit schematic diagram of a pixel driving circuit according to an exemplary embodiment of the disclosure. As shown in fig. 4, the pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7), 1 storage capacitor C, and a plurality of signal lines (a data signal line D, a first scanning signal line S1, a second scanning signal line S2, an initial signal line INIT, a first power supply line VDD, a second power supply line VSS, and a light emission control signal line E).

In some exemplary embodiments, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first pole of the first transistor T1 is connected to the initial signal line INIT, and the second pole of the first transistor T1 is connected to the first node N1. A gate electrode of the second transistor T2 is connected to the first scan signal line S1, a first pole of the second transistor T2 is connected to the third node N3, and a second pole of the second transistor T2 is connected to the first node N1. A gate electrode of the third transistor T3 is connected to the first node N1, a first pole of the third transistor T3 is connected to the second node N2, and a second pole of the third transistor T3 is connected to the third node N3. A gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first pole of the fourth transistor T4 is connected to the data signal line D, and a second pole of the fourth transistor T4 is connected to the second node N2. A gate electrode of the fifth transistor T5 is connected to the emission control signal line E, a first pole of the fifth transistor T5 is connected to the first power line VDD, and a second pole of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is connected to the light emission control signal line E, a first pole of the sixth transistor T6 is connected to the third node N3, and a second pole of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first pole of the light emitting element). A gate electrode of the seventh transistor T7 is connected to the first scan signal line S1 or the Reset control signal line Reset, a first pole of the seventh transistor T7 is connected to the initial signal line INIT, and a second pole of the seventh transistor T7 is connected to the fourth node N4. A first terminal of the storage capacitor C is connected to the first power supply line VDD, and a second terminal of the storage capacitor C is connected to the first node N1.

In some example embodiments, the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

In some exemplary embodiments, the second electrode of the light emitting element is connected to a second power line VSS, the second power line VSS continuously supplying a low level signal, and the first power line VDD continuously supplying a high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the display line, the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display line, that is, for the nth display line, the first scanning signal line S1 is S (n), the second scanning signal line S2 is S (n-1), and the second scanning signal line S2 of the display line and the first scanning signal line S1 in the pixel driving circuit of the previous display line may be the same signal line, so as to reduce the signal lines of the display panel and realize the narrow frame of the display panel.

In some exemplary embodiments, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E, and the initial signal line INIT all extend in a horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in a vertical direction.

In some exemplary embodiments, the light emitting element may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

Fig. 5 is a timing diagram illustrating an operation of the pixel driving circuit shown in fig. 4. The exemplary embodiment of the present disclosure will be explained below by the operation process of the pixel driving circuit illustrated in fig. 5, and the pixel driving circuit in fig. 4 includes 7 transistors (the first transistor T1 to the sixth transistor T7), 1 storage capacitor C1, and 7 signal lines (the DATA signal line DATA, the first scanning signal line S1, the second scanning signal line S2, the initial signal line INIT, the first power supply line VDD, the second power supply line VSS, and the light emitting signal line EM), and all of the 7 transistors are P-type transistors.

In an exemplary embodiment, the operation of the pixel driving circuit may include:

in the first phase a1, which is referred to as a reset phase, the signal of the second scan signal line S2 is a low level signal, and the signals of the first scan signal line S1 and the light-emitting signal line E are high level signals. The signal of the second scan signal line S2 is a low level signal, turning on the first transistor T1, and the signal of the initialization signal line INIT is provided to the first node N1, initializing the storage capacitor C, and clearing the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light emitting signal line E are high level signals, turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, and the OLED does not emit light at this stage.

In the second phase a2, which is referred to as a data write phase or a threshold compensation phase, the signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs a data voltage. At this stage, the second terminal of the storage capacitor C is at a low level, so the third transistor T3 is turned on. The signal of the first scan signal line S1 is a low level signal to turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output from the data signal line D is supplied to the first node N1 through the second node N2, the turned-on third transistor T3, the turned-on third node N3, and the turned-on second transistor T2, and the sum of the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, the voltage of the second terminal (the second node N2) of the storage capacitor C is Vdata + Vth, Vdata is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on to supply the initial voltage of the initial signal line INIT to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, clear the pre-stored voltage therein, complete the initialization, and ensure that the OLED does not emit light. The signal of the second scanning signal line S2 is a high level signal, turning off the first transistor T1. The signal of the light emitting signal line E is a high level signal, turning off the fifth transistor T5 and the sixth transistor T6.

In the third stage a3, referred to as a light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light emitting signal line E is a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power voltage output from the first power line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, thereby driving the OLED to emit light.

During the driving of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is Vdata + Vth, the driving current of the third transistor T3 is:

I＝K*(Vgs-Vth)²＝K*[(Vdata+Vth-Vdd)-Vth]²＝K*[(Vdata–Vdd)]²

where I is a driving current flowing through the third transistor T3, that is, a driving current driving the OLED, K is a constant, Vgs is a voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is a threshold voltage of the third transistor T3, Vdata is a data voltage output from the data signal line D, and Vdd is a power voltage output from the first power line Vdd.

As can be seen from the above formula, the current I flowing through the light emitting element is independent of the threshold voltage Vth of the third transistor T3, eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I, and ensuring uniformity of luminance.

Based on the working time sequence, the pixel circuit eliminates the residual positive charges of the light-emitting element after last light-emitting, realizes the compensation of the grid voltage of the third transistor, avoids the influence of the threshold voltage drift of the third transistor on the driving current of the light-emitting element, and improves the uniformity of the displayed image and the display quality of the display panel.

In the conventional pixel circuit design, the signal lines between the pixel circuits in the first display area are connected by transparent Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO) traces, but the transparent ITO or IZO traces have a large resistance value, which is very disadvantageous for high frequency display applications.

Fig. 6a is a schematic structural view of a display substrate in a first display region according to an embodiment of the disclosure, and fig. 6b is a cross-sectional view taken along a position a-a in fig. 6 a. As shown in fig. 6a and 6b, in the first display region, the plurality of first sub-pixels include pixel circuits (located in the non-light-transmitting region), the pixel circuits include a plurality of signal lines, adjacent pixel circuits are connected to each other through the signal lines, and each signal line is used for providing different signals for the pixel circuits; in the light transmission area of the first display area, at least part of the signal lines adopt transparent routing lines; at least part of the signal lines are metal wires in the area outside the light-transmitting area of the first display area.

In some exemplary embodiments, the plurality of signal lines include a scan signal line, a data signal line D, a first power supply line VDD, an initial signal line INIT, and a light emitting signal line E. The scanning signal line is used for providing scanning signals for the pixel circuit, the data signal line D is used for providing data signals for the pixel circuit, the first power line VDD is used for providing first power signals for the pixel circuit, the initial signal line INIT is used for providing initial signals for the pixel circuit, and the light-emitting signal line E is used for providing light-emitting control signals for the pixel circuit.

In some exemplary embodiments, the scan signal line, the data signal line D, the first power line VDD, and the initial signal line INIT are all metal wires, and the light emitting signal line E is a transparent wire.

In some exemplary embodiments, the display substrate includes a base 90 and a plurality of conductive layers on the base 90, the scan signal lines include a first scan signal line S1 and a second scan signal line S2, and the first scan signal line S1 and the second scan signal line S2 are on different conductive layers on a plane perpendicular to the display substrate.

In some exemplary embodiments, the pixel circuit includes a driving sub-circuit configured to generate a driving current between the second node and the third node under the control of the first node; the data writing sub-circuit is configured to write a data signal to the second node under the control of the first scanning signal line S1; the first reset sub-circuit is configured to reset the first node under the control of the second scanning signal line S2.

In some exemplary embodiments, the first scan signal line S1 and the second scan signal line S2 are both metal traces.

Because the loads of the first scanning signal line S1, the second scanning signal line S2, the data signal line D, the first power line VDD, the initial signal line INIT and other signal lines have a large influence on high frequency, the display substrate according to the embodiment of the disclosure changes ITO traces of the first scanning signal line S1, the second scanning signal line S2, the data signal line D, the first power line VDD, the initial signal line INIT and other signal lines into conventional metal traces, reduces the resistance of the signal traces, and is favorable for better high frequency display in the first display region; in addition, since the light emitting signal line E has less influence on high frequency display, transparent conductive traces such as ITO or IZO are still used without modification.

In some exemplary embodiments, as shown in fig. 7 to 15, on a plane perpendicular to a display substrate, the display substrate includes a substrate, and a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a first transparent conductive layer, and a second source-drain metal layer sequentially disposed on the substrate;

the semiconductor layer includes active layers of a plurality of transistors, at least one of the first gate metal layer and the second gate metal layer includes a second scan signal line S2, the first source-drain metal layer includes an initial signal line INIT and a first power supply line VDD, the first transparent conductive layer includes a light emitting signal line E, and the second source-drain metal layer includes a first scan signal line S1 and a data signal line D.

In some exemplary embodiments, as shown in fig. 7, the first display region includes a plurality of columns of first sub-pixels, and the semiconductor layer in the first sub-pixel of each column is staggered with the semiconductor layer in the first sub-pixel of an adjacent column in the first direction X.

In some exemplary embodiments, as shown in fig. 6a, in the first display region, there is an overlapping region of the orthogonal projection of the first scanning signal line S1 on the substrate and the orthogonal projection of the second scanning signal line S2 on the substrate. In this embodiment, the first scanning signal line S1 and the second scanning signal line S2 are overlapped and routed, so that the influence of the metal routing on the transmittance can be reduced to the greatest extent.

In some exemplary embodiments, as shown in fig. 8, in the first display region, the second scan signal line S2 extends along a first direction X (horizontal direction), the second scan signal line S2 includes bent portions arranged at intervals, the bent portions extend along a second direction Y (vertical direction), and the first direction X and the second direction Y are orthogonal.

In some exemplary embodiments, as shown in fig. 7 to 15, in the first display region, the first scan signal line includes a plurality of branches, the first transparent conductive layer includes a fourteenth connection electrode 44 and a fifteenth connection electrode 45, the first source-drain metal layer includes a sixth connection electrode 33 and a seventh connection electrode 34, the first gate metal layer includes the first connection electrode 11;

the sixth connection electrode 33 and the seventh connection electrode 34 are electrically connected to both ends of the first connection electrode 11 through via holes, respectively, the fourteenth connection electrode 44 is electrically connected to the seventh connection electrode 34 through a via hole, and the fifteenth connection electrode 45 is electrically connected to the sixth connection electrode 33 through a via hole;

each branch of the first scanning signal line S1 is electrically connected to the fourteenth connection electrode 44 and the fifteenth connection electrode 45 in two adjacent first sub-pixels of the same row through a via hole, respectively.

In some exemplary embodiments, as shown in fig. 7 to 15, in the first display region, there is a region where the orthographic projection of the first scanning signal line S1 on the substrate, the orthographic projection of the initial signal line INIT on the substrate, and the orthographic projection of the second scanning signal line S2 on the substrate overlap. In this embodiment, in order to reduce signal crosstalk caused by stacked traces of signals of the first scanning signal line S1 and the second scanning signal line S2, the display substrate according to the embodiment of the disclosure uses an intermediate layer of the two signal traces to trace the initial signal line INIT (direct current signal), so as to shield the influence of crosstalk to the greatest extent.

In some exemplary embodiments, in the first display region, the initial signal line INIT includes a plurality of branches, and the second gate metal layer includes the third connection electrode 21; each branch of the initial signal line INIT is electrically connected to the third connection electrodes 21 in the adjacent two first subpixels of the same row through a via hole, respectively.

In some exemplary embodiments, as shown in fig. 6a, in the first display region, there is an overlapping region where a forward projection of the first power line VDD on the substrate overlaps a forward projection of the data signal line D on the substrate. In this embodiment, the first power line VDD and the data signal line D are overlapped and routed, so that the influence of the metal routing on the transmittance can be reduced to the greatest extent.

In some exemplary embodiments, as shown in fig. 11 to 15, in the first display region, the first power line VDD includes a plurality of branches, the first transparent conductive layer includes an eleventh connection electrode 41 and a twelfth connection electrode 42, and the second source-drain metal layer includes a seventeenth connection electrode 51;

the seventeenth connection electrode 51 is electrically connected to the eleventh connection electrode 41 and the twelfth connection electrode 42 through via holes, respectively, and each branch of the first power line VDD is electrically connected to the eleventh connection electrode 41 and the twelfth connection electrode 42 in two adjacent first sub-pixels in the same column through via holes, respectively.

The structure of the display substrate according to the embodiments of the present disclosure is exemplified by the process of manufacturing the display substrate. The "patterning process" referred to in this disclosure includes processes of depositing a film layer, coating a photoresist, mask exposing, developing, etching, and stripping a photoresist. The deposition may employ any one or more selected from sputtering, evaporation and chemical vapor deposition, the coating may employ any one or more selected from spray coating and spin coating, and the etching may employ any one or more selected from dry etching and wet etching. "thin film" refers to a layer of a material deposited or coated onto a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. When the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The "a and B are disposed in the same layer" in the present disclosure means that a and B are simultaneously formed by the same patterning process. "the orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

In some exemplary embodiments, the process of preparing the display substrate shown in fig. 6a and 6b may include the steps of:

(1) a semiconductor layer pattern is formed on the substrate 90. Forming the semiconductor layer pattern on the substrate 90 includes: an insulating film is first deposited on the substrate 90 to form a pattern of a first insulating layer 91 covering the entire substrate 90. Subsequently, an active layer film is deposited and patterned through a patterning process to form a semiconductor layer pattern disposed on the first insulating layer 91, as shown in fig. 7. Among them, the semiconductor layer pattern of the first display region may include the active layer 10 of the first transistor T1, the active layer 20 of the second transistor T2, the active layer 30 of the third transistor T3, the active layer 40 of the fourth transistor T4, the active layer 50 of the fifth transistor T5, the active layer 60 of the sixth transistor T6, and the active layer 70 of the seventh transistor T7. In some example embodiments, the first, second, third, fourth, fifth, sixth, and seventh active layers 10, 20, 30, 40, 50, 60, and 70 may be a unitary structure connected to each other.

In some exemplary embodiments, the first active layer 10 may have a shape of a door frame, and the second active layer 20 may have a shape of a door frameIn the shape of the third active layer 30, the fourth active layer 40, the fifth active layer 50 and the sixth active layer 60, and the seventh active layer 70 may be in the shape of a dumbbell, and the shape of the third active layer 30 may be in the shape of a zigzag, and the shape of the fourth active layer 40 may be in the shape of a zigzag.

In some example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In some exemplary embodiments, the second region 102 of the first active layer 10 simultaneously serves as the second region 202 of the second active layer 20, i.e., the second region 102 of the first active layer 10 and the second region 202 of the second active layer 20 are connected to each other. The first region 301 of the third active layer 30 serves as both the second region 402 of the fourth active layer 40 and the second region 502 of the fifth active layer 50, i.e., the first region 301 of the third active layer 30, the second region 402 of the fourth active layer 40 and the second region 502 of the fifth active layer 50 are connected to each other. The second region 302 of the third active layer 30 serves as both the first region 601 of the sixth active layer 60 and the first region 201 of the second active layer 20, i.e., the second region 302 of the third active layer 30, the first region 601 of the sixth active layer 60 and the first region 201 of the second active layer 20 are connected to each other. The first region 101 of the first active layer 10 simultaneously serves as the first region 701 of the seventh active layer 70, i.e., the first region 101 of the first active layer 10 and the first region 701 of the seventh active layer 70 are connected to each other. The first region 401 of the fourth active layer 40, the first region 501 of the fifth active layer 50, the second region 602 of the sixth active layer 60, and the second region 702 of the seventh active layer 70 are separately provided.

In some exemplary embodiments, in the first display region 100, the plurality of first sub-pixels includes two or more columns, and the semiconductor layer of the first sub-pixel of each column is staggered with the semiconductor layer of the first sub-pixel of the adjacent column in the first direction. By arranging the semiconductor layers of the first sub-pixels of the adjacent columns in a staggered manner in the first direction, the distance (Margin) of the semiconductor layers of the first sub-pixels of the adjacent columns in the first direction is increased, so that light-transmitting areas for imaging on two sides of the first sub-pixels are larger.

In some example embodiments, the semiconductor layer may employ polycrystalline silicon (p-Si), that is, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor may all be LTPS thin film transistors.

After this process, the display substrate includes a first insulating layer 91 disposed on the substrate 90 and a semiconductor layer disposed on the first insulating layer 91, and the semiconductor layer may include active layers of a plurality of transistors.

(2) A first conductive layer pattern is formed. In some exemplary embodiments, the forming of the first conductive layer pattern may include: depositing a second insulating film and a first metal film in sequence on the substrate 90 on which the aforementioned patterns are formed, and patterning the first metal film through a patterning process to form a second insulating layer 92 covering the semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer 92, the first conductive layer pattern of the first display region at least including: the second scan signal line S2, the first connection electrode 11, the second connection electrode 12, and the first plate Ce1 of the storage capacitor are illustrated in fig. 8. In some example embodiments, the first conductive layer may be referred to as a first GATE metal (GATE1) layer.

In the embodiment of the present disclosure, the second scanning signal line S2 in the first display area is made of metal, so that the influence of the trace load on the high-frequency display can be reduced, and the high-frequency display can be better realized in the first display area.

In some exemplary embodiments, within each sub-pixel, the second scan signal line S2 is positioned at a side of the first connection electrode 11 distant from the first plate Ce1 of the storage capacitor, and the first plate Ce1 of the storage capacitor is disposed between the first connection electrode 11 and the second connection electrode 12.

In some exemplary embodiments, a region where the second scan signal line S2 overlaps the first active layer of the first transistor T1 serves as a gate electrode of the first transistor T1 dual gate structure.

In some exemplary embodiments, in the first display area 100, the second scan signal line S2 is a zigzag structure. Since the semiconductor layer of the first sub-pixel of each column and the semiconductor layer of the first sub-pixel of the adjacent column are staggered in the first direction in the first display region 100, and the second scan signal line S2 and the first active layer of the first transistor T1 in the first sub-pixel of one row include an overlapping region, the second scan signal line S2 has a zigzag structure.

In some example embodiments, a region where the first connection electrode 11 overlaps the fourth active layer of the fourth transistor T4 serves as a gate electrode of the fourth transistor T4. The first connection electrode 11 is provided with a gate block 11-1 protruded toward one side of the second scan signal line S2, an overlapping region where an orthographic projection of the gate block 11-1 on the substrate 90 and an orthographic projection of the second active layer of the second transistor T2 on the substrate 90 exist, and a region where the first connection electrode 11 and the gate block 11-1 overlap with the second active layer of the second transistor T2 serves as a gate electrode of the second transistor T2 dual gate structure. A region where the first connection electrode 11 overlaps the seventh active layer of the seventh transistor T7 serves as a gate electrode of the seventh transistor T7. That is, the gate electrode of the second transistor T2, the gate electrode of the fourth transistor T4, and the gate electrode of the seventh transistor T7 are connected to each other in an integrated structure.

In some exemplary embodiments, a region where the second connection electrode 12 overlaps with the fifth active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5, and a region where the second connection electrode 12 overlaps with the sixth active layer of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6. That is, the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 are connected to each other in an integrated structure.

In some exemplary embodiments, the first plate Ce1 may have a rectangular shape, corners of the rectangular shape may be chamfered, and an overlapping region exists between an orthographic projection of the first plate Ce1 on the substrate 90 and an orthographic projection of the third active layer of the third transistor T3 on the substrate 90. In some exemplary embodiments, the first plate Ce1 serves as a gate electrode of the third transistor T3 at the same time, a region of the third transistor T3 where the third active layer overlaps the first plate Ce1 serves as a channel region of the third transistor T3, and one end of the channel region is connected to the first region of the third active layer and the other end is connected to the second region of the third active layer.

In some exemplary embodiments, after the first conductive layer pattern is formed, the semiconductor layer may be subjected to a semiconducting process using the first conductive layer as a mask, the semiconductor layer in a region masked by the first conductive layer forms a channel region of each transistor, and the semiconductor layer in a region not masked by the first conductive layer is semiconducting, that is, both the first region and the second region of each active layer are semiconducting.

After this process, the display substrate includes a first insulating layer 91 disposed on the substrate 90, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, and a first conductive layer disposed on the second insulating layer 92, and the first conductive layer may include the second scan signal line S2, the first connection electrode 11, the second connection electrode 12, and the first plate Ce1 of the storage capacitor.

(3) Forming a second conductive layer pattern. In some exemplary embodiments, the forming of the second conductive layer pattern may include: depositing a third insulating film and a second metal film in sequence on the substrate 90 with the patterns, patterning the second metal film by using a patterning process, and forming a third insulating layer 93 covering the first conductive layer and a second conductive layer pattern disposed on the third insulating layer 93, wherein the second conductive layer pattern of the first display area at least includes: the second plate Ce2 of the storage capacitor and the third connection electrode 21 are shown in fig. 9. In some example embodiments, the second conductive layer may be referred to as a second GATE metal (GATE2) layer.

In some exemplary embodiments, within each sub-pixel, the third connection electrode 21 is positioned at a side of the second scan signal line S2 away from the first connection electrode 11, and the third connection electrode 21 is used to connect a subsequently formed initial signal line INIT.

In some exemplary embodiments, the outline of the second plate Ce2 may be rectangular with a notch H, corners of the rectangular shape may be chamfered, and an overlapping region exists between an orthographic projection of the second plate Ce2 on the substrate 90 and an orthographic projection of the first plate Ce1 on the substrate 90. The notch H may be located at a corner of the second pole plate Ce 2. The notch H may be polygonal, the notch H exposes the third insulating layer covering the first plate Ce1, and an orthographic projection of the first plate Ce1 on the substrate 90 overlaps with an orthographic projection of the notch H on the substrate 90. In some exemplary embodiments, the notch H is configured to receive a third via formed subsequently, the third via is located in the notch H and exposes the first plate Ce1, so that the second pole of the second transistor T2 formed subsequently is connected with the first plate Ce 1.

After this process, the display substrate includes a first insulating layer 91 disposed on the substrate 90, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, a first conductive layer disposed on the second insulating layer 92, a third insulating layer 93 covering the first conductive layer, and a second conductive layer disposed on the third insulating layer 93, where the second conductive layer includes at least the second plate Ce2 of the storage capacitor and the third connection electrode 21.

(4) The fourth insulating layer 94 is patterned. Forming the fourth insulating layer 94 pattern includes: depositing a fourth insulating film on the substrate 90 with the above structure, patterning the fourth insulating film by a patterning process, and forming a fourth insulating layer 94 pattern with a plurality of via holes, wherein the plurality of via holes include: the first via V1, the second via V2, the third via V3, the fourth via V4, the fifth via V5, the sixth via V6, the seventh via V7, the eighth via V8, the ninth via V9, the tenth via V10, the eleventh via V11, the twelfth via V12, the thirteenth via V13, and the fourteenth via V14, as shown in fig. 10.

In an exemplary embodiment, the fourth insulating layer in the first via hole V1 is etched away, exposing the surface of the second plate Ce2 of the storage capacitor, and is configured such that the second branch VDD-B2 of the first power line VDD formed later is electrically connected to the second plate Ce2 of the storage capacitor through the via hole.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via hole V2 are etched away to expose a surface of the first region 501 of the fifth active layer, configured such that the subsequently formed second branch VDD-B2 of the first power line VDD is connected to the first region 501 of the fifth active layer through the via hole.

In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the third via hole V3 are etched away to expose a surface of the first plate Ce1 of the storage capacitor, and configured such that the subsequently formed fourth connection electrode 31 is electrically connected to the first plate Ce1 of the storage capacitor through the via hole.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer and the second insulating layer within the fourth via hole V4 are etched away, exposing the surface of the second region 102 of the first active layer (also the second region 202 of the second active layer), configured to connect the second pole of the subsequently formed first transistor T1 to the first active layer through the via hole, and to connect the second pole of the subsequently formed second transistor T2 to the second active layer through the via hole.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fifth via hole V5 are etched away to expose a surface of the second region 702 of the seventh active layer, configured such that the fifth connection electrode 32 formed later is electrically connected to the second region 702 of the seventh active layer through the via hole.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via hole V6 are etched away to expose a surface of the second region 602 of the sixth active layer, configured such that the fifth connection electrode 32 formed later is electrically connected to the second region 602 of the sixth active layer through the via hole.

In an exemplary embodiment, the fourth insulating layer in the seventh via hole V7 is etched away, exposing the surface of one end of the third connection electrode 21, configured such that the first branch INIT-B1 of the initial signal line INIT formed later is electrically connected to one end of the third connection electrode 21 through the via hole.

In an exemplary embodiment, the fourth insulating layer in the eighth via hole V8 is etched away, exposing the surface of the other end of the third connection electrode 21, configured such that the second branch INIT-B2 of the subsequently formed initial signal line INIT is electrically connected to the other end of the third connection electrode 21 through the via hole.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the ninth via hole V9 are etched away, exposing the surface of the first region 101 of the first active layer (also the first region 701 of the seventh active layer), configured such that a subsequently formed initial signal line is electrically connected to the first region 101 of the first active layer (also the first region 701 of the seventh active layer) through the via hole.

In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the tenth via hole V10 are etched away to expose a surface of one end of the first connection electrode 11, configured such that the sixth connection electrode 33, which is subsequently formed, is electrically connected to one end of the first connection electrode 11 through the via hole.

In an exemplary embodiment, the fourth insulating layer in the eleventh via hole V11 is etched away to expose a surface of the other end of the first connection electrode 11, configured such that the seventh connection electrode 34 formed later is electrically connected to the other end of the first connection electrode 11 through the via hole.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer and the second insulating layer within the twelfth via hole V12 are etched away to expose a surface of the first region 401 of the fourth active layer, configured such that the eighth connection electrode 35 formed later is electrically connected to the first region 401 of the fourth active layer through the via hole.

In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the thirteenth via hole V13 are etched away to expose a surface of one end of the second connection electrode 12, configured such that the ninth connection electrode 36 formed later is electrically connected to one end of the second connection electrode 12 through the via hole.

In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the fourteenth via hole V14 are etched away to expose a surface of the other end of the second connection electrode 12, configured such that the tenth connection electrode 37 formed later is electrically connected to the other end of the second connection electrode 12 through the via hole.

(5) Forming a third conductive layer pattern. In some exemplary embodiments, forming the third conductive layer may include: on the substrate 90 with the aforementioned pattern formed thereon, a third metal film is deposited, and the third metal film is patterned by a patterning process to form a third conductive layer disposed on the fourth insulating layer 94. As shown in fig. 11, the third conductive layer of the first display region may include a first branch VDD-B1 of the first power line VDD, a second branch VDD-B2 of the first power line VDD, a first branch INIT-B1 of the initial signal line INIT, a second branch INIT-B2 of the initial signal line INIT, a fourth connection electrode 31, a fifth connection electrode 32, a sixth connection electrode 33, a seventh connection electrode 34, an eighth connection electrode 35, a ninth connection electrode 36, and a tenth connection electrode 37. In some example embodiments, the third conductive layer may be referred to as a first source drain metal (SD1) layer.

In the embodiment of the disclosure, the first power line VDD and the initial signal line INIT in the first display area are wired by using metal, so that the influence of wiring load on high-frequency display can be reduced, and the high-frequency display can be better realized in the first display area.

In some exemplary embodiments, the first branch VDD-B1 of the first power line VDD is electrically connected to the second branch VDD-B2 of the first power line VDD through a plurality of via holes (here, the plurality of via holes include a fifteenth via hole V15, a sixteenth via hole V16, a twenty sixth via hole and a twenty seventh via hole V27, and the plurality of connection electrodes include an eleventh connection electrode 41, a twelfth connection electrode 42 and a seventeenth connection electrode 51) which are formed later.

In some exemplary embodiments, the second branch VDD-B2 of the first power line VDD is electrically connected to the second plate Ce2 of the storage capacitor through the first via V1 and connected to the first region 501 of the fifth active layer through the second via V2 such that the first pole of the fifth transistor T5 has the same potential as the first power line VDD.

In some exemplary embodiments, the first branch VDD-B1 of the first power line VDD is electrically connected to the second branch VDD-B2 of the first power line VDD in the current sub-pixel through a plurality of vias and a plurality of connection electrodes formed subsequently on one side, and extends to the previous sub-pixel in the column of the current sub-pixel as the second branch VDD-B2 of the first power line VDD in the previous sub-pixel in the column of the current sub-pixel.

In some exemplary embodiments, the second branch VDD-B2 of the first power line VDD is electrically connected to the first branch VDD-B1 of the first power line VDD in the current sub-pixel through a plurality of vias and a plurality of connection electrodes formed subsequently on one hand, and extends to the next sub-pixel in the column where the current sub-pixel is located as the first branch VDD-B1 of the first power line VDD in the next sub-pixel in the column where the current sub-pixel is located on the other hand.

In some exemplary embodiments, the first branch INIT-B1 of the initial signal line INIT is connected to one end of the third connection electrode 21 through a seventh via V7, and the second branch INIT-B2 of the initial signal line INIT is connected to the other end of the third connection electrode 21 through an eighth via V8. In the present embodiment, the electrical connection of the first branch INIT-B1 of the initial signal line INIT and the second branch INIT-B2 of the initial signal line INIT is achieved through the third connection electrode 21, the seventh via V7, and the eighth via V8.

In some exemplary embodiments, the second branch INIT-B2 of the initial signal line INIT is connected to the first region 101 of the first active layer (also the first region 701 of the seventh active layer) through the ninth via V9, so that the first pole of the first transistor T1 (also the first pole of the seventh transistor T7) has the same potential as the first initial signal line INIT 1.

In some exemplary embodiments, the first branch INIT-B1 of the initial signal line INIT is electrically connected to the second branch INIT-B2 of the initial signal line INIT in the present sub-pixel through the third connection electrode 21 on one hand, and extends toward the previous sub-pixel of the row of the present sub-pixel as the second branch INIT-B2 of the initial signal line INIT in the previous sub-pixel of the row of the present sub-pixel on the other hand.

In some exemplary embodiments, the second branch INIT-B2 of the initial signal line INIT is electrically connected to the first branch INIT-B1 of the initial signal line INIT in the present sub-pixel through the third connecting electrode 21 on one hand, and extends toward the next sub-pixel of the row where the present sub-pixel is located on the other hand, as the first branch INIT-B1 of the initial signal line INIT in the next sub-pixel of the row where the present sub-pixel is located.

In some exemplary embodiments, the orthographic projection of the first branch INIT-B1 of the initial signal line INIT and the second branch INIT-B2 of the initial signal line INIT on the substrate has an overlapping region with the orthographic projection of the second scanning signal line S2 on the substrate.

In some exemplary embodiments, the fourth connection electrode 31 is electrically connected to the first plate Ce1 of the storage capacitor through the third via V3, and is connected to the second region 102 of the first active layer (also the second region 202 of the second active layer) through the fourth via V4. In some example embodiments, the fourth connection electrode 31 may serve as the second pole of the first transistor T1 and the second pole of the second transistor T2.

In some exemplary embodiments, the fifth connection electrode 32 is electrically connected to the second region 702 of the seventh active layer through the fifth via V5, and is connected to the second region 602 of the sixth active layer through the sixth via V6. In some exemplary embodiments, the fifth connection electrode 32 may serve as a second pole of the seventh transistor T7 and a second pole of the sixth transistor T6.

In some exemplary embodiments, the sixth connection electrode 33 is electrically connected to one end of the first connection electrode 11 through the tenth via V10.

In some exemplary embodiments, the seventh connection electrode 34 is electrically connected to the other end of the first connection electrode 11 through an eleventh via V11.

In some exemplary embodiments, the eighth connection electrode 35 is electrically connected to the first region 401 of the fourth active layer through a twelfth via hole V12. In some exemplary embodiments, the eighth connection electrode 35 may serve as the first pole of the fourth transistor T4.

In some exemplary embodiments, the ninth connection electrode 36 is electrically connected to one end of the second connection electrode 12 through a thirteenth via V13.

In some exemplary embodiments, the tenth connection electrode 37 is electrically connected to the other end of the second connection electrode 12 through a fourteenth via V14.

(6) A fifth insulating layer 95 is patterned. Forming the fifth insulating layer 95 pattern includes: a fifth insulating film is coated on the substrate 90 on which the patterns are formed, a fifth insulating layer 95 pattern covering the third conductive layer is formed through a photolithography process of mask exposure and development, and a fifteenth via hole V15, a sixteenth via hole V16, a seventeenth via hole V17, an eighteenth via hole V18, a nineteenth via hole V19, a twentieth via hole V20, a twenty-first via hole V21, and a twenty-second via hole V22 are formed in the fifth insulating layer 95 of the first display region, as shown in fig. 12.

In some exemplary embodiments, the fifth insulating layer in the fifteenth via V15 is etched away, exposing the surface of the second branch VDD-B2 of the first power line VDD, and configured such that the eleventh connection electrode 41 formed later is electrically connected to the second branch VDD-B2 of the first power line VDD through the via.

In some exemplary embodiments, the fifth insulating layer in the sixteenth via V16 is etched away to expose a surface of the first branch VDD-B1 of the first power line VDD, configured such that the twelfth connection electrode 42 formed later is electrically connected to the first branch VDD-B1 of the first power line VDD through the via.

In some exemplary embodiments, the fifth insulating layer within the seventeenth via hole V17 is etched away, exposing the surface of the ninth connection electrode 36, configured such that the first branch E-B1 of the subsequently formed light emitting signal line E is electrically connected to the ninth connection electrode 36 through the via hole.

In some exemplary embodiments, the fifth insulating layer within the eighteenth via hole V18 is etched away, exposing the surface of the tenth connection electrode 37, configured such that the second branch E-B2 of the subsequently formed light emitting signal line E is electrically connected to the tenth connection electrode 37 through the via hole.

In some exemplary embodiments, the fifth insulating layer within the nineteenth via V19 is etched away, exposing the surface of the fifth connection electrode 32, configured to electrically connect the thirteenth connection electrode 43, which is formed later, with the fifth connection electrode 32 through the via.

In some exemplary embodiments, the fifth insulating layer within the twentieth via hole V20 is etched away, exposing the surface of the seventh connection electrode 34, configured to electrically connect the fourteenth connection electrode 44, which is formed later, with the seventh connection electrode 34 through the via hole.

In some exemplary embodiments, the fifth insulating layer within the twenty-first via hole V21 is etched away, exposing the surface of the sixth connection electrode 33, configured to electrically connect the fifteenth connection electrode 45 formed later with the sixth connection electrode 33 through the via hole.

In some exemplary embodiments, the fifth insulating layer within the twenty-second via hole V22 is etched away, exposing the surface of the eighth connection electrode 35, configured to electrically connect the sixteenth connection electrode 46, which is formed later, with the eighth connection electrode 35 through the via hole.

(7) Forming a fourth conductive layer pattern. In some exemplary embodiments, forming the fourth conductive layer may include: on the substrate 90 with the aforementioned pattern formed thereon, a first transparent conductive film is deposited, and the first transparent conductive film is patterned by a patterning process to form a fourth conductive layer disposed on the fifth insulating layer 95. As shown in fig. 13, the fourth conductive layer of the first display region may include a first branch E-B1 of the light emitting signal line E, a second branch E-B2 of the light emitting signal line E, an eleventh connection electrode 41, a twelfth connection electrode 42, a thirteenth connection electrode 43, a fourteenth connection electrode 44, a fifteenth connection electrode 45, and a sixteenth connection electrode 46. In some exemplary embodiments, the fourth conductive layer may be referred to as a first transparent conductive layer.

In the embodiment of the disclosure, the light emitting signal line E of the first display area is made of a transparent conductive material, so that the light transmittance of the camera area is increased, and the imaging effect is improved; meanwhile, since the signal load of the light emitting signal line E has a small influence on the high frequency display, the light emitting signal line E is made of a transparent conductive material, and the high frequency display effect is not affected.

In some exemplary embodiments, the first branch E-B1 of the light emitting signal line E is electrically connected to one end of the second connection electrode 12 in the present sub-pixel through the seventeenth via V17, and extends to the previous sub-pixel on the row of the present sub-pixel, and is electrically connected to the other end of the second connection electrode 12 in the previous sub-pixel on the row of the present sub-pixel through the eighteenth via V18 in the previous sub-pixel on the row of the present sub-pixel.

In some exemplary embodiments, the second branch E-B2 of the light emitting signal line E is electrically connected to the other end of the second connection electrode 12 in the present subpixel through an eighteenth via V18, and extends toward the next subpixel of the row of the present subpixel, and is electrically connected to one end of the second connection electrode 12 in the next subpixel of the row of the present subpixel through a seventeenth via V17 in the next subpixel of the row of the present subpixel.

In the present embodiment, the electrical connection of the first branch E-B1 of the light emitting signal line E and the second branch E-B2 of the light emitting signal line E is achieved through the second connection electrode 12, the seventeenth via V17, and the eighteenth via V18.

In some exemplary embodiments, the eleventh connection electrode 41 is electrically connected to the second branch VDD-B2 of the first power line VDD through a fifteenth via V15.

In some exemplary embodiments, the twelfth connection electrode 42 is electrically connected to the first branch VDD-B1 of the first power line VDD through a sixteenth via V16.

In some exemplary embodiments, the thirteenth connection electrode 43 is electrically connected to the fifth connection electrode 32 through a nineteenth via V19.

In some exemplary embodiments, the fourteenth connection electrode 44 is electrically connected to the seventh connection electrode 34 through the twentieth via V20.

In some exemplary embodiments, the fifteenth connection electrode 45 is electrically connected to the sixth connection electrode 33 through the twenty-first via V21.

In some exemplary embodiments, the sixteenth connection electrode 46 is electrically connected to the eighth connection electrode 35 through a twenty-second via V22.

(8) A first planarization layer 96 is patterned. Forming the first planarization layer 96 pattern includes: depositing a first flat film on the substrate 90 on which the pattern is formed, patterning the first flat film by using a patterning process to form a first flat layer 96 disposed on the fourth conductive layer, where the first flat layer 96 is provided with a twenty-third via hole V23, a twenty-fourth via hole V24, a twenty-fifth via hole V25, a twenty-sixth via hole V26, a twenty-seventh via hole V27, and a twenty-eighth via hole V28, the thirteenth via hole V13 exposes the fourth connecting line L4, and the fourteenth via hole V14 exposes the seventh connecting line L7, as shown in fig. 14.

In some exemplary embodiments, the first planarization layer in the twenty-third via hole V23 is etched away to expose the surface of the fourteenth connection electrode 44, and is configured such that the first branch S1-B1 of the subsequently formed first scanning signal line S1 is electrically connected to the fourteenth connection electrode 44 through the via hole.

In some exemplary embodiments, the first planarization layer within the twenty-fourth via hole V24 is etched away, exposing the surface of the fifteenth connection electrode 45, configured such that the second branch S1-B2 of the subsequently formed first scanning signal line S1 is electrically connected with the fifteenth connection electrode 45 through the via hole.

In some exemplary embodiments, the first planarization layer within the twenty-fifth via hole V25 is etched away, exposing the surface of the sixteenth connection electrode 46, configured such that the subsequently formed data signal line D is electrically connected to the sixteenth connection electrode 46 through the via hole.

In some exemplary embodiments, the first planarization layer within the twenty-sixth via hole V26 is etched away, exposing the surface of the twelfth connection electrode 42, configured to electrically connect the seventeenth connection electrode 51 formed later with the twelfth connection electrode 42 through the via hole.

In some exemplary embodiments, the first planarization layer within the twenty-seventh via hole V27 is etched away, exposing the surface of the eleventh connection electrode 41, configured to electrically connect the seventeenth connection electrode 51 formed later with the eleventh connection electrode 41 through the via hole.

In some exemplary embodiments, the first planarization layer within the twenty-eighth via V28 is etched away, exposing the surface of the thirteenth connection electrode 43, configured to electrically connect the eighteenth connection electrode 52 formed later with the thirteenth connection electrode 43 through the via.

(9) Forming a fifth conductive layer pattern. Forming the fifth conductive layer may include: depositing a fifth metal film on the substrate 90 with the pattern, and patterning the fifth metal film by using a patterning process to form a fifth conductive layer disposed on the first planarization layer. As shown in fig. 15, the fifth conductive layer of the first display region may include a first branch S1-B1 of the first scanning signal line S1, a second branch S1-B2 of the first scanning signal line S1, a data signal line D, a seventeenth connection electrode 51, and an eighteenth connection electrode 52. In some example embodiments, the fifth conductive layer may be referred to as a second source drain metal (SD2) layer.

In the embodiment of the present disclosure, the first scanning signal line S1 and the data signal line D in the first display area are wired with metal, so that the influence of the wiring load on the high-frequency display can be reduced, and the high-frequency display can be better realized in the first display area.

In some exemplary embodiments, the first branch S1-B1 of the first scanning signal line S1 is electrically connected to the fourteenth connecting electrode 44 in the current sub-pixel through the twenty-third via V23 on one hand, and extends to the previous sub-pixel on the row of the current sub-pixel on the other hand, and is electrically connected to the fifteenth connecting electrode 45 in the previous sub-pixel on the row of the current sub-pixel through the twenty-fourth via V24 in the previous sub-pixel on the row of the current sub-pixel.

In some exemplary embodiments, the second branch S1-B2 of the first scanning signal line S1 is electrically connected to the fifteenth connecting electrode 45 in the current sub-pixel through the twenty-fourth via V24 on one hand, extends to the sub-pixel next to the row of the current sub-pixel on the other hand, and is electrically connected to the fourteenth connecting electrode 44 in the sub-pixel next to the row of the current sub-pixel through the twenty-third via V23 in the sub-pixel next to the row of the current sub-pixel.

Since the fourteenth connection electrode 44 is electrically connected to the seventh connection electrode 34 through the twentieth via hole V20, the fifteenth connection electrode 45 is electrically connected to the sixth connection electrode 33 through the twenty-first via hole V21, the sixth connection electrode 33 is electrically connected to one end of the first connection electrode 11 through the tenth via hole V10, and the seventh connection electrode 34 is electrically connected to the other end of the first connection electrode 11 through the eleventh via hole V11, electrical connection between the first branches S1-B1 of the first scan signal line S1 and the second branches S1-B2 of the first scan signal line S1 is achieved.

In some exemplary embodiments, there is an overlapping area between the orthographic projection of the first branch S1-B1 of the first scanning signal line S1 on the substrate 90 and the orthographic projection of the first branch INIT-B1 of the initial signal line INIT on the substrate 90, and there is an overlapping area between the orthographic projection of the second branch S1-B2 of the first scanning signal line S1 on the substrate 90 and the orthographic projection of the second branch INIT-B2 of the initial signal line INIT on the substrate 90.

In some exemplary embodiments, the orthographic projection of the first branch S1-B1 of the first scanning signal line S1 and the second branch S1-B2 of the first scanning signal line S1 on the substrate 90 have an overlapping region with the orthographic projection of the second scanning signal line S2 on the substrate 90.

In some exemplary embodiments, the overlapping area exists in the orthographic projection of the first branch S1-B1 of the first scanning signal line S1, the first branch INIT-B1 of the initial signal line INIT, and the second scanning signal line S2 on the substrate 90, and the overlapping area exists in the orthographic projection of the second branch S1-B2 of the first scanning signal line S1, the second branch INIT-B2 of the initial signal line INIT, and the second scanning signal line S2 on the substrate 90.

In the embodiment of the disclosure, by making the orthographic projections of the first scanning signal line S1 and the second scanning signal line S2 on the substrate 90 have an overlapping region, the influence of the metal wiring on the transmittance can be reduced to the greatest extent, the light transmittance of the first display area is higher, and the shooting performance is better. And by arranging the initial signal line INIT between the first scanning signal line S1 and the second scanning signal line S2, the signal crosstalk between the first scanning signal line S1 and the second scanning signal line S2 can be reduced, so that the first display area can better realize high-frequency display, and the display quality is greatly improved.

In some exemplary embodiments, the data signal line D is electrically connected to the sixteenth connection electrode 46 through a twenty-fifth via V25. Since the sixteenth connection electrode 46 is electrically connected to the eighth connection electrode 35 through the twelfth via V22, and the eighth connection electrode 35 is electrically connected to the first region 401 of the fourth active layer through the twelfth via V12, electrical connection of the data signal line and the first pole of the fourth transistor is achieved, so that the data signal transmitted by the data signal line D can be written into the fourth transistor.

In some exemplary embodiments, there is an overlapping region in the positive projection of the data signal line D, the first branch VDD-B1 of the first power line VDD, and the second branch VDD-B2 of the first power line VDD on the substrate 90.

In the embodiment of the disclosure, the overlapping area exists by making the orthographic projection of the data signal line D and the first power line VDD on the substrate, the influence of the metal wiring on the transmittance can be reduced to the greatest extent, the light transmittance of the first display area is higher, and the shooting performance is better. In addition, the first power line VDD can shield the signal crosstalk generated by the metal wiring below the third conductive layer to the data signal line D, so that the first display area can better realize high-frequency display, and the display quality is greatly improved.

In some exemplary embodiments, the seventeenth connecting electrode 51 is electrically connected to the twelfth connecting electrode 42 through the twenty-sixth via V26 on the one hand, and to the tenth connecting electrode 41 through the twenty-seventh via V27 on the other hand. Since the twelfth connection electrode 42 is electrically connected to the first branch VDD-B1 of the first power line VDD through the sixteenth via V16 and the eleventh connection electrode 41 is electrically connected to the second branch VDD-B2 of the first power line VDD through the fifteenth via V15, electrical connection of the first branch VDD-B1 of the first power line VDD and the second branch VDD-B2 of the first power line VDD is achieved.

In some exemplary embodiments, the eighteenth connection electrode 52 is electrically connected to the thirteenth connection electrode 43 through a twenty-eighth via V28.

(10) A second planarization layer 97 is patterned. In some exemplary embodiments, patterning the second planarization layer 97 may include: a second flat film is coated on the substrate 90 on which the pattern is formed, and the second flat film is patterned by a patterning process to form a second flat layer 97 covering the fifth conductive layer, wherein at least a twenty-ninth via hole V29 is formed in the second flat layer 97 of the first display region, as shown in fig. 6 a.

In some exemplary embodiments, the twenty-ninth via V29 is located at the area of the eighteenth connection electrode 52, the second planarization layer in the twenty-ninth via V29 is removed to expose the surface of the eighteenth connection electrode 52, and the twenty-ninth via V29 is configured to electrically connect the subsequently formed anode to the eighteenth connection electrode 52 through the via.

(11) In some exemplary embodiments, forming the anode pattern may include: on the substrate 90 on which the foregoing pattern is formed, a transparent conductive film is deposited, and the transparent conductive film is patterned by a patterning process to form an anode disposed on the second planarization layer 97.

In some exemplary embodiments, the anode is connected to the eighteenth connection electrode 52 through the twenty ninth via V29 in the first display region. Since the eighteenth connection electrode 52 is electrically connected to the thirteenth connection electrode 43 through the twenty-eighth via V28, the thirteenth connection electrode 43 is electrically connected to the fifth connection electrode 32 through the nineteenth via V19, and the fifth connection electrode 32 is electrically connected to the second region 702 of the seventh active layer through the fifth via V5 and is connected to the second region 602 of the sixth active layer through the sixth via V6, it is realized that the pixel circuit can drive the light emitting element to emit light.

In some exemplary embodiments, the subsequent preparation process may include: a pixel defining film is coated and patterned by a patterning process to form a Pixel Defining Layer (PDL), and the pixel defining layer of each sub-pixel is provided with a sub-pixel opening (SA) exposing the anode. And forming an organic light-emitting layer by adopting an evaporation or ink-jet printing process, and forming a cathode on the organic light-emitting layer. The packaging layer is formed and can comprise a first packaging layer, a second packaging layer and a third packaging layer which are arranged in a stacked mode, the first packaging layer and the third packaging layer can be made of inorganic materials, the second packaging layer can be made of organic materials, the second packaging layer is arranged between the first packaging layer and the third packaging layer, and the fact that external water vapor cannot enter the light-emitting structure layer can be guaranteed.

In some exemplary embodiments, the substrate 90 may be a flexible substrate, or may be a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass, quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some exemplary embodiments, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked, the first flexible material layer and the second flexible material layer may be made of Polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, the first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx), silicon oxide (SiOx), or the like, for improving the water and oxygen resistance of the substrate, and the semiconductor layer may be made of amorphous silicon (a-si).

In some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, and the fifth conductive layer may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, and the like. The fourth conductive layer and the anode can be made of transparent conductive materials such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer is called a Buffer (BUF) layer for improving the water and oxygen resistance of the substrate, the second insulating layer is called a first gate insulating (GI1) layer, the third insulating layer is called a second gate insulating (GI2) layer, the fourth insulating layer is called an interlayer Insulating (ILD) layer, and the fifth insulating layer is called a Passivation (PVX) layer. The first planar (PLN1) layer and the second planar (PLN2) layer may employ organic materials. The semiconductor layer may use polysilicon (p-Si) or oxide.

The display substrate of the embodiment of the present disclosure changes the ITO routing of the signal routing such as the first scanning signal line S1, the second scanning signal line S2, the data signal line D, the first power line VDD and the initial signal line INIT into the conventional metal routing, the resistance of the signal routing is reduced, thereby being beneficial to better performing high-frequency display in the first display area, in addition, the routing is overlapped through a plurality of signal lines, the metal routing occupation area of the first display area is effectively reduced, the light transmittance of the first display area is increased, the self-timer of the front camera is improved, and the camera functions such as face recognition are improved. In addition, the preparation process disclosed by the invention can be well compatible with the existing preparation process, and is simple in process implementation, easy to implement, high in production efficiency, low in production cost and high in yield.

The structure of the display substrate and the preparation process thereof shown in the present disclosure are merely exemplary illustrations, and in some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs, and the present disclosure is not limited herein. The structure of the display substrate and the manufacturing process thereof shown in the present disclosure are illustrated by taking the pixel circuit of 8T1C shown in fig. 3 as an example, in other exemplary embodiments, the pixel circuit may also be a structure such as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C, which is not limited in this disclosure.

The present disclosure further provides a method for manufacturing a display substrate to manufacture the display substrate provided in the above embodiment, where the display substrate includes a first display area, the first display area includes a plurality of first sub-pixels and a light-transmitting area located between the plurality of first sub-pixels, the first sub-pixels include pixel circuits, and the pixel circuits include a plurality of signal lines. In some exemplary embodiments, the method of manufacturing a display substrate may include the steps of:

forming a semiconductor layer on a substrate;

forming a first gate metal layer on the semiconductor layer;

forming a second gate metal layer on the first gate metal layer;

forming a first source drain metal layer on the second gate metal layer;

forming a first transparent conducting layer on the first source drain metal layer;

forming a second source drain metal layer on the first transparent conductive layer; the first transparent conducting layer is used for running at least part of signal lines in a light transmitting area of the first display area; and in the region outside the light-transmitting region of the first display region, at least one of the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer is used for running at least part of signal lines.

The display substrate prepared by the preparation method of the display substrate provided by the disclosure has the similar realization principle and the similar realization effect as the realization principle and the realization effect of the display substrate, and is not repeated herein.

The present disclosure further provides a display panel, which includes the display substrate, and the polarizer and the cover plate disposed on the light-emitting side of the display substrate, and the support layer and the heat dissipation layer disposed on the backlight side of the display substrate. The display panel may be used to: the present invention relates to a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and other products or components with a display function.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the present disclosure is to be limited only by the terms of the appended claims.