阅读说明：本技术 成像装置 (Image forming apparatus with a plurality of image forming units ) 是由 坂直树 冈本晋太郎 幸山裕亮 森茂贵 于 2020-06-25 设计创作，主要内容包括：根据本公开实施方案的成像装置包括：第一基板,其包括执行光电转换的传感器像素；第二基板,其包括基于从所述传感器像素输出的电荷而输出像素信号的像素电路；和第三基板,其包括对所述像素信号进行信号处理的处理电路,第一基板、第二基板和第三基板按该顺序层叠,并且在设有所述像素电路的场效应晶体管的至少一个或多个半导体层中,在第一基板侧的区域中的导电型杂质的浓度高于在第三基板侧的区域中的导电型杂质的浓度。(An image forming apparatus according to an embodiment of the present disclosure includes: a first substrate including sensor pixels that perform photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal, the first substrate, the second substrate, and the third substrate being stacked in this order, and a concentration of a conductive type impurity in a region on the first substrate side being higher than a concentration of a conductive type impurity in a region on the third substrate side in at least one or more semiconductor layers of a field effect transistor provided with the pixel circuit.)

1. An image forming apparatus comprising:

a first substrate including sensor pixels that perform photoelectric conversion;

a second substrate including a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel; and

a third substrate including a processing circuit that performs signal processing on the pixel signal,

the first substrate, the second substrate and the third substrate are laminated in this order, and

in at least one or more semiconductor layers of a field effect transistor provided with the pixel circuit, a concentration of a conductive type impurity in a region on the first substrate side is higher than a concentration of a conductive type impurity in a region on the third substrate side.

2. The imaging apparatus of claim 1, wherein

The sensor pixel includes a photoelectric conversion element, a transfer transistor electrically connected to the photoelectric conversion element, and a floating diffusion portion temporarily holding a charge output from the photoelectric conversion element via the transfer transistor, and

The pixel circuit includes a reset transistor that resets the potential of the floating diffusion to a predetermined potential, an amplification transistor that generates a voltage signal corresponding to the level of charge held in the floating diffusion as the pixel signal, and a selection transistor that controls the output timing of the pixel signal from the amplification transistor.

3. The imaging apparatus of claim 2, wherein

The first substrate includes a first semiconductor substrate including the photoelectric conversion element, the transfer transistor, and the floating diffusion on a front surface side of the first semiconductor substrate,

the second substrate includes a second semiconductor substrate including the reset transistor, the amplifying transistor, and the selection transistor on a front surface side thereof, and

the second substrate is bonded so that a back surface side facing the front surface of the second semiconductor substrate faces the front surface side of the first semiconductor substrate.

4. The imaging device according to claim 3, wherein a back surface of the second semiconductor substrate is attached to a front surface of the first semiconductor substrate via an insulating layer.

5. The imaging device of claim 4, wherein the interface between the second semiconductor substrate and the insulating layer comprises a bonded interface between the first substrate and the second substrate.

6. The imaging device according to claim 4, wherein a first region containing the conductivity-type impurity at a higher concentration than other regions of the second semiconductor substrate is provided in a region including an interface between the second semiconductor substrate and the insulating layer.

7. The imaging device of claim 6, wherein at least one or more of the field effect transistors of the pixel circuits comprises a fin field effect transistor comprising

A diffusion layer provided so as to protrude from the second semiconductor substrate in such a manner as to extend in one direction,

a gate electrode provided across the diffusion layer so as to extend in a direction orthogonal to the one direction, and

a source region and a drain region provided in the diffusion layer sandwiching both sides of the gate electrode.

8. The imaging device according to claim 7, wherein a body contact portion which supplies a predetermined potential to the second semiconductor substrate is provided on a front face of the second semiconductor substrate.

9. The imaging device according to claim 8, wherein the body contact portion is provided in a planar region on the same side as the source region with respect to the gate electrode.

10. The imaging device according to claim 6, wherein the first region is provided over an entire surface of the second semiconductor substrate.

11. The imaging device according to claim 6, wherein the first region includes an epitaxially grown layer containing boron atoms as the conductive type impurity.

12. The imaging device according to claim 6, wherein the first region includes a polysilicon layer containing boron atoms as the conductivity type impurity.

13. The imaging device according to claim 6, wherein a second region which is electrically connected to a contact plug which supplies a predetermined potential and contains the conductive type impurity at a high concentration is further provided in a part of a region on a front face side of the second semiconductor substrate.

14. The imaging device according to claim 13, wherein a third region containing the conductive type impurity at a lower concentration than the first region and the second region and being adjacent to the first region and the second region is further provided in the second semiconductor substrate.

15. The imaging device according to claim 13, wherein the contact plug is provided through the second semiconductor substrate and directly connected to the first region.

16. The imaging device according to claim 6, wherein the first region contains boron atoms as the conductive type impurity, and further contains carbon atoms as a non-conductive type impurity.

17. The imaging apparatus of claim 2, wherein

The first substrate includes the photoelectric conversion element, the transfer transistor, and the floating diffusion for each sensor pixel, an

The second substrate includes the pixel circuit for each sensor pixel.

18. The imaging apparatus of claim 2, wherein

The first substrate includes the photoelectric conversion element, the transfer transistor, and the floating diffusion for each sensor pixel, an

The second substrate includes the pixel circuit for each of the plurality of sensor pixels.

19. The imaging apparatus of claim 2, wherein

The first substrate includes the photoelectric conversion element and the transfer transistor for each sensor pixel, and includes the floating diffusion shared by each of the plurality of sensor pixels, an

The second substrate includes the pixel circuit for each of a plurality of sensor pixels sharing the floating diffusion.

20. The imaging device according to claim 1, wherein the third substrate comprises a third semiconductor substrate provided with the processing circuit on a front surface side.

Technical Field

The present disclosure relates to an image forming apparatus.

Background

By introducing a fine process and increasing the packing density, reduction in the area per pixel of an imaging device of a three-dimensional structure has been achieved. In recent years, imaging devices of three-dimensional structure have been developed to achieve further reduction in size of the imaging devices and higher density of pixels. An imaging device of a three-dimensional structure is configured by, for example, stacking a semiconductor substrate including a plurality of sensor pixels and a semiconductor substrate including a signal processing circuit that processes signals obtained by the respective sensor pixels on each other (see patent document 1).

List of cited documents

Patent document

Patent document 1: japanese laid-open patent publication No. 2010-24506

Disclosure of Invention

In order to achieve high-speed electrical connection between semiconductor substrates, reduction in chip size, and the like in an imaging device of a three-dimensional structure, a semiconductor substrate including a pixel circuit that reads out charges photoelectrically converted in each sensor pixel is thinned. However, the thinned semiconductor substrate has an extremely small thickness as compared with the semiconductor substrate before thinning. Therefore, a technique for appropriately forming a transistor or the like on a thinned semiconductor substrate is required.

That is, it is desirable to enhance the electrical characteristics of the pixel circuit in an imaging device of a three-dimensional structure in which stacked semiconductor substrates are thinned.

An image forming apparatus according to an embodiment of the present disclosure includes: a first substrate including sensor pixels that perform photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal, the first substrate, the second substrate, and the third substrate being stacked in this order, and a concentration of a conductive type impurity in a region on the first substrate side being higher than a concentration of a conductive type impurity in a region on the third substrate side in at least one or more semiconductor layers of a field effect transistor provided with the pixel circuit.

An image forming apparatus according to an embodiment of the present disclosure includes: a first substrate including sensor pixels that perform photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal, the first substrate, the second substrate, and the third substrate being stacked in this order, and provided with at least one or more semiconductor layers provided with a field effect transistor of the pixel circuit such that a concentration of a conductive type impurity in a region on the first substrate side is higher than a concentration of a conductive type impurity in a region on the third substrate side. This enables the imaging device according to the embodiment of the present disclosure to suitably form the well region of the second semiconductor substrate included in the second substrate, for example.

Drawings

Fig. 1 is a schematic diagram of an example of a schematic configuration of an image forming apparatus 1 according to an embodiment of the present disclosure.

Fig. 2 is a circuit diagram showing an example of the sensor pixel 12 and the pixel circuit 22.

Fig. 3 is a circuit diagram showing other examples of the sensor pixel 12 and the pixel circuit 22.

Fig. 4 is a circuit diagram showing other examples of the sensor pixel 12 and the pixel circuit 22.

Fig. 5 is a circuit diagram showing other examples of the sensor pixel 12 and the pixel circuit 22.

Fig. 6 is a circuit diagram showing an example of connections between the plurality of pixel circuits 22 and the plurality of vertical signal lines 24.

Fig. 7 is a longitudinal sectional view of an example of a sectional configuration in the stacking direction of the imaging device 1.

Fig. 8 is a schematic diagram of an example of a horizontal sectional configuration of the imaging device 1.

Fig. 9 is a schematic diagram of an example of a horizontal sectional configuration of the imaging device 1.

Fig. 10 is a schematic diagram of an example of a wiring layout in the horizontal plane of the imaging device 1.

Fig. 11 is a schematic diagram of an example of a wiring layout in the horizontal plane of the imaging device 1.

Fig. 12 is a schematic diagram of an example of a wiring layout in the horizontal plane of the imaging device 1.

Fig. 13 is a schematic diagram of an example of a wiring layout in the horizontal plane of the imaging device 1.

Fig. 14A is a perspective view showing an example of the field effect transistor 1100 provided in the second semiconductor substrate 21 according to the first embodiment.

Fig. 14B is a schematic diagram of a sectional configuration of the field effect transistor shown in fig. 14A taken along the extending direction of the diffusion layer 1120.

Fig. 15 is a schematic diagram illustrating an outline of a method for forming the semiconductor layer 1110 including the first region 1111.

Fig. 16 is a schematic perspective view of a modification of the structure of the field-effect transistor 1100 according to the first embodiment.

Fig. 17 is a schematic diagram of a modification in which the field-effect transistor 1100 according to the first embodiment and the field-effect transistor 1900 in general are mounted together.

Fig. 18 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 19 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 20 is a sequential schematic view of processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 21 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 22 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 23 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 24 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 25 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 26 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 27 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 28 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 29 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 30 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 31 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 32 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 33 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 34 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 35 is a sequential schematic view of respective processes of a manufacturing method of a field effect transistor 1100 to which the technique according to the first embodiment is applied.

Fig. 36 is a schematic view of a mode in which a second semiconductor substrate 1210 according to the second embodiment is attached to a first substrate 1201.

Fig. 37 is a schematic view of another mode of attaching a second semiconductor substrate 1210 according to the second embodiment to a first substrate 1201.

Fig. 38 is a schematic view of another mode of attaching the second semiconductor substrate 1210 according to the second embodiment to the first substrate 1201.

Fig. 39 is a schematic view of another mode of attaching the second semiconductor substrate 1210 according to the second embodiment to the first substrate 1201.

Fig. 40 is a schematic view of still another mode of attaching the second semiconductor substrate 1210 according to the second embodiment to the first substrate 1201.

Fig. 41 is a schematic view of still another mode of attaching the second semiconductor substrate 1210 according to the second embodiment to the first substrate 1201.

Fig. 42 is a schematic view of still another mode of attaching the second semiconductor substrate 1210 according to the second embodiment to the first substrate 1201.

Fig. 43 is a schematic view of still another mode of attaching the second semiconductor substrate 1210 according to the second embodiment to the first substrate 1201.

Fig. 44 is a schematic longitudinal cross-sectional view of a modification of the structure of a contact plug with respect to a well region of a field effect transistor provided in the second semiconductor substrate 1210 according to the second embodiment.

Fig. 45 is a schematic longitudinal cross-sectional view of a modification of the structure of a contact plug with respect to a well region of a field effect transistor provided in the second semiconductor substrate 1210 according to the second embodiment.

Fig. 46 is a schematic longitudinal cross-sectional view of a modification of the structure of a contact plug with respect to a well region of a field effect transistor provided in the second semiconductor substrate 1210 according to the second embodiment.

Fig. 47 is a schematic longitudinal cross-sectional view of a modification of the structure of a contact plug with respect to a well region of a field effect transistor provided in the second semiconductor substrate 1210 according to the second embodiment.

Fig. 48 is a schematic view of a mode of forming a first region 1311 and forming a field-effect transistor in a second semiconductor substrate 1310 according to a third embodiment.

Fig. 49 is a schematic view of a mode of forming a first region 1311 and forming a field-effect transistor in a second semiconductor substrate 1310 according to a third embodiment.

Fig. 50 is a schematic cross-sectional view of a modification of the structure of a field-effect transistor provided in a second semiconductor substrate 1310 according to the third embodiment.

Fig. 51 is a schematic cross-sectional view of a modification of the structure of a field-effect transistor provided in a second semiconductor substrate 1310 according to the third embodiment.

Fig. 52 is a longitudinal sectional view of a modification of the sectional structure shown in fig. 7.

Fig. 53 is a longitudinal sectional view of a modification of the sectional structure shown in fig. 7.

Fig. 54 is a sectional view showing a thickness direction of a configuration example of an imaging device according to modification 3.

Fig. 55 is a sectional view showing a thickness direction of a configuration example of an imaging device according to modification 3.

Fig. 56 is a sectional view showing a thickness direction of a configuration example of an imaging device according to modification 3.

Fig. 57 is a cross-sectional view in the horizontal direction showing an example of the layout of a plurality of pixel cells according to modification 3.

Fig. 58 is a cross-sectional view in the horizontal direction showing an example of the layout of a plurality of pixel cells according to modification 3.

Fig. 59 is a cross-sectional view in the horizontal direction showing an example of the layout of a plurality of pixel cells according to modification 3.

Fig. 60 is a schematic view of a modification of the cross-section along the cutting planes Sec1 and Sec2 in fig. 7.

Fig. 61 is a schematic view of a modification of the cross-section along the cutting planes Sec1 and Sec2 in fig. 7.

Fig. 62 is a schematic view of a modification of the cross-section along the cutting planes Sec1 and Sec2 in fig. 7.

Fig. 63 is a schematic view of a modification of the cross-section along the cutting planes Sec1 and Sec2 in fig. 7.

Fig. 64 is a schematic view of a modification of the cross-section along the cutting planes Sec1 and Sec2 in fig. 7.

Fig. 65 is a schematic diagram showing another example of the cross-sectional configuration along the cutting plane Sec2 of the imaging device 1 of modification 7.

Fig. 66 is a schematic diagram showing another example of the cross-sectional configuration along the cutting plane Sec2 of the imaging device 1 of modification 7.

Fig. 67 is a schematic diagram of a circuit configuration of a CMOS image sensor mounted on a column-parallel ADC.

Fig. 68 is a diagram of an example in which the imaging device 1 shown in fig. 67 includes three substrates that are stacked.

Fig. 69 is a schematic diagram of an example of a sectional configuration of the imaging device 1 according to modification 10.

FIG. 70 is a diagram in which a CoSi such as CoSi is to be contained₂Or a silicide such as NiSi is suitable for a schematic view of an example of the imaging device 1 including three substrates stacked.

Fig. 71 is a block diagram showing an example of a functional configuration of an image forming apparatus according to an embodiment of the present disclosure.

Fig. 72 is a schematic plan view showing a schematic configuration of the image forming apparatus shown in fig. 71.

Fig. 73 is a schematic view showing a sectional configuration taken along the line III-III' shown in fig. 72.

Fig. 74 is an equivalent circuit diagram of the pixel sharing unit shown in fig. 71.

Fig. 75 is a diagram showing an example of a connection pattern of a plurality of pixel sharing units and a plurality of vertical signal lines.

Fig. 76 is a schematic cross-sectional view showing an example of a specific configuration of the imaging apparatus shown in fig. 73.

Fig. 77A is a schematic diagram showing an example of a planar configuration of a main portion of the first substrate shown in fig. 76.

Fig. 77B is a schematic diagram showing a planar configuration of the pad portion together with the main portion of the first substrate shown in fig. 77A.

Fig. 78 is a schematic diagram showing an example of a planar configuration of the second substrate (semiconductor layer) shown in fig. 76.

Fig. 79 is a schematic diagram showing an example of a planar configuration of the pixel circuit and a main part of the first substrate together with the first wiring layer shown in fig. 76.

Fig. 80 is a schematic diagram illustrating an example of planar configurations of the first wiring layer and the second wiring layer illustrated in fig. 76.

Fig. 81 is a schematic diagram illustrating an example of planar configurations of the second wiring layer and the third wiring layer illustrated in fig. 76.

Fig. 82 is a schematic diagram illustrating an example of a planar configuration of the third wiring layer and the fourth wiring layer illustrated in fig. 76.

Fig. 83 is a schematic diagram for explaining a path of an input signal to the imaging apparatus shown in fig. 73.

Fig. 84 is a schematic diagram for explaining signal paths of pixel signals of the imaging device shown in fig. 73.

Fig. 85 is a schematic view showing a modification of the planar configuration of the second substrate (semiconductor layer) shown in fig. 78.

Fig. 86 is a schematic diagram showing a planar configuration of the first wiring layer and a main part of the first substrate together with the pixel circuit shown in fig. 85.

Fig. 87 is a schematic diagram showing an example of a planar configuration of the second wiring layer together with the first wiring layer shown in fig. 86.

Fig. 88 is a schematic diagram showing an example of a planar configuration of the third wiring layer together with the second wiring layer shown in fig. 87.

Fig. 89 is a schematic diagram showing an example of a planar configuration of the fourth wiring layer together with the third wiring layer shown in fig. 88.

Fig. 90 is a schematic view showing a modification of the planar configuration of the first substrate shown in fig. 77A.

Fig. 91 is a schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) stacked on the first substrate shown in fig. 90.

Fig. 92 is a schematic diagram showing an example of a planar configuration of the pixel circuit and the first wiring layer shown in fig. 91.

Fig. 93 is a schematic diagram showing an example of planar constitution of the second wiring layer together with the first wiring layer shown in fig. 92.

Fig. 94 is a schematic diagram showing an example of a planar configuration of the third wiring layer together with the second wiring layer shown in fig. 93.

Fig. 95 is a schematic diagram showing an example of a planar configuration of the fourth wiring layer together with the third wiring layer shown in fig. 94.

Fig. 96 is a schematic view showing another example of the planar configuration of the first substrate shown in fig. 90.

Fig. 97 is a schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) stacked on the first substrate shown in fig. 96.

Fig. 98 is a schematic diagram showing an example of a planar configuration of the first wiring layer together with the pixel circuit shown in fig. 97.

Fig. 99 is a schematic diagram showing an example of planar constitution of the second wiring layer together with the first wiring layer shown in fig. 98.

Fig. 100 is a schematic diagram showing an example of a planar configuration of the third wiring layer together with the second wiring layer shown in fig. 99.

Fig. 101 is a schematic diagram showing an example of a planar configuration of the fourth wiring layer together with the third wiring layer shown in fig. 100.

Fig. 102 is a schematic cross-sectional view illustrating another example of the imaging apparatus illustrated in fig. 73.

Fig. 103 is a schematic diagram for explaining a path of an input signal to the imaging apparatus shown in fig. 102.

Fig. 104 is a schematic diagram for explaining signal paths of pixel signals of the imaging device shown in fig. 102.

Fig. 105 is a schematic cross-sectional view illustrating another example of the imaging apparatus illustrated in fig. 76.

Fig. 106 is a diagram showing other examples of the equivalent circuit shown in fig. 74.

Fig. 107 is a schematic plan view showing another example of the pixel separation section in fig. 77A and the like.

Fig. 108 is a diagram showing an example of a schematic configuration of an imaging system including the imaging device according to the above-described embodiment and its modification.

Fig. 109 is a diagram illustrating an example of an imaging process in the imaging system of fig. 108.

Fig. 110 is a block diagram showing an example of a schematic configuration of a vehicle control system.

Fig. 111 is an explanatory view showing an example of the mounting positions of the vehicle exterior information detecting unit and the imaging unit.

Fig. 112 is a diagram showing an example of a schematic configuration of the endoscopic surgery system.

Fig. 113 is a block diagram showing an example of a functional configuration of a camera head and a Camera Control Unit (CCU).

Detailed Description

Some embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. The embodiments described below are merely examples of the present disclosure, and the technique according to the present disclosure is not limited to the modes described below. Further, the characteristics of the respective constituent elements of the present disclosure, such as the configuration, the size, and the size ratio shown in the drawings of the present disclosure, are not limited to those shown in the drawings. Note that, description will be made in the following order.

1. Constitution of image forming apparatus

2. First embodiment

3. Second embodiment

4. Third embodiment

5. Modification example

6. Detailed description of the invention

6.1. Embodiment (image forming apparatus having a laminated structure of three substrates)

6.2. Modification 1 (example of planar Structure 1)

6.3. Modification 2 (example of planar Structure 2)

6.4. Modification 3 (example of planar Structure 3)

6.5. Modification 4 (example including a contact portion between substrates in the center of a pixel array section)

6.6. Modification 5 (example including planar transfer transistor)

6.7. Modification 6 (example in which one pixel is connected to one pixel circuit)

6.8. Modification 7 (example of the Pixel separating portion)

6.9. Application example (imaging system)

6.10. Application example

Constitution of imaging apparatus

First, an image forming apparatus to which the technique according to the present disclosure is applied will be described with reference to fig. 1 to 13.

Fig. 1 is a schematic diagram of an example of a schematic configuration of an image forming apparatus 1 according to an embodiment of the present disclosure. As shown in fig. 1, the imaging device 1 is an imaging device including a first substrate 10, a second substrate 20, and a third substrate 30 and having a three-dimensional structure of a constitution in which these three substrates are bonded together. Note that the first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

The first substrate 10 includes a first semiconductor substrate 11, and the first semiconductor substrate 11 includes a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix in the pixel region 13 of the first substrate 10.

The second substrate 20 includes a second semiconductor substrate 21, and the second semiconductor substrate 21 includes a pixel circuit 22 that outputs a pixel signal based on the electric charge output from the sensor pixel 12. For example, one pixel circuit 22 is provided every four sensor pixels 12. In addition, the second substrate 20 includes a plurality of pixel driving lines 23 extending in a row direction and a plurality of vertical signal lines 24 extending in a column direction.

The third substrate 30 includes a third semiconductor substrate 31, and the third semiconductor substrate 31 includes a processing circuit 32 that performs signal processing on pixel signals. Further, the processing circuit 32 includes, for example, a vertical driving circuit 33, a column signal processing circuit 34, a horizontal driving circuit 35, and a system control circuit 36. The processing circuit 32 can output the output voltage Vout for each sensor pixel 12 from the horizontal driving circuit 35 to the outside.

The vertical drive circuit 33 sequentially selects, for example, a plurality of sensor pixels 12 in units of rows. The column signal processing circuit 34 performs, for example, Correlated Double Sampling (CDS) processing on pixel signals output from the respective sensor pixels 12 in a row selected by the vertical driving circuit 33. The column signal processing circuit 34 extracts the signal level of the pixel signal by performing CDS processing, for example, and holds pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35 sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside, for example. The system control circuit 36 controls driving of each component in the processing circuit 32, for example. This enables the processing circuit 32 to output pixel data based on the amount of light received by each sensor pixel 12 to the outside.

Fig. 2 is a circuit diagram showing an example of the sensor pixel 12 and the pixel circuit 22. In fig. 2, four sensor pixels 12 share one pixel circuit 22. The term "shared" used herein means that outputs from four sensor pixels 12 are input to a common one of the pixel circuits 22.

Each sensor pixel 12 has a common component. Hereinafter, in the case where it is necessary to distinguish the constituent elements of each sensor pixel 12 from each other, identification numbers (1, 2, 3, and 4) are added at the ends of the reference numerals of the constituent elements. On the other hand, in the case where it is not necessary to distinguish the components of each sensor pixel 12 from each other, the identification number at the end of the reference numeral of the component is omitted.

Each sensor pixel 12 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds electric charges output from the photodiode PD via the transfer transistor TR. The photodiode PD is a photoelectric conversion element that performs photoelectric conversion to generate electric charges corresponding to the amount of received light. The transfer transistor TR is, for example, a MOS (metal-oxide-semiconductor) transistor.

A cathode of the photodiode PD is electrically connected to a source of the transfer transistor TR, and an anode of the photodiode PD is electrically connected to a reference potential line (for example, ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the pixel driving line 23.

The floating diffusion portions FD of the respective sensor pixels 12 of the shared pixel circuit 22 are electrically connected to each other, and are electrically connected to the input terminal of the shared pixel circuit 22. The pixel circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. In addition, the pixel circuit 22 may optionally include a selection transistor SEL.

A source of the reset transistor RST (i.e., an input terminal of the pixel circuit 22) is electrically connected to the floating diffusion FD, and a drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel driving line 23. The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. A source of the selection transistor SEL (i.e., an output terminal of the pixel circuit 22) is electrically connected to the vertical signal line 24, and a gate of the selection transistor SEL is electrically connected to the pixel driving line 23.

When the transfer transistor TR is turned on, the charge of the photodiode PD is transferred to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 22.

The amplification transistor AMP generates, as a pixel signal, a signal having a voltage corresponding to the level of the electric charge held in the floating diffusion FD. The amplifying transistor AMP forms a so-called source follower type amplifier, and outputs a pixel signal having a voltage corresponding to the level of the electric charge generated by the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD, and outputs a voltage corresponding to the potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, MOS transistors.

Fig. 3 to 5 are each a circuit diagram showing other examples of the sensor pixel 12 and the pixel circuit 22.

As shown in fig. 3, the selection transistor SEL may be disposed between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. A source of the selection transistor SEL is electrically connected to a drain of the amplification transistor AMP, and a gate of the selection transistor SEL is electrically connected to the pixel driving line 23. The source of the amplification transistor AMP (i.e., the output terminal of the pixel circuit 22) is electrically connected to the vertical signal line 24, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

Further, as shown in fig. 4 or 5, an FD conversion gain switching transistor FDG may be provided between the source of the reset transistor RST and the gate of the amplifying transistor AMP.

Charge Q is represented by the product of capacitance C and voltage V; therefore, when the capacitance C of the floating diffusion FD is large, the converted voltage V of the amplifying transistor AMP becomes low. On the other hand, in the case where the charge Q of the pixel signal is large, the floating diffusion FD cannot hold the charge Q from the photodiode PD unless the capacitance C of the floating diffusion FD is sufficiently large. Further, it is also important that the capacitance C of the floating diffusion FD is appropriately large so as not to increase the voltage V converted by the amplifying transistor AMP too much. Therefore, the FD conversion gain switching transistor FDG is set to switch the charge-voltage conversion efficiency in the pixel circuit 22.

When the FD conversion gain switching transistor FDG is turned on, the capacitance C of the floating diffusion FD increases by the amount of the gate capacitance of the FD conversion gain switching transistor FDG compared to when it is turned off. Therefore, by switching on and off of the FD conversion gain switching transistor FDG, the FD capacitance C can be made variable and the charge-voltage conversion efficiency in the pixel circuit 22 can be switched.

Fig. 6 is a circuit diagram showing an example of connections between the plurality of pixel circuits 22 and the plurality of vertical signal lines 24.

As shown in fig. 6, in the case where a plurality of pixel circuits 22 are arranged side by side in the extending direction (for example, column direction) of the vertical signal lines 24, each pixel circuit 22 may be assigned to one of the plurality of vertical signal lines 24. Note that, in fig. 6, identification numbers (1, 2, 3, and 4) are added to the ends of the reference numerals of the respective vertical signal lines 24 in order to distinguish the respective vertical signal lines 24.

Fig. 7 is a longitudinal sectional view of an example of a sectional configuration in the stacking direction of the imaging device 1.

As shown in fig. 7, the image forming apparatus 1 has a configuration in which a first substrate 10, a second substrate 20, and a third substrate 30 are stacked in this order. For example, a color filter 40 and a light receiving lens 50 are provided for each sensor pixel 12 on the light incident surface side (also referred to as the back surface side) of the first substrate 10. That is, the imaging device 1 is a so-called back-illuminated type imaging device.

The first substrate 10 has a structure in which a first insulating layer 46 is laminated on the first semiconductor substrate 11. The first semiconductor substrate 11 is a silicon substrate, and includes, for example, a p-well layer 42 in a part of the front face and the vicinity thereof and a photodiode PD in another region (i.e., a region deeper than the p-well layer). The p-well layer 42 is composed of a p-type semiconductor region, and the photodiode PD is composed of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42. The first semiconductor substrate 11 includes a floating diffusion FD in a p-well layer 42 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.

The first substrate 10 includes a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel 12. The first substrate 10 includes a transfer transistor TR and a floating diffusion FD in a portion on the side opposite to the light incident surface side of the first semiconductor substrate 11 (i.e., the front surface side or the second substrate 20 side).

The first substrate 10 includes an element separating portion 43 that separates each sensor pixel 12. The element separating portion 43 is formed to extend in a normal direction of the main surface of the first semiconductor substrate 11 (a direction perpendicular to the front surface of the first semiconductor substrate 11), and electrically separates the adjacent sensor pixels 12 from each other. The element isolation portion 43 includes, for example, silicon oxide penetrating the first semiconductor substrate 11.

The first substrate 10 further includes, for example, a p-well layer 44 in contact with the side surface of the element separating portion 43 on the photodiode PD side. The p-well layer 44 is composed of a semiconductor region of a different conductivity type (specifically, p-type) from that of the photodiode PD. The first substrate 10 further includes, for example, a fixed charge film 45 in contact with the back surface of the first semiconductor substrate 11. The fixed charge film 45 includes an insulating film having negative fixed charges to suppress generation of dark current caused by an interface state on the light receiving surface side of the first semiconductor substrate 11. Examples of the material of the fixed charge film 45 include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, or tantalum oxide. A hole accumulation layer that suppresses generation of electrons from the interface is formed at the interface on the light receiving surface side of the first semiconductor substrate 11 by an electric field induced by the fixed charge film 45.

The color filter 40 is provided on the rear surface side of the first semiconductor substrate 11. Specifically, the color filter 40 is, for example, in contact with the fixed charge film 45, and is disposed at a position opposite to the sensor pixel 12 with respect to the fixed charge film 45. The light receiving lens 50 is disposed, for example, in contact with the color filter 40, and is disposed at a position opposite to the sensor pixel 12 with respect to the color filter 40 and the fixed charge film 45.

The second substrate 20 includes a second insulating layer laminated on the second semiconductor substrate 21. The second semiconductor substrate 21 is a silicon substrate, and includes one pixel circuit 22 for every four sensor pixels 12. The second substrate 20 includes the pixel circuit 22 in a part of the third substrate 30 side (i.e., the front surface side) of the second semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 such that the back surface of the second semiconductor substrate 21 faces the front surface of the first semiconductor substrate 11. That is, the second substrate 20 is attached to the first substrate 10 in a back-to-back manner.

The second semiconductor substrate 21 includes a separation insulating layer 53, and a through wiring 54 is provided in the separation insulating layer 53. The through wiring 54 is electrically insulated from the second semiconductor substrate 21 by covering the side surface thereof with the separation insulating layer 53. The through wiring 54 extends in the normal direction of the main surface of the second semiconductor substrate 21, and electrically connects the respective elements of the first substrate 10 and the respective elements of the second substrate 20 to each other. Specifically, the through wiring 54 electrically connects the floating diffusion FD and the connection wiring 55 to each other. For example, one through wiring 54 is provided for each sensor pixel 12.

The second substrate 20 includes a plurality of connection portions 59 within the second insulating layer 52, for example, electrically connected to the pixel circuits 22 or the second semiconductor substrate 21. The wiring layer 56 includes, for example, an interlayer insulating layer 57, and a plurality of pixel driving lines 23 and a plurality of vertical signal lines 24 provided within the interlayer insulating layer 57. The wiring layer 56 includes, for example, one connection wiring 55 provided for every four sensor pixels 12 within the interlayer insulating layer 57. The connection wiring 55 electrically connects the through wirings 54 of the four sensor pixels 12 sharing the pixel circuit 22 together.

The wiring layer 56 also includes a plurality of pad electrodes 58, for example, within the interlayer insulating layer 57. Each pad electrode 58 is formed of, for example, a metal such as Cu (copper). Each pad electrode 58 is exposed to the front of the wiring layer 56, and is used for attaching the second substrate 20 and the third substrate 30 together and for electrically connecting the second substrate 20 and the third substrate 30 together. One of the plurality of pad electrodes 58 is provided for each pixel driving line 23 and each vertical signal line 24.

Here, the second substrate 20 may be provided as a stacked structure of a plurality of semiconductor substrates and a plurality of insulating layers.

Specifically, the second substrate 20 may include two semiconductor substrates stacked in a thickness direction. For example, the second substrate 20 may be provided to allow an additional semiconductor substrate to be stacked on the second insulating layer 52 stacked on the second semiconductor substrate 21. For example, a transistor is provided in a semiconductor substrate provided on the second insulating layer 52, and is electrically connected to the transistor provided in the second semiconductor substrate 21 via the connection portion 59.

That is, the pixel circuits 22 provided in the second substrate 20 may be separately provided in the second semiconductor substrate 21 and in a semiconductor substrate further laminated on the second insulating layer 52. Specifically, at least one or more of the amplifying transistor AMP, the reset transistor RST, and the selection transistor SEL included in the pixel circuit 22 may be provided in the second semiconductor substrate 21, and the remaining transistors thereof may be provided in a semiconductor substrate further stacked on the second insulating layer 52. As an example, the amplification transistor AMP may be provided in the second semiconductor substrate 21, and the reset transistor RST and the selection transistor SEL may be provided in a semiconductor substrate further stacked on the second insulating layer 52.

Alternatively, the second substrate 20 may include three semiconductor substrates stacked in the thickness direction. For example, the second substrate 20 may be provided to allow an upper first semiconductor substrate to be further laminated on the second insulating layer 52 laminated on the second semiconductor substrate 21 and to allow an upper second semiconductor substrate to be further laminated on the upper first semiconductor substrate via the insulating layer. For example, transistors are provided in the upper first semiconductor substrate and the upper second semiconductor substrate which are laminated, and are electrically connected to the transistors provided in the second semiconductor substrate 21 via the connection portion 59 or the like.

That is, the pixel circuits 22 provided in the second substrate 20 may be separately provided in the second semiconductor substrate 21 and the stacked upper first semiconductor substrate and upper second semiconductor substrate. Specifically, at least one or more transistors among the amplifying transistor AMP, the reset transistor RST, and the selection transistor SEL included in the pixel circuit 22 may be provided in each of the second semiconductor substrate 21, the upper first semiconductor substrate, and the upper second semiconductor substrate. As an example, the amplifying transistor AMP may be provided in the second semiconductor substrate 21; the reset transistor RST may be provided in an upper first semiconductor substrate further provided on the second semiconductor substrate 21; and the selection transistor SEL may be disposed in an upper second semiconductor substrate further disposed on the upper first semiconductor substrate.

In the second substrate 20 including a plurality of semiconductor substrates stacked in the thickness direction, separately stacking the semiconductor substrates makes it possible to further reduce the area of the semiconductor substrate occupied by one pixel circuit 22. The use of such a second substrate 20 enables the imaging device 1 to have a smaller chip area than the imaging device 1.

Further, the use of such a second substrate 20 enables the imaging apparatus 1 to selectively expand the area of any of the amplification transistor AMP, the reset transistor RST and the selection transistor SEL included in the pixel circuit 22. This enables the imaging apparatus 1 to further reduce noise by the enlargement of the area of the amplifying transistor AMP.

The third substrate 30 includes, for example, a third insulating film 61 laminated on the third semiconductor substrate 31. The third semiconductor substrate 31 is a silicon substrate, and includes a processing circuit 32. Note that the front-surface-side surfaces of the third substrate 30 and the second substrate 20 are bonded to each other, and therefore, in the description of the structure of the third substrate 30, the vertical relationship to be described is opposite to the vertical direction in the drawing. The third substrate 30 is bonded to the second substrate 20 such that the front surface of the third semiconductor substrate 31 faces the front surface side of the second semiconductor substrate 21. That is, the third substrate 30 is bonded to the second substrate 20 in a face-to-face manner.

The third substrate 30 includes, for example, a wiring layer 62 on a third insulating film 61. The wiring layer 62 includes, for example, an interlayer insulating layer 63 and a plurality of pad electrodes 64 provided in the interlayer insulating layer 63 and electrically connected to the processing circuit 32. Each pad electrode 64 is formed of a metal such as copper (Cu). The pad electrodes 64 are exposed to the front of the wiring layer 62, and are used for attaching the second substrate 20 and the third substrate 30 together and for electrically connecting the second substrate 20 and the third substrate 30 together. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding between the pad electrodes 58 and 64. That is, the gate (transfer gate TG) of the transfer transistor TR is electrically connected to the processing circuit 32 via the through wiring 54 and the pad electrodes 58 and 64.

Fig. 8 and 9 are each a schematic diagram of an example of a sectional configuration in the horizontal direction of the imaging device 1. Each of the upper diagrams of fig. 8 and 9 is a schematic diagram of an example of a cross-section along the cutting plane Sec1 in fig. 7, and each of the lower diagrams of fig. 8 and 9 is a schematic diagram of an example of a cross-section along the cutting plane Sec2 in fig. 7.

Fig. 8 illustrates a configuration in which two groups of four sensor pixels 12 arranged 2 × 2 are arranged side by side in the first direction V1, and fig. 9 illustrates a configuration in which four groups of four sensor pixels 12 arranged 2 × 2 are arranged side by side in the first direction V1 and the second direction V2.

The first direction Vl is parallel to one of two arrangement directions (for example, a row direction and a column direction) of the plurality of sensor pixels 12 arranged in a matrix shape. In addition, the second direction V2 is parallel to an arrangement direction (for example, column direction) orthogonal to the first direction.

For example, a through wiring 54 is provided for each sensor pixel 12, and the floating diffusion FD is electrically connected to a connection wiring 55 described later. For example, the through wirings 47 and 48 are provided for each sensor pixel 12. The through wiring 47 electrically connects the p-well layer 42 of the first semiconductor substrate 11 and the wiring in the second substrate 20. The through wiring 48 electrically connects the transfer gate TG and the pixel drive line 23 together.

As shown in fig. 8, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in a strip-like manner in a second direction V2 (vertical direction in fig. 8) within the surface of the first substrate 10. Fig. 8 illustrates a case where the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two rows in the second direction V2.

As shown in fig. 9, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in a stripe shape in a first direction V1 (left-right direction in fig. 9) in the surface of the first substrate 10. Fig. 9 illustrates a case where the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two rows in the first direction V1.

In the four sensor pixels 12 sharing the pixel circuit 22, for example, four floating diffusion portions FD are arranged adjacent to each other via the element separating portion 43. In the four sensor pixels 12 sharing the pixel circuit 22, four transfer gates TG are arranged so as to surround the four floating diffusions FD, and the four transfer gates TG form, for example, a ring shape.

As shown in fig. 8, the separation insulating layer 53 includes a plurality of blocks extending in the second direction V2. The second semiconductor substrate 21 includes a plurality of island-shaped blocks 21A extending in the second direction V2 and arranged side by side in the second direction V2. Each block 21A includes a plurality of groups of, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One pixel circuit 22 shared by the four sensor pixels 12 includes, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL in an area corresponding to the four sensor pixels 12. The pixel circuit 22 includes, for example, an amplification transistor AMP in the block 21A adjacent to the left of the separation insulating layer 53 and a reset transistor RST and a selection transistor SEL in the block 21A adjacent to the right of the separation insulating layer 53.

As shown in fig. 9, the separation insulating layer 53 includes a plurality of blocks extending in the first direction V1. The second semiconductor substrate 21 includes a plurality of island-shaped blocks 21A extending in the first direction V1 and arranged side by side in the first direction V1. Each block 21A includes a plurality of groups of, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One pixel circuit 22 shared by the four sensor pixels 12 includes, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL in an area corresponding to the four sensor pixels 12. The pixel circuit 22 includes, for example, an amplification transistor AMP in the block 21A adjacent to the left of the separation insulating layer 53 and a reset transistor RST and a selection transistor SEL in the block 21A adjacent to the right of the separation insulating layer 53.

Fig. 10 to 13 are each a schematic diagram of an example of a wiring layout in the horizontal plane of the imaging device 1. Similar to fig. 8, fig. 10 to 13 respectively show examples of wiring layouts in the case where one pixel circuit 22 shared by four sensor pixels 12 is provided in an area corresponding to the four sensor pixels 12. For example, fig. 10 to 13 each show a wiring layout provided in different layers from each other in the wiring layer 56.

For example, as shown in fig. 10, four through wirings 54 adjacent to each other are electrically connected to the connection wiring 55. The through wiring 54 is electrically connected to the gate of the amplification transistor AMP included in the block 21A adjacent to the left of the separation insulating layer 53 and the gate of the reset transistor RST included in the block 21A adjacent to the right of the separation insulating layer 53 via the connection wiring 55 and the connection portion 59.

For example, as shown in fig. 11, the power supply line VDD is arranged at a position corresponding to each of the pixel circuits 22 arranged side by side in the first direction V1. The power supply line VDD is electrically connected to the drain of the amplifying transistor AMP and the drain of the reset transistor RST in each of the pixel circuits 22 arranged side by side in the first direction V1 via the connection portion 59. For example, two pixel driving lines 23 are arranged at positions corresponding to the respective pixel circuits 22 arranged side by side in the first direction V1. For example, one pixel driving line 23 is used as a wiring RSTG electrically connected to the gates of the reset transistors RST of the pixel circuits 22 arranged side by side in the first direction V1. The other pixel driving line 23 serves as a wiring SELG electrically connected to the gates of the selection transistors SEL of the pixel circuits 22 arranged side by side in the first direction V1. For example, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically connected to each other via a wiring 25.

For example, as shown in fig. 12, the two power supply lines VSS are arranged at positions corresponding to the respective pixel circuits 22 arranged side by side in the first direction V1. For example, each power supply line VSS is electrically connected to the plurality of through-wirings 47 at a position corresponding to each sensor pixel 12 arranged side by side in the first direction V1. For example, four pixel driving lines 23 are arranged at positions corresponding to the respective pixel circuits 22 arranged side by side in the first direction V1. For example, each of the four pixel drive lines 23 serves as a wiring TRG electrically connected to the through wiring 48 of one sensor pixel 12 corresponding to each pixel circuit 22 arranged side by side in the first direction V1. The four pixel driving lines 23 are electrically connected to the gates of the transfer transistors TR of the respective sensor pixels 12 arranged side by side in the first direction V1. In fig. 12, identifiers (1, 2, 3, and 4) are added to the end of each wiring TRG to distinguish each wiring TRG.

For example, as shown in fig. 13, the vertical signal lines 24 are arranged at positions corresponding to the pixel circuits 22 arranged side by side in the second direction V2. For example, the vertical signal line 24 is electrically connected to the source of the amplifying transistor AMP of each pixel circuit 22 arranged side by side in the second direction V2.

The technique according to the present disclosure is applicable to the above-described stacked image forming apparatus 1. Hereinafter, techniques according to the present disclosure are described in the first to third embodiments, respectively.

< 2 > first embodiment

First, a technique according to a first embodiment of the present disclosure is explained with reference to fig. 14A to 35. The technique according to the present embodiment relates to a field effect transistor provided in the second semiconductor substrate 21 of the second substrate 20.

In the imaging device 1 configured by laminating three substrates, the second semiconductor substrate 21 included in the second substrate 20 is thinned after being attached to the first substrate 10. In addition, since the second substrate 20 is bonded to the first substrate 10 in a back-to-back manner, the first insulating layer 46 is provided on the back surface side of the second semiconductor substrate 21 (i.e., the side opposite to the front surface side on which the pixel circuits 22 are provided).

In this case, in order to avoid the potential of the second semiconductor substrate 21 from entering a floating state, the field effect transistor provided in the second semiconductor substrate 21 includes a bulk terminal that supplies a predetermined potential to the second semiconductor substrate 21 in addition to the gate, the source, and the drain.

However, in the thinned second semiconductor substrate 21, the depletion layer extending from the drain region may reach the first insulating layer 46, resulting in electrical isolation of a partial region of the second semiconductor substrate 21. Therefore, depending on the configuration of the body terminal, the supply of the electric potential from the body terminal to the second semiconductor substrate 21 is electrically cut off, thereby bringing the second semiconductor substrate 21 into an electrically floating state, which may degrade the characteristics of the field effect transistor.

In view of this situation, the technique according to the present embodiment has been conceived. The technique according to the present embodiment involves providing a region having a higher concentration of conductive type impurities than other regions of the second semiconductor substrate 21 on the back surface side of the second semiconductor substrate 21 on which the pixel circuits 22 are provided, thereby more easily supplying a potential to the second semiconductor substrate 21 which is a body region of a field effect transistor.

Note that in the case where the second substrate 20 includes a plurality of semiconductor substrates stacked in the thickness direction, a region in which the concentration of conductive type impurities is higher than other regions of the semiconductor substrates may be provided on the back side of each of the plurality of stacked semiconductor substrates (i.e., the second semiconductor substrate 21 and at least one or more semiconductor substrates provided on the second semiconductor substrate 21).

Fig. 14A is a perspective view of an example of the field effect transistor 1100 provided in the second semiconductor substrate 21.

As shown in fig. 14A, the field-effect transistor 1100 includes a semiconductor layer 1110, a first region 1111 provided near an interface between the semiconductor layer 1110 and a first insulating layer 1140, a diffusion layer 1120 protrudingly provided on an upper portion of the semiconductor layer 1110, a source region 1120S and a drain region 1120D provided in the diffusion layer 1120, a gate electrode 1131 provided on the diffusion layer 1120 via a not-shown gate insulating film, and a body terminal 1132 electrically connected to the semiconductor layer 1110. That is, the field effect transistor 1100 is, for example, a fin-type field effect transistor provided in the semiconductor layer 1110 stacked on the first insulating layer 1140.

The first insulating layer 1140 corresponds to the first insulating layer 46. The first insulating layer 1140 contains, for example, silicon oxide (SiO)₂)。

The semiconductor layer 1110 corresponds to the thinned second semiconductor substrate 21. The semiconductor layer 1110 is a silicon layer into which a first conductive type impurity (e.g., a p-type impurity such as boron (B) or aluminum (Al)) is introduced.

The first region 1111 is disposed in a region including an interface between the semiconductor layer 1110 and the first insulating layer 1140, and is a region in which a concentration of a first conductive type impurity (e.g., a p-type impurity such as boron (B) or aluminum (Al)) is higher than other regions of the semiconductor layer 1110. Specifically, the first region 1111 is provided in a region including an interface between the semiconductor layer 1110 and the first insulating layer 1140 and not including an interface between the semiconductor layer 1110 and the diffusion layer 1120. In the case where the first region 1111 extends to the vicinity of the interface between the semiconductor layer 1110 and the diffusion layer 1120, the characteristics of the field effect transistor 1100 may be affected. Therefore, the first region 1111 is preferably disposed away from the interface between the semiconductor layer 1110 and the diffusion layer 1120.

The first region 1111 is set to contain, for example, 10¹⁸/cm³And boron (B) as an impurity of the first conductivity type. In addition, a region other than the first region 1111 of the semiconductor layer 1110 is provided to include 10 ¹⁶/cm³The following region of boron (B) as the first conductive type impurity.

The first region 1111 is disposed at least under the drain region 1120D to electrically connect a body region and a body terminal 1132 disposed under a channel region of the field effect transistor 1100 to each other. This enables the first region 1111 to prevent the potential supply from the body terminal 1132 to the semiconductor layer 1110 from being cut off due to electrical isolation of a partial region of the semiconductor layer 1110 by the depletion layer Dep extending from the drain region 1120D.

In order to more reliably perform potential supply from the body terminal 1132 to the semiconductor layer 1110, the first region 1111 is preferably provided across the entire region where the field-effect transistor 1100 is provided. Further, in order to form the first region 1111 more easily, it is more preferable that the first region 1111 is provided on the entire surface of the semiconductor layer 1110.

The body terminal 1132 is provided on the front surface side of the semiconductor layer 1110, and supplies a predetermined potential to the body region of the field-effect transistor 1100 via the first region 1111. For example, body terminal 1132 is electrically connected to ground to supply ground potential to the body region of field effect transistor 1100.

The body terminal 1132 may be provided anywhere on the front surface side of the semiconductor layer 1110 as long as electrical connection with the first region 1111 is possible. However, the semiconductor layer 1110 on the drain region 1120D side where the depletion layer Dep is formed has higher resistance than the semiconductor layer 1110 on the source region 1120S side. Thus, providing the body terminal 1132 on the source region 1120S side with respect to the gate electrode 1131 makes it possible to reduce the resistance value from the body terminal 1132 to the body region.

The diffusion layer 1120 is provided to protrude from one main surface of the semiconductor layer 1110 in such a manner as to extend in one direction. The diffusion layer 1120 includes silicon or the like similarly to the semiconductor layer 1110. The diffusion layer 1120 can be formed, for example, by protecting a region corresponding to the diffusion layer 1120 with a resist or the like, then etching the semiconductor layer 1110 and removing the semiconductor layer 1110 in a region other than the region corresponding to the diffusion layer 1120.

The source region 1120S and the drain region 1120D are provided in the diffusion layer 1120 sandwiching both sides of the gate electrode 1131. Specifically, the source region 1120S and the drain region 1120D are formed by introducing a second conductivity type impurity (e.g., an n-type impurity such As phosphorus (P) or arsenic (As)) into a region of the diffusion layer 1120 which is not covered with the gate electrode 1131. At this time, the diffusion layer 1120 on one side sandwiching the gate electrode 1131 functions as a source region 1120S, and the diffusion layer 1120 on the other side thereof functions as a drain region 1120D. Therefore, the source region 1120S and the drain region 1120D may be replaced with each other, unlike the example shown in fig. 14A.

The gate electrode 1131 extends in a direction orthogonal to the extending direction of the diffusion layer 1120, and is disposed so as to straddle above the diffusion layer 1120. The gate electrode 1131 is provided over the diffusion layer 1120 via a gate insulating film, not shown, to form a gate structure on three faces of the upper face and the side face of the diffusion layer 1120. The gate electrode 1131 contains, for example, a conductive material such as polysilicon, and the gate insulating film contains, for example, silicon oxide or the like.

Here, fig. 14B shows a sectional configuration of the field effect transistor 1100 taken along the extending direction of the diffusion layer 1120 for specifically explaining the gate structure of the field effect transistor 1100. Fig. 14B is a schematic diagram of a sectional configuration of the field effect transistor shown in fig. 14A taken along the extending direction of the diffusion layer 1120.

As shown in fig. 14B, a gate electrode 1131 is provided over the diffusion layer 1120 via a gate insulating film 1130. Further, a source region 1120S and a drain region 1120D are each formed in the diffusion layer 1120 sandwiching both sides of the gate electrode 1131. This allows the region of the diffusion layer 1120 between the source region 1120S and the drain region 1120D to become the channel region 1120C. The resistance of the channel region 1120C is controlled by a voltage to be applied to the gate electrode 1131 disposed above the channel region 1120C.

Subsequently, a method of forming the semiconductor layer 1110 including the first region 1111 is explained with reference to fig. 15. Fig. 15 is a schematic diagram illustrating an outline of a method for forming the semiconductor layer 1110 including the first region 1111.

As shown in fig. 15, before the first substrate 10 and the second substrate 20 are attached together, a first region 1111 is formed in advance in the semiconductor layer 1110 (second semiconductor substrate 21) of the second substrate 20. Specifically, in the case where the second substrate 20 including the semiconductor layer 1110 is bonded to the first substrate 10 in which the first semiconductor substrate 11 in which the photodiode PD and the like are formed and the first insulating layer 46 are laminated, the first region 1111 is formed in advance on the bonding surface side of the semiconductor layer 1110.

The first region 1111 can be formed by introducing a first conductivity type impurity into a region on the bonding surface side of the semiconductor layer 1110. As a method of introducing the first-conductivity-type impurity into the first region 1111, a known doping method such as ion implantation, solid phase diffusion, or plasma doping can be used. In the case where the first region 1111 is formed before being bonded to the first substrate 10, the first conductivity type impurity may be introduced into the semiconductor layer 1110 from the bonding surface side with the first substrate 10. In this case, doping of the first conductive type impurity can be performed from the surface closer to the region where the first region 1111 is formed, so that the depth where the first region 1111 is formed can be more precisely controlled.

Subsequently, a modification of the technique according to the present embodiment is explained with reference to fig. 16 and 17. Fig. 16 is a schematic perspective view of a modification of the structure of the field-effect transistor 1100 according to the present embodiment.

As shown in fig. 16, the first region 1111A may be disposed to extend from a region including an interface between the semiconductor layer 1110 and the first insulating layer 1140 to a region where the body terminal 1132 is disposed at the front surface side of the semiconductor layer 1110. In this case, the on-resistance from the body terminal 1132 to the body region of the field effect transistor 1100 can be further reduced.

In this case, however, the first region 1111A disposed on the front surface side of the semiconductor layer 1110 and the source region 1120S or the drain region 1120D disposed in the diffusion layer 1120 are close to each other. Thus, the body and source or drain terminals of the field effect transistor 1100 may cause unintended conduction. For this, a film containing a material such as SiO is provided between the first region 1111A provided on the front surface side of the semiconductor layer 1110 and the source region 1120S or the drain region 1120D provided in the diffusion layer 1120₂And the element separation layer 1115 of an insulating material. Therefore, in the field effect transistor 1100, providing the element separation layer 1115 in a suitable region can prevent the extended first region 1111A from conducting to an unintended element or causing leakage.

Fig. 17 is a schematic diagram of a modification in which the field-effect transistor 1100 according to the first embodiment and the field-effect transistor 1900 in general are mounted together.

As shown in fig. 17, the semiconductor layer 1110 may be mounted together with the field effect transistor 1100 and the flat type field effect transistor 1900 according to the present embodiment.

Specifically, as described above, the field effect transistor 1100 is a fin-type field effect transistor in which the gate electrode 1131 straddles the diffusion layer 1120 provided to protrude from the semiconductor layer 1110 via the gate insulating film 1130 so as to extend in one direction. The source region 1120S and the drain region 1120D are provided in the diffusion layer 1120 sandwiching both sides of the gate electrode 1131.

On the other hand, the field-effect transistor 1900 is a flat type field-effect transistor in which a gate electrode 1931 is provided on the semiconductor layer 1110 via a gate insulating film 1930. A source region 1920S and a drain region 1920D are provided in the semiconductor layer 1110 which sandwiches both sides of the gate electrode 1931.

The regions provided with the fin field effect transistor 1100, the planar field effect transistor 1900, and the body terminal 1132 are electrically isolated from each other by the element separation layer 1115 including an insulating material that does not cause unintended conduction or the like.

Here, the first region 1111A formed in the region including the interface between the semiconductor layer 1110 and the first insulating layer 1140 may be disposed not only under the fin type field effect transistor 1100 but also under the flat type field effect transistor 1100. Therefore, the first region 1111A extends to a region on the front surface side of the semiconductor layer 1110 provided with the body terminal 1132, so that a uniform potential can be supplied to the body regions of both the fin type field effect transistor 1100 and the flat type field effect transistor 1900.

Next, a more specific structure of the field effect transistor 1100 to which the technique according to the present embodiment is applied and a method for manufacturing the same will be described with reference to fig. 18 to 35. Fig. 18 to 35 are schematic diagrams each showing a sequence of processes of a method for manufacturing a field effect transistor 1100 to which the technique of this embodiment is applied.

First, as shown in fig. 18, a first insulating layer 1140 is formed on the first semiconductor substrate 11 (not shown) in which the sensor pixels are formed. Next, the semiconductor layer (second semiconductor substrate) 1110 is doped with a first conductivity type impurity (for example, a p-type impurity), thereby forming a first region 1111. The semiconductor layer 1110 is bonded to the first semiconductor substrate 11 so that the surface on the side where the first region 1111 is formed faces the first insulating layer 1140. Subsequently, the semiconductor layer 1110 is thinned to have a predetermined thickness, then the front side of the semiconductor layer 1110 is oxidized (not shown), and further a SiN film 1160 is deposited on the oxidized front side of the semiconductor layer 1110.

Next, as shown in fig. 19, the SiN film 1160 and the semiconductor layer 1110 are etched to form an opening 1160A. As shown in a plan view on the lower side of fig. 19, this allows the formation of a main pattern 1121 of a rectangular shape extending in one direction and open at one side of the extending direction, and dummy patterns 1122 located on both sides of the main pattern 1121 and extending in a direction parallel to the extending direction of the main pattern 1121. The main pattern 1121 ultimately serves as a channel, a source, and a drain of the field effect transistor 1100.

Subsequently, as shown in FIG. 20, the opening 1160A is filled with SiO ₂A membrane 1171.

Next, as shown in FIG. 21, SiO is etched₂Film 1171 is recessed (receded), thereby forming SiO therein₂Membrane 1171 remains in bottom opening 1160B. At this time, the dummy pattern 1122 makes the density of the etching pattern uniform, thereby preventing the dispersion of the depth of the openings 1116B of the main pattern 1121 due to the micro-loading effect of etching. Therefore, this configuration enables the field effect transistor 1100 to have more favorable characteristics.

Subsequently, as shown in fig. 22, a BSG (boron doped silicate glass) film 1172 as a material having a high etching rate is deposited to fill the opening 1160B.

Next, as shown in fig. 23, an etching mask 1173 is formed on the BSG film 1172, and then the BSG film 1172, the SiN film 1160, and the semiconductor layer 1110 in the region corresponding to the dummy pattern 1122 are etched to form an opening 1160C. This allows the dummy pattern 1122 to be removed, as shown in the lower plan view of fig. 23.

Subsequently, as shown in fig. 24, a SiN film 1161 is deposited, and then etching is performed isotropically, so that the SiN film 1161 is deposited only at the bottom of the opening 1160C.

Next, as shown in fig. 25, the BSG film 1172 is selectively removed using a Hydrogen Fluoride (HF) solution or the like in a vapor (vapor) state. As shown in the lower plan view of fig. 25, the main pattern 1121 is formed only in the semiconductor layer 1110.

Subsequently, as shown in fig. 26, a BSG (boron doped silicate glass) film 1174 is deposited at a predetermined film thickness.

Thereafter, as shown in fig. 27, the BSG film 1174 is etched at a predetermined film thickness, thereby forming the BSG film 1174 as a side wall on the side surface of the main pattern 1121. This allows the formation of the BSG film 1174 patterned along the periphery of the main pattern 1121, as shown in the plan view of the lower side of fig. 27.

Next, as shown in fig. 28, SiO is deposited on the entire surface of the semiconductor layer 1110₂And a membrane 1180.

Subsequently, as shown in fig. 29, the deposited SiO is planarized using CMP (chemical mechanical polishing) or the like₂Film 1180, exposing SiN film 1160.

Thereafter, as shown in fig. 30, the SiN film 1160 in the region to be a channel in the subsequent stage is selectively etched to form an opening 1160D. As shown in the lower plan view of fig. 30. A region to be a channel in a subsequent stage is a region intersecting the center of the main pattern 1121 in a direction orthogonal to the extending direction of the main pattern 1121.

Next, as shown in fig. 31, the BSG film 1174 is removed using a Hydrogen Fluoride (HF) solution or the like in a vapor (vapor) state. Therefore, as shown in a plan view of the lower side of fig. 31, the semiconductor layer 1110 is exposed through the opening 1160D in a partial region of the main pattern 1121.

Subsequently, as shown in fig. 32, the front surface of the semiconductor layer 1110 exposed through the opening 1160D is oxidized, thereby forming a gate insulating film (not shown). Thereafter, polysilicon is deposited and then planarized by CMP or the like, thereby forming the gate electrode 1131. At this time, as shown in a plan view of the lower side of fig. 32, the gate electrode 1131 is formed in a planar region corresponding to the periphery of the main pattern 1121 and the opening 1160D.

Next, as shown in fig. 33, a hard mask 1175 is formed, and spacers 1176 are further formed on the sides of the hard mask 1175. Further, ion implantation of a second conductivity type impurity (e.g., an n-type impurity) into the semiconductor layer 1110 is performed with the hard mask 1175 and the spacer 1176 as masks, thereby forming the diffusion layer 1120 which functions as a source or a drain.

Note that as shown in the lower plan view of fig. 33, the channel width of the field effect transistor 1100 is determined by the size of the hard mask 1175. In addition, spacers 1176 are provided to isolate the channel region and the source and drain regions from each other. The size of the spacer 1176 is appropriately adjusted according to the characteristics of the field effect transistor 1100.

Subsequently, as shown in fig. 34, the spacers 1176 are removed, and then the exposed polysilicon (deposited during formation of the gate electrode 1131) is removed using the hard mask 1175 as a mask.

Next, as shown in FIG. 35, SiO for opening is formed by removing polysilicon₂Etc. to remove hard mask 1175. Thereafter, as shown in a lower plan view of fig. 35, a contact hole is formed in a planar region partially including the gate electrode 1131, and the formed contact hole is filled with tungsten, thereby forming a contact plug 1190 which is in contact with the gate electrode 1131 from the upper face toward the side face. The contact plugs 1190 are electrically connected to floating diffusion portions FD of the sensor pixels 12 formed in the first substrate 10, not shown.

Through such a process, the field effect transistor 1100 to which the technique according to the present embodiment is applied can be manufactured.

The technique according to the first embodiment of the present disclosure has been described above in detail. According to the technique of the present embodiment, in the second semiconductor substrate 21 including the pixel circuit 22, a predetermined potential can be easily supplied to the body region of the field-effect transistor. Therefore, according to the technique of the present embodiment, the reliability of the electrical characteristics of the field effect transistor provided in the second semiconductor substrate 21 can be improved.

< 3 > second embodiment

Next, a technique according to a second embodiment of the present disclosure is explained with reference to FIGS. 36 to 43. The technique according to the present embodiment relates to the second semiconductor substrate 21 of the second substrate 20.

In the imaging device 1 configured by laminating three substrates, a well region into which a conductive type impurity is introduced is provided on the back surface side of the second semiconductor substrate 21 to fix the potential of the second semiconductor substrate 21 included in the second substrate 20 to a predetermined potential. The well region is electrically connected to an external power supply or ground so as to supply a reverse bias potential or a ground potential to the field effect transistors provided in the second semiconductor substrate 21.

For example, such a well region may be formed by attaching the first substrate 10 and the second substrate 20 together and then ion-implanting conductive type impurities into a predetermined region of the second semiconductor substrate 21 included in the second substrate 20.

Specifically, after the gate structure is formed in the thinned second semiconductor substrate 21 included in the second substrate 20 after the attachment between the first substrate 10 and the second substrate 20, the ion implantation of the conductive type impurity is performed.

Here, the thinning of the second semiconductor substrate 21 is performed with an accuracy of about several hundred nm, and thus the thickness of the thinned second semiconductor substrate 21 varies by about several hundred nm. For this reason, in the case where the ion implantation of the conductive type impurity is performed under certain conditions, it is difficult to stably form the well region in the second semiconductor substrate 21 in the vicinity of the interface with the first substrate 10. In addition, in the case where the thickness of the second semiconductor substrate 21 is thinner than assumed, ion implantation may be performed on the first substrate 10, so that it is difficult to form a well region in a deep region on the back surface side of the second semiconductor substrate 21. Therefore, it is difficult to uniformize the characteristics of the field effect transistors provided in the second semiconductor substrate 21.

In addition, the fin field effect transistor is expected to be a transistor capable of increasing transconductance more easily because the gate width thereof can be larger than that of a flat field effect transistor of the same plane area. In addition, in the fin-type field effect transistor, electric charges pass through a region distant from an interface between the semiconductor and the insulator, and are less affected by traps existing at the interface between the semiconductor and the insulator; therefore, the fin field effect transistor is expected to be a transistor having good random noise characteristics. For this reason, it has been considered to apply the fin field effect transistor to the amplifying transistor AMP or the like provided in the second semiconductor substrate 21.

However, in the case where the conductive type impurity formed in the well region of the shallow region is diffused into the fin structure of the fin type field effect transistor, the current-voltage characteristics of the field effect transistor are caused to be lowered. For this reason, in the case where the finfet is formed in the second semiconductor substrate 21, it is important to form the well region in an appropriate region of the second semiconductor substrate 21 away from the fin structure.

In view of this situation, the technique according to the present embodiment has been conceived. The technique according to the present embodiment involves forming a well region in an appropriate region of the second semiconductor substrate 21 by introducing a conductivity type impurity in advance from the bonding surface side of the second semiconductor substrate 21 before bonding to the first substrate 10.

In particular, the technique according to the present embodiment relates to forming a well region by performing deposition containing a conductivity type impurity on the bonding face side of the second semiconductor substrate 21 before bonding to the first substrate 10. This makes it possible to form a well region having a steeper concentration profile than a doping method such as ion implantation in the second semiconductor substrate 21. Therefore, according to the technique of the present embodiment, the conductive type impurity can be selectively introduced into a desired region on the bonding surface side of the second semiconductor substrate 21.

Note that in the case where the second substrate 20 includes a plurality of semiconductor substrates stacked in the thickness direction, the technique according to the present embodiment is also applicable to each of the plurality of stacked semiconductor substrates (i.e., the second semiconductor substrate 21 and at least one or more semiconductor substrates provided on the second semiconductor substrate 21). Specifically, the conductive type impurity may be introduced into a desired region on the bonding surface side of each of the stacked plurality of semiconductor substrates (i.e., the second semiconductor substrate 21 and at least one or more semiconductor substrates provided on the second semiconductor substrate 21), and then bonded to another substrate or the like.

Fig. 36 is a schematic view of a mode in which the second semiconductor substrate 1210(21) is attached to the first substrate 1201 (10).

As shown in the figure, the first region 1211 functioning as a well region of the field effect transistor is provided in the second semiconductor substrate 1210(21) at a stage before the first substrate 1201(10) is attached.

The first substrate 1201 is formed by laminating a first insulating layer 1240(46) over the first semiconductor substrate 1230 (11).

The first semiconductor substrate 1230(11) is a silicon substrate, and includes, for example, a p-well layer 1231(42) in a part of the front face or in the vicinity thereof and photodiodes PD in other regions (i.e., regions deeper than the p-well layer 1231). The p-well layer 1231 is formed of a p-type semiconductor region, and the photodiode PD is formed of a semiconductor region of a different conductivity type (e.g., n-type) from the p-well layer 1231. The first semiconductor substrate 1230 includes, inside the p-well layer 1231, a floating diffusion FD that is a semiconductor region of a different conductivity type (e.g., n-type) from the p-well layer 1231, and a transfer gate TG of a transfer transistor TR that extracts electric charges from the photodiode PD.

Further, the first semiconductor substrate 1230 includes an element isolation portion 1241(43) that isolates the photodiodes PD from each other, and a p-well layer 1242(44) that is in contact with the side surface of the element isolation portion 1241 on the photodiode PD side. The element separating portion 1241 is formed to extend in a normal direction of the main surface of the first semiconductor substrate 1230 (a direction perpendicular to the front surface of the first semiconductor substrate 1230), and electrically separates the adjacent photodiodes PD from each other. The element isolation portion 1241 includes, for example, silicon oxide penetrating the first semiconductor substrate 1230. The p-well layer 1242 is formed of a semiconductor region of a conductivity type (specifically, p-type) different from that of the photodiode PD.

Further, a plurality of insulating films 1251, 1252, and 1253 and a support substrate 1250 are provided on a surface of the first substrate 1201 on the side opposite to the bonding surface with the second semiconductor substrate 1210. The insulating film 1251 is, for example, a TEOS (tetraethyl orthosilicate) film; the insulating film 1252 is, for example, a SiN film; insulating film 1253 is, for example, SiO₂And (3) a membrane. The support substrate 1250 is, for example, a silicon substrate, and is provided to hold the first substrate 1201 and ensure rigidity in the manufacturing process of the imaging device 1.

The second semiconductor substrate 1210 is, for example, a silicon substrate. The second semiconductor substrate 1210 includes a first region 1211 into which a first conductivity type impurity (for example, a p-type impurity such as boron (B)) is introduced on the bonding surface side with the first substrate 1201. After the first region 1211 is formed, a semiconductor substrate 1210 is attached to the first substrate 1201.

The first region 1211 is a region formed by introducing the first conductivity type impurity into a region on the bonding surface side of the second semiconductor substrate 1210. As a method of introducing the first conductive type impurity into the first region 1211, a known doping method such as ion implantation, solid phase diffusion, or plasma doping may be used.

In the case where the first region 1211 is formed in the second semiconductor substrate 1210 before being bonded to the first substrate 1201, doping of the first conductivity-type impurity into the second semiconductor substrate 1210 using the above-described known doping method can be performed from the bonding surface side with the first substrate 1201. In this case, doping of the first conductivity type impurity can be performed from the surface side close to the first region 1211, and thus the depth at which the first region 1211 is formed can be more accurately controlled. In addition, the first conductive type impurity may be doped into the second semiconductor substrate 1210 before thinning, so that the first region 1211 may be formed in an appropriate region without being affected by thickness deviation of the second semiconductor substrate 1210 due to thinning.

Further, the first region 1211 is preferably formed by deposition containing a first conductivity type impurity (for example, a p-type impurity such as boron (B)). Specifically, in the case where the second semiconductor substrate 1210 is a silicon substrate, the first region 1211 is preferably formed as an epitaxially grown layer containing an impurity of the first conductivity type (e.g., boron). Alternatively, in the case where the second semiconductor substrate 1210 is a silicon substrate, the first region 1211 is preferably formed as a polycrystalline silicon layer containing a first conductive type impurity (e.g., boron).

This makes a layer deposited by selectively introducing the first conductivity type impurity to be the first region 1211, so that the impurity can be introduced into a single atomic layer in the crystal (i.e., so-called δ doping is performed). Therefore, the concentration distribution in the thickness direction of the first conductive type impurity in the first region 1211 can be allowed to be steeper.

In particular, in the case where the first region 1211 is formed as an epitaxially grown layer containing the first conductivity-type impurity, the concentration distribution of the first conductivity-type impurity in the first region 1211 can be more accurately controlled. On the other hand, in the case where the first region 1211 is formed as a polysilicon layer containing the first conductive type impurity, the first region 1211 can be formed by a simpler manufacturing process.

Fig. 37 to 39 are schematic views of another mode of bonding the second semiconductor substrate 1210(21) to the first substrate 1201(10), respectively.

As shown in fig. 37 to 39, this mode is a mode in which the first region 1211 is formed by diffusing the first conductivity type impurity (for example, boron (B)) from the impurity introduced film 1212 containing the first conductivity type impurity.

Specifically, as shown in fig. 37, an impurity introduced film 1212 may be deposited on the bonding face side of the second semiconductor substrate 1210. In addition, a cap layer 1213 may be further deposited on the front surface of the impurity introducing film 1212

The impurity introduced film 1212 is a film containing borosilicate glass (BSG) and diffusing boron (B) as an impurity of the first conductivity type into the second semiconductor substrate 1210 by thermal diffusion. The cap layer 1213 is a layer containing SiO or SiN deposited by ALD or the like and suppressing film quality change of the impurity introduction film 1212 or diffusion of the first conductivity type impurity into the first insulating layer 1240.

In this case, the impurity introduced film 1212 can diffuse the first conductivity type impurity (e.g., boron (B)) into the second semiconductor substrate 1210 by using heat generated in a process after the second semiconductor substrate 1210 is attached to the first substrate 1201. This enables the impurity introduction film 1212 to form the first region 1211 containing the first conductivity type impurity in the second semiconductor substrate 1210.

Note that the second semiconductor substrate 1210 may be thinned to a thickness of about 500nm by polishing or the like after being attached to the first substrate 10. Diffusion of the first conductivity type impurity (e.g., boron (B)) from the impurity introduced film 1212 may be performed after thinning the second semiconductor substrate 1210.

Further, as shown in fig. 38, an impurity introduced film 1212 may be deposited on the bonding surface side of the second semiconductor substrate 1210.

Also, the impurity introduced film 1212 is a film containing borosilicate glass (BSG) and diffusing boron (B) as an impurity of the first conductivity type into the second semiconductor substrate 1210 by thermal diffusion. In this case, the impurity introduced film 1212 can diffuse the first conductivity type impurity (e.g., boron (B)) into the second semiconductor substrate 1210 by using heat generated in a process after the second semiconductor substrate 1210 is attached to the first substrate 1201. This enables the impurity introduction film 1212 to form the first region 1211 containing the first conductivity type impurity in the second semiconductor substrate 1210.

Further, as shown in fig. 39, an impurity introduced film 1212 may be deposited on the bonding surface side of the first substrate 1201.

The impurity introduced film 1212 is a film containing borosilicate glass (BSG) and diffusing boron (B) as an impurity of the first conductivity type into the bonded second semiconductor substrate 1210 by thermal diffusion. In this case, the impurity introduced film 1212 can diffuse the first conductivity type impurity (e.g., boron (B)) into the second semiconductor substrate 1210 by using heat generated in a process after the second semiconductor substrate 1210 is attached to the first substrate 1201. This enables the impurity introduction film 1212 to form the first region 1211 containing the first conductivity type impurity in the second semiconductor substrate 1210.

Fig. 40 to 43 are schematic views of another mode of bonding the second semiconductor substrate 1210(21) to the first substrate 1201(10), respectively.

As shown in fig. 40 to 43, this mode is a mode in which the first regions 1211P and 1211N different in conductivity type are formed in the second semiconductor substrate 1210.

Specifically, first, as shown in fig. 40, first conductive type impurities are implanted into the second semiconductor substrate 121 by using a resist 1299 provided to cover a predetermined region of the second semiconductor substrate 1210 as a mask, thereby forming a first region 1211P. For example, the first region 1211P may be formed by implanting boron (B) as a first conductive type impurity into the second semiconductor substrate 121.

Subsequently, as shown in fig. 41, a second conductivity type impurity is implanted into the second semiconductor substrate 121 by using a resist 1299 provided so as to cover a region other than the first region 1211P of the second semiconductor substrate 1210 as a mask, thereby forming a first region 1211N. For example, the first region 1211N may be formed by implanting phosphorus (P) or arsenic (As), which is an impurity of the second conductivity type, into the second semiconductor substrate 121. Note that the formation order of the first regions 1211N and 1211P may be reversed.

Next, as shown in fig. 42, the second semiconductor substrate 1210 is bonded to the first substrate 1201 with the surface on the side where the first regions 1211P and 1211N are formed as a bonding surface.

The first substrate 1201 is configured by laminating a first insulating layer 1240 on the first semiconductor substrate 1230. The first semiconductor substrate 1230 is a silicon substrate, and includes, for example, a p-well layer 1231 in a part of the front face or in the vicinity thereof and photodiodes PD in other regions (i.e., regions deeper than the p-well layer 1231). The p-well layer 1231 is formed of a p-type semiconductor region, and the photodiode PD is formed of a semiconductor region of a different conductivity type (e.g., n-type) from the p-well layer 1231.

Inside the p-well layer 1231, a floating diffusion FD that is a semiconductor region of a different conductivity type (e.g., n-type) from the p-well layer 1231 and a well contact "well" that is a semiconductor region of the same conductivity type (e.g., p-type) as the p-well layer 1231 are provided. On the p-well layer 1231, a transfer gate TG that extracts charges from the photodiode PD to the floating diffusion FD, an electrode 1243 electrically connected to the floating diffusion FD, and an electrode 1245 electrically connected to a well contact "well" are provided.

Further, the first semiconductor substrate 1230 includes an element separation portion 1241 that separates the photodiodes PD from each other, and a p-well layer 1242 that is in contact with the side surface of the element separation portion 1241 on the photodiode PD side. The element separating portion 1241 is formed to extend in a normal direction of the main surface of the first semiconductor substrate 1230 (a direction perpendicular to the front surface of the first semiconductor substrate 1230), and electrically separates the adjacent photodiodes PD from each other. The element isolation portion 1241 includes, for example, silicon oxide penetrating the first semiconductor substrate 1230. The p-well layer 1242 is formed of a semiconductor region of a conductivity type (specifically, p-type) different from that of the photodiode PD.

Thereafter, as shown in fig. 43, a p-type transistor TrP, an n-type transistor TrN, and a Fin-type transistor TrF are provided in the second semiconductor substrate 1210. A second insulating layer 1220 is stacked on the second semiconductor substrate 1210 to bury the p-type transistor TrP, the n-type transistor TrN, and the Fin-type transistor TrF. Note that an electrode 1243 electrically connected to the floating diffusion FD is electrically connected to a gate electrode of an amplification transistor provided in the second semiconductor substrate 1210 via a contact portion, not shown, which penetrates the first insulating layer 1240 and the second semiconductor substrate 1210. The electrode 1245 electrically connected to the well contact "well" may be electrically connected to, for example, a P-well (e.g., a first region 1211P or a P-well region 1210P, which will be described later) of the second semiconductor substrate 1210 via a contact, not shown, penetrating the first insulating layer 1240.

Specifically, a P-well region 1210P of the same first conductivity type (i.e., P-type) as the first region 1211P is further provided on a partial region of the first region 1211P, so that an n-type transistor TrN can be formed in the P-well region 1210P. In addition, an N-well region 1210N of the same second conductivity type (i.e., N-type) as the first region 1211N is further provided on a partial region of the first region 1211N, so that the p-type transistor TrP can be formed in the N-well region 1210N. In addition, the fin transistor TrF is disposed over the other region of each of the first regions 1211P and 1211N via the undoped region of the second semiconductor substrate 1210.

This enables the first regions 1211P and 1211N provided in the deep region of the second semiconductor substrate 1210 to reduce the resistance under the depletion layer in the Fin-type transistor TrF. Therefore, potential supply to the body region of the Fin type transistor TrF can be further stabilized. Further, forming the first regions 1211P and 1211N of different conductivity types in the second semiconductor substrate 1210 enables the N-type transistor TrN and the P-type transistor TrP having different polarities to be formed in the second semiconductor substrate 1210, respectively.

Subsequently, a modification of the technique according to the present embodiment is explained with reference to FIGS. 44 to 47. Fig. 44 to 47 are schematic longitudinal cross-sectional views of modifications of the structure of a contact plug with respect to a well region of a field effect transistor provided in a second semiconductor substrate 1210, respectively. Note that in the case where the second substrate 20 includes a plurality of semiconductor substrates stacked in the thickness direction, in the structure set forth below, a contact plug may be provided in each of the stacked plurality of semiconductor substrates (i.e., the second semiconductor substrate 1210 and at least one or more semiconductor substrates provided on the second semiconductor substrate 1210).

Fig. 44 to 47 respectively show a stacked body in which a first substrate 1201(10) formed by stacking a first insulating layer 1240(46) on a first semiconductor substrate 1230(11) and a second substrate 1202(20) formed by stacking a second insulating layer 1220(52) on a second semiconductor substrate 1210(21) are bonded together. Accordingly, fig. 44 to 47 omit illustration of the color filter 40 and the light receiving lens 50 provided on the back surface side of the first substrate 1201 and the third substrate 30 provided on the front surface side of the second substrate 1202.

As shown in fig. 44 to 47, the first substrate 1201 includes the photodiode PD and the transistor Tr1, and the second substrate 1202 includes the transistor Tr2 and the first region 1211 functioning as a well region of the transistor Tr 2. The first region 1211 disposed in the second substrate 1202 is fixed to a predetermined potential via a Contact Plug (Contact Plug) CP electrically connected thereto.

Here, as shown in fig. 44, the contact plug CP may supply a potential to the first region 1211 as a well region via the second region 1260 provided in a part of the region of the front surface of the second semiconductor substrate 1210.

The second region 1260 is, for example, a region containing the first conductivity type impurity at a high concentration to the same extent as the first region 1211, and is provided in a part of the region of the front surface of the second semiconductor substrate 1210. The second region 1260 is not disposed adjacent to the first region 1211, but reduces contact resistance between the contact plug CP and the second semiconductor substrate 1210, so that conductivity between the contact plug CP and the first region 1211 may be enhanced.

As shown in fig. 45, the contact plug CP may supply a potential to the first region 1211 as a well region via the second region 1260 provided in a part of a region of the front surface of the second semiconductor substrate 1210 and the third region 1261 provided in a region adjacent to the second region 1260 and the first region 1211.

The second region 1260 is, for example, a region containing the first conductivity type impurity at a high concentration to the same extent as the first region 1211, and is provided in a part of the region of the front surface of the second semiconductor substrate 1210. The third region 1261 is a region containing a first conductivity type impurity at a lower concentration than the first region 1211 and the second region 1260, and is provided in a region adjacent to the first region 1211 and the second region 1260. Specifically, the third region 1261 may be disposed in a region between the first region 1211 and the second region 1260 in a thickness direction of the second semiconductor substrate 1210. This enables the second region 1260 and the third region 1261 to further enhance the conductivity between the contact plug CP and the first region 1211.

Further, as shown in fig. 46, a contact plug CP1 may be provided to penetrate the second semiconductor substrate 1210 and may be in direct contact with the first region 1211. This enables the contact plugs CP1 to directly supply a potential to the first region 1211, which is the well region, and thus makes it possible to supply a potential to the first region 1211 with a lower resistance.

Note that the second region 1260 containing the first conductive type impurity at a high concentration to the same extent as the first region 1211 may be optionally provided in a part of the region of the front surface of the second semiconductor substrate 1210. The second region 1260 can further enhance the conduction between the contact plug CP1 and the first region 1211.

Further, as shown in fig. 47, a contact plug CP2 may be provided to penetrate the second semiconductor substrate 1210 and the first insulating layer 1240 and to directly contact the first region 1211 and the fourth region 1280 provided in the first semiconductor substrate 1230. The fourth region 1280 is a region containing the first conductive type impurity at a high concentration to the same extent as the first region 1211, and is provided in a part of the region of the front surface of the first semiconductor substrate 1230. The fourth region 1280 is provided to supply a potential to the well region of the first semiconductor substrate 1230.

This enables the contact plugs CP2 to directly supply a potential to the first region 1211 of the second semiconductor substrate 1210 and the fourth region 1280 of the first semiconductor substrate 1230. Therefore, one contact plug CP2 can supply a potential to each of the first semiconductor substrate 1230 and the second semiconductor substrate 1210 laminated together, so that the area efficiency of the imaging device 1 can be improved.

Note that the second region 1260 containing the first conductive type impurity at a high concentration to the same extent as the first region 1211 may be optionally provided in a part of the region of the front surface of the second semiconductor substrate 1210. The second region 1260 can further enhance the conduction between the contact plug CP2 and the first region 1211.

The technique according to the second embodiment of the present disclosure has been described above in detail. According to the technique of the present embodiment, in the second semiconductor substrate 21 including the pixel circuits 22, a well region in which the first conductivity type impurity is introduced into an appropriate region of the second semiconductor substrate 21 can be formed. Therefore, according to the technique of the present embodiment, the reliability of the electrical characteristics of the field effect transistor provided in the second semiconductor substrate 21 can be improved.

(4) third embodiment

Subsequently, a technique according to a third embodiment of the present disclosure is explained with reference to fig. 48 to 55. The technique according to the present embodiment relates to the second semiconductor substrate 21 of the second substrate 20.

In the imaging device 1 configured by laminating three substrates, a well region into which a conductive type impurity is introduced is provided on the back surface side of the second semiconductor substrate 21 to fix the potential of the second semiconductor substrate 21 included in the second substrate 20 to a predetermined potential. The well region is electrically connected to an external power supply or ground so as to supply a reverse bias potential or a ground potential to the field effect transistors provided in the second semiconductor substrate 21.

For example, such a well region may be formed by attaching the first substrate 10 and the second substrate 20 together and then ion-implanting conductive type impurities into a predetermined region of the second semiconductor substrate 21 included in the second substrate 20.

Specifically, after the attachment between the first substrate 10 and the second substrate 20, before the gate structure is formed in the thinned second semiconductor substrate 21 included in the second substrate 20, ion implantation of conductive type impurities is performed.

Here, the thinned second semiconductor substrate 21 has a thickness of about several hundred nm. Therefore, the ion-implanted first conductivity type impurity is widely diffused into the second semiconductor substrate 21, so that the electrical characteristics of the field effect transistor may be affected.

For example, in the case where a conductive type impurity in the well region is diffused into a fin structure of a finfet, current-voltage characteristics of the finfet may be degraded. Therefore, in order to maintain the electrical characteristics of the field effect transistor provided in the second semiconductor substrate 21 well, it is important to appropriately control the diffusion of the conductive type impurity so as not to diffuse the conductive type impurity of the well region to the front surface of the second semiconductor substrate 21.

In view of this situation, the technique according to the present embodiment has been conceived. The technique according to the present embodiment relates to appropriately controlling diffusion of a conductive type impurity by further introducing a non-conductive type impurity to suppress diffusion of the conductive type impurity into a well region of the second semiconductor substrate 21.

Note that in the case where the second substrate 20 includes a plurality of semiconductor substrates stacked in the thickness direction, the technique according to the present embodiment is also applicable to each of the plurality of stacked semiconductor substrates (i.e., the second semiconductor substrate 1310 and at least one or more semiconductor substrates provided on the second semiconductor substrate 1310). Specifically, in addition to the first conductive type impurity, a non-conductive type impurity that suppresses diffusion of the conductive type impurity may be introduced into the first region 1311 of the stacked plurality of semiconductor substrates (i.e., the second semiconductor substrate 1310 and at least one or more semiconductor substrates provided on the second semiconductor substrate 1310).

Fig. 48 and 49 are schematic views of modes of forming the first region 1311 in the second semiconductor substrate 1310 and forming a field-effect transistor, respectively.

As shown in fig. 48 and 49, a first substrate 1301(10) is formed by stacking a first insulating layer 1340(46) over a first semiconductor substrate 1330 (11). A second semiconductor substrate 1310(21) is attached to the first substrate 1301 so as to allow the surface on the side where the first region 1311 is formed to face the first insulating layer 1340. In addition, on the surface on the side opposite to the side where the first region 1311 of the second semiconductor substrate 1310 is formed, the field effect transistor 1300 including the gate electrode 1320, the gate insulating film 1321, the source region 1310S, the drain region 1310D, and the sidewall insulating film 1322 is provided.

The first region 1311 is formed by introducing a first conductivity type impurity and a non-conductivity type impurity into a region on the bonding surface side of the second semiconductor substrate 1310. As a method of introducing the first conductive type impurity and the non-conductive type impurity into the first region 1311, ion implantation can be used. In addition, other known doping methods, such as solid phase diffusion or plasma doping, may be used.

The timing when the first conductive type impurity and the non-conductive type impurity are introduced into the first region 1311 may be after the bonding between the first substrate 1301 and the second semiconductor substrate 1310 as shown in fig. 48, or may be before the bonding between the first substrate 1301 and the second semiconductor substrate 1310 as shown in fig. 49.

For example, the first region 1311 is provided at least in a planar region where field effect transistors are provided, among the entire surface of the second semiconductor substrate 1310. However, to further simplify the manufacturing process, the first region 1311 may be disposed on the entire surface of the second semiconductor substrate 1310.

The non-conductive impurity is a substance that inhibits diffusion of the first-conductivity-type impurity by bonding with the first-conductivity-type impurity. Specifically, in the case where the first conductive type impurity corresponds to boron (B), carbon (C) may be used as the non-conductive type impurity to be combined with the first conductive type impurity. By introducing carbon into the first region 1311 at the same concentration as or higher than the concentration of boron introduced into the second semiconductor substrate 1310 in order to form the first region 1311, diffusion of boron in the second semiconductor substrate 1310 can be suppressed.

In the case where the first conductivity type impurity corresponds to boron (B), fluorine (F) may be used as the non-conductive type impurity to be combined with the first conductivity type impurity. Diffusion of boron in the second semiconductor substrate 1310 can be suppressed by introducing fluorine into the first region 1311 at a higher concentration than boron introduced into the second semiconductor substrate 1310 in order to form the first region 1311.

Therefore, according to the technique of the present embodiment, the first conductivity type impurity introduced into the first region 1311 formed on the back surface side of the second semiconductor substrate 1310 can be suppressed from diffusing to the front surface side of the second semiconductor substrate 1310. This enables the technique according to the present embodiment to suppress a decrease in the electrical characteristics of the field-effect transistor 1300 provided in the second semiconductor substrate 1310.

Subsequently, a modification of the technique according to the present embodiment is explained with reference to fig. 50 and 51. Fig. 50 and 51 are each a schematic cross-sectional view of a modification of the structure of a field-effect transistor provided in the second semiconductor substrate 1310. Fig. 50 and 51 are side views of the field effect transistor viewed in two directions orthogonal to each other in the plane of the second semiconductor substrate 1310.

As shown in fig. 50 and 51, a field effect transistor 1300A is provided over a second semiconductor substrate 1310 attached to a first substrate 1301, and the first substrate 1301 includes a first semiconductor substrate 1330 on which a first insulating layer 1340 is stacked. The field effect transistor 1300A is a fin-type field effect transistor in which a gate electrode 1320 is provided astride a diffusion layer 1312 provided to protrude on the front face of the second semiconductor substrate 1310 via a gate insulating film 1321.

In the field effect transistor 1300A, second conductivity type impurities are introduced into the diffusion layers 1312 provided on both sides sandwiching the gate electrode 1320, thereby forming a source region and a drain region. Further, in the field effect transistor 1300A, the diffusion layer 1312 between the source region and the drain region is covered with the gate electrode 1320 via the gate insulating film 1321 to serve as a channel region. In the field effect transistor 1300A, the gate structure is formed on three surfaces of the upper surface and both side surfaces of the diffusion layer 1312 covered with the gate electrode 1320, and therefore the gate width can be increased as compared with the field effect transistor 1300 formed in the same planar area.

According to the technique of this embodiment, diffusion of the first-conductivity-type impurity contained in the first region 1311 can be suppressed, so that the possibility that the first-conductivity-type impurity may enter the diffusion layer 1312 in which the channel is formed can be reduced. This makes it possible to suppress a decrease in the effective gate width caused by the first conductivity type impurity entering the diffusion layer 1312, so that the electrical characteristics of the field effect transistor 1300A can be favorably maintained.

The technique according to the third embodiment of the present disclosure has been described above in detail. According to the technique of the present embodiment, in the second semiconductor substrate 21 including the pixel circuit 22, by further introducing the non-conductive type impurity combined with the first conductivity type impurity into the well region, the diffusion of the first conductivity type impurity can be suppressed. Therefore, according to the technique of the present embodiment, it is possible to suppress a decrease in the electrical characteristics of the field-effect transistor provided in the second semiconductor substrate 21 caused by diffusion of the first conductivity type impurity.

5. modification

Hereinafter, a modification of the imaging apparatus 1 to which the technique according to the present disclosure is applied is explained. Note that, in the following modification, the components common to those of the above-described image forming apparatus 1 are denoted by the same reference numerals.

(modification 1)

First, a modification 1, which is a cross-sectional configuration in the stacking direction of the imaging device 1, will be described with reference to fig. 52. Fig. 52 is a longitudinal sectional view of a modification of the sectional structure shown in fig. 7.

As shown in fig. 52, in the imaging apparatus 1 according to modification 1, the transfer transistor TR includes a transfer gate TG of a planar type. Therefore, the transfer gate TG does not penetrate the p-well layer 42, but is formed on the front surface of the first semiconductor substrate 11. Even in the case where a planar-type transfer gate TG is used for the transfer transistor TR, the imaging device 1 can achieve effects similar to those described above.

(modification 2)

Next, a modified example 2, which is a modified example of the cross-sectional structure in the stacking direction of the imaging device 1, will be described with reference to fig. 53. Fig. 53 is a longitudinal sectional view of a modification of the sectional structure shown in fig. 7.

As shown in fig. 53, in the imaging device 1 according to modification 2, the electrical connection between the second substrate 20 and the third substrate 30 is formed in the region corresponding to the peripheral region 14 of the first substrate 10. The peripheral region 14 is a region corresponding to a frame region provided around the pixel region 13 of the first substrate 10. In the imaging device 1 according to modification 2, the second substrate 20 includes a plurality of pad electrodes 58 in a region corresponding to the peripheral region 14, and the third substrate 30 includes a plurality of pad electrodes 64 in a region corresponding to the peripheral region 14. This allows the second substrate 20 and the third substrate 30 to be electrically connected to each other by the bonding between the pad electrodes 58 and 64 provided in the region corresponding to the peripheral region 14. Therefore, the imaging device 1 according to modification 2 can reduce the possibility that the pixel region 13 may be affected by the bonding between the pad electrodes 58 and 64, as compared with the case where the pad electrodes 58 and 64 are bonded to each other in the region corresponding to the pixel region 13.

(modification 3)

Further, a configuration example of an imaging device 1B according to modification 3 will be described with reference to fig. 54 to 59. Fig. 54 to 56 are sectional views in the thickness direction showing a configuration example of an imaging device 1B according to modification 3. Fig. 57 to 59 are cross-sectional views in the horizontal direction showing layout examples of a plurality of pixel units PU in the imaging device 1B according to modification 3. Note that the cross-sectional views shown in fig. 57 to 59 are schematic views, and are not intended to strictly and accurately illustrate actual configurations. In the cross-sectional views shown in fig. 57 to 59, the positions of the transistor and the impurity diffusion layer in the horizontal direction are intentionally changed from the position sec1 to the position sec3 in order to easily explain the configuration of the imaging device 1B on the paper surface.

Specifically, in the pixel unit PU of the imaging apparatus 1B shown in fig. 54, the section at the position sec1 is a section taken along the line a1-a1 ' of fig. 57, the section at the position sec2 is a section taken along the line B1-B1 ' of fig. 58, and the section at the position sec3 is a section taken along the line C1-C1 ' of fig. 59. Likewise, in the imaging apparatus 1B shown in fig. 55, the section at the position sec1 is a section taken along the line a2-a2 ' of fig. 57, the section at the position sec2 is a section taken along the line B2-B2 ' of fig. 58, and the section at the position sec3 is a section taken along the line C2-C2 ' of fig. 59. In the imaging apparatus 1B shown in fig. 56, the section at the position sec1 is a section taken along the line A3-A3 ' of fig. 57, the section at the position sec2 is a section taken along the line B3-B3 ' of fig. 58, and the section at the position sec3 is a section taken along the line C3-C3 ' of fig. 59.

As shown in fig. 54 to 59, the second substrate 20 is laminated on the front surface 10a (one surface) side of the first substrate (base substrate) 10. The photodiode PD, the transfer transistor TR, and the floating diffusion FD are disposed on the front face 10a side of the first substrate 10. A photodiode PD, a transfer transistor TR, and a floating diffusion FD are provided for each sensor pixel 12.

The other side (e.g., the back side) of the first substrate 10 is a light incident surface. The imaging device 1B is a back-side illumination type imaging device, and includes a color filter and a light receiving lens on the back side. A color filter and a light receiving lens are provided for each sensor pixel 12.

The first semiconductor substrate 11 of the first substrate 10 includes, for example, a silicon substrate. The first semiconductor substrate 11 includes a well layer WE of a first conductivity type (e.g., p-type) in a part of the front face and the vicinity thereof, and includes a photodiode PD of a second conductivity type (e.g., n-type) in a region deeper than the well layer WE. Further, the well layer WE includes therein a well contact layer having a higher p-type concentration than the well layer WE and an n-type floating diffusion FD. The well contact layer is provided to reduce contact resistance between the well layer WE and the wiring.

The first semiconductor substrate 11 includes an element separation layer 16 that electrically separates adjacent sensor pixels 12 from each other. The element separation layer 16 includes, for example, an STI (shallow trench isolation) structure, and extends in the depth direction of the first semiconductor substrate 11. The element separation layer 16 contains, for example, silicon oxide. Further, the first semiconductor substrate 11 includes an impurity diffusion layer 17 between the element separation layer 16 and the photodiode PD. The impurity diffusion layer 17 includes, for example, a p-type layer and an n-type layer provided extending in the thickness direction of the first semiconductor substrate 11. The p-type layer is on the element separation layer 16 side, and the n-type layer is on the photodiode PD side.

The insulating film 2015 is provided on the front surface 11a side of the first semiconductor substrate 11. The insulating film 2015 is, for example, a film in which one or two or more of a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), and a silicon carbonitride film (SiCN) are stacked.

The second substrate 20 includes a lower substrate 2210 and an upper substrate 2220. The lower substrate 2210 includes a semiconductor substrate 2211. Semiconductor substrate 2211 is a silicon substrate including, for example, single crystal silicon. The amplification transistor AMP and the element separation layer 2213 surrounding the periphery of the amplification transistor AMP are provided on one surface (for example, the front surface 2211a) side of the semiconductor substrate 2211. The element separation layer 2213 electrically separates one amplification transistor AMP and the other amplification transistors AMP of the adjacent pixel units PU from each other.

The lower substrate 2210 includes an insulating film 2215 covering the front surface 2211a of the semiconductor substrate 2211. The insulating film 2215 covers the amplifying transistor AMP and the element separation layer 2213. Further, the lower substrate 2210 includes an insulating film 2217 covering the other surface (e.g., the back surface 2211b) of the semiconductor substrate 2211. The insulating films 2215 and 2217 are each, for example, a film in which one or two or more of SiO, SiN, SiON, and SiCN are stacked. The insulating film 2015 of the first substrate 10 and the insulating film 2217 of the lower substrate 2210 are bonded to each other to constitute an interlayer insulating film 2051.

The upper substrate 2220 includes a semiconductor substrate 2221. The semiconductor substrate 2221 is a silicon substrate including, for example, single crystal silicon. The reset transistor RST, the selection transistor SEL, and the element separation layer 2223 are provided on one surface (for example, the front surface 2221a) side of the semiconductor substrate 2221. For example, the element separation layer 2223 is provided between the reset transistor RST and the selection transistor SEL and between the selection transistor SEL and a well layer of the semiconductor substrate 2221.

The upper substrate 2220 includes an insulating film 2225 covering the front surface 2221a, the back surface 2221b, and the side surfaces of the semiconductor substrate 2221. The insulating film 2225 is, for example, a film in which one or two or more of SiO, SiN, SiON, and SiCN are stacked together. The insulating film 2215 of the lower substrate 2210 and the insulating film 2225 of the upper substrate 2220 are bonded to each other to constitute an interlayer insulating film 2053.

The imaging device 1B includes a plurality of wirings L1 to L10 provided in the interlayer insulating films 2051 and 2053 and electrically connected to at least one of the first substrate 10 or the second substrate 20. The wiring L1 electrically connects the drain of the amplifying transistor AMP and the power supply line VDD. The wiring L2 electrically connects together the four floating diffusion portions FD included in one pixel unit PU and the gate electrode AG of the amplification transistor AMP. The wiring L3 electrically connects the source of the amplification transistor AMP and the drain of the selection transistor SEL together. The wiring L4 electrically connects the gate electrode SG of the selection transistor SEL and the pixel drive line together.

The wiring L5 electrically connects the source of the selection transistor SEL and the vertical signal line together. The wiring L6 electrically connects the drain of the reset transistor RST and the power supply line VDD. The wiring L7 electrically connects the gate electrode RG of the reset transistor RST and the pixel driving line together. The wiring L8 electrically connects the source of the reset transistor RST and the wiring L2. The wiring L9 electrically connects the gate electrode TG of the transfer transistor TR and the pixel drive line together. The wiring L10 electrically connects the well contact layer and a reference potential line for supplying a reference potential (for example, a ground potential: 0V).

In the wirings L1 to L10, the portion extending in the thickness direction of the laminate contains tungsten (W), and the portion extending in a direction (for example, horizontal direction) orthogonal to the thickness direction of the laminate contains copper (Cu) or a Cu alloy mainly containing Cu. However, the materials contained in the wirings L1 to L10 are not limited thereto; other materials may be included.

The second substrate 20 includes a plurality of pad electrodes 2227 connected to any of the above-described wirings L1 to L10 (e.g., wirings L1, L4 to L7, L9, and L10). Each of the plurality of pad electrodes 2227 contains, for example, Cu or a Cu alloy.

The third substrate 30 is disposed on a side (e.g., front surface side) of the second substrate 20 opposite to a surface facing the first substrate 10. The third substrate 30 includes a semiconductor substrate 2301, an insulating film 2304 covering the front face 2301a side of the semiconductor substrate 2301, a plurality of wirings L30 provided on the front face 2301a side of the semiconductor substrate 2301, and pad electrodes 2305 connected to the respective wirings L30. Note that the front surface of the second substrate 20 and the front surface of the third substrate 30 are attached together as described later. For this reason, the front surface 2301a of the semiconductor substrate 2301 faces downward.

The semiconductor substrate 2301 is a silicon substrate including, for example, single crystal silicon. The semiconductor substrate 2301 includes an impurity diffusion layer and a plurality of transistors included in a logic circuit on the front side 2301 a. The insulating film 2304 covers the impurity diffusion layer and a plurality of transistors included in the logic circuit. The insulating film 2304 includes contact holes connected to the transistors and the impurity diffusion layers.

The wiring L30 is disposed in the contact hole. In the wiring L30, a portion extending in the thickness direction of the third substrate 30 contains titanium (Ti) or cobalt (Co), and a portion extending in a direction (for example, horizontal direction) orthogonal to the thickness direction of the third substrate 30 contains Cu or a Cu alloy mainly containing Cu. However, the material contained in the wiring L30 is not limited thereto; other materials may be included.

Silicide 2303 (e.g., titanium silicide (TiSi) or cobalt silicide (CoSi)₂) Is formed at the connection portion between the wiring L30 and the semiconductor substrate 2301. The silicide 2303 allows the connection between the wiring L30 and the semiconductor substrate 2301 to be close to ohmic contact, thereby reducing contact resistance. This enables higher operation speed of the logic circuit.

Note that silicide is not formed in the first substrate 10 and the second substrate 20. This enables heat treatment or the like at a temperature exceeding the heat-resistant temperature of the silicide when the first substrate 10 and the second substrate 20 are formed. However, a silicide may be formed in at least one of the first substrate 10 and the second substrate 20.

Each of the plurality of pad electrodes 2305 contains, for example, Cu or a Cu alloy. In the thickness direction of the imaging device 1B, the pad electrode 2305 of the third substrate 30 faces the pad electrode 2227 of the second substrate 20 to allow electrical connection. For example, the pad electrodes 2305 and 2227 are integrated by Cu — Cu bonding in a state of facing each other. This allows electrical connection between the second substrate 20 and the third substrate 30, and allows the bonding strength between the second substrate 20 and the third substrate 30 to be enhanced.

In the imaging device 1B according to modification 3, one floating diffusion contact may be provided for each of the plurality of sensor pixels 12. For example, four sensor pixels 12 adjacent to each other may share one contact for a floating diffusion. Similarly, one well contact may be provided for each of the plurality of sensor pixels 12. For example, four sensor pixels 12 adjacent to each other may share one well contact.

Specifically, as shown in fig. 54 and 59, the imaging device 1B shares a common pad electrode 2102 arranged across the plurality of sensor pixels 12 and one wiring L2 provided on the common pad electrode 2102. For example, in the imaging device 1B, there are the following areas: the floating diffusion portions FD1 to FD4 of the four sensor pixels 12 are adjacent to each other via the element separation layer 16 in plan view. The common pad electrode 2102 is disposed in this area. The common pad electrode 2102 is disposed across the four floating diffusions FD 1-FD 4, and is electrically connected to each of the four floating diffusions FD 1-FD 4. The common pad electrode 2102 is made of, for example, a polysilicon film doped with an n-type impurity or a p-type impurity.

One line L2 (i.e., a floating diffusion contact) is provided in the center of the common pad electrode 2102. As shown in fig. 55 and fig. 57 to 59, the wiring L2 provided on the central portion of the common pad electrode 2102 extends from the first substrate 10 to the upper substrate 2220 of the second substrate 20 through the lower substrate 2210 of the second substrate 20, and is connected to the gate electrode AG of the amplifying transistor AMP via a wiring or the like provided in the upper substrate 2220.

Further, as shown in fig. 54 and fig. 59, the imaging device 1B shares the common pad electrode 2110 arranged across the plurality of sensor pixels 12 and the one wiring L10 provided on the common pad electrode 2110. For example, in the imaging device 1B, there are the following areas: in a plan view, the respective well layers WE of the four sensor pixels 12 are adjacent to each other via the element separation layer 16. The common pad electrode 2110 is provided in this region. The common pad electrode 2110 is disposed across the respective well layers WE of the four sensor pixels 12, and is electrically connected to the respective well layers WE of the four sensor pixels 12. As an example, the common pad electrode 2110 is disposed between one common pad electrode 2102 and the other common pad electrode 2102 disposed in the Y-axis direction. In the Y-axis direction, the common pad electrodes 2102 and 2110 are alternately arranged. The common pad electrode 2110 is made of, for example, a polysilicon film doped with an n-type impurity or a p-type impurity.

One wiring L10 (i.e., a well contact) is provided in the center of the common pad electrode 2110. As shown in fig. 54 and fig. 57 to 59, the wiring L10 provided at the center of the common pad electrode 2110 extends from the first substrate 10 through the lower substrate 2210 of the second substrate 20 to the upper substrate 2220 of the second substrate 20, and is connected to a reference potential line supplying a reference potential (for example, a ground potential: 0V) via a wiring or the like provided in the upper substrate 2220.

The wiring L10 provided on the center portion of the common pad electrode 2110 is electrically connected to the upper surface of the common pad electrode 2110, the inner side surface of the through hole provided in the lower substrate 2210, and the inner side surface of the through hole provided in the upper substrate 2220. Therefore, the well layer WE of the first semiconductor substrate 11 of the first substrate 10, the well layer of the lower substrate 2210, and the well layer of the upper substrate 2220 of the second substrate 20 are connected to a reference potential (e.g., ground potential: 0V).

The imaging device 1B according to modification 3 further includes common pad electrodes 2102 and 2110 that are provided on the front face 11a side of the first semiconductor substrate 11 constituting the first substrate 10 and are arranged adjacent to each other across a plurality of (e.g., four) sensor pixels 12. The common pad electrode 2102 is electrically connected to the floating diffusions FD of the four sensor pixels 12, and therefore the wiring L2 connected to the floating diffusion FD can be shared for every four sensor pixels 12. Further, the common pad electrode 2110 is electrically connected to the well layers WE of the four sensor pixels 12, and therefore the wiring L10 connected to the well layers WE can be shared for every four sensor pixels 12. Therefore, since the number of the wirings L2 and L10 can be reduced, the area of the sensor pixel 12 can be reduced, and the size of the imaging device 1B can be reduced.

(modification 4)

Subsequently, a modification 4 configured as a cross section in the horizontal direction of the imaging apparatus 1 will be described with reference to fig. 60 and 61. Fig. 60 and 61 each show a modification of the cross-sectional configuration along the cutting plane Sec1 in fig. 7 in the upper view, and fig. 60 and 61 each show a modification of the cross-sectional configuration along the cutting plane Sec2 in fig. 7 in the lower view.

As shown in fig. 60 and 61, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in a stripe shape in the first direction V1 (the left-right direction in fig. 60 and 61) within the plane of the first substrate 10. Fig. 60 and 61 illustrate a case where the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two rows in the first direction V1.

In the four sensor pixels 12 sharing the pixel circuit 22, for example, four floating diffusion portions FD are arranged close to each other via the element isolation portion 43. In the four sensor pixels 12 sharing the pixel circuit 22, four transfer gates (TG1, TG2, TG3, and TG4) are arranged so as to surround the four floating diffusions FD, and the four transfer gates TG form, for example, a ring shape.

The separation insulating layer 53 includes a plurality of blocks extending in the second direction V2. The second semiconductor substrate 21 includes a plurality of island-shaped blocks 21A extending in the first direction V1 and arranged side by side in the first direction V1. Each block 21A is provided with, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. For example, one pixel circuit 22 shared by four sensor pixels 12 is not arranged corresponding to the four sensor pixels 12, but arranged offset in the second direction V2.

In fig. 60, one pixel circuit 22 shared by four sensor pixels 12 includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL in a region of the second substrate 20 where regions corresponding to the four sensor pixels 12 are shifted in the second direction V2. One pixel circuit 22 shared by the four sensor pixels 12 includes, for example, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL within one block 21A.

In fig. 61, one pixel circuit 22 shared by four sensor pixels 12 includes a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD conversion gain switching transistor FDG in a region of the second substrate 20 where regions corresponding to the four sensor pixels 12 are shifted in the second direction V2. One pixel circuit 22 shared by the four sensor pixels 12 includes, for example, an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, and an FD conversion gain switching transistor FDG within one block 21A.

In the imaging device 1 according to modification 4, one pixel circuit 22 shared by four sensor pixels 12 is not arranged directly opposite to the four sensor pixels 12, but is shifted in the second direction V2 from a position directly opposite to the four sensor pixels 12. According to such a configuration, the imaging device 1 according to modification 4 may shorten the wiring 25, or may omit the wiring 25 and form the source of the amplification transistor AMP and the drain of the selection transistor SEL in a common impurity region. As a result, the imaging device 1 according to modification 4 can reduce the size of the pixel circuit 22.

(modification 5)

Next, a modification 5, which is a modification of the horizontal cross-sectional configuration of the imaging device 1, will be described with reference to fig. 62. Fig. 62 is a schematic view of a modification of the cross-section along the cutting planes Sec1 and Sec2 in fig. 7.

As shown in fig. 62, the second semiconductor substrate 21 includes a plurality of island-shaped blocks 21A arranged side by side in the first direction V1 and the second direction V2 via the separation insulating layer 53. Each block 21A includes, for example, one set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In this case, the imaging device 1 according to modification 5 can suppress crosstalk between the pixel circuits 22 adjacent to each other by the separation insulating layer 53, and can suppress a decrease in resolution of an image and deterioration in image quality caused by color mixing.

(modification 6)

Next, a modification 6 as a modification of the horizontal cross-sectional configuration of the imaging device 1 will be described with reference to fig. 63. Fig. 63 is a schematic view of a modification of the cross-section along the cutting planes Sec1 and Sec2 in fig. 7.

In fig. 63, in the second semiconductor substrate 21, one pixel circuit 22 shared by four sensor pixels 12 is not disposed corresponding to the four sensor pixels 12, for example, but is offset in the first direction V1. In addition, in the imaging device 1 of modification 6, the second semiconductor substrate 21 includes a plurality of island-shaped blocks 21A arranged side by side in the first direction V1 and the second direction V2 via the separation insulating layer 53. Each block 21A is provided with, for example, one set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. Further, in the imaging device 1 according to modification 6, the plurality of through wirings 47 and the plurality of through wirings 54 are arranged in the second direction V2.

This allows the plurality of through wirings 47 to be arranged between the four through wirings 54 sharing one pixel circuit 22 and the four through wirings 54 sharing the other pixel circuit 22 adjacent to this pixel circuit 22 in the second direction V2. This makes it possible for the imaging device 1 according to modification 6 to suppress crosstalk between the pixel circuits 22 adjacent to each other by separating the insulating layer 53 through wirings 47, and to suppress a decrease in resolution of an image and deterioration in image quality caused by color mixing.

(modification 7)

Next, a modification 7, which is a modification of the horizontal cross-sectional configuration of the imaging device 1, will be described with reference to fig. 64 to 66. Fig. 64 is a schematic view of a modification of the cross-section along the cutting planes Sec1 and Sec2 in fig. 7.

As shown in fig. 64, in the imaging apparatus 1 according to modification 7, the first substrate 10 has a photodiode PD and a transfer transistor TR (i.e., a transfer gate TG) for each sensor pixel 12, and the floating diffusion FD is shared by every four sensor pixels 12. Therefore, the imaging device 1 according to modification 7 provides one through wiring 54 for every four sensor pixels 12.

In addition, in the imaging apparatus 1 according to modification 7, one through wiring 47 is provided for a region obtained by shifting unit regions corresponding to four sensor pixels 12 sharing one floating diffusion FD by one sensor pixel 12 in the second direction V2. That is, in the imaging apparatus 1 according to modification 7, the through wiring 47 is provided between the unit regions corresponding to the four sensor pixels 12 sharing one floating diffusion FD and the adjacent unit region adjacent to the unit region in the second direction V2. The through wiring 47 is shared by two sensor pixels 12 in a unit region around the through wiring 47 and two sensor pixels 12 in an adjacent unit region around the through wiring 47.

Further, in the imaging device 1 according to modification 7, the first substrate 10 has an element separating portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12. When viewed from the normal direction of the main surface of the first semiconductor substrate 11, the element separating portion 43 does not completely surround the periphery of the sensor pixel 12, and therefore an air gap (non-formed region) exists in the vicinity of the floating diffusion FD (i.e., the through wiring 54) and in the vicinity of the through wiring 47. The air gap enables the four sensor pixels 12 to share the through wiring 54, and enables the four sensor pixels 12 to share the through wiring 47 between the unit region and the adjacent unit region. Note that in the imaging apparatus 1 according to modification 7, the second substrate 20 includes the pixel circuit 22 for every four sensor pixels 12 sharing the floating diffusion FD.

Fig. 65 and 66 are each a schematic diagram of another example constituted along a cross section of the cutting plane Sec2 of the imaging device 1 according to modification 7. As shown in fig. 65, the first substrate 10 may have a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion FD may be shared by every four sensor pixels 12. Further, the first substrate 10 may have an element separating portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12. Further, as shown in fig. 66, there may be a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion FD may be shared by every four sensor pixels 12. Further, the first substrate 10 may have an element separating portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

(modification 8)

Next, a modified example 8 as a modified example of the circuit configuration of the imaging device 1 will be described with reference to fig. 67. Fig. 67 is a schematic diagram of a circuit configuration of a CMOS image sensor mounted with column-parallel ADCs (analog-to-digital converters).

As shown in fig. 67, an imaging device 1 according to modification 8 includes a pixel region 13, a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply section 38, a horizontal drive circuit 35, a horizontal output line 37, and a system control circuit 36, wherein each pixel region 13 includes a plurality of sensor pixels 12 including photoelectric conversion elements two-dimensionally arranged in a row-column shape (matrix shape).

The system control circuit 36 generates a clock signal, a control signal, and the like based on the master clock MCK as a reference for the operations of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply section 38, the horizontal drive circuit 35, and the like. The system control circuit 36 further supplies the generated clock signal, control signal, and the like to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply section 38, the horizontal drive circuit 35, and the like.

The vertical driving circuit 33 is formed in each of the first substrate 10 in which the respective sensor pixels 12 of the pixel region 13 are formed and the second substrate 20 in which the pixel circuits 22 are formed. The column signal processing circuit 34, the reference voltage supply section 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 are formed in the third substrate 30.

Although not shown here, the sensor pixel 12 includes, for example, a photodiode PD and a transfer transistor TR that transfers charges photoelectrically converted in the photodiode PD to a floating diffusion FD. The pixel circuit 22 includes, for example, a reset transistor RST for controlling the potential of the floating diffusion FD, an amplification transistor AMP for outputting a signal corresponding to the potential of the floating diffusion FD, and a selection transistor SEL for selecting a pixel.

The sensor pixels 12 are two-dimensionally arranged in the pixel region 13. For example, in the pixel region 13 in which the sensor pixels 12 are arranged in n rows and m columns in a matrix, the pixel drive lines 23 are wired for each row, and the vertical signal lines 24 are wired for each column. One end of each of the plurality of pixel drive lines 23 is connected to an output terminal corresponding to each row of the vertical drive circuit 33. The vertical drive circuit 33 includes a shift register or the like, and performs control of row addressing or row scanning of the pixel region 13 via a plurality of pixel drive lines 23.

The column signal processing circuit 34 includes, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m, each provided for each pixel column of the pixel region 13, that is, for each vertical signal line 24. The column signal processing circuit 34 converts an analog signal output from each column of the respective sensor pixels 12 in the pixel region 13 into a digital signal, and outputs the digital signal.

The reference voltage supply section 38 includes, for example, a DAC (digital-analog conversion circuit) 38A, and generates a reference voltage Vref of a so-called RAMP (RAMP) waveform whose level changes with time inclination. Note that the reference voltage supply section 38 may generate the reference voltage Vref of the ramp waveform by means other than the DAC 38A.

The DAC 38A generates a reference voltage Vref of a ramp waveform based on a control signal CS1 supplied from the system control circuit 36 and a clock CK, and supplies the generated reference voltage Vref to the ADCs 34-1 to 34-m of the column processing unit 15.

Note that each of the ADCs 34-1-34-m is configured to selectively perform an AD conversion operation corresponding to each operation mode, including a normal frame rate mode in a progressive scanning manner in which information of all the sensor pixels 12 is read out, and a high-speed frame rate mode in which the exposure time of the sensor pixels 12 is set to 1/N of the normal frame rate mode to increase the frame rate by N times (e.g., twice). Switching between the operation modes is performed by control of control signals CS2 and CS3 supplied from the system control circuit 36. In addition, based on instruction information from an external system controller (not shown), the system control circuit 36 generates control signals CS2 and CS3 for switching between operation modes of the normal frame rate mode and the high speed frame rate mode.

The ADCs 34-1 to 34-m all have the same configuration, and the ADC34-m is described here as an example.

ADC34-m includes comparator 34A, up/down counter (U/D CNT)34B, transfer switch 34C, and storage device 34D.

The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 in the mth column of the pixel region 13 with the reference voltage Vref of the ramp waveform supplied from the reference voltage supply section 38. For example, the comparator 34A sets the output Vco to the "H" level in the case where the reference voltage Vref is greater than the signal voltage Vx, and sets the output Vco to the "L" level in the case where the reference voltage Vref is equal to or less than the signal voltage Vx.

The up/down counter 34B is an asynchronous counter. The up/down counter 34B is supplied with a clock CK from the system control circuit 36 in accordance with a control signal CS2 supplied from the system control circuit 36. The UP/DOWN counter 34B performs DOWN (DOWN) counting or UP (UP) counting in synchronization with the clock CK, thereby measuring a comparison period from the start to the end of the comparison operation in the comparator 34A.

Specifically, in the normal frame rate mode, the up/down counter 34B performs down-counting at the first readout operation from one sensor pixel 12, thereby measuring the comparison time at the first readout. Further, the up/down counter 34B performs up-counting at the time of the second readout operation, thereby measuring the comparison time at the time of the second readout.

On the other hand, in the high speed frame rate mode, the up/down counter 34B holds the count results of the sensor pixels 12 of a certain row as they are. Thereafter, the up/down counter 34B performs down-counting at the first readout operation by following the previous count result for the sensor pixels 12 of the next row, thereby measuring the comparison time at the first readout. Further, the up/down counter 34B performs up-counting at the time of the second readout operation, thereby measuring the comparison time at the time of the second readout.

The transfer switch 34C operates based on a control signal CS3 supplied from the system control circuit 36. In the normal frame rate mode, when the counting operation by the up/down counter 34B is completed for the sensor pixels 12 of a certain row, the transfer switch 34C becomes ON (closed) state, thereby transferring the count result of the up/down counter 34B to the storage device 34D.

On the other hand, for example, at a high-speed frame rate of N ═ 2, when the counting operation by the up/down counter 34B is completed for the sensor pixels 12 of a certain row, the transfer switch 34C is held in the OFF (on) state. Thereafter, when the counting operation by the up/down counter 34B for the sensor pixel 12 of the next row is completed, the transfer switch 34C becomes the ON state, thereby transferring the counting results of the two vertical pixels of the up/down counter 34B to the storage device 34D.

As described above, the analog signals supplied column by column from the sensor pixels 12 in the pixel region 13 via the vertical signal lines 24 are converted into N-bit digital signals by the respective operations of the comparators 34A and the up/down counters 34B in the ADCs 34-1 to 34-m, and the digital signals are stored in the storage device 34D.

The horizontal drive circuit 35 includes a shift register and the like, and performs control of column addressing and column scanning for the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, N-bit digital signals obtained by A/D conversion in each of the ADCs 34-1 to 34-m are sequentially read out to the horizontal output line 37. The read N-bit digital signal is output as imaging data via the horizontal output line 37.

Note that although a specific illustration is not given, a circuit or the like that performs various kinds of signal processing on imaging data output via the horizontal output line 37 may be provided in addition to the above-described constituent elements.

In the image forming apparatus 1 according to modification 8, the count result of the up/down counter 34B can be selectively transmitted to the storage device 34D via the transmission switch 34C. This makes it possible for the imaging device 1 according to modification 8 to independently control the counting operation of the up/down counter 34B and the operation of reading out the count result of the up/down counter 34B to the horizontal output line 37.

(modification 9)

Next, a modification 9 as a modification of the laminated structure of the image forming apparatus 1 will be described with reference to fig. 68. Fig. 68 is a schematic diagram of a configuration example in which the imaging device 1 shown in fig. 67 includes three substrates stacked.

As shown in fig. 68, an image forming apparatus 1 according to modification 9 has a configuration in which a first substrate 10, a second substrate 20, and a third substrate are stacked. A pixel region 13 including a plurality of sensor pixels 12 is formed at a central portion of the first substrate 10, and a vertical driving circuit 33 is formed around the pixel region 13. Further, a pixel circuit region 15 including a plurality of pixel circuits 22 is formed at a central portion of the second substrate 20, and a vertical driving circuit 33 is formed around the pixel circuit region 15. Further, a column signal processing circuit 34, a horizontal driving circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply section 38 are formed in the third substrate 30. Note that the vertical driving circuit 33 may be formed in both the first substrate 10 and the second substrate 20 as described above, may be formed only in the first substrate 10, or may be formed only in the second substrate 20. The imaging device 1 according to modification 9 can suppress an increase in chip size or an increase in pixel area due to the structure in which the substrates are electrically connected to each other. This makes it possible for the imaging apparatus 1 according to modification 9 to be more miniaturized in area per pixel.

(modification 10)

Next, a modified example 10, which is a modified example of the cross-sectional configuration of the imaging device 1, will be described with reference to fig. 69 and 70. Fig. 69 is a schematic diagram of an example of a sectional configuration of the imaging device 1 according to modification 10.

The above-described embodiment and the modifications exemplify a configuration in which the image forming apparatus 1 includes three substrates of the first substrate 10, the second substrate 20, and the third substrate 30, which are laminated. However, the technique according to the present disclosure is not limited to the above example. For example, the imaging device 1 may be configured by laminating two substrates, the first substrate 10 and the second substrate 20.

As shown in fig. 69, in this case, for example, the processing circuits 32 are formed in the first substrate 10 and the second substrate 20, respectively.

The circuit 32A provided on the first substrate 10 side among the processing circuits 32 includes a transistor having a gate configuration in which a high dielectric constant film containing a material resistant to a high temperature process (e.g., a high-k material) and a metal gate electrode are laminated.

On the other hand, in the circuit 32B provided on the second substrate 20 side among the processing circuits 32, such as CoSi is contained₂And a low-resistance region 26 of silicide such as NiSi is provided on the front surface of the impurity diffusion region in contact with the source electrode and the drain electrode. The low-resistance region containing silicide is formed of a compound of a material of the semiconductor substrate and a metal, and has high heat resistance. Thus, can use A high temperature process such as thermal oxidation forms the sensor pixels 12. In addition, containing such as CoSi₂And the low-resistance region 26 of silicide such as NiSi can reduce contact resistance, thereby making it possible to achieve higher operation speed in the processing circuit 32.

Note that inclusion of, for example, CoSi may be provided in the image forming apparatus 1 according to any one of the above-described embodiments and modifications₂And a low resistance region 26 of silicide such as NiSi. Specifically, the imaging device 1 configured by laminating three substrates, i.e., the first substrate 10, the second substrate 20, and the third substrate 30, further includes a substrate including a material such as CoSi₂And a low resistance region 26 of silicide such as NiSi. FIG. 70 is a diagram in which a CoSi such as CoSi is to be contained₂And a low-resistance region 26 of silicide such as NiSi are applicable to a schematic view of an example of the imaging device 1 including three substrates stacked.

As shown in fig. 70, a film containing an impurity such as CoSi may be provided on the front face of the impurity diffusion region in contact with the source electrode and the drain electrode₂And a low resistance region 26 of silicide such as NiSi. This allows the sensor pixel 12 to be formed using a high temperature process such as thermal oxidation. In addition, containing such as CoSi₂And the low-resistance region 26 of silicide such as NiSi can reduce contact resistance, thereby making it possible to achieve higher operation speed in the processing circuit 32.

EXAMPLE 6 concrete

The above-described technique according to the present disclosure is applicable to various imaging apparatuses and the like. Hereinafter, an image forming apparatus and an apparatus including the image forming apparatus, to which the technique according to the present disclosure is applied, are explained with reference to specific examples.

<6.1 > first embodiment

(functional constitution of image Forming apparatus 1)

Fig. 71 is a block diagram illustrating an example of a functional configuration of an image forming apparatus (image forming apparatus 1) according to an embodiment of the present disclosure.

The imaging device 1 of fig. 71 includes, for example, an input unit 510A, a row driving unit 520, a timing control unit 530, a pixel array unit 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

In the pixel array unit 540, the pixels 541 are repeatedly arranged in an array. More specifically, the pixel sharing units 539 including a plurality of pixels form a repeating unit, and are repeatedly arranged in an array shape in the row direction and the column direction. Note that in this specification, for convenience, the row direction may be referred to as an H direction, and the column direction orthogonal to the row direction may be referred to as a V direction. In the example of fig. 71, one pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (shown in fig. 76 and the like described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (a pixel circuit 210 in fig. 73 to be described later). In other words, one pixel circuit (a pixel circuit 210 described later) is provided for every four pixels (the pixels 541A, 541B, 541C, and 541D). By operating the pixel circuit in a time-division manner, respective pixel signals of the pixels 541A, 541B, 541C, and 541D are sequentially read out. The pixels 541A, 541B, 541C, and 541D are arranged in two rows × two columns, for example. In the pixel array unit 540, a plurality of row driving signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 are provided along with the pixels 541A, 541B, 541C, and 541D. The row driving signal line 542 drives a pixel 541 included in each of a plurality of pixel sharing units 539 arranged side by side in the row direction in the pixel array unit 540. In the pixel sharing unit 539, pixels arranged side by side in the row direction are driven. As will be described later in detail with reference to fig. 74, the pixel sharing unit 539 is provided with a plurality of transistors. To drive each of the plurality of transistors, a plurality of row driving signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to a vertical signal line (column readout line) 543. Pixel signals are read out from the respective pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 via a vertical signal line (column readout line) 543.

The row driving unit 520 includes, for example, a row address control section (in other words, a row decoder unit) which determines a row position for pixel driving, and a row driving circuit unit which generates signals for driving the pixels 541A, 541B, 541C, and 541D.

The column signal processing unit 550 includes, for example, a load circuit unit which is connected to the vertical signal line 543 and forms a source follower circuit with the pixels 541A, 541B, 541C, and 541D (the pixel sharing unit 539). The column signal processing unit 550 may have an amplifier circuit unit that amplifies a signal read out from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may have a noise processing unit. In the noise processing unit, for example, as a result of photoelectric conversion, the noise level of the system is removed from the signal read out from the pixel sharing unit 539.

The column signal processing unit 550 has, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, a signal read out from the pixel sharing unit 539 or the above-described analog signal subjected to noise processing is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, an analog signal to be converted and a reference signal as a comparison object of the signal are compared. In the counter unit, the time until the comparison result in the comparator unit is inverted is measured. The column signal processing unit 550 may include a horizontal scanning circuit unit that performs control to scan out columns.

The timing control unit 530 supplies a signal for controlling timing to the row driving unit 520 and the column signal processing unit 550 based on a reference clock signal and a timing control signal input to the device.

The image signal processing unit 560 is a circuit that performs various signal processes on data obtained as a result of photoelectric conversion (in other words, data obtained as an imaging operation in the imaging apparatus 1). The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may include a processor unit.

An example of the signal processing performed by the image signal processing unit 560 is tone curve correction processing that increases the gradation in the case where the AD-converted imaging data is data obtained by imaging a dark subject, and decreases the gradation in the case where it is data obtained by imaging a bright subject. In this case, regarding the tone curve to be corrected based on the gradation of the imaged data, it is desirable to store the characteristic data of the tone curve in the data holding unit of the image signal processing unit 560 in advance.

The input unit 510A is used to input, for example, the above-described reference clock signal, timing control signal, characteristic data, and the like from outside the apparatus to the imaging apparatus 1. The timing control signal is, for example, a vertical synchronization signal, a horizontal synchronization signal, or the like. The characteristic data is stored in the data holding unit of the image signal processing unit 560, for example. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is used to acquire a signal input to the input terminal 511 to the inside of the imaging device 1. In the input amplitude changing unit 513, the amplitude of the signal acquired by the input circuit unit 512 is changed to an amplitude that can be easily used inside the imaging apparatus 1. In the input data conversion circuit unit 514, the arrangement of the data columns of the input data is changed. The input data conversion circuit unit 514 includes, for example, a serial-parallel conversion circuit. In the serial-parallel conversion circuit, a serial signal received as input data is converted into a parallel signal. Note that in the input unit 510A, the input amplitude changing unit 513 and the input data converting circuit unit 514 may be omitted. The power supply unit supplies power set to various voltages necessary inside the image forming apparatus 1 based on power supplied from the outside to the image forming apparatus 1.

When the imaging apparatus 1 is connected to an external storage device, the input unit 510A may be provided with a storage interface circuit that receives data from the external storage device. Examples of the external storage device include flash memory, SRAM, DRAM, and the like.

The output unit 510B outputs the image data to the outside of the apparatus. The image data includes, for example, image data captured by the imaging apparatus 1, image data signal-processed by the image signal processing unit 560, and the like. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude change unit 516, an output circuit unit 517, and an output terminal 518.

The output data conversion circuit unit 515 is constituted by, for example, a parallel-to-serial conversion circuit, and in the output data conversion circuit unit 515, parallel signals used inside the imaging device 1 are converted into serial signals. The output amplitude changing unit 516 changes the amplitude of a signal used inside the imaging apparatus 1. The signal having the changed amplitude is easily used in an external device connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from the inside of the imaging device 1 to the outside of the device, and the output circuit unit 517 drives wiring outside the imaging device 1 connected to the output terminal 518. At the output terminal 518, data is output from the imaging apparatus 1 to the outside of the apparatus. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude changing unit 516 may be omitted.

When the imaging apparatus 1 is connected to an external storage device, the output unit 510B may be provided with a storage interface circuit that outputs data to the external storage device. Examples of the external storage device include flash memory, SRAM, DRAM, and the like.

[ schematic constitution of image Forming apparatus 1 ]

Fig. 72 and 73 show an example of a schematic configuration of the imaging apparatus 1. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). Fig. 72 schematically shows a planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300, and fig. 73 schematically shows a sectional configuration of the first substrate 100, the second substrate 200, and the second substrate 300 stacked on each other. Fig. 73 corresponds to a sectional configuration taken along the line III-III' shown in fig. 72. The imaging device 1 is an imaging device having a three-dimensional structure formed by bonding three substrates (a first substrate 100, a second substrate 200, and a third substrate 300) together. The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film surrounding the wiring is referred to as a wiring layer (100T, 200T, and 300T) provided in each substrate (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are laminated in this order, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are sequentially arranged along the lamination direction. Specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrow shown in fig. 73 indicates the direction of the light L incident on the imaging device 1. In this specification, for convenience, in the following sectional views, the light incident side in the imaging device 1 may be referred to as "lower portion", "lower side", and "lower side" and the side opposite to the light incident side as "upper portion", "upper side", and "upper side". In addition, in this specification, for convenience, with respect to a substrate including a semiconductor layer and a wiring layer, a surface on the wiring layer side may be referred to as a front surface and a surface on the semiconductor layer side may be referred to as a back surface. Note that the description of the present specification is not limited to the above terms. The imaging device 1 is, for example, a back-illuminated type imaging device in which light is incident from the back side of the first substrate 100 having the photodiode.

The pixel array unit 540 and the pixel sharing unit 539 included in the pixel array unit 540 are configured by using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C and a pixel 541D included in the pixel sharing unit 539. Each of the pixels 541 has a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (a pixel circuit 210 described later) included in the pixel sharing unit 539. The pixel circuit reads out a pixel signal transmitted from the photodiode of each of the pixels 541A, 541B, 541C, and 541D via the transfer transistor, or resets the photodiode. In addition to such pixel circuits, the second substrate 200 has a plurality of row driving signal lines 542 extending in a row direction and a plurality of vertical signal lines 543 extending in a column direction. The second substrate 200 further includes a power supply line 544 (a power supply line VDD and the like described later) extending in the row direction. The third substrate 300 has, for example, an input unit 510A, a row driving unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. For example, the row driving unit 520 is disposed in a region partially overlapping the pixel array unit 540 in a lamination direction (hereinafter, simply referred to as a lamination direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, in the stacking direction, the row driving unit 520 is disposed in a region overlapping with the vicinity of the end in the H direction of the pixel array unit 540 (fig. 72). In the stacking direction, the column signal processing unit 550 is disposed, for example, in a region partially overlapping with the pixel array unit 540. More specifically, in the stacking direction, the column signal processing unit 550 is disposed in a region overlapping with the vicinity of the end in the V direction of the pixel array unit 540 (fig. 72). Although not shown, the input unit 510A and the output unit 510B may be disposed in a portion other than the third substrate 300, and may be disposed, for example, in the second substrate 200. Alternatively, the input unit 510A and the output unit 510B may be disposed on the rear surface (light incident surface) side of the first substrate 100. Note that the pixel circuit provided over the second substrate 200 may also be referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit as an alternative. In this specification, the term "pixel circuit" is used.

The first substrate 100 and the second substrate 200 are electrically connected to each other by, for example, through-electrodes (through-electrodes 120E and 121E in fig. 76 described later). The second substrate 200 and the third substrate 300 are electrically connected to each other via, for example, contacts 201, 202, 301, and 302. The second substrate 200 is provided with contacts 201 and 202, and the third substrate 300 is provided with contacts 301 and 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R provided with a plurality of contacts 201 and a contact region 202R provided with a plurality of contacts 202. The third substrate 300 has a contact region 301R provided with a plurality of contacts 301 and a contact region 302R provided with a plurality of contacts 302. The contact regions 201R and 301R are disposed between the pixel array unit 540 and the row driving unit 520 in the stacking direction (fig. 73). In other words, the contact regions 201R and 301R are provided in a region where the row driving unit 520 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, for example, or in the vicinity of the region. The contact regions 201R and 301R are arranged at, for example, the ends in the H direction in this region (fig. 72). In the third substrate 300, for example, the contact region 301R is provided at a position overlapping with a part of the row driving unit 520 (specifically, an end portion of the row driving unit 520 in the H direction) (fig. 72 and 73). The contact portions 201 and 301 connect, for example, the row driving unit 520 provided in the third substrate 300 and the row driving line 542 provided in the second substrate 200. The contacts 201 and 301 may connect, for example, the input cell 510A provided in the third substrate 300 to a power supply line 544 and a reference potential line (reference potential line VSS described later). The contact regions 202R and 302R are disposed between the pixel array unit 540 and the column signal processing unit 550 in the stacking direction (fig. 73). In other words, the contact regions 202R and 302R are provided in a region where the column signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, for example, or in the vicinity of the region. The contact regions 202R and 302R are arranged at, for example, the ends in the V direction in this region (fig. 72). In the third substrate 300, for example, the contact region 301R is provided at a position overlapping with a part of the column signal processing unit 550 (specifically, the end in the V direction of the column signal processing unit 550) (fig. 72 and 73). For example, the contacts 202 and 302 are used to connect a pixel signal (a signal corresponding to the amount of charge generated as photoelectric conversion by a photodiode) output from each of the plurality of pixel sharing units 539 included in the pixel array unit 540 to the column signal processing unit 550 provided in the third substrate 300. The pixel signal is transmitted from the second substrate 200 to the third substrate 300.

Fig. 73 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the image forming apparatus 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, the contacts 201, 202, 301, and 302 are formed of electrodes formed from a conductive material. The conductive material is formed of, for example, a metal material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate 200 and the third substrate 300 by directly bonding wires formed as electrodes to each other, for example, so that signals can be input and/or output between the second substrate 200 and the third substrate 300.

An electrical connection portion electrically connecting the second substrate 200 and the third substrate 300 may be provided at a desired position. For example, similar to the contact regions 201R, 202R, 301R, and 302R illustrated in fig. 73, the electrical connection portion may be provided in a region overlapping with the pixel array unit 540 in the stacking direction. Further, the electrical connection portion may be provided in a region that does not overlap with the pixel array unit 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region overlapping in the stacking direction with a peripheral portion arranged outside the pixel array unit 540.

The first substrate 100 and the second substrate 200 are provided with connection holes H1 and H2, for example. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 (fig. 73). The connection holes H1 and H2 are provided outside the pixel array unit 540 (or a portion overlapping the pixel array unit 540) (fig. 72). For example, the connection hole H1 is arranged outside the pixel array unit 540 in the H direction, and the connection hole H2 is arranged outside the pixel array unit 540 in the V direction. For example, the connection hole H1 reaches the input cell 510A provided in the third substrate 300, and the connection hole H2 reaches the output cell 510B provided in the third substrate 300. The connection holes H1 and H2 may be hollow or at least a portion thereof may contain a conductive material. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input unit 510A and/or the output unit 510B. Alternatively, there is a configuration in which the electrodes formed as the input cell 510A and/or the output cell 510B are connected to the conductive material disposed in the connection holes H1 and H2. The conductive material disposed in the connection holes H1 and H2 may be buried in a part or all of the connection holes H1 and H2, or the conductive material may be formed on the sidewalls of the connection holes H1 and H2.

Note that, in fig. 73, the third substrate 300 is provided with an input unit 510A and an output unit 510B, but the present disclosure is not limited thereto. For example, the input unit 510A and/or the output unit 510B may be provided in the second substrate 200 by transmitting a signal of the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T. Similarly, the input unit 510A and/or the output unit 510B may be provided in the first substrate 100 by transmitting signals of the second substrate 200 to the first substrate 100 via the wiring layers 100T and 200T.

Fig. 74 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (four pixels 541 of the pixels 541A, 541B, 541C, and 541D are shown in fig. 74), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, by operating one pixel circuit 210 in a time-division manner, the pixel sharing unit 539 sequentially outputs the respective pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543. A mode in which one pixel circuit 210 is connected to a plurality of pixels 541 and pixel signals of the plurality of pixels 541 are output in a time-division manner by one pixel circuit 210 is referred to as "one pixel circuit 210 is shared by a plurality of pixels 541".

The pixels 541A, 541B, 541C, and 541D have components common to each other. Hereinafter, in order to distinguish the constituent elements of the pixels 541A, 541B, 541C, and 541D from each other, the identification number 1 is added to the end of the reference numeral of the constituent element of the pixel 541A, the identification number 2 is added to the end of the reference numeral of the constituent element of the pixel 541B, the identification number 3 is added to the end of the reference numeral of the constituent element of the pixel 541C, and the identification number 4 is added to the end of the reference numeral of the constituent element of the pixel 541D. In the case where it is not necessary to distinguish the constituent elements of the pixels 541A, 541B, 541C, and 541D from one another, the identification number at the end of the reference numeral of the constituent elements of the pixels 541A, 541B, 541C, and 541D is omitted.

The pixels 541A, 541B, 541C, and 541D each have, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion portion FD electrically connected to the transfer transistor TR. In the photodiode PD (PD1, PD2, PD3, or PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on incident light and generates electric charges corresponding to the amount of received light. The transfer transistor TR (the transfer transistor TR1, TR2, TR3, or TR4) is, for example, an n-type Complementary Metal Oxide Semiconductor (CMOS) transistor. In the transfer transistor TR, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to the driving signal line. The driving signal line is a part of a plurality of row driving signal lines 542 (refer to fig. 71) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusion FD1, FD2, FD3, or FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion portion FD is charge holding means that temporarily holds the charge transferred from the photodiode PD, and is charge-voltage conversion means that generates a voltage corresponding to the amount of charge.

The four floating diffusions FD (the floating diffusions FD1, FD2, FD3, and FD4) included in one pixel sharing unit 539 are electrically connected to each other, and to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. A drain of the FD conversion gain switching transistor FDG is connected to a source of the reset transistor RST, and a gate of the FD conversion gain switching transistor FDG is connected to the driving signal line. The driving signal line is a part of a plurality of row driving signal lines 542 connected to one pixel sharing unit 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the driving signal line. The driving signal line is a part of a plurality of row driving signal lines 542 connected to one pixel sharing unit 539. A gate of the amplification transistor AMP is connected to the floating diffusion FD, a drain of the amplification transistor AMP is connected to the power supply line VDD, and a source of the amplification transistor AMP is connected to a drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the driving signal line. The driving signal line is a part of a plurality of row driving signal lines 542 connected to one pixel sharing unit 539.

When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The gate electrode (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and is provided to extend from the surface of the semiconductor layer (semiconductor layer 100S in fig. 76) to a depth reaching the PD, as shown in fig. 76 described later. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates, as a pixel signal, a signal having a voltage corresponding to the level of the electric charge held in the floating diffusion FD. The amplification transistor AMP is connected to the vertical signal line 543 via a selection transistor SEL. In the column signal processing unit 550, the amplifying transistor AMP constitutes a source follower together with a load circuit unit (refer to fig. 71) connected to the vertical signal line 543. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.

The FD conversion gain switching transistor FDG is used when changing the gain of charge-voltage conversion in the floating diffusion FD. In general, when an image is taken in a dark place, a pixel signal is small. In the case of performing charge-voltage conversion based on Q ═ CV, when the capacitance of the floating diffusion FD (FD capacitance C) is large, V at the time of conversion into voltage by the amplifying transistor AMP becomes small. On the other hand, in a bright place, since the pixel signal becomes large, the floating diffusion FD cannot receive the charge of the photodiode PD unless the FD capacitance C is large. Further, the FD capacitance C needs to be large so that V at the time of conversion into a voltage by the amplifying transistor AMP does not become too large (in other words, so that it becomes small). Thus, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases. Therefore, the entire FD capacitance C increases. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the entire FD capacitance C decreases. In this way, by switching on and off of the FD conversion gain switching transistor FDG, the FD capacitance C can be made variable and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

Note that a configuration in which the FD conversion gain switching transistor FDG is not provided is also possible. At this time, for example, the pixel circuit 210 includes three transistors, for example, an amplifying transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one of pixel transistors such as an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

The selection transistor SEL may be disposed between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. A source of the selection transistor SEL is electrically connected to a drain of the amplification transistor AMP, and a gate of the selection transistor SEL is electrically connected to the row driving signal line 542 (refer to fig. 71). The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Note that although not shown, the number of pixels 541 sharing one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

Fig. 75 shows an example of a connection pattern of a plurality of pixel sharing units 539 and a vertical signal line 543. For example, four pixel sharing units 539 arranged in the column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. For simplicity of explanation, fig. 75 shows an example in which each of four groups has one pixel sharing unit 539, but each of the four groups may include a plurality of pixel sharing units 539. As described above, in the imaging apparatus 1, the plurality of pixel-sharing units 539 aligned in the column direction may be divided into groups including one or more pixel-sharing units 539. For example, the vertical signal line 543 and the column signal processing unit 550 are connected to each of these groups, and pixel signals can be read out from the respective groups at the same time. Alternatively, in the imaging apparatus 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 juxtaposed in the column direction. At this time, pixel signals are sequentially read out from the plurality of pixel sharing units 539 connected to one vertical signal line 543 in a time-division manner.

[ specific constitution of image Forming apparatus 1 ]

Fig. 76 shows an example of the sectional configuration in the direction perpendicular to the main faces of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1. For easy understanding, fig. 76 schematically shows the positional relationship of the constituent elements, and may be different from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 further has a light receiving lens 401 on the back surface side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be disposed between the light receiving lens 401 and the first substrate 100. For example, a light-receiving lens 401 is provided in each of the pixels 541A, 541B, 541C, and 541D. The imaging device 1 is, for example, a back-illuminated type imaging device. The imaging device 1 includes a pixel array unit 540 disposed in a central portion and a peripheral portion 540B disposed outside the pixel array unit 540.

The first substrate 100 has an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T in this order from the light receiving lens 401 side. The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in a part of the surface (surface on the wiring layer 100T side) and its vicinity, and an n-type semiconductor region 114 in other regions (regions deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

Fig. 77A shows an example of a planar configuration of the first substrate 100. Fig. 77A mainly shows the planar configuration of the pixel separating section 117, the photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR. The constitution of the first substrate 100 will be described using fig. 77A together with fig. 76.

The floating diffusion FD and the VSS contact region 118 are disposed near the surface of the semiconductor layer 100S. The floating diffusion FD includes an n-type semiconductor region provided in the p-well layer 115. The respective floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D are disposed close to each other, for example, in the central portion of the pixel sharing unit 539 (fig. 77A). Details will be described later, and the four floating diffusions (the floating diffusions FD1, FD2, FD3, and FD4) included in the pixel sharing unit 539 are electrically connected to each other via an electrical connection means (a pad portion 120 described later) within the first substrate 100 (more specifically, within the wiring layer 100T). The floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical means (a through electrode 120E described later). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG by electrical means.

The VSS contact region 118 is a region electrically connected to the reference potential line VSS, and is arranged apart from the floating diffusion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion FD is arranged at one end of each pixel in the V direction, and the VSS contact region 118 is arranged at the other end of each pixel (fig. 77A). The VSS contact region 118 is composed of, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. Thus, the reference potential is supplied to the semiconductor layer 100S.

The transfer transistor TR is also provided in the first substrate 100 in addition to the photodiode PD, the floating diffusion FD, and the VSS contact region 118. A photodiode PD, a floating diffusion FD, a VSS contact region 118, and a transfer transistor TR are disposed in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is disposed on the front face side (the side opposite to the light incident face side, i.e., the second substrate 200 side) of the semiconductor layer 100S. The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front of the semiconductor layer 100S and a vertical portion TGa disposed within the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb and the other end is disposed within the n-type semiconductor region 114. Since the transfer transistor TR is configured by such a vertical transistor, a transfer failure of a pixel signal hardly occurs, and the readout efficiency of the pixel signal is improved.

The horizontal portion TGb of the transfer gate TG extends from a position facing the vertical portion TGa toward a central portion of the pixel sharing unit 539, for example, in the H direction (fig. 77A). Therefore, the position in the H direction of the through electrode (through electrode TGV described later) reaching the transfer gate TG can be made close to the position in the H direction of the through electrodes (through electrodes 120E and 121E described later) connected to the floating diffusion FD and the VSS contact region 118. For example, a plurality of pixel sharing units 539 provided on the first substrate 100 have the same configuration as one another (fig. 77A).

The semiconductor layer 100S is provided with a pixel separation portion 117 which separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separation portion 117 is formed to extend in a normal direction of the semiconductor layer 100S (a direction perpendicular to the surface of the semiconductor layer 100S). The pixel separation section 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from one another, and has a planar shape of, for example, a lattice (fig. 77A and 77B). The pixel separation section 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from one another, for example. The pixel separation portion 117 includes, for example, a light-shielding film 117A and an insulating film 117B. For the light-shielding film 117A, for example, tungsten (W) or the like is used. An insulating film 117B is provided between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is formed of, for example, silicon oxide (SiO). The pixel separating portion 117 has, for example, a Full Trench Isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separating portion 117 is not limited to the FTI structure penetrating the semiconductor layer 100S. For example, a Deep Trench Isolation (DTI) structure that does not penetrate the semiconductor layer 100S may be used. The pixel separation portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is disposed near the back surface of the semiconductor layer 100S, and is disposed between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is disposed at a side of the pixel separating part 117, specifically, between the pixel separating part 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are formed of, for example, p-type semiconductor regions.

A fixed charge film 112 having negative fixed charges is provided between the semiconductor layer 100S and the insulating film 111. A first pinning region 113 of the hole accumulation layer is formed on the interface on the light receiving surface (back surface) side of the semiconductor layer 100S by an electric field induced by the fixed charge film 112. Therefore, generation of dark current due to an interface state on the light receiving surface side of the semiconductor layer 100S is suppressed. The fixed charge film 112 is formed of, for example, an insulating film having negative fixed charges. Examples of the material of the insulating film having negative fixed charges include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

The light-shielding film 117A is disposed between the fixed charge film 112 and the insulating film 111. The light shielding film 117A may be provided continuously with the light shielding film 117A constituting the pixel separation portion 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separation section 117 within the semiconductor layer 100S. The insulating film 111 is provided to cover the light shielding film 117A. The insulating film 111 is formed of, for example, silicon oxide.

The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has, in order from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124. The horizontal portion TGb of the transfer gate TG is disposed in the wiring layer 100T, for example. The interlayer insulating film 119 is provided on the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is made of, for example, a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to the above, and may be a configuration having a wiring and an insulating film.

Fig. 77B shows the configuration of the pad portions 120 and 121 and the planar configuration shown in fig. 77A. The pad portions 120 and 121 are disposed in selected regions on the interlayer insulating film 119. The pad portion 120 is used to connect the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to each other. For example, the pad portion 120 is arranged in the center portion of the pixel sharing unit 539 in plan view for each pixel sharing unit 539 (fig. 77B). The pad portion 120 is provided astride the pixel separation portion 117, and is configured to overlap at least a part of each of the floating diffusion portions FD1, FD2, FD3, and FD4 (fig. 76 and 77B). Specifically, the pad section 120 is formed in a region overlapping at least a part of each of the plurality of floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the shared pixel circuit 210 and at least a part of the pixel separating section 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) of the shared pixel circuit 210 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 120C for electrically connecting the pad portion 120 with the floating diffusion portions FD1, FD2, FD3, and FD 4. A connection via 120C is provided for each of the pixels 541A, 541B, 541C, and 541D. For example, since a part of the pad portion 120 is buried in the connection via 120C, the pad portion 120 is electrically connected to the floating diffusion portions FD1, FD2, FD3, and FD 4.

The pad portion 121 serves to connect the plurality of VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in the pixels 541C and 541D of one pixel-sharing unit 539 adjacent in the V direction and the VSS contact regions 118 provided in the pixels 541A and 541B of the other pixel-sharing unit 539 are electrically connected through the pad portion 121. The pad portion 121 is disposed, for example, astride the pixel separating portion 117, and is configured to overlap at least a part of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region overlapping with at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of the pixel separating portion 117 formed between the plurality of VSS contact regions 118 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 121C for electrically connecting the pad portion 121 and the VSS contact region 118. A connection via 121C is provided for each of the pixels 541A, 541B, 541C, and 541D. For example, since a portion of the pad portion 121 is buried in the connection via 121C, the pad portion 121 is electrically connected to the VSS contact region 118. For example, the pad portion 120 and the pad portion 121 of each of the plurality of pixel sharing units 539 juxtaposed in the V direction are arranged at substantially the same position in the H direction (fig. 77B).

By providing the pad portion 120, wiring for connecting each floating diffusion FD to the pixel circuit 210 (for example, the gate electrode of the amplifying transistor AMP) in the entire chip can be reduced. Similarly, by providing the pad portion 121, wiring for supplying electric potential to each VSS contact region 118 in the entire chip can be reduced. Therefore, it is possible to reduce the area of the entire chip, suppress electrical interference between wirings in miniaturized pixels, and/or reduce the cost and the like by reducing the number of components.

The pad parts 120 and 121 may be disposed at desired positions on the first and second substrates 100 and 200. Specifically, the pad portions 120 and 121 may be disposed in the insulation region 212 of the wiring layer 100T or the semiconductor layer 200S. In the case of being provided in the wiring layer 100T, the pad portions 120 and 121 may be brought into direct contact with the semiconductor layer 100S. Specifically, the pad portions 120 and 121 may be directly connected to at least a portion of each of the respective floating diffusion FD and/or VSS contact regions 118. Further, the following configuration may be adopted: connection vias 120C and 121C may be provided from each of the floating diffusion FD and/or VSS contact regions 118 connected to the pad portions 120 and 121, and the pad portions 120 and 121 may be provided at desired positions in the insulation regions 212 of the wiring layer 100T and the semiconductor layer 200S.

In particular, in the case where the pad portions 120 and 121 are provided in the wiring layer 100T, wirings connected to the floating diffusion FD and/or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S can be reduced. Therefore, in the second substrate 200 for forming the pixel circuit 210, the area of the insulating region 212 for forming the through wiring for connecting the floating diffusion FD to the pixel circuit 210 can be reduced. Accordingly, a large area of the second substrate 200 for forming the pixel circuit 210 may be secured. By securing an area for the pixel circuit 210, a large pixel transistor can be formed, and image quality can be improved by reducing noise or the like.

In particular, in the case where the FTI structure is used for the pixel separating portion 117, it is preferable that the floating diffusion FD and/or the VSS contact region 118 be provided in each pixel 541. Therefore, by using the configuration of the pad parts 120 and 121, the number of wirings connecting the first substrate 100 and the second substrate 200 can be greatly reduced.

Further, as shown in fig. 77B, for example, pad portions 120 to which a plurality of floating diffusion portions FD are connected and pad portions 121 to which a plurality of VSS contact regions 118 are connected are alternately arranged linearly in the V direction. Further, the pad portions 120 and 121 are formed at positions surrounded by the plurality of photodiodes PD, the plurality of transfer gates TG, and the plurality of floating diffusion portions FD. Therefore, in the first substrate 100 for forming a plurality of elements, elements other than the floating diffusion FD and the VSS contact region 118 can be freely arranged, and the layout efficiency of the entire chip can be improved. Further, symmetry of the layout of the elements formed in each pixel sharing unit 539 is secured, and variations in the characteristics of each pixel 541 can be suppressed.

The pad parts 120 and 121 are formed of, for example, polycrystalline silicon (Poly Si), more specifically, doped polycrystalline silicon to which impurities are added. It is preferable that the pad portions 120 and 121 be formed of a conductive material having high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). Accordingly, the pixel circuit 210 may be formed after the semiconductor layer 200S of the second substrate 200 is attached to the first substrate 100. The reason for this will be explained below. Note that in the following description, a method of forming the pixel circuit 210 after bonding the semiconductor layers 200S of the first substrate 100 and the second substrate 200 together is referred to as a first manufacturing method.

Here, it is also conceivable to form the pixel circuit 210 on the second substrate 200 and then bond the pixel circuit 210 to the first substrate 100 (hereinafter referred to as a second manufacturing method). In the second manufacturing method, electrodes for electrical connection are formed in advance on the surface of the first substrate 100 (the surface of the wiring layer 100T) and the surface of the second substrate 200 (the surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are attached together, at the same time, electrodes for electrical connection formed on each of the surface of the first substrate 100 and the surface of the second substrate 200 are in contact with each other. Accordingly, electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by adopting the constitution of the imaging device 1 using the second manufacturing method, it is possible to manufacture by using an appropriate process according to the respective constitutions of the first substrate 100 and the second substrate 200, and it is possible to manufacture a high-quality, high-performance imaging device.

In the second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded together, an alignment error may occur due to the cause of the manufacturing equipment used for bonding. Further, the first and second substrates 100 and 200 have a size of, for example, about several tens of centimeters in diameter, and when the first and second substrates 100 and 200 are attached together, in a microscopic region of each part of the first and second substrates 100 and 200, expansion and contraction of the substrates may occur. The expansion and contraction of the substrates is caused by a slight shift in the contact timing between the substrates. Due to such expansion and contraction of the first substrate 100 and the second substrate 200, an error may occur in the position of the electrode for electrical connection formed on each of the surface of the first substrate 100 and the surface of the second substrate. In the second manufacturing method, it is preferable to take measures such that the respective electrodes of the first substrate 100 and the second substrate 200 contact each other even if such an error occurs. Specifically, in consideration of the above-described error, at least one of the electrodes of the first and second substrates 100 and 200 is added, or preferably, both are added. Therefore, when the second manufacturing method is used, for example, the size of the electrode formed on the surface of the first substrate 100 or the second substrate 200 (the size in the planar direction of the substrate) becomes larger than the size of the internal electrode extending from the inside of the first substrate 100 or the second substrate 200 to the surface in the thickness direction.

On the other hand, since the pad portions 120 and 121 are formed of a heat-resistant conductive material, the above-described first manufacturing method can be used. In the first manufacturing method, after the first substrate 100 including the photodiode PD and the transfer transistor TR and the like is formed, the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are attached together. At this time, the second substrate 200 is in a state where the active elements, the wiring layer, and the like constituting the pixel circuit 210 are not patterned. Since the second substrate 200 is in a state before the pattern is formed, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded, the bonding error does not cause an alignment error between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are attached together. Note that when a pattern is formed on the second substrate, for example, in an exposure apparatus for pattern formation, the pattern is formed while taking the pattern formed on the first substrate as an alignment target. For the above reason, in manufacturing the imaging device 1 by the first manufacturing method, an error in the bonding position between the first substrate 100 and the second substrate 200 does not constitute a problem. For the same reason, the error caused by the expansion and contraction of the substrate by the second manufacturing method does not pose a problem in manufacturing the imaging device 1 by the first manufacturing method.

In the first manufacturing method, after the first substrate 100 and the second substrate 200 (the semiconductor layer 200S) are bonded together in this way, active elements are formed on the second substrate 200. Thereafter, through electrodes 120E and 121E and a through electrode TGV are formed (fig. 76). In forming the through electrodes 120E, 121E and TGV, for example, a pattern of the through electrodes is formed from above the second substrate 200 by reduced projection exposure using an exposure apparatus. Since the reduced exposure projection is used, even if an error occurs in the alignment between the second substrate 200 and the exposure apparatus, the magnitude of the error is only the error fraction (inverse of the reduced exposure projection magnification) of the error of the above-described second manufacturing method in the second substrate 200. Therefore, by forming the imaging device 1 using the first manufacturing method, it is easy to align the respective elements formed on the first substrate 100 and the second substrate 200, and a high-quality and high-performance imaging device can be manufactured.

The imaging device 1 manufactured by using the first manufacturing method has different characteristics from the imaging device manufactured by the second manufacturing method. Specifically, in the imaging device 1 manufactured by the first manufacturing method, for example, the through electrodes 120E, 121E, and TGV have a substantially constant thickness (dimension in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E and TGV have a tapered shape, they have a tapered shape of a constant inclination angle. In the imaging device 1 having such through electrodes 120E, 121E, and TGV, the pixels 541 can be easily miniaturized.

Here, when the imaging device 1 is manufactured by the first manufacturing method, since the active elements are formed on the second substrate 200 after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together, the first substrate 100 is also affected by the heat treatment required for forming the active elements. Therefore, as described above, it is preferable that a conductive material having high heat resistance be used for the pad portions 120 and 121 provided on the first substrate 100. For example, the pad portions 120 and 121 are preferably formed of a material having a higher melting point (i.e., higher heat resistance) than at least a part of the wiring material contained in the wiring layer 200T of the second substrate 200. For example, a conductive material having high heat resistance, such as doped polysilicon, tungsten, titanium, or titanium nitride, is used for the pad portions 120 and 121. Therefore, the imaging device 1 can be manufactured by using the above-described first manufacturing method.

For example, the passivation film 122 is provided on the entire surface of the semiconductor layer 100S to cover the pad portions 120 and 121 (fig. 76). The passivation film 122 is formed of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 with the passivation film 122 interposed therebetween. The interlayer insulating film 123 is provided on the entire surface of the semiconductor layer 100S, for example. The interlayer insulating film 123 is formed of, for example, an oxide of Silicon (SiO). The bonding film 124 is provided on the bonding face of the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is provided on the entire main surface of the first substrate 100. The bonding film 124 is formed of, for example, a silicon nitride film.

The light receiving lens 401 faces the semiconductor layer 100S, for example, via the fixed charge film 112 and the insulating film 111 (fig. 76). The light receiving lens 401 is disposed, for example, at a position facing the respective photodiodes PD of the pixels 541A, 541B, 541C, and 541D.

The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T in order from the first substrate 100 side. The semiconductor layer 200S is formed of a silicon substrate. In the semiconductor layer 200S, a well region 211 is provided in the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 is provided with a pixel circuit 210 configured for each pixel sharing unit 539. The pixel circuit 210 is provided on the front side (wiring layer 200T side) of the semiconductor layer 200S, for example. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 in such a manner that the back surface side (semiconductor layer 200S side) of the second substrate 200 faces the front surface side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 in a front-to-back manner.

Fig. 78 to 82 schematically show examples of the planar configuration of the second substrate 200. Fig. 78 shows the configuration of the pixel circuit 210 provided in the vicinity of the surface of the semiconductor layer 200S. Fig. 79 schematically shows the configuration of the wiring layer 200T (specifically, a first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and parts of the first substrate 100. Fig. 80 to 82 show examples of planar configurations of the wiring layer 200T. Hereinafter, the constitution of the second substrate 200 will be described with reference to FIGS. 78 to 82 together with FIG. 76. In fig. 78 and 79, the outline of the photodiode PD (the boundary between the pixel separation section 117 and the photodiode PD) is indicated by a broken line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 212 at a portion overlapping with the gate electrode of each transistor constituting the pixel circuit 210 is indicated by a dotted line. In a portion overlapping with the gate electrode of the amplification transistor AMP, a boundary between the semiconductor layer 200S and the element isolation region 213 and a boundary between the element isolation region 213 and the insulating region 212 are provided on one side in the channel width direction.

The second substrate 200 is provided with an insulating region 212 for dividing the semiconductor layer 200S and an element isolation region 213 provided in a part of the thickness direction of the semiconductor layer 200S (fig. 76). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other in the H direction, the through electrodes 120E and 121E and the through electrode TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to the two pixel sharing units 539 of the two pixel circuits 210 are arranged (fig. 79).

The insulating region 212 has a thickness substantially the same as that of the semiconductor layer 200S (fig. 76). The semiconductor layer 200S is divided by the insulating region 212. The through electrodes 120E and 121E and the through electrode TGV are arranged in the insulating region 212. The insulating region 212 is formed of, for example, silicon oxide.

The through electrodes 120E and 121E are provided so as to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wires of the wiring layer 200T (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4, which will be described later). The through electrodes 120E and 121E are provided in such a manner as to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends thereof are connected to the pad portions 120, 121 (fig. 76). The through electrode 120E is used to electrically connect the pad part 120 and the pixel circuit 210. That is, the through electrode 120E electrically connects the floating diffusion FD of the first substrate 100 to the pixel circuit 210 of the second substrate 200. The through electrode 121E is used for electrically connecting the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the through electrode 121E electrically connects the VSS contact region 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

The through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring layer 200T. The through electrode TGV is provided in such a manner as to pass through the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transfer gate TG (fig. 76). The through electrode TGV is used to electrically connect the transfer gate TG (transfer gate TG1, TG2, TG3, or TG4) of each of the pixels 541A, 541B, 541C, and 541D to the wiring (a part of the row driving signal line 542, specifically, the wirings TRG1, TRG2, TRG3, and TRG4 of fig. 81 described later) of the wiring layer 200T. That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the through electrode TGV, and a driving signal is transmitted to each transfer transistor TR (transfer transistors TR1, TR2, TR3, and TR 4).

The insulating region 212 is a region for insulating the through electrodes 120E and 121E and the through electrode TGV for electrically connecting the first substrate 100 and the second substrate 200 from the semiconductor layer 200S. For example, in the insulating region 212 provided between two pixel circuits 210 (pixel sharing units 539) adjacent to each other in the H direction, the through electrodes 120E, 121E and the through electrode TGV (through electrodes TGV1, TGV2, TGV3 and TGV4) connected to the two pixel circuits 210 are arranged. The insulating region 212 is provided to extend in, for example, the V direction (fig. 78 and 79). Here, by devising the configuration of the horizontal portion TGb of the transfer gate TG, the position of the through electrode TGV in the H direction is arranged closer to the positions of the through electrodes 120E and 121E in the H direction than the positions of the vertical portions TGa (fig. 77A and 79). For example, the through electrode TGV is arranged at substantially the same position as the through electrodes 120E and 120E in the H direction. Therefore, the through electrodes 120E and 121E and the through electrode TGV may be provided together in the insulating region 212 extending in the V direction. As another configuration example, it is conceivable to provide the horizontal portion TGb only in the region overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed substantially directly above the vertical portion TGa, and is disposed, for example, substantially in the center portion in the H direction and the V direction of each pixel 541. At this time, the position of the through electrode TGV in the H direction is greatly deviated from the positions of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is provided around the through electrode TGV and the through electrodes 120E and 121E to electrically insulate them from the adjacent semiconductor layer 200S. In the case where the position of the through electrode TGV in the H direction is greatly separated from the positions of the through electrodes 120E and 121E in the H direction, the insulating region 212 needs to be provided independently around each of the through electrodes 120E, 121E and TGV. Therefore, the semiconductor layer 200S is finely divided. In contrast to this, in the layout in which the through electrodes 120E and 121E and the through electrode TGV are arranged together in the insulating region 212 extending along the V direction, the size of the semiconductor layer 200S in the H direction can be increased. Therefore, a large area of the semiconductor element formation region in the semiconductor layer 200S can be secured. Therefore, for example, it is possible to increase the size of the amplifying transistor AMP and suppress noise.

As explained with reference to fig. 74, the pixel sharing unit 539 has a structure in which respective floating diffusion portions FD provided in a plurality of pixels 541 are electrically connected, and the plurality of pixels 541 share one pixel circuit 210. The electrical connection between the floating diffusion portions FD is made by the pad portions 120 provided on the first substrate 100 (fig. 76 and 77B). The electrical connection portion (pad portion 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected via one through electrode 120E. As another configuration example, it is conceivable to provide an electrical connection portion between the floating diffusion portions FD on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes connected to the floating diffusions FD1, FD2, FD3, and FD 4. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 insulating the periphery of these through electrodes becomes large. In contrast to this, in the structure in which the pad portion 120 is provided on the first substrate 100 (fig. 76 and 77B), the number of through electrodes can be reduced and the insulating region 212 can be reduced. Therefore, a large area of the semiconductor element formation region in the semiconductor layer 200S can be secured. Therefore, for example, it is possible to increase the size of the amplifying transistor AMP and suppress noise.

The element isolation region 213 is provided on the surface side of the semiconductor layer 200S. The element isolation region 213 has an STI (shallow trench isolation) structure. In the element isolation region 213, the semiconductor layer 200S is dug in the thickness direction (the direction perpendicular to the main surface of the second substrate 200), and the insulating film is buried in the dug portion. The insulating film is formed of, for example, silicon oxide. The element isolation region 213 isolates a plurality of transistors constituting the pixel circuit 210 from each other according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (deep portion of the semiconductor layer 200S).

Here, with reference to fig. 77A, 77B, and 78, a difference between the outline shape of the pixel-sharing unit 539 in the first substrate 100 (outline shape in the planar direction of the substrate) and the outline shape of the pixel-sharing unit 539 in the second substrate 200 will be explained.

In the imaging device 1, the pixel sharing unit 539 is disposed on both the first substrate 100 and the second substrate 200. For example, the external shape of the pixel sharing unit 539 disposed on the first substrate 100 and the external shape of the pixel sharing unit 539 disposed on the second substrate 200 are different from each other.

In fig. 77A and 77B, outlines of the pixels 541A, 541B, 541C, and 541D are indicated by alternate long and short dash lines, and an outline shape of the pixel-sharing unit 539 is indicated by a thick line. For example, the pixel sharing unit 539 of the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent thereto in the V direction. That is, the pixel-sharing unit 539 of the first substrate 100 includes four pixels 541 of two adjacent rows × two columns, and the pixel-sharing unit 539 of the first substrate 100 has a substantially square outer shape. In the pixel array unit 540, such pixel sharing units 539 are arranged adjacent to each other at two pixel pitches (pitches correspond to two pixels 541) in the H direction and two pixel pitches (pitches correspond to two pixels 541) in the V direction.

In fig. 78 and 79, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by alternate long and short dash lines, and the outline shape of the pixel-sharing unit 539 is indicated by a thick line. For example, the outline shape of the pixel-sharing unit 539 of the second substrate 200 is smaller than the pixel-sharing unit 539 of the first substrate 100 in the H direction and larger than the pixel-sharing unit 539 of the first substrate 100 in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed in a size (area) corresponding to one pixel in the H direction and a size corresponding to four pixels in the V direction. That is, the pixel-sharing units 539 of the second substrate 200 are formed in a size corresponding to pixels arranged in adjacent one row × four columns, and the pixel-sharing units 539 of the second substrate 200 have a substantially rectangular outline shape.

For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged side by side in the V direction in order (fig. 78). As described above, by setting the outline shape of each pixel circuit 210 to a substantially rectangular shape, four transistors (the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG) can be arranged side by side in one direction (the V direction in fig. 78). Therefore, the drain of the amplification transistor AMP and the drain of the reset transistor RST can be shared by one diffusion region (diffusion region connected to the power supply line VDD). For example, the formation region of each pixel circuit 210 may be formed in a substantially square shape (see fig. 91 described later). In this case, two transistors are arranged along one direction, and it is difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by setting the formation region of the pixel circuit 210 to a substantially rectangular shape, it is easy to arrange four transistors close to each other, and the formation region of the pixel circuit 210 can be reduced. That is, the pixels can be miniaturized. Further, when it is not necessary to reduce the formation area of the pixel circuit 210, it is possible to increase the formation area of the amplification transistor AMP and suppress noise.

For example, in the vicinity of the surface of the semiconductor layer 200S, a VSS contact region 218 connected to the reference potential line VSS is provided in addition to the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The VSS contact region 218 is formed, for example, by a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through electrode 121E. The VSS contact region 218 is provided at a position adjacent to the source of the FD conversion gain switching transistor FDG via, for example, the element isolation region 213 (fig. 78).

Next, a positional relationship between the pixel-sharing units 539 provided in the first substrate 100 and the pixel-sharing units 539 provided in the second substrate 200 will be described with reference to fig. 77B and 78. For example, one pixel sharing unit 539 (e.g., the upper side of the paper in fig. 77B) of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 is connected to one pixel sharing unit 539 (e.g., the left side of the paper in fig. 78) of the two pixel sharing units 539 arranged in the H direction of the second substrate 200. For example, another pixel-sharing unit 539 (e.g., the lower side of the paper in fig. 77B) of the two pixel-sharing units 539 arranged in the V direction of the first substrate 100 is connected to another pixel-sharing unit 539 (e.g., the right side of the paper in fig. 78) of the two pixel-sharing units 539 arranged in the H direction of the second substrate 200.

For example, in two pixel-sharing cells 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel-sharing cell 539 is substantially equal to a layout in which the internal layout of the other pixel-sharing cell 539 is inverted in the V direction and the H direction. The effects obtained by this layout will be described below.

In the two pixel-sharing units 539 arranged in the V direction of the first substrate 100, each pad portion 120 is disposed at the center portion of the outline shape of the pixel-sharing unit 539, that is, at the center portions of the pixel-sharing unit 539 in the V direction and the H direction (fig. 77B). On the other hand, as described above, since the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outer shape that is long in the V direction, for example, the amplification transistor AMP connected to the pad portion 120 is disposed at a position shifted in the paper surface upward from the center of the pixel sharing unit 539 in the V direction. For example, when the internal layout of two pixel-sharing units 539 arranged in the H direction of the second substrate 200 is the same, the distance between the amplification transistor AMP of one pixel-sharing unit 539 and the pad portion 120 (e.g., the pad portion 120 of the pixel-sharing unit 539 on the upper side of the paper in fig. 7) is relatively short. However, the distance between the amplification transistor AMP of the other pixel-sharing unit 539 and the pad portion 120 (e.g., the pad portion 120 of the pixel-sharing unit 539 on the lower side of the paper in fig. 7) is long. For this reason, the area of the wiring required to connect the amplification transistor AMP and the pad portion 120 increases, and the wiring layout of the pixel sharing unit 539 may be complicated. This may affect miniaturization of the imaging apparatus 1.

In contrast, in the two pixel-sharing units 539 arranged in the H direction of the second substrate 200, by inverting the internal layouts of each other at least in the V direction, the distance between the amplification transistor AMP and the pad portion 120 of both of the two pixel-sharing units 539 can be shortened. Therefore, the imaging device 1 can be easily miniaturized compared to a configuration in which the internal layout of two pixel sharing units 539 arranged in the H direction of the second substrate 200 is the same. Note that, although the planar layout of each of the plurality of pixel-sharing units 539 of the second substrate 200 is bilaterally symmetric within the range shown in fig. 78, the planar layout is bilaterally asymmetric when a layout of the first wiring layer W1 shown in fig. 79 described later is included.

Further, it is preferable that the internal layouts of the two pixel-sharing units 539 arranged in the H direction of the second substrate 200 are inverted from each other in the H direction. The reason for this will be explained below. As shown in fig. 79, two pixel sharing units 539 arranged in the H direction of the second substrate 200 are connected to the pad portions 120 and 121 of the first substrate 100, respectively. For example, the pad portions 120 and 121 are arranged in the center portion in the H direction of two pixel-sharing units 539 arranged in the H direction of the second substrate 200 (between the two pixel-sharing units 539 arranged in the H direction). Accordingly, by inverting the internal layouts of the two pixel-sharing cells 539 arranged in the H direction of the second substrate 200 to each other also in the H direction, the distance between each of the plurality of pixel-sharing cells 539 of the second substrate 200 and the pad portions 120 and 121 can be reduced. That is, the image forming apparatus 1 can be more easily miniaturized.

In addition, the positions of the outlines of the pixel-sharing units 539 of the second substrate 200 may not be aligned with the positions of any outlines of the pixel-sharing units 539 of the first substrate 100. For example, in one pixel sharing unit 539 (for example, the left side of the paper surface in fig. 79) of two pixel sharing units 539 arranged in the H direction of the second substrate 200, the outline of one side in the V direction (for example, the upper side of the paper surface in fig. 79) is arranged outside the outline of one side in the V direction of the corresponding pixel sharing unit 539 (for example, the upper side of the paper surface in fig. 77B) of the first substrate 100. Further, in another pixel-sharing unit 539 (for example, the right side of the paper in fig. 79) of the two pixel-sharing units 539 arranged in the H direction of the second substrate 200, the outline of the other side in the V direction (for example, the lower side of the paper in fig. 79) is arranged outside the outline of the other side in the V direction of the corresponding pixel-sharing unit 539 (for example, the lower side of the paper in fig. 77B) of the first substrate 100. As described above, by arranging the pixel sharing units 539 of the second substrate 200 and the pixel sharing units 539 of the first substrate 100 side by side with each other, the distance between the amplifying transistor AMP and the pad portion 120 can be shortened. Therefore, the imaging apparatus 1 can be easily miniaturized.

In addition, the positions of the outlines of the plurality of pixel-sharing units 539 of the second substrate 200 may not be aligned with each other. For example, two pixel sharing units 539 arranged in the H direction of the second substrate 200 are arranged such that the positions of the outlines of the V direction thereof are shifted. Therefore, the distance between the amplifying transistor AMP and the pad portion 120 can be shortened. Therefore, the imaging apparatus 1 can be easily miniaturized.

A repetitive configuration of the pixel sharing unit 539 in the pixel array unit 540 is explained with reference to fig. 77B and 79. The pixel sharing unit 539 of the first substrate 100 has the size of two pixels 541 in the H direction and the size of two pixels 541 in the V direction (fig. 77B). For example, in the pixel array unit 540 of the first substrate 100, the pixel-sharing units 539 having a size corresponding to four pixels 541 are adjacently and repeatedly arranged at two pixel pitches in the H direction (a pitch corresponding to two pixels 541) and two pixel pitches in the V direction (a pitch corresponding to two pixels 541). Alternatively, the pixel array unit 540 of the first substrate 100 may be provided with a pair of pixel-sharing units 539, wherein each two pixel-sharing units 539 are disposed adjacent to each other in the V direction. In the pixel array unit 540 of the first substrate 100, for example, the pair of pixel-sharing units 539 are adjacently and repeatedly arranged at two pixel pitches (pitches correspond to two pixels 541) in the H direction and four pixel pitches (pitches correspond to four pixels 541) in the V direction. The pixel sharing unit 539 of the second substrate 200 has the size of one pixel 541 in the H direction and the size of four pixels 541 in the V direction (fig. 79). For example, the pixel array unit 540 of the second substrate 200 is provided with a pair of pixel-sharing units 539 including two pixel-sharing units 539 having a size corresponding to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and are arranged shifted in the V direction. In the pixel array unit 540 of the second substrate 200, for example, such a pair of pixel-sharing units 539 is repeatedly arranged adjacently without a gap at two pixel pitches in the H direction (the pitch corresponds to two pixels 541) and at four pixel pitches in the V direction (the pitch corresponds to four pixels 541). Therefore, by such repeated arrangement of the pixel sharing units 539, the pixel sharing units 539 can be arranged without gaps. Therefore, the imaging apparatus 1 can be easily miniaturized.

The amplifying transistor AMP preferably has a three-dimensional structure of, for example, a Fin type (fig. 76). Therefore, the size of the effective gate width becomes large, and noise can be suppressed. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG have, for example, a planar structure. The amplifying transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG may have a three-dimensional structure.

The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221 is, for example, in contact with the surface of the semiconductor layer 200S, and covers the entire surface of the semiconductor layer 200S. The passivation film 221 covers the respective gate electrodes of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is disposed between the passivation film 221 and the third substrate 300. The plurality of wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4) are separated by the interlayer insulating film 222. The interlayer insulating film 222 is formed of, for example, silicon oxide.

The wiring layer 200T is provided with, for example, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contacts 201 and 202 in this order from the semiconductor layer 200S side. The interlayer insulating film 222 is provided with a plurality of connection portions for connecting the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the lower layer thereof. The connection portion is a portion in which a conductive material is buried in a connection hole provided in the interlayer insulating film 222. For example, the interlayer insulating film 222 is provided with a connection portion 218V that connects the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the hole diameter of the connection portion connecting the elements of the second substrate 200 to each other is different from the hole diameters of the through electrodes 120E and 121E and the through electrode TGV. Specifically, it is preferable that the aperture of the connection hole connecting the elements of the second substrate 200 to each other is smaller than the apertures of the through electrodes 120E and 121E and the through electrode TGV. The reason for this will be explained below. The depth of the connection portion (connection portion 218V and the like) provided in the wiring layer 200T is smaller than the depth of the through electrodes 120E and 121E and the through electrode TGV. Therefore, the connection portion allows the connection hole to be easily filled with the conductive material, compared to the through electrodes 120E and 121E and the through electrode TGV. By making the aperture of the connection portion smaller than the apertures of the through electrodes 120E and 121E and the through electrode TGV, the imaging apparatus 1 can be easily miniaturized.

For example, the first wiring layer W1 connects the through electrode 120E, the gate of the amplification transistor AMP, and the source of the FD conversion gain switching transistor FDG (specifically, the connection hole reaches the source of the FD conversion gain switching transistor FDG). The first wiring layer W1 connects, for example, the through electrode 121E and the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S.

Next, the planar configuration of the wiring layer 200T will be explained with reference to FIGS. 80 to 82. Fig. 80 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2. Fig. 81 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3. Fig. 82 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4.

For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL (fig. 81) extending in the H direction (row direction). These wirings correspond to the plurality of row driving signal lines 542 described with reference to fig. 74. The wirings TRG1, TRG2, TRG3, and TRG4 are used to transmit drive signals to the transfer gates TG1, TG2, TG3, and TG4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to transfer gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through electrode 120E, respectively. The wiring SELL is used to transmit a driving signal to the gate of the selection transistor SEL, the wiring RSTL is used to transmit a driving signal to the gate of the reset transistor RST, and the wiring FDGL is used to transmit a driving signal to the gate of the FD conversion gain switching transistor FDG. The wirings SELL, RSTL, and FDGL are connected to the gates of the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG via the second wiring layer W2, the first wiring layer W1, and the connection portions, respectively.

For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 (fig. 82) extending in the V direction (column direction). The power supply line VDD is connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion. The reference potential line VSS is connected to the VSS contact region 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion 218V. Further, the reference potential line VSS is connected to the VSS contact region 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection portion.

The contacts 201 and 202 may be provided at positions overlapping the pixel array unit 540 in plan view (e.g., fig. 73), or may be provided on a peripheral portion 540B outside the pixel array unit 540 (e.g., fig. 76). The contact portions 201 and 202 are provided on the surface of the second substrate 200 (the surface on the wiring layer 200T side). The contacts 201 and 202 are formed of, for example, a metal such as Cu (copper) and Al (aluminum). The contact portions 201 and 202 are exposed on the surface of the wiring layer 200T (the surface on the third substrate 300 side). The contacts 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for attaching the second substrate 200 and the third substrate 300 to each other.

Fig. 76 shows an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200. The peripheral circuit may include a portion of the row driving unit 520 or a portion of the column signal processing unit 550, and the like. Further, as shown in fig. 73, the peripheral circuit may not be arranged in the peripheral portion 540B of the second substrate 200, and the connection holes H1 and H2 may be arranged in the vicinity of the pixel array unit 540.

The third substrate 300 has, for example, a wiring layer 300T and a semiconductor layer 300S in order from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is disposed on the second substrate 200 side. The semiconductor layer 300S is formed of a silicon substrate. A circuit is provided on a part of the front surface side of the semiconductor layer 300S. Specifically, on a part of the front side of the semiconductor layer 300S, for example, at least a part of the input unit 510A, the row driving unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, or the output unit 510B is provided. The wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact portions 301 and 302. The contact portions 301 and 302 are exposed on the surface of the wiring layer 300T (the surface on the second substrate 200 side), the contact portion 301 is in contact with the contact portion 201 of the second substrate 200, and the contact portion 302 is in contact with the contact portion 202 of the second substrate 200. The contacts 301 and 302 are electrically connected to a circuit (e.g., at least one of the input unit 510A, the row driving unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B) formed in the semiconductor layer 300S. The contacts 301 and 302 are formed of, for example, a metal such as Cu (copper) and Al (aluminum). For example, the external terminal TA is connected to the input cell 510A via the connection hole H1, and the external terminal TB is connected to the output cell 510B via the connection hole H2.

Here, the features of the imaging device 1 will be explained.

In general, an imaging device includes a photodiode and a pixel circuit as main components. Here, if the area of the photodiode is increased, the electric charges generated as a result of the photoelectric conversion increase, and therefore, the signal-to-noise ratio (S/N ratio) of the pixel signal improves, and the imaging apparatus can output better image data (image information). On the other hand, if the size of the transistor included in the pixel circuit (particularly, the size of the amplifying transistor) is increased, noise generated in the pixel circuit is reduced, and therefore, the S/N ratio of the imaging signal is improved, and the imaging apparatus can output better image data (image information).

However, in an imaging device in which a photodiode and a pixel circuit are provided on the same semiconductor substrate, if the area of the photodiode is increased within a limited area of the semiconductor substrate, it is conceivable that the size of a transistor provided in the pixel circuit may become small. Further, if the size of the transistor provided in the pixel circuit is increased, it is conceivable that the area of the photodiode may be made small.

To solve these problems, for example, the imaging device 1 of the present embodiment uses a structure in which one pixel circuit 210 is shared by a plurality of pixels 541 and the shared pixel circuit 210 is configured by overlapping with the photodiode PD. Therefore, it is possible to realize that the area of the photodiode PD is as large as possible, and the size of the transistor provided in the pixel circuit 210 is as large as possible within a limited area of the semiconductor substrate. Therefore, the S/N ratio of the pixel signal can be improved, and the imaging device 1 can output better image data (image information).

When a structure is realized in which a plurality of pixels 541 share one pixel circuit 210 and the pixel circuit 210 is configured by overlapping with the photodiode PD, a plurality of wirings connected to the one pixel circuit 210 extend from respective floating diffusion portions FD of the plurality of pixels 541. In order to secure a large area of the semiconductor substrate 200 for forming the pixel circuit 210, for example, a connection wiring that interconnects and integrates a plurality of extension wirings into one may be formed. Similarly, for a plurality of wirings extending from the VSS contact regions 118, a connection wiring that interconnects and integrates a plurality of extension wirings into one may be formed.

For example, if connection wirings interconnecting a plurality of wirings extending from respective floating diffusion portions FD of a plurality of pixels 541 are formed on the semiconductor substrate 200 on which the pixel circuit 210 is formed, it is conceivable that the area where the transistors included in the pixel circuit 210 are formed becomes small. Similarly, if a connection wiring that interconnects and integrates a plurality of wirings extending from respective VSS contact regions 118 of a plurality of pixels 541 into one is formed on the semiconductor substrate 200 where the pixel circuit 210 is formed, it is conceivable that the area where the transistors included in the pixel circuit 210 are formed becomes small.

To solve these problems, for example, in the imaging apparatus 1 of the present embodiment, a configuration may be provided in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is configured by overlapping with the photodiode PD, wherein a connection wiring that interconnects and integrates the respective floating diffusion portions FD of the plurality of pixels 541 into one and a connection wiring that interconnects and integrates the respective VSS contact regions 118 provided in the plurality of pixels 541 into one are provided on the first substrate 100.

Here, if the above-described second manufacturing method is used as a manufacturing method for providing, in the first substrate 100, the connection wiring that interconnects and integrates the respective floating diffusions FD of the plurality of pixels 541 into one and the connection wiring that interconnects and integrates the respective VSS contact regions 118 of the plurality of pixels 541 into one, for example, manufacturing may be performed using an appropriate process in accordance with the configuration of each of the first substrate 100 and the second substrate 200, and a high-quality, high-performance imaging device may be manufactured. In addition, the connection wiring of the first substrate 100 and the second substrate 200 may be formed by a simple process. Specifically, in the case of using the second manufacturing method described above, the electrode connected to the floating diffusion FD and the electrode connected to the VSS contact region 118 are provided on the surface of the first substrate 100 and the surface of the second substrate 200, which are the bonding boundary surfaces between the first substrate 100 and the second substrate 200, respectively. Further, it is preferable that the electrodes formed on the surfaces of the first and second substrates 100 and 200 are enlarged such that the electrodes formed on the surfaces of the two substrates contact each other even if the electrodes provided on the surfaces of the two substrates are displaced when the two substrates are attached together. In this case, it is conceivable that it may be difficult to arrange the above-described electrodes in a limited area of each pixel provided in the imaging device 1.

In order to solve the problem that a large electrode is required on the bonding boundary surface between the first substrate 100 and the second substrate 200, for example, as a manufacturing method of the imaging device 1 of the present embodiment in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is configured by overlapping with the photodiode PD, the above-described first manufacturing method may be used. Accordingly, the respective elements formed on the first and second substrates 100 and 200 may be easily aligned with each other, and an image forming apparatus having high quality and high performance may be manufactured. Further, an intrinsic structure produced by using the manufacturing method may be provided. That is, a structure is provided in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are sequentially laminated, in other words, the first substrate 100 and the second substrate 200 are laminated face to back, and the through electrodes 120E and 121E penetrating the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front face side of the semiconductor layer 200S of the second substrate 200 to reach the front face of the semiconductor layer 100S of the first substrate 100 are provided.

In the structure in which the connection wiring that interconnects and integrates the respective floating diffusions FD of the plurality of pixels 541 into one and the connection wiring that interconnects and integrates the respective VSS contact regions 118 of the plurality of pixels 541 into one are provided on the first substrate 100, if such a structure and the second substrate 200 are stacked and the pixel circuit 210 is formed on the second substrate 200 using the first manufacturing method, there is a possibility that the heat treatment required to form the active element provided on the pixel circuit 210 affects the above-described connection wiring formed on the first substrate 100.

Therefore, in order to solve the above-described problem that the heat treatment when forming the active elements affects the connection wirings, in the imaging device 1 of the present embodiment, it is desirable to use a conductive material having high heat resistance for the connection wirings that interconnect and integrate the respective floating diffusions FD of the plurality of pixels 541 into one and the connection wirings that interconnect and integrate the respective VSS contact regions 118 of the plurality of pixels 541 into one. Specifically, as the conductive material having high heat resistance, a material having a higher melting point than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200 may be used.

As described above, for example, the imaging device 1 of the present embodiment has (1) a structure in which the first substrate 100 and the second substrate 200 are laminated face to back (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are sequentially laminated), (2) a structure in which the through electrodes 120E and 121E penetrating the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front face side of the semiconductor layer 200S of the second substrate 200 and reaching the front face of the semiconductor layer 100S of the first substrate 100 are provided, and (3) a structure in which the connection wirings interconnecting and integrating the respective floating diffusions FD provided in the plurality of pixels 541 into one and the connection wirings interconnecting and integrating the respective VSS contact regions 118 provided in the plurality of pixels 541 into one are formed of a conductive material having high heat resistance, accordingly, in the case where a large electrode is not provided at the interface between the first substrate 100 and the second substrate 200, the first substrate 100 may be provided with a connection wiring that interconnects and integrates the respective floating diffusions FD provided in the plurality of pixels 541 into one and a connection wiring that interconnects and integrates the respective VSS contact regions 118 provided in the plurality of pixels 541 into one.

[ operation of the image Forming apparatus 1 ]

Next, the operation of the image forming apparatus 1 will be explained with reference to fig. 83 and 84. Fig. 83 and 84 are diagrams obtained by adding arrows indicating paths of respective signals to fig. 73. In fig. 83, paths of an input signal and the power supply potential and the reference potential which are input to the imaging device 1 from the outside are indicated by arrows. In fig. 84, signal paths of pixel signals output from the imaging device 1 to the outside are indicated by arrows. For example, input signals (e.g., pixel clock and synchronization signals) input to the imaging device 1 via the input unit 510A are transferred to the row driving unit 520 of the third substrate 300, and the row driving signals are created in the row driving unit 520. The row driving signal is transmitted to the second substrate 200 via the contacts 301 and 201. Further, the row driving signal reaches each pixel sharing unit 539 of the pixel array unit 540 via a row driving signal line 542 within the wiring layer 200T. Among the row driving signals that have reached the pixel sharing unit 539 of the second substrate 200, driving signals other than the transfer gate TG are input to the pixel circuit 210, and the respective transistors included in the pixel circuit 210 are driven. A driving signal for the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, and drives the pixels 541A, 541B, 541C, and 541D (fig. 83). Further, the power supply potential and the reference potential supplied from the outside of the imaging device 1 to the input unit 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via the contacts 301 and 201, and are supplied to the respective pixel circuits 210 of the pixel sharing unit 539 via the wiring within the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. On the other hand, pixel signals photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuits 210 of the second substrate 200 in each pixel sharing unit 539 via the through electrode 120E. A pixel signal based on the pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contacts 202 and 302. The pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300 and then output to the outside via the output unit 510B.

[ Effect ]

In this embodiment, the pixels 541A, 541B, 541C, and 541D (pixel sharing units 539) and the pixel circuits 210 are disposed on different substrates (the first substrate 100 and the second substrate 200), respectively. Therefore, the areas of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 can be enlarged as compared with a case where the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 are formed over the same substrate. Therefore, it is possible to increase the amount of pixel signals obtained by photoelectric conversion and reduce noise of the transistors of the pixel circuit 210. Therefore, the signal-to-noise ratio of the pixel signal improves, and the imaging apparatus 1 can output better pixel data (image information). Further, the imaging device 1 can be miniaturized (in other words, the pixel size can be reduced and the size of the imaging device 1 can be reduced). The imaging apparatus 1 can increase the number of pixels per unit area by reducing the pixel size, and can output a high-quality image.

Further, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other through the through electrodes 120E and 121E provided in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes to each other, or a method of connecting by a wire (e.g., a Through Silicon Via (TSV)) penetrating a semiconductor layer may be considered. By providing the through-electrodes 120E and 121E in the insulating region 212, the area for connecting the first substrate 100 and the second substrate 200 can be reduced as compared with this method. Therefore, the pixel size can be reduced, and the size of the imaging apparatus 1 can be further reduced. In addition, the resolution can be further improved by further minimizing the area of each pixel. When the chip size does not need to be reduced, the formation regions of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 can be enlarged. Therefore, it is possible to increase the amount of pixel signals obtained by photoelectric conversion and reduce noise of transistors provided in the pixel circuit 210. Therefore, the signal-to-noise ratio of the pixel signal improves, and the imaging apparatus 1 can output better pixel data (image information).

Further, in the imaging device 1, the pixel circuits 210, the column signal processing units 550, and the image signal processing units 560 are respectively provided on substrates (the second substrate 200 and the third substrate 300) different from each other. Therefore, the area of the pixel circuit 210 and the areas of the column signal processing unit 550 and the image signal processing unit 560 can be enlarged as compared with the case where the pixel circuit 210 and the column signal processing unit 550 and the image signal processing unit 560 are formed on the same substrate. Therefore, noise generated in the column signal processing unit 550 can be reduced, and an advanced image processing circuit can be mounted in the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signal improves, and the imaging apparatus 1 can output better pixel data (image information).

Further, in the imaging device 1, the pixel array unit 540 is disposed on the first substrate 100 and the second substrate 200, and the column signal processing unit 550 and the image signal processing unit 560 are disposed on the third substrate 300. In addition, contacts 201, 202, 301, and 302 connecting the second substrate 200 and the third substrate 300 are formed above the pixel array unit 540. Therefore, the contacts 201, 202, 301, and 302 can be freely laid out without interference of various wirings provided in the pixel array with the layout. Therefore, the contacts 201, 202, 301, and 302 may be used for electrical connection between the second substrate 200 and the third substrate 300. By using the contact portions 201, 202, 301, and 302, for example, the column signal processing unit 550 and the image signal processing unit 560 have a high degree of freedom in layout. Therefore, noise generated in the column signal processing unit 550 can be reduced, and an advanced image processing circuit can be mounted in the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signal improves, and the imaging apparatus 1 can output better pixel data (image information).

Further, in the imaging device 1, the pixel separation portion 117 penetrates the semiconductor layer 100S. Therefore, even in the case where the distance between adjacent pixels (the pixels 541A, 541B, 541C, and 541D) is shortened due to the miniaturization of the area of each pixel, color mixing between the pixels 541A, 541B, 541C, and 541D can be suppressed. Therefore, the signal-to-noise ratio of the pixel signal improves, and the imaging apparatus 1 can output better pixel data (image information).

Further, in the imaging apparatus 1, the pixel circuit 210 is provided for each pixel sharing unit 539. Therefore, compared to the case where the pixel circuit 210 is provided for each of the pixels 541A, 541B, 541C, and 541D, the formation area of the transistors (the amplification transistor AMP, the reset transistor RST, the selection transistor SEL, the FD conversion gain switching transistor FDG) constituting the pixel circuit 210 can be increased. For example, noise can be suppressed by increasing the formation area of the amplification transistor AMP. Therefore, the signal-to-noise ratio of the pixel signal improves, and the imaging apparatus 1 can output better pixel data (image information).

Further, in the imaging device 1, the pad portion 120 for electrically connecting the floating diffusions FD (the floating diffusions FD1, FD2, FD3, and FD4) of the four pixels (the pixels 541A, 541B, 541C, and 541D) is provided in the first substrate 100. Therefore, the number of through-electrodes (through-electrodes 120E) connecting the first substrate 100 and the second substrate 200 can be reduced as compared with the case where such pad portions 120 are provided on the second substrate 200. Therefore, the insulating region 212 can be made small, and a sufficient size of a formation region (the semiconductor layer 200S) of a transistor constituting the pixel circuit 210 can be secured. Therefore, noise of transistors provided in the pixel circuit 210 can be reduced and the signal-to-noise ratio of pixel signals can be improved, and the imaging device 1 can output better pixel data (image information).

Hereinafter, a modification of the image forming apparatus 1 according to the above-described embodiment will be explained. In the following modification, the same configurations as those of the above embodiment will be described with the same reference numerals.

<6.2. modified example 1>

Fig. 85 to 89 show a modification of the planar configuration of the image forming apparatus 1 according to the above embodiment. Fig. 85 schematically shows a planar configuration in the vicinity of the front face of the semiconductor layer 200S of the second substrate 200, and corresponds to fig. 78 explained in the above-described embodiment. Fig. 86 schematically shows the constitution of the first wiring layer W1, and the semiconductor layer 200S connected to the first wiring layer W1 and the respective portions of the first substrate 100, and corresponds to fig. 79 explained in the above-described embodiment. Fig. 87 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to fig. 80 explained in the above-described embodiment. Fig. 88 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to fig. 81 explained in the above-described embodiment. Fig. 89 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to fig. 82 explained in the above-described embodiment.

In the present modification, as shown in fig. 86, of the two pixel-sharing units 539 arranged in the H direction of the second substrate 200, the internal layout of one pixel-sharing unit 539 (e.g., the right side of the paper) has a configuration in which the internal layout of the other pixel-sharing unit 539 (e.g., the left side of the paper) is inverted only in the H direction. Further, the displacement in the V direction between the outline of one pixel-sharing unit 539 and the outline of another pixel-sharing unit 539 is larger than that illustrated in the above-described embodiment (fig. 79). In this way, by increasing the shift in the V direction, the distance between the amplification transistor AMP of the other pixel-sharing unit 539 and the pad portion 120 connected thereto (the pad portion 120 of the other (lower side of the paper surface) of the two pixel-sharing units 539 juxtaposed in the V direction shown in fig. 7) can be reduced. With such a layout, in modification 1 of the imaging device 1 shown in fig. 85 to 89, in the case where the planar layouts of two pixel-sharing units 539 juxtaposed in the H direction are not inverted from each other in the V direction, the areas thereof can be made the same as the areas of the pixel-sharing units 539 of the second substrate 200 described in the above-described embodiment. Note that the planar layout of the pixel-sharing unit 539 of the first substrate 100 is the same as that described in the above-described embodiment (fig. 77A and 77B). Therefore, the image forming apparatus 1 of the present modification can obtain the effects similar to those described in the above embodiment. The configuration of the pixel-sharing unit 539 of the second substrate 200 is not limited to the configuration described in the above-described embodiment and the present modification.

[6.3 ] modification 2]

Fig. 90 to 95 show a modification of the planar configuration of the image forming apparatus 1 according to the above embodiment. Fig. 90 schematically shows a planar configuration of the first substrate 100, and corresponds to fig. 77A explained in the above-described embodiment. Fig. 91 schematically shows a planar configuration in the vicinity of the front face of the semiconductor layer 200S of the second substrate 200, and corresponds to fig. 78 explained in the above-described embodiment. Fig. 92 schematically shows the constitution of the first wiring layer W1, and the semiconductor layer 200S connected to the first wiring layer W1 and the respective portions of the first substrate 100, and corresponds to fig. 79 explained in the above-described embodiment. Fig. 93 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to fig. 80 explained in the above-described embodiment. Fig. 94 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to fig. 81 explained in the above-described embodiment. Fig. 95 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to fig. 82 explained in the above-described embodiment.

In the present modification, the outer shape of each pixel circuit 210 has a substantially square planar shape (fig. 91 and the like). In this regard, the planar configuration of the image forming apparatus 1 of the present modification is different from that of the image forming apparatus 1 described in the above embodiment.

For example, as explained in the above-described embodiment, the pixel sharing unit 539 of the first substrate 100 is formed on the pixel regions of two rows × two columns and has a substantially square planar shape (fig. 90). For example, in each pixel sharing unit 539, the horizontal portions TGb of the transfer gates TG1 and TG3 of the pixels 541A and 541C of one pixel column extend in the H direction toward the direction of the central portion of the pixel sharing unit 539 (more specifically, toward the direction of the outer edges of the pixels 541A and 541C and toward the direction of the central portion of the pixel sharing unit 539) from the positions where they overlap the vertical portion TGa, and the horizontal portions TGb of the transfer gates TG2 and TG4 of the pixels 541B and 541D of the other pixel column extend in the H direction toward the direction of the outer side of the pixel sharing unit 539 (more specifically, toward the direction of the outer edges of the pixels 541B and 541D and toward the direction of the outer side of the pixel sharing unit 539) from the positions where they overlap the vertical portion TGa. The pad portion 120 connected to the floating diffusion FD is disposed in the center portion of the pixel-sharing unit 539 (the center portion in the H direction and the V direction of the pixel-sharing unit 539), and the pad portion 121 connected to the VSS contact region 118 is disposed at the end portion of the pixel-sharing unit 539 at least in the H direction (in the H direction and the V direction in fig. 90).

As another configuration example, it is conceivable that the horizontal portions TGb of the transfer gates TG1, TG2, TG3, and TG4 are provided only in the region facing the vertical portion TGa. At this time, as explained in the above embodiment, the semiconductor layer 200S is easily finely divided. Therefore, it is difficult to form a large transistor of the pixel circuit 210. On the other hand, similarly to the above-described modification, if the horizontal portion TGb of the transfer gates TG1, TG2, TG3, and TG4 extends in the H direction from the position where it overlaps the vertical portion TGa, the width of the semiconductor layer 200S can be increased similarly to that explained in the above-described embodiment. Specifically, the positions in the H direction of the through electrodes TGV1 and TGV3 connected to the transfer gates TG1 and TG3 may be arranged close to the positions in the H direction of the through electrode 120E, and the positions in the H direction of the through electrodes TGV2 and TGV4 connected to the transfer gates TG2 and TG4 may be arranged close to the through electrode 121E (fig. 92). Therefore, as explained in the above embodiment, the width (the size in the H direction) of the semiconductor layer 200S extending in the V direction can be increased. Therefore, the size of the transistor of the pixel circuit 210, particularly, the size of the amplifying transistor AMP can be increased. Therefore, the signal-to-noise ratio of the pixel signal improves, and the imaging apparatus 1 can output better pixel data (image information).

The pixel sharing units 539 of the second substrate 200 have, for example, substantially the same size as the size of the H direction and the V direction of the pixel sharing units 539 of the first substrate 100, and are disposed on regions corresponding to, for example, pixel regions of about two rows × two columns. For example, in each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged side by side in the V direction on one semiconductor layer 200S extending in the V direction, and the FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side in the V direction on one semiconductor layer 200S extending in the V direction. The one semiconductor layer 200S provided with the selection transistor SEL and the amplification transistor AMP and the one semiconductor layer 200S provided with the FD conversion gain switching transistor FDG and the reset transistor RST are juxtaposed in the H direction via the insulating region 212. The insulating region 212 extends in the V direction (fig. 91).

Here, the outer shape of the pixel sharing unit 539 of the second substrate 200 will be explained with reference to fig. 91 and 92. For example, the pixel sharing unit 539 of the first substrate 100 shown in fig. 90 is connected to an amplifying transistor AMP and a selecting transistor SEL provided on one side (left side of the paper surface in fig. 92) of the H direction of the pad portion 120 and an FD conversion gain switching transistor FDG and a reset transistor RST provided on the other side (right side of the paper surface in fig. 92) of the H direction of the pad portion 120. The outline of the pixel sharing unit 539 of the second substrate 200 including the amplification transistor AMP, the selection transistor SEL, the FD conversion gain switching transistor FDG, and the reset transistor RST is determined by the four outer edges as follows.

The first outer edge is an outer edge at one end (an end on the upper side of the paper surface in fig. 92) in the V direction of the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP. The first outer edge is disposed between the amplifying transistor AMP included in the pixel-sharing unit 539 and the selection transistor SEL included in the pixel-sharing unit 539 adjacent to one side (the upper side of the paper in fig. 92) in the V direction of the pixel-sharing unit 539. More specifically, the first outer edge is disposed in the center portion in the V direction of the element isolation region 213 between the amplification transistor AMP and the selection transistor SEL. The second outer edge is an outer edge at the other end (end on the lower side of the paper surface in fig. 92) in the V direction of the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP. The second outer edge is provided between the selection transistor SEL included in the pixel-sharing unit 539 and the amplification transistor AMP included in the pixel-sharing unit 539 adjacent to the other side (lower side of the paper surface in fig. 92) of the V direction of the pixel-sharing unit 539. More specifically, the second outer edge is disposed at the center portion in the V direction of the element isolation region 213 between the selection transistor SEL and the amplification transistor AMP. The third outer edge is an outer edge at the other end (end on the lower side of the paper surface in fig. 92) in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. A third outer edge is provided between the FD conversion gain switching transistor FDG included in this pixel-sharing unit 539 and the reset transistor RST included in the pixel-sharing unit 539 adjacent to the other side (the lower side of the paper surface in fig. 92) of the V direction of this pixel-sharing unit 539. More specifically, the third outer edge is provided at the center portion in the V direction of the element isolation region 213 between the FD conversion gain switching transistor FDG and the reset transistor RST. The fourth outer edge is an outer edge at one end (an end on the upper side of the paper surface in fig. 92) in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. The fourth outer edge is provided between the reset transistor RST included in the pixel-sharing unit 539 and the FD conversion gain switching transistor FDG (not shown) included in the pixel-sharing unit 539 adjacent to the one side (the upper side of the paper surface in fig. 92) in the V direction of the pixel-sharing unit 539. More specifically, the fourth outer edge is provided at the center portion in the V direction of the element isolation region 213 (not shown) between the reset transistor RST and the FD conversion gain switching transistor FDG.

In the outline of the pixel sharing unit 539 of the second substrate 200 that includes the first outer edge, the second outer edge, the third outer edge, and the fourth outer edge, the third outer edge and the fourth outer edge are configured to be shifted to one side in the V direction (in other words, shifted to one side in the V direction) with respect to the first outer edge and the second outer edge. By using such a layout, both the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG can be arranged as close to the pad section 120 as possible. Therefore, the area of the wiring connecting the amplifying transistor AMP and the FD conversion gain switching transistor FDG is reduced, and the imaging device 1 can be easily miniaturized. Note that the VSS contact region 218 is provided between the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, the plurality of pixel circuits 210 have the same configuration as each other.

The image forming apparatus 1 having such a second substrate 200 can also obtain effects similar to those explained in the above-described embodiment. The configuration of the pixel-sharing unit 539 of the second substrate 200 is not limited to the configuration described in the above-described embodiment and the present modification.

[6.4 ] modification 3]

Fig. 96 to 101 show a modification of the planar configuration of the image forming apparatus 1 according to the above embodiment. Fig. 96 schematically shows a planar configuration of the first substrate 100, and corresponds to fig. 77B explained in the above-described embodiment. Fig. 97 schematically shows a planar configuration in the vicinity of the front face of the semiconductor layer 200S of the second substrate 200, and corresponds to fig. 78 explained in the above-described embodiment. Fig. 98 schematically shows the constitution of the first wiring layer W1, and the semiconductor layer 200S connected to the first wiring layer W1 and the respective portions of the first substrate 100, and corresponds to fig. 79 explained in the above-described embodiment. Fig. 99 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to fig. 80 explained in the above-described embodiment. The diagram 100 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to the diagram 81 explained in the above-described embodiment. Fig. 101 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to fig. 82 explained in the above-described embodiment.

In the present modification, the semiconductor layer 200S of the second substrate 200 extends in the H direction (fig. 98). That is, it basically corresponds to a configuration in which the planar configuration of the imaging apparatus 1 shown in the above-described fig. 91 and the like is rotated by 90 degrees.

For example, as explained in the above-described embodiment, the pixel sharing unit 539 of the first substrate 100 is formed on the pixel regions of two rows × two columns and has a substantially square planar shape (fig. 96). For example, in each pixel sharing unit 539, the transfer gates TG1 and TG2 of the pixels 541A and 541B of one pixel row extend toward the central portion of the pixel sharing unit 539 in the V direction, and the transfer gates TG3 and TG4 of the pixels 541C and 541D of another pixel row extend toward the outside direction of the pixel sharing unit 539 in the V direction. A pad portion 120 connected to the floating diffusion FD is disposed in the center portion of the pixel sharing unit 539, and a pad portion 121 connected to the VSS contact region 118 is disposed at least in the V direction (in the V direction and the H direction in fig. 96) at the end portion of the pixel sharing unit 539. At this time, the V-direction positions of the through electrodes TGV1 and TGV2 of the transfer gates TG1 and TG2 are close to the V-direction position of the through electrode 120E, and the V-direction positions of the through electrodes TGV3 and TGV4 of the transfer gates TG3 and TG4 are close to the V-direction position of the through electrode 121E (fig. 98). Therefore, for similar reasons as explained in the above-described embodiment, the width (the size in the V direction) of the semiconductor layer 200S extending in the H direction can be increased. Therefore, it is possible to increase the size of the amplifying transistor AMP and suppress noise.

In each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged side by side in the H direction, and the reset transistor RST is arranged at a position adjacent to each other in the V direction with the selection transistor SEL and the insulating region 212 interposed therebetween (fig. 97). The FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side in the H direction. The VSS contact region 218 is disposed in an island shape in the insulating region 212. For example, the third wiring layer W3 extends in the H direction (fig. 100), and the fourth wiring layer W4 extends in the V direction (fig. 101).

The image forming apparatus 1 having such a second substrate 200 can also obtain effects similar to those explained in the above-described embodiment. The configuration of the pixel-sharing unit 539 of the second substrate 200 is not limited to the configuration described in the above-described embodiment and the present modification. For example, the semiconductor layer 200S described in the above embodiment and modification example 1 may extend in the H direction.

[6.5 ] modification 4]

Fig. 102 schematically shows a modification of the sectional configuration of the image forming apparatus 1 according to the above-described embodiment. Fig. 102 corresponds to fig. 73 explained in the above embodiment. In the present modification, the imaging device 1 has the contacts 203, 204, 303, and 304 at positions facing the central portion of the pixel array unit 540 in addition to the contacts 201, 202, 301, and 302. In this regard, the image forming apparatus 1 of the present modification is different from the image forming apparatus 1 described in the above embodiment.

The contact portions 203 and 204 are provided on the second substrate 200, and are exposed on the bonding surface with the third substrate 300. The contact portions 303 and 304 are provided on the third substrate 300, and are exposed on the bonding surface with the second substrate. The contact portion 203 is in contact with the contact portion 303, and the contact portion 204 is in contact with the contact portion 304. That is, in the imaging device 1, the second substrate 200 and the third substrate 300 are connected by the contact portions 203, 204, 303, and 304 in addition to the contact portions 201, 202, 301, and 302.

Next, the operation of the imaging apparatus 1 will be explained using fig. 103 and 104. In fig. 103, paths of an input signal and the power supply potential and the reference potential which are input to the imaging device 1 from the outside are indicated by arrows. In fig. 104, signal paths of pixel signals output from the imaging device 1 to the outside are indicated by arrows. For example, an input signal input to the imaging device 1 via the input unit 510A is transferred to the row driving unit 520 of the third substrate 300, and a row driving signal is created in the row driving unit 520. The row driving signal is transmitted to the second substrate 200 via the contacts 303 and 203. Further, the row driving signal reaches each pixel sharing unit 539 of the pixel array unit 540 via a row driving signal line 542 within the wiring layer 200T. Among the row driving signals that have reached the pixel sharing unit 539 of the second substrate 200, driving signals other than the transfer gate TG are input to the pixel circuit 210, and the respective transistors included in the pixel circuit 210 are driven. A driving signal for the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, and drives the pixels 541A, 541B, 541C, and 541D. Further, the power supply potential and the reference potential supplied from the outside of the imaging device 1 to the input unit 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via the contacts 303 and 203, and are supplied to the respective pixel circuits 210 of the pixel sharing unit 539 via the wiring within the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. On the other hand, pixel signals photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuits 210 of the second substrate 200 in each pixel sharing unit 539. A pixel signal based on the pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contacts 204 and 304. The pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300 and then output to the outside via the output unit 510B.

The imaging device 1 having such contact portions 203, 204, 303, and 304 can also obtain effects similar to those explained in the above-described embodiment. The position, number, and the like of the contact portions (to which the wiring is connected via the contact portions 303 and 304) may be changed according to the design of the circuit and the like of the third substrate 300.

[6.6 ] modification 5]

Fig. 105 shows a modification of the sectional configuration of the imaging device 1 according to the above-described embodiment. Fig. 105 corresponds to fig. 76 explained in the above embodiment. In the present modification, the transfer transistor TR having a planar structure is provided on the first substrate 100. In this regard, the image forming apparatus 1 of the present modification is different from the image forming apparatus 1 described in the above embodiment.

In the transfer transistor TR, the transfer gate TG includes only the horizontal portion TGb. In other words, the transfer gate TG does not have the vertical portion TGa, and is disposed to face the semiconductor layer 100S.

The imaging device 1 having the transfer transistor TR including such a planar structure can also obtain effects similar to those explained in the above-described embodiment. Further, by providing the planar type transfer gate TG on the first substrate 100, it is conceivable to form the photodiode PD closer to the front surface of the semiconductor layer 100S, thereby increasing the saturation signal amount (Qs), as compared with the case where the vertical type transfer gate TG is provided on the first substrate 100. Further, the method of forming the planar-type transfer gate TG on the first substrate 100 has fewer manufacturing steps than the method of forming the vertical-type transfer gate TG on the first substrate 100, and it is also conceivable that adverse effects on the photodiode PD caused by the manufacturing steps are less likely to occur.

[6.7 ] modification 6]

Fig. 106 shows a modification of the pixel circuit of the imaging device 1 according to the above-described embodiment. Fig. 106 corresponds to fig. 74 explained in the above embodiment. In the present modification, the pixel circuit 210 is provided for each pixel (pixel 541A). That is, the pixel circuit 210 is not shared by a plurality of pixels. In this regard, the image forming apparatus 1 of the present modification is different from the image forming apparatus 1 described in the above embodiment.

The imaging device 1 of the present modification is the same as the imaging device 1 described in the above embodiment in that the pixel portion 541A and the pixel circuit 210 are provided on different substrates (the first substrate 100 and the second substrate 200). Therefore, the image forming apparatus 1 according to the present modification can also obtain effects similar to those described in the above embodiment.

[6.8 ] modification 7]

Fig. 107 shows a modification of the planar configuration of the pixel separating portion 117 described in the above embodiment. A gap may be provided in the pixel separation section 117 surrounding each of the pixels 541A, 541B, 541C, and 541D. That is, the entire periphery of the pixels 541A, 541B, 541C, and 541D may not be surrounded by the pixel separation portion 117. For example, the gap of the pixel separating portion 117 is provided near the pad portions 120 and 121 (refer to fig. 77B).

In the above-described embodiment, the example in which the pixel separating portion 117 has the FTI structure penetrating the semiconductor layer 100S (refer to fig. 76) has been described, but the pixel separating portion 117 may have a configuration other than the FTI structure. For example, the pixel separating portion 117 may not be provided to completely penetrate the semiconductor layer 100S, and may have a so-called Deep Trench Isolation (DTI) structure.

<6.9 application example >

Fig. 108 shows an example of a schematic configuration of an imaging system 7 including the imaging device 1 according to the above-described embodiment and its modifications.

The imaging system 7 is, for example, an electronic device which is an imaging apparatus such as a digital camera or a video camera or a portable terminal device such as a smartphone or a tablet terminal. The imaging system 7 includes, for example, the imaging device 1 according to the above-described embodiment and its modifications, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 7, the imaging device 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 according to the above-described embodiment and the modifications thereof are connected to each other via the bus 249.

The imaging device 1 according to the above-described embodiment and its modifications outputs image data corresponding to incident light. The DSP circuit 243 is a signal processing circuit that processes signals (image data) output from the imaging device 1 according to the above-described embodiment and its modifications. The frame memory 244 temporarily holds image data processed by the DSP circuit 243 in units of frames. The display unit 245 includes, for example, a panel-type display device such as a liquid crystal panel or an organic Electroluminescence (EL) panel, and displays a moving image or a still image captured by the imaging device 1 according to the above-described embodiment and its modifications. The storage unit 246 records image data of a moving image or a still image captured by the imaging apparatus 1 according to the above-described embodiment and its modifications in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation instructions for various functions of the imaging system 7 according to an operation by a user. The power supply unit 248 suitably supplies various power supplies serving as operation power supplies of the imaging apparatus 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, and the operation unit 247 according to the above-described embodiment and its modifications to these supply targets.

Next, an imaging step in the imaging system 7 will be explained.

Fig. 109 shows an example of the flow of the imaging operation in the imaging system 7. The user gives an instruction on the start of imaging by operating the operation unit 247 (step S101). Then, the operation unit 247 transmits an imaging instruction to the imaging apparatus 1 (step S102). When receiving the imaging instruction, the imaging apparatus 1 (specifically, the system control circuit 36) performs imaging by a predetermined imaging manner (step S103).

The imaging device 1 outputs image data obtained by imaging to the DSP circuit 243. Here, the image data is data of all pixels based on the pixel signal generated by the charge temporarily held in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing, etc.) based on the image data input from the imaging apparatus 1 (step S104). The DSP circuit 243 causes the frame memory 244 to hold the image data subjected to the predetermined signal processing, and the frame memory 244 causes the storage unit 246 to store the image data (step S105). In this way, imaging in the imaging system 7 is performed.

In an application example, the image forming apparatus 1 according to the above-described embodiment and the modifications thereof is applied to the image forming system 7. Therefore, since the imaging apparatus 1 can be miniaturized or has high definition, a compact or high definition imaging system 7 can be provided.

[6.10 application example ]

[ application example 1]

The technique according to the present disclosure (present technique) can be applied to various products. For example, the technology according to the present disclosure may be implemented as a device mounted on any type of moving body such as an automobile, an electric automobile, a hybrid electric automobile, a motorcycle, a bicycle, a personal mobile device, an airplane, an unmanned aerial vehicle, a ship, a robot, and the like.

Fig. 110 is a block diagram of a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technique according to the embodiment of the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example shown in fig. 110, the vehicle control system 12000 includes a drive system control unit 12010, a main body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network interface (I/F)12053 are shown.

The drive system control unit 12010 controls the operations of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device of a driving force generation device for generating a driving force of the vehicle, such as an internal combustion engine or a drive motor, a driving force transmission mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting a steering angle of the vehicle, and a brake device for generating a braking force of the vehicle.

The main body system control unit 12020 controls the operations of various devices mounted to the vehicle body according to various programs. For example, the main body system control unit 12020 functions as a control device of a keyless entry system, a smart key system, a power window device, or various lights such as a head light, a tail light, a stop light, a turn signal light, or a fog light. In this case, a radio wave transmitted from the portable device or a signal of various switches for replacing the key may be input to the main body system control unit 12020. The main body system control unit 12020 receives input of radio waves or signals and controls the door lock device, power window device, lamp, and the like of the vehicle.

Vehicle exterior information detection section 12030 detects information on the exterior of the vehicle to which vehicle control system 12000 is attached. For example, the imaging unit 12031 is connected to the vehicle exterior information detecting unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 can perform object detection processing such as a person, a car, an obstacle, a sign, characters on a road, or distance detection processing based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal corresponding to the amount of received light. The imaging unit 12031 may output an electrical signal as an image, or may output an electrical signal as ranging information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects information in the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that images the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 may calculate the fatigue or concentration of the driver, or may determine whether the driver is drowsy.

For example, the microcomputer 12051 may calculate control target values of the driving force generation device, the steering mechanism, or the brake device based on the information of the interior and exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and may output a control instruction to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize functions of an Advanced Driver Assistance System (ADAS) including collision avoidance or collision mitigation of vehicles, follow-up running based on a distance between vehicles, vehicle speed keeping running, vehicle collision warning, lane departure warning of vehicles, and the like.

Further, the microcomputer 12051 can perform coordinated control by controlling the driving force generation device, the steering mechanism, the brake device, and the like based on the information on the vehicle surroundings obtained by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040 to realize automatic driving and the like in which the vehicle autonomously travels without depending on the operation of the driver.

Further, the microcomputer 12051 can output a control instruction to the subject system control unit 12020 based on the information outside the vehicle obtained by the vehicle-exterior information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control by controlling headlights according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle-exterior information detection unit 12030 to realize glare prevention such as switching a high beam to a low beam.

The audio/image output unit 12052 transmits an output signal of at least one of audio and image to an output device capable of visually or aurally notifying a vehicle occupant or information outside the vehicle. In the example of fig. 110, as output devices, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a flat-view display.

Fig. 111 is a diagram illustrating an example of the mounting position of the imaging unit 12031.

In fig. 111, a vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the head, side mirrors, rear bumper, rear door, and upper portion of a windshield in the vehicle 12100. The imaging unit 12101 provided at the vehicle head and the imaging unit 12105 provided at the upper portion of the windshield in the vehicle mainly obtain images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly obtain images of the sides of the vehicle 12100. An imaging unit 12104 provided at a rear bumper or a rear door mainly obtains an image of the rear of the vehicle 12100. The front images acquired by the imaging units 12101 and 12105 are mainly used to detect a front vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, and the like.

Further, FIG. 111 shows an example of imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 represents an imaging range of the imaging unit 12101 provided at the vehicle head, imaging ranges 12112 and 12113 represent imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors, respectively, and an imaging range 12114 represents an imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's eye view image of the vehicle 12100 as seen from above is obtained by superimposing image data captured by the imaging units 12101 to 12104.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, based on the distance information obtained from the imaging units 12101 to 12104, by obtaining the distance to each solid object within the imaging ranges 12111 to 12114 and the temporal change in the distance (relative speed to the vehicle 12100), the microcomputer 12051 extracts, as the preceding vehicle, the solid object that is on the traveling route of the vehicle 12100, particularly the closest solid object, and that travels at a predetermined speed (for example, 0km/h or more) in substantially the same direction as the vehicle 12100. Further, the microcomputer 12051 may set a distance between vehicles secured in advance for the preceding vehicle, and may perform automatic braking control (including follow-up running stop control), automatic acceleration control (including follow-up running start control), and the like. As described above, it is possible to perform cooperative control for automatic driving or the like in which the vehicle autonomously travels without depending on the operation of the driver.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 may classify three-dimensional object data on a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles, extract the three-dimensional object data, and automatically avoid an obstacle using the three-dimensional object data. For example, the microcomputer 12051 recognizes obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult to visually recognize. Then, the microcomputer 12051 judges a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, it is possible to perform driving assistance for collision avoidance by outputting a warning to the driver via the audio speaker 12061 and the display unit 12062 or performing forced deceleration or avoidance steering via the drive system control unit 12010.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101 to 12104. For example, the identification of a pedestrian is performed by a step of extracting feature points in an image captured by the imaging units 12101 to 12104 as infrared cameras and a step of performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 judges that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies a pedestrian, the audio/image output portion 12052 causes the display unit 12062 to superimpose and display a quadrangular contour line for emphasis on the identified pedestrian. Further, the audio/image output portion 12052 may cause the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

One example of a moving body control system to which the technique according to the present disclosure can be applied has been described above. The technique according to the present disclosure can be applied to the imaging unit 12031 in the above-described configuration. Specifically, the image forming apparatus 1 according to the above-described embodiment and its modifications may be applied to the image forming unit 12031. Since a high-definition captured image with little noise can be obtained by applying the technique according to the present disclosure to the imaging unit 12031, high-precision control can be performed using the captured image in the moving body control system.

[ application example 2]

Fig. 112 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technique (present technique) according to the embodiment of the present disclosure can be applied.

Fig. 112 shows a state in which an operator (doctor) 11131 is performing an operation on a patient 11132 on a bed 11133 using the endoscopic surgery system 11000. As shown in fig. 112, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a veress tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

The endoscope 11100 includes a lens barrel 11101 in which a region of a predetermined length from the distal end is inserted into a body cavity of a patient 11132, and a camera 11102 connected to the proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100 configured as a so-called hard scope having the hard lens barrel 11101 is shown, but the endoscope 11100 may be configured as a so-called soft scope having a soft lens barrel.

An opening portion into which the objective lens is fitted is provided at the distal end of the lens barrel 11101. The light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the distal end of the lens barrel by a light guide extending to the inside of the lens barrel 11101 and emitted toward an observation object within the body cavity of the patient 11132 via the objective lens. Note that the endoscope 11100 may be a direct-view endoscope, a strabismus endoscope, or a side-view endoscope.

The optical system and the imaging element are provided inside the camera 11102, and reflected light (observation light) from an observation target is condensed on the imaging element by the optical system. The observation light is photoelectrically converted by the imaging element, and an electric signal corresponding to the observation light, that is, an image signal corresponding to an observation image is generated. The image signal is transmitted as RAW data to a Camera Control Unit (CCU) 11201.

The CCU 11201 includes a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and the like, and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Further, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing such as development processing (demosaicing processing) for displaying an image based on the image signal, for example, on the image signal.

The display device 11202 displays an image based on the image signal subjected to image processing by the CCU 11201 under the control of the CCU 11201.

For example, the light source device 11203 includes a light source such as a Light Emitting Diode (LED), and supplies irradiation light for imaging a surgical site or the like to the endoscope 11100.

The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction or the like by using the endoscope 11100 to change the imaging conditions (the type of irradiation light, magnification, focal length, and the like).

The treatment instrument control device 11205 controls driving of the energy treatment instrument 11112 for cauterization and incision of tissue, sealing of blood vessels, and the like. The pneumoperitoneum device 11206 injects a gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to inflate the body cavity of the patient 11132 for securing the field of view of the endoscope 11100 and securing the working space of the operator. The recorder 11207 is a device capable of recording various information relating to the operation. The printer 11208 is a device capable of printing various information related to the operation in various forms such as text, images, graphics, and the like.

Note that the light source device 11203 that supplies irradiation light at the time of imaging the surgical site to the endoscope 11100 may include, for example, an LED, a laser light source, or a white light source including a combination thereof. In the case where the white light source is configured by a combination of RGB laser light sources, since the output intensity and the output timing of each color (each wavelength) can be controlled with high accuracy, adjustment of the white balance of the captured image can be performed in the light source device 11203. Further, in this case, by irradiating the laser light from each of the RGB laser light sources onto the observation target time-divisionally and controlling the driving of the imaging element of the camera 11102 in synchronization with the irradiation timing, an image corresponding to each of RGB can also be captured time-divisionally. According to this method, a color image can be obtained without providing a color filter in the imaging element.

Further, the driving of the light source device 11203 may be controlled so as to change the intensity of light to be output every predetermined time. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity to acquire images divisionally by time and synthesize the images, an image of a high dynamic range without so-called underexposed shadows and overexposed highlights can be generated.

Further, the light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to special light observation. In the special light observation, for example, so-called narrow-band light observation (narrow-band imaging) is performed in which predetermined tissues such as blood vessels of a mucosal surface are imaged with high contrast by irradiating light of a narrower band than that of irradiation light (i.e., white light) at the time of ordinary observation by using wavelength dependence of light absorption in body tissues. Alternatively, in the special light observation, fluorescence observation for obtaining an image by fluorescence generated by irradiation of excitation light may be performed. In fluorescence observation, for example, a body tissue may be irradiated with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or a fluorescence image may be obtained by locally injecting an agent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the agent. The light source device 11203 may be configured to supply narrow-band light and/or excitation light corresponding to such special light observation.

Fig. 113 is a block diagram showing an example of a functional configuration of the camera 11102 and the CCU 11201 shown in fig. 112.

The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are communicably connected to each other by a transmission cable 11400.

The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light received from the distal end of the lens barrel 11101 is guided to the camera 11102 and is incident on the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

The imaging unit 11402 includes an imaging element. The number of imaging elements constituting the imaging unit 11402 may be one element (so-called single plate type) or a plurality of (so-called multi-plate type). When the imaging unit 11402 is configured as a multi-plate type, for example, an image signal corresponding to each of RGB may be generated by each imaging element, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 11402 may include a pair of imaging elements for acquiring image signals for right and left eyes corresponding to three-dimensional (3D) display. By performing the 3D display, the operator 11131 can grasp the depth of the body tissue in the surgical site more accurately. Note that when the imaging unit 11402 is configured as a multi-plate type, a plurality of lens units 11401 corresponding to each imaging element may be provided.

Further, the imaging unit 11402 is not necessarily provided in the camera 11102. For example, the imaging unit 11402 may be disposed right behind the objective lens inside the lens barrel 11101.

The driving unit 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. Accordingly, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

A communication unit 11404 includes communication devices for transmitting and receiving various information to/from the CCU 11201. The communication unit 11404 transmits the image signal acquired from the imaging unit 11402 to the CCU 11201 as RAW data via the transmission cable 11400.

Further, the communication unit 11404 receives a control signal for controlling driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control signal includes, for example, information relating to imaging conditions, such as information for specifying a frame rate of a captured image, information for specifying an exposure value at the time of imaging, and/or information for specifying a magnification and a focus of the captured image, and the like.

Note that imaging conditions such as a frame rate, an exposure value, a magnification, and a focus may be appropriately specified by a user, or may be automatically set by the control unit 11413 of the CCU 11201 based on a captured image signal. In the latter case, a so-called Auto Exposure (AE) function, an Auto Focus (AF) function, and an Auto White Balance (AWB) function are installed in the endoscope 11100.

The camera control unit 11405 controls driving of the camera 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 via the transmission cable 11400.

Further, the communication unit 11411 transmits a control signal for controlling driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted by electrical communication, optical communication, or the like.

The image processing unit 11412 performs various image processes on an image signal as RAW data transmitted from the camera 11102.

The control unit 11413 performs various controls related to imaging of a surgical site or the like by using the endoscope 11100 and display of a captured image obtained by imaging the surgical site or the like. For example, the control unit 11413 generates a control signal for controlling driving of the camera 11102.

Further, the control unit 11413 causes the display device 11202 to display a captured image of the surgical site or the like based on the image signal subjected to the image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects within the captured image by using various image recognition techniques. For example, the control unit 11413 may recognize a surgical instrument such as a forceps, a specific living body part, bleeding, fog when the energy treatment instrument 11112 is used, or the like by detecting an edge shape and/or a color or the like of an object included in the captured image. When the captured image is displayed in the display device 11202, the control unit 11413 may superimpose and display various kinds of operation support information on the image of the operation site by using the recognition result. Since the operation support information is superimposed and displayed and presented to the operator 11131, the burden on the operator 11131 can be reduced and the operator 11131 can reliably perform an operation.

The transmission cable 11400 connecting the camera 11102 and the CCU 11201 is an electric signal cable corresponding to communication of electric signals, an optical fiber corresponding to optical communication, or a composite cable thereof.

Here, in the illustrated example, communication is performed by wire by using the transmission cable 11400, but communication between the camera 11102 and the CCU 11201 may be performed wirelessly.

Examples of endoscopic surgical systems to which techniques according to the present disclosure may be applied have been described above. The technique according to the present disclosure can be suitably applied to the imaging unit 11402 provided at the camera 11102 of the endoscope 11100 in the above-described configuration. Since the imaging unit 11402 can be miniaturized or have high definition by applying the technique according to the present disclosure to the imaging unit 11402, the endoscope 11100 having a small size or high definition can be provided.

The technique according to the present disclosure has been described above with reference to the first to third embodiments, the modifications, and the specific examples. However, the technique according to the present disclosure is not limited to the above-described embodiments and the like, and may be modified in various ways.

For example, in the above-described embodiments, modifications, and specific examples, the conductivity type may be reversed. For example, in the description of the above embodiment and modification, p-type may be read as n-type, and n-type may be read as p-type. Even in this case, similar effects can be achieved in the above-described embodiment and modification.

In addition, not all the constituent elements and operations described in the embodiments are essential as the constituent elements and operations of the present disclosure. For example, among the constituent elements of the embodiments, those not recited in any independent claims, which represent the broadest concept of the present disclosure, are considered optional constituent elements.

Terms used throughout this specification and the appended claims should be construed as "open" terms. For example, the term "include" and its grammatical variants are intended to be non-limiting, such that items in a list are not exclusive of other similar items that may be substituted or added to the listed items. The term "having" and grammatical variants thereof are intended to be non-limiting such that items in a list are not exclusive of other similar items that can be substituted or added to the listed items. It will be apparent to those skilled in the art that modifications may be made to the embodiments of the disclosure without departing from the scope of the appended claims.

Note that the terms used herein include terms used only for convenience of description, and do not limit the configuration and operation. For example, the terms "right", "left", "upper" and "lower" merely indicate directions in the drawings to which reference is made. Further, the terms "inner side" and "outer side" respectively denote a direction toward the center of the attention element and a direction away from the center of the attention element. The same applies to the terms similar thereto and to the terms having similar meanings.

Note that the technique according to the present disclosure may also have the following configuration. According to the technique of the present disclosure including the following configuration, the electrical characteristics of the field-effect transistor provided in the second semiconductor substrate can be enhanced, so that the electrical characteristics of the pixel circuit can be enhanced. The effect achieved by the technique according to the present disclosure is not necessarily limited to the effect described herein, and may be any effect described in the present disclosure.

(1) An image forming apparatus comprising:

a first substrate including sensor pixels that perform photoelectric conversion;

a second substrate including a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel; and

a third substrate including a processing circuit that performs signal processing on the pixel signal,

the first substrate, the second substrate and the third substrate are laminated in this order, and

in at least one or more semiconductor layers of a field effect transistor provided with the pixel circuit, a concentration of a conductive type impurity in a region on the first substrate side is higher than a concentration of a conductive type impurity in a region on the third substrate side.

(2) The image forming apparatus according to (1), wherein

The sensor pixel includes a photoelectric conversion element, a transfer transistor electrically connected to the photoelectric conversion element, and a floating diffusion portion temporarily holding a charge output from the photoelectric conversion element via the transfer transistor, and

The pixel circuit includes a reset transistor that resets the potential of the floating diffusion to a predetermined potential, an amplification transistor that generates a voltage signal corresponding to the level of charge held in the floating diffusion as the pixel signal, and a selection transistor that controls the output timing of the pixel signal from the amplification transistor.

(3) The image forming apparatus according to (2), wherein

The first substrate includes a first semiconductor substrate including the photoelectric conversion element, the transfer transistor, and the floating diffusion on a front surface side of the first semiconductor substrate,

the second substrate includes a second semiconductor substrate including the reset transistor, the amplifying transistor, and the selection transistor on a front surface side thereof, and

the second substrate is bonded so that a back surface side facing the front surface of the second semiconductor substrate faces the front surface side of the first semiconductor substrate.

(4) The imaging device according to (3), wherein the back surface of the second semiconductor substrate is bonded to the front surface of the first semiconductor substrate via the insulating layer.

(5) The imaging device according to (4), wherein the interface between the second semiconductor substrate and the insulating layer includes a bonding interface between the first substrate and the second substrate.

(6) The imaging device according to (4) or (5), wherein a first region containing the conductivity type impurity at a higher concentration than other regions of the second semiconductor substrate is provided in a region including an interface between the second semiconductor substrate and the insulating layer.

(7) The imaging device of (6), wherein at least one or more of the field effect transistors of the pixel circuits comprises a fin field effect transistor comprising

A diffusion layer provided so as to protrude from the second semiconductor substrate in such a manner as to extend in one direction,

a gate electrode provided across the diffusion layer so as to extend in a direction orthogonal to the one direction, and

a source region and a drain region provided in the diffusion layer sandwiching both sides of the gate electrode.

(8) The imaging device according to (7), wherein a body contact portion which supplies a predetermined potential to the second semiconductor substrate is provided on a front face of the second semiconductor substrate.

(9) The imaging device according to (8), wherein the body contact portion is provided in a planar region on the same side as the source region with respect to the gate electrode.

(10) The imaging device according to any one of (6) to (9), wherein the first region is provided over an entire surface of the second semiconductor substrate.

(11) The imaging device according to any one of (6) to (10), wherein the first region includes an epitaxially grown layer containing boron atoms as the conductivity-type impurity.

(12) The imaging device according to any one of (6) to (11), wherein the first region includes a polycrystalline silicon layer containing boron atoms as the conductivity type impurity.

(13) The imaging device according to any one of (6) to (12), wherein a second region which is electrically connected to the contact plug which supplies a predetermined potential and contains the conductive type impurity at a high concentration is further provided in a part of the region on the front face side of the second semiconductor substrate.

(14) The imaging device according to (13), wherein a third region containing the conductivity type impurity at a lower concentration than the first region and the second region and being adjacent to the first region and the second region is further provided in the second semiconductor substrate.

(15) The imaging device according to (13), wherein the contact plug is provided to penetrate the second semiconductor substrate and directly connected to the first region.

(16) The imaging device according to any one of (6) to (15), wherein the first region contains a boron atom as the conductivity type impurity, and further contains a carbon atom as a non-conductivity type impurity.

(17) The image forming apparatus according to any one of (2) to (16), wherein

The first substrate includes the photoelectric conversion element, the transfer transistor, and the floating diffusion for each sensor pixel, an

The second substrate includes the pixel circuit for each sensor pixel.

(18) The image forming apparatus according to any one of (2) to (16), wherein

The first substrate includes the photoelectric conversion element, the transfer transistor, and the floating diffusion for each sensor pixel, an

The second substrate includes the pixel circuit for each of the plurality of sensor pixels.

(19) The image forming apparatus according to any one of (2) to (16), wherein

The first substrate includes the photoelectric conversion element and the transfer transistor for each sensor pixel, and includes the floating diffusion shared by each of the plurality of sensor pixels, an

The second substrate includes the pixel circuit for each of a plurality of sensor pixels sharing the floating diffusion.

(20) The imaging device according to any one of (1) to (19), wherein the third substrate includes a third semiconductor substrate provided with the processing circuit on a front surface side.

This application claims the benefit of a prior japanese patent application JP2019-118489, filed on 26.6.2019 with the sun in the office, the entire contents of which are incorporated herein by reference.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may be made according to design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.