阅读说明：本技术 数模转换器(dac)和模数转换器(adc)的线性化和相关方法 (Linearization and related methods for digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) ) 是由 T·于 A·玛迪塞提 于 2020-03-14 设计创作，主要内容包括：本实施例引入了使用非理想组件设计完美线性DAC的方法。该方法可以消除DAC的非线性并去除性能和复杂性之间的传统权衡。一个实施例包括接收输入数字信号,将输入数字信号分段成多个段,每个段被温度计编码,生成多个段中的每个段的冗余表示,定义多个冗余段,执行多个段的冗余映射,定义冗余映射段,为冗余映射段分配概率分配,由子数模转换器(DAC)将每个冗余映射段转换为模拟信号,以及组合模拟信号以定义输出模拟信号。(This embodiment introduces a method of designing a perfectly linear DAC using non-ideal components. This approach may eliminate the non-linearity of the DAC and remove the traditional trade-off between performance and complexity. One embodiment includes receiving an input digital signal, segmenting the input digital signal into a plurality of segments, each segment being thermometer coded, generating a redundant representation of each of the plurality of segments, defining a plurality of redundant segments, performing a redundant mapping of the plurality of segments, defining a redundant mapped segment, assigning a probability assignment to the redundant mapped segment, converting each redundant mapped segment to an analog signal by a sub-digital-to-analog converter (DAC), and combining the analog signals to define an output analog signal.)

1. A method for linearizing digital to analog conversion, comprising:

receiving an input digital signal;

segmenting the input digital signal into a plurality of segments, each segment being thermometer encoded;

generating a redundant representation of each segment of the plurality of segments, defining a plurality of redundant segments;

performing redundancy mapping on the plurality of segments, defining redundancy mapping segments;

distributing probability distribution for the redundant mapping sections;

converting each redundancy mapping segment into an analog signal by a sub-digital-to-analog converter (DAC); and

the analog signals are combined to define an output analog signal.

2. The method of claim 1, wherein performing the redundancy mapping comprises sequentially performing a recursive redundancy mapping on segment pairs for each of the plurality of segments and the plurality of redundant segments.

3. The method of claim 1, wherein:

the plurality of segments comprises m segments, and the first segment x₁Second section x₂To the m-th section x_mIs equal to the input digital signal, as shown in the following equation

Wherein N is_iCan be and segment x_iThe number of elements activated by the associated sub-DAC;

the redundant mapping of the input digital signal comprises m segments, a first segment v₁Second section v₂To the m-th section v_mIs equal to the input digital signal, as shown in the following equation

Such that at least one segment x_iIs not equal to the mapping v_iWherein i has an integer value between 1 and m.

4. The method of claim 1, wherein the plurality of segments comprises m segments, the first segment x₁Second section x₂To the m-th section x_mIs equal to the outputInputting a digital signal; and wherein performing the recursive redundant mapping comprises:

computing a first segment pair (x)_m，x_m-1) Redundant mapping of (x'_m，x′_m-1)；

According to x_mAnd x'_mDetermining the mth segment v_mA final value of;

according to x_m-1And x'_m-1Determining the median value u_m-1；

Calculate middle segment pair (u)_m-1，x_m-2) Redundant mapping of (u'_m-1，x′_m-2)；

According to u_m-1And u'_m-1Determining the (m-1) th segment v_m-1Final value of, and according to x_m-2And x'_m-2Determining the median value u_m-2(ii) a And

recursively computing a redundant mapping of pairs of intermediate segments and intermediate values thereof up to x_m-n＝x₁。

5. The method of claim 4, wherein x_(k，m)Is determined by the segments k to m and is defined by

Wherein N is_kCan be and segment x_kThe number of elements activated by the associated sub-DAC; wherein the redundant mapping is recursively computed from the last segment x_mTo the first segment x₁Sequentially on pairs of (a); wherein segments m-1 to m are defined as

Wherein (u)_m-1，v_m) Is defined as

Wherein x'_m-1Is defined as

x′_m-1＝x_m-1+δx_m-1·sgn(x_m)

Wherein x'_mIs defined as

x′_m＝x_m-N_m·δx_m-1·sgn(x_m)

Wherein N is_mCan be and segment x_mNumber of elements of associated sub-DAC activation, further, p'_m-1And p_m-1Is defined as

Wherein segments k-1 to k are defined as

Wherein (u)_k-1，v_k) Is defined as

Wherein x'_k-1Is defined as

x′_k-1＝x_k-1+δx_k-1·sgn(x_k，m)

Wherein u'_kIs defined as

u′_k＝u_k-N_k·δx_k-1·sgn(x_k，m)

Wherein N is_kCan be and section u_kNumber of elements of associated sub-DAC activation, further, p'_k-1And p_k-1Is defined as

Wherein when k-2 and v₁＝u₁The redundancy mapping is completed.

6. The method of claim 4, wherein the resolution of each sub-DAC associated with the middle segment pair is one bit greater than the resolution of the sub-DACs of the first segment pair.

7. The method of claim 1, wherein each segment x of the plurality of segments_nIs in the range defined by

x_n∈[-N_n+2：2：N_n-2]

Wherein N is_nCan be and segment x_nThe number of elements activated by the associated sub-DAC;

middle section x_nRedundant representation of x'_nHas a value within a range defined by

x′_n∈[-N_n+1：2：n-1]

Middle section x_nIs mapped x_pHas a value within a range defined by

x_p∈[-N_p+1：2：N_p-1]；

And

wherein redundant segment x'_nOf x'_pHas a value within a range defined by

x′_p∈[-2N_p+1：2：-N_p-1]∪[N_p+1：2：2N_p-1]。

8. The method of claim 1, wherein the plurality of segments comprises B segments, the first segment x₁Second section x₂To the B-th section x_BIs equal to the input digital signal; wherein each segment comprises three elements that can be activated for each sub-DAC; wherein each segment has a value of one of-3, -1, or 3; and wherein performing the recursive redundant mapping comprises:

computing a first segment pair (x)_B，x_B-1) Redundant mapping of (x'_B，x′_B-1)；

According to x_BAnd x'_BDetermining the B segment v_BA final value of;

according to x_B-1And x'_B-1Determining the median value u_B-1；

Calculate middle segment pair (u)_B-1，x_B-2) Redundant mapping of (u'_B-1，x′_B-2)；

According to u_B-1And u'_B-1Determination of the (B-1) th segment v_B-1Final value of, and according to x_B-2And x'_B-2Determining the median value u_B-2(ii) a And

recursively computing a redundant mapping of pairs of intermediate segments and intermediate values thereof up to x_B-n＝x₁。

9. The method of claim 8, wherein variable x_(k，m)Determined by segments k through B and defined by

Wherein N is_kCan be and segment x_kThe number of elements activated by the associated sub-DAC; wherein the redundant mapping is recursively computed from the last segment x_BTo the first segment x₁Sequentially on pairs of (a); wherein segments B-1 to B are defined as

(x_B-1，x_B)→(u_B-1，v_B)

Wherein (u)_B-1，v_B) Is defined as

Wherein x'_B-1Is defined as

x′_B-1＝x_B-1+2·sgn(x_B)

Wherein x'_BIs defined as

x′_B＝x_B-4·sgn(x_B)

Wherein p'_B-1And p_B-1Is defined as

Wherein segments k-1 to k are defined as

Wherein (u)_k-1，v_k) Is defined as

Wherein x'_k-1Is defined as

x′_k-1＝x_k-1+2·sgn(u_k+v_k+1，B)

Wherein u'_kIs defined as

u′_k＝u_k-4·sgn(u_k+v_k+1，B)

Wherein p'_k-1And p_k-1Is defined as

Wherein when k is 2 and v_k-1＝u_k-1The redundancy mapping is completed.

10. The method of claim 1, wherein the plurality of segments comprises m segments, wherein each segment of the plurality of segments comprises a plurality of bits B; middle section x_nB of (A)_nLog of (a)₂N_nLowest level ofSignificant bit and segment x_n-1B of (A)_n-1Log of (a)₂N_n-1Most significant bit overlap, where N can be equal to segment x_nThe number of elements activated by the associated sub-DAC; and wherein performing the recursive redundant mapping comprises:

computing a first segment pair (x)_m，x_m-1) Redundant mapping of (x'_m，x′_m-1)；

According to x_mAnd x'_mDetermining the mth segment v_mA final value of;

according to x_m-1And x'_m-1Determining the median value u_m-1；

Calculate middle segment pair (u)_m-1，x_m-2) Redundant mapping of (u'_m-1，x′_m-2)；

According to u_m-1And u'_m-1Determining the (m-1) th segment v_m-1Final value of, and according to x_m-2And x'_m-2Determining the median value u_m-2(ii) a And

recursively computing a redundant mapping of pairs of intermediate segments and intermediate values thereof up to x_m-n＝x₁。

11. The method of claim 1, wherein the number of elements that can be activated for the sub-DAC associated with the redundancy map segment and the next segment x are based on the absolute value of the redundancy map segment_n-1To determine a redundant mapped segment x_nProbability distribution.

12. The method of claim 11, wherein the probability function is defined as

Wherein p'_m-1Is redundant representation x'_m-1Probability distribution of redundant mapping of (1), p_m-1Is segment x_m-1Is mapped to a redundancy, and N_mCan be of the formula_mAssociated sub-DAC laserNumber of living elements.

13. A system for linearizing analog-to-digital conversion, comprising:

a comparator positioned to receive the analog signal as a first input;

a successive approximation register positioned to receive the output of the comparator as an input and configured to generate an output comprising B bits; and

a digital-to-analog converter (DAC) configured to:

receiving an input digital signal;

segmenting the input digital signal into a plurality of segments, each segment being thermometer encoded;

generating a redundant representation of each segment of the plurality of segments, defining a plurality of redundant segments;

performing redundancy mapping on the plurality of segments, defining redundancy mapping segments;

distributing probability distribution for the redundant mapping segment;

converting each redundant mapping segment into an analog signal by a sub-digital-to-analog converter; and

combining the analog signals to define an output analog signal,

wherein the comparator is configured to receive the combined analog signal as a second input.

14. The system of claim 13, wherein performing the redundancy mapping comprises sequentially performing a recursive redundancy mapping on segment pairs for each of the plurality of segments and the plurality of redundant segments.

15. The system of claim 13, wherein:

the plurality of segments comprises m segments, a first segment x₁Second section x₂To the m-th section x_mIs equal to the input digital signal, as shown in the following equation

Wherein N is_iCan be and segment x_iThe number of elements activated by the associated sub-DAC;

the redundant mapping of the input digital signal comprises m segments, a first segment v₁Second section v₂To the m-th section v_mIs equal to the input digital signal, as shown in the following equation

Such that at least one segment x_iIs not equal to the mapping v_iWherein i has an integer value between 1 and m.

16. The system of claim 13, wherein the plurality of segments comprises m segments, a first segment x₁Second section x₂To the m-th section x_mIs equal to the input digital signal; and wherein performing the recursive redundant mapping comprises:

computing a first segment pair (x)_m，x_m-1) Redundant mapping of (x'_m，x′_m-1)；

According to x_mAnd x'_mDetermining the mth segment v_mA final value of;

according to x_m-1And x'_m-1Determining the median value u_m-1；

Calculate middle segment pair (u)_m-1，x_m-2) Redundant mapping of (u'_m-1，x′_m-2)；

According to u_m-1And u'_m-1Determining the (m-1) th segment v_m-1Final value of, and according to x_m-2And x'_m-2Determining the median value u_m-2(ii) a And

recursively computing a redundant mapping of pairs of intermediate segments and intermediate values thereof up to x_m-n＝x₁。

17. The system of claim 16, wherein the first and second sensors are arranged in a single unit,wherein x_(k，m)Is determined by the segments k to m and is defined by

Wherein N is_kCan be and segment x_kThe number of elements activated by the associated sub-DAC; wherein the redundant mapping is recursively computed from the last segment x_mTo the first segment x₁Sequentially on pairs of (a); wherein segments m-1 to m are defined as

Wherein (u)_m-1，v_m) Is defined as

Wherein x'_m-1Is defined as

x′_m-1＝x_m-1+δx_m-1·sgn(x_m)

Wherein x'_mIs defined as

x′_m＝x_m-N_m·δx_m-1·sgn(x_m)

Wherein N is_mCan be and segment x_mNumber of elements of associated sub-DAC activation, further, p'_m-1And p_m-1Is defined as

Wherein segments k-1 to k are defined as

Wherein (u)_k-1，v_k) Is defined as

Wherein x'_k-1Is defined as

x′_k-1＝x_k-1+δx_k-1·sgn(x_k，m)

Wherein u'_kIs defined as

u′_k＝u_k-N_k·δx_k-1·sgn(x_k，m)

Wherein N is_kCan be and section u_kNumber of elements of associated sub-DAC activation, further, p'_k-1And p_k-1Is defined as

Wherein when k-2 and v₁＝u₁The redundancy mapping is completed.

18. The system of claim 13, wherein each segment x of the plurality of segments_nIs in the range defined by

x_n∈[-N_n+2：2：N_n-2]

Wherein N is_nCan be and segment x_nThe number of elements activated by the associated sub-DAC;

middle section x_nRedundant representation of x'_nHas a value within a range defined by

x′_n∈[-N_n+1：2：n-1]

Middle section x_nIs mapped x_pHas a value within a range defined by

x_p∈[-N_p+1：2：N_p-1]；

And

wherein redundant segment x'_nOf x'_pHas a value within a range defined by

x′_p∈[-2N_p+1：2：-N_p-1]∪[N_p+1：2：2N_p-1]。

19. The system of claim 13, wherein the plurality of segments comprises B segments, a first segment x₁Second section x₂To the B-th section x_BIs equal to the input digital signal; wherein each segment comprises three elements that can be activated for each sub-DAC; wherein each segment has a value of one of-3, -1, or 3; and wherein performing the recursive redundant mapping comprises:

computing a first segment pair (x)_B，x_B-1) Redundant mapping of (x'_B，x′_B-1)；

According to x_BAnd x'_BDetermining the B segment v_BA final value of;

according to x_B-1And x'_B-1Determining the median value u_B-1；

Calculate middle segment pair (u)_B-1，x_B-2) Redundant mapping of (u'_B-1，x′_B-2)；

According to u_B-1And u'_B-1Determination of the (B-1) th segment v_B-1Final value of, and according to x_B-2And x'_B-2Determining the median value u_B-2(ii) a And

recursively computing a redundant mapping of pairs of intermediate segments and intermediate values thereof up to x_B-n＝x₁。

20. The system of claim 19, wherein the variable x_(k，m)Determined by segments k through B and defined by

Wherein N is_kIs to be able toCan be equal to segment x_kThe number of elements activated by the associated sub-DAC; wherein the redundant mapping is recursively computed from the last segment x_BTo the first segment x₁Sequentially on pairs of (a); wherein segments B-1 to B are defined as

(x_B-1，x_B)→(u_B-1，v_B)

Wherein (u)_B-1，v_B) Is defined as

Wherein x'_B-1Is defined as

x′_B-1＝x_B-1+2·sgn(x_B)

Wherein x'_BIs defined as

x′_B＝x_B-4·sgn(x_B)

Wherein p'_B-1And p_B-1Is defined as

Wherein segments k-1 to k are defined as

Wherein (u)_k-1，v_k) Is defined as

Wherein x'_k-1Is defined as

x′_k-1＝x_k-1+2·sgn(u_k+v_k+1，B)

Wherein u'_kIs defined as

u′_k＝u_k-4·sgn(u_k+v_k+1，B)

Wherein p'_k-1And p_k-1Is defined as

Wherein when k is 2 and v_k-1＝u_k-1The redundancy mapping is completed.

Technical Field

The present invention relates to systems and methods for processing and storing digital information.

Background

Modern electronic systems digitally process and store information. However, due to the analog nature of the world, conversion between the analog and digital domains is always required and performed by data converters. Analog-to-digital converters (ADCs) are used to convert analog signals (voltage, current, etc.) into digital code words. On the other hand, digital-to-analog converters (DACs) are used to convert digital codewords into analog signals (voltages, currents, etc.).

A DAC is a device that converts high-precision digital format numbers (usually finite length binary format numbers) into analog electrical quantities such as voltages, currents or charges. To construct an analog signal, there are two basic types of DAC output formats: non-return-to-zero (NRZ) and return-to-zero (RZ). As shown in fig. 1, for NRZ, the DAC updates its analog output and holds the output according to its digital input at fixed time intervals of Ts, where Ts is referred to as the update and sampling period. For RZ, after updating the output at each time interval Ts, the DAC only holds the output for a certain time (Th) and then returns to zero. In both cases, the output of the DAC is held for a certain time Th, where 0< Th < ═ Ts, called zero order hold. The output of the DAC is typically a stepped or pulsed analog signal and may be low pass filtered to construct the desired analog signal, as shown in fig. 1.

The deviation of the actual DAC output f (x) from the ideal DAC output may be characterized by the following metrics, for example: 1) offset and gain errors; 2) differential Nonlinearity (DNL); 3) integral Nonlinearity (INL); 4) spurious Free Dynamic Range (SFDR); and 5) Signal-to-noise ratio (SNR).

The offset error of a DAC is defined as the deviation of the linearized transfer curve of the DAC output from the ideal zero. The linearized transfer curve is based on the actual DAC output, a simple min max line connecting the min and max DAC output values or a best fit line of all the output values of the DAC. Since offset and gain errors do not introduce non-linearity, they have no impact on the spectral performance of the DAC.

Differential Nonlinearity (DNL) is defined as the deviation of the actual step size from the ideal step size (LSB) between any two adjacent digital output codes, called its ideal size (1 LSB). Thus, DNL results in unequal steps in the transfer function. The integral non-linearity (INL) is defined as the deviation of the actual DAC output from the linearized transfer curve of each code, as shown in fig. 2. INL is also described as the accumulation of previous DNL errors. To ensure monotonicity, the conditions DNL <0.5LSB and INL <1LSB need to be satisfied.

Spurious Free Dynamic Range (SFDR) is a measure of the nonlinearity of the DAC and is the ratio of the single tone that generates the highest unwanted component in the nyquist band. SFDR is typically expressed in decibels (dB).

The signal-to-noise ratio (SNR) is defined as the ratio of the power of the measured output signal to the integrated power of the noise floor in the nyquist band ([0, sample frequency/2 ], except DC and harmonics). The value of SNR is also typically expressed in decibels (dB).

Mismatches in analog circuitry have an effect. Thermal noise, quantization noise, mismatch and non-linearity are major contributors to analog circuit inaccuracy and impose minimum requirements on device area and power. Thermal noise is white and may benefit from averaging. Similarly, well-designed quantizers have white quantization noise. Quantization noise also benefits from averaging and oversampling. Both thermal noise and quantization noise are expressed in dBc/Hz, which is a measure of how the noise power is spectrally distributed over the nyquist bandwidth. For narrow-band systems, the thermal noise and quantization noise integrated over the receiver bandwidth are directly related to the receiver SNR. In general, the sources of non-linearity are input buffers, amplifiers, and output drivers, whose linearity can be modeled as a lower order smooth polynomial function. Spurs caused by the smooth polynomial approximation result in predictable harmonics at multiples of the fundamental frequency. Their impact in narrow band systems can be mitigated by appropriate frequency planning.

Mismatch is a phenomenon in which devices (resistors, capacitors, MOS transistors) of the same design are not identical. The difference in threshold voltages Δ VT and the difference in current factors Δ β are the main sources of device mismatch. Both Δ VT and Δ β are unknown during design, but are fixed (and still unknown) after fabrication. Anecdotal evidence and extensive measurement data suggest that mismatches generally improve as device area increases. Thus, increasing the area four times will reduce the 1-bit mismatch. However, it may be impractical to adjust the size of the current source transistors to match over 14 bits and result in large parasitic capacitances.

The non-linearity is mainly caused by mismatches, which may be random, systematic or a combination of both. Mismatches may be caused by wafer-to-wafer variations, within-chip variations, or device-to-device variations. The mismatch may be systematic (following a gradient) or completely random. Although systematic mismatches can generally be mitigated with the choice of layout method and circuit architecture, random mismatches due to the random nature of the physical geometry and doping cannot be avoided. In addition, the current source is strongly temperature dependent, which greatly exacerbates the problem. Random mismatch results in predictably unpredictable performance.

In analog circuits, receiver sensitivity is defined as the minimum signal that can be processed correctly in the presence of noise. The device needs to be dimensioned to meet the RX sensitivity specification. Increasing the size can negatively impact speed and power due to the larger capacitance. For a given bandwidth and accuracy, the limit on minimum power consumption imposed by device matching is about two orders of magnitude greater than the limit imposed by noise of deep sub-micron CMOS processes. It is therefore a device mismatch that sets a limit on the minimum analog signal that can be processed, rather than thermal noise.

This background information is provided to reveal information believed by the applicant to be of relevance to the present invention. It is not necessary, nor should it be construed, that any of the preceding information constitutes prior art against the present invention.

Drawings

Fig. 1 is a graph of typical DAC outputs (step-wise NRZ and RZ) and a graph resulting from the application of a low pass filter as known in the art.

Fig. 2 is a graph of differential nonlinearity and integral nonlinearity compared to an ideal transfer function as known in the art.

Fig. 3 is a diagram of a 3-bit binary DAC as known in the art.

Fig. 4 is a 3-bit thermometer DAC including a 7-unit element according to an embodiment of the invention.

Fig. 5A is a two-section 6-bit DAC with a 3-bit thermometer most significant bit and a 3-bit binary least significant bit.

Fig. 5B is a graph of the transfer function of the DAC of fig. 5A.

Fig. 6 is an output spectrum of a nyquist DAC with a single-tone sine wave input according to an embodiment of the present invention.

FIG. 7 is an architecture of a single-ended 4-bit thermometer coded DAC according to an embodiment of the present invention.

Fig. 8 is a differential DAC architecture for a complementary output DAC of the architecture of fig. 7, according to an embodiment of the invention.

Fig. 9 is a plot of a plurality of analog output values of a DAC according to an embodiment of the invention.

FIG. 10 is a schematic diagram of a 4-bit thermometer DEM DAC according to an embodiment of the present invention.

Fig. 11 is a graph of an ideal transfer function and a linearized DEM DAC, according to an embodiment of the present invention.

Fig. 12 is a graph demonstrating a higher resolution DAC achieved by combining the outputs of several smaller sub-DACs according to an embodiment of the present invention.

Fig. 13 is a schematic diagram of an implementation of a multi-segment DAC according to an embodiment of the invention.

Fig. 14 is a graph of a DAC transfer function with a normal mapping according to an embodiment of the invention.

Fig. 15 is a graph of a DAC transfer function with redundant mapping according to an embodiment of the invention.

Fig. 16 is a graph of probability assignments between DAC transfer functions and respective normal and redundant maps according to an embodiment of the invention.

Fig. 17 is a schematic diagram of an implementation of a two-segment DAC with redundancy and probability mapping, according to an embodiment of the invention.

FIG. 18 is a schematic diagram of an implementation of 4-segment linearization with sequential pairwise operation according to an embodiment of the invention.

FIG. 19 is an architecture of a B-bit successive approximation register ADC according to an embodiment of the present invention.

FIG. 20 is a representation of the generation of SAR register values in a 4-bit SAR time trellis diagram from DAC voltages according to an embodiment of the invention.

Detailed Description

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Those of ordinary skill in the art realize that the following description of the embodiments of the present invention is illustrative and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. Like numbers refer to like elements throughout.

Before the present disclosure is described in detail, it is to be understood that this disclosure is not limited to the particular illustrated parameters of systems, methods, apparatus, products, processes, and/or kits, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments of the disclosure only, and is not necessarily intended to limit the scope of the disclosure in any particular manner. Thus, although the present disclosure will be described in detail with reference to particular embodiments, features, aspects, configurations, etc., the description is illustrative and should not be construed as limiting the scope of the claimed invention. Various modifications may be made to the illustrated embodiments, features, aspects, configurations, etc. without departing from the spirit and scope of the invention as defined by the claims. Thus, while various aspects and embodiments have been disclosed herein, other aspects and embodiments are contemplated.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this technology belongs. Although many methods and materials similar or equivalent to those described herein can be used in the practice of the present disclosure, only certain exemplary materials and methods are described herein.

Various aspects of the disclosure, including apparatus, systems, methods, etc., may be described with reference to one or more exemplary embodiments or implementations. As used herein, the terms "embodiment," "alternative embodiment," and/or "exemplary implementation" mean "serving as an example, instance, or illustration," and are not necessarily to be construed as preferred or advantageous over other embodiments or implementations disclosed herein. In addition, references to "an implementation" of the present disclosure or invention include specific references to one or more embodiments thereof, and vice versa, and are intended to provide illustrative examples without limiting the scope of the invention, which is indicated by the appended claims rather than the following description.

It should be noted that, as used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. Thus, for example, reference to "a sensor" includes one, two or more sensors.

As used throughout this application, the words "may" and "may" are used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Also, as used herein, the terms "comprises," comprising, "" has, "" involves, "" including, "" characterized by, "" variants thereof (e.g., "comprising," "having," "involving," "including," etc.) and similar terms, including the claims, are intended to be inclusive and/or open-ended, should have the same meaning as the word "comprising" and variants thereof (e.g., "comprises" and "comprising"), and illustratively do not exclude additional unrecited elements or method steps.

Various aspects of the present disclosure may be illustrated by describing components coupled, attached, connected, and/or joined together. As used herein, the terms "coupled," "attached," "connected," and/or "coupled" are used to indicate either a direct connection between two components or an indirect connection to each other through intervening or intermediate components, where appropriate. In contrast, when an element is referred to as being "directly coupled," "directly attached," "directly connected," and/or "directly joined" to another element, there are no intervening elements present or contemplated. Thus, as used herein, the terms "connected," "connected," and the like do not necessarily mean direct contact between two or more elements. In addition, components that are coupled, attached, connected, and/or joined together are not necessarily (reversibly or permanently) secured to one another. For example, coupling, attaching, connecting, and/or joining may include placing, positioning, and/or arranging components together or otherwise adjacent in some implementations.

As used herein, directions and/or any terms such as "top," "bottom," "front," "back," "left," "right," "upper," "lower," "inner," "outer," "proximal," "distal," and the like may be used solely to indicate relative direction and/or orientation, and may not be intended to otherwise limit the scope of the disclosure, including the description, invention, and/or claims.

Where possible, like numbering of elements is used in the various figures. Additionally, similar elements and/or elements having similar functionality may be designated by similar numbers. Further, alternative configurations of specific elements may each include a separate letter appended to the element number. Accordingly, the accompanying letters may be used to designate alternative designs, structures, functions, implementations and/or embodiments of elements or features that are not the accompanying letters. Similarly, multiple instances of a sub-element of an element and a parent element may each include a separate letter appended to the element number. In each case, the element numbers may be used to refer collectively to the elements or to any one instance of an alternate element without the accompanying letter. Element numbers including accompanying letters may be used to refer to particular instances of elements or to distinguish or note multiple uses of elements. However, element designations including the accompanying letters are not meant to be limiting to illustrate specific and/or particular embodiment(s) thereof. In other words, references to specific features of an embodiment should not be construed as limited to application within that embodiment.

It should also be understood that where a range of values is disclosed or recited (e.g., less than, greater than, at least, and/or up to a certain value and/or between two recited values), any particular value or range of values that falls within the disclosed range of values is also disclosed and contemplated herein.

It should also be noted that systems, methods, apparatus, devices, products, processes, compositions, and/or kits, and the like, according to certain embodiments of the present invention may include, incorporate, or otherwise include the properties, features, aspects, steps, components, means, and/or elements described in other embodiments disclosed and/or described herein. Thus, references to particular features, aspects, steps, components, members, elements, etc. of an embodiment should not be construed as limited to application within that embodiment. Furthermore, references to specific benefits, advantages, problems, solutions to problems, methods of use, etc., for one embodiment should not be construed as limited to application within that embodiment.

The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description or the claims. To facilitate understanding, similar reference numerals have been used, where possible, to designate similar elements that are common to the figures.

A typical 4-bit binary DAC architecture will be described with reference to fig. 3. In a binary architecture, each binary input bit corresponds to a binary weighted element (voltage, current, or charge). The advantage of the binary architecture is its simplicity and low implementation cost. However, a large ratio between the least important and the most important elements may result in a large mismatch between them. This results in large DNL and INL errors. One way to improve non-linearity in a binary DAC architecture is to reduce the mismatch of the unit cells.

To overcome the disadvantages of binary DAC architectures, thermometer coded DAC architectures have been developed. A B-bit thermometer coded DAC has 2B-1 unit elements. For example, a 3-bit thermometer DAC with 7-unit elements is shown in fig. 4. These unit cells are turned on or off in a sequence according to an input number code. The thermometer coded architecture reduces INL/DNL at the cost of a significant increase in implementation cost compared to the binary coded architecture.

In the segmented architecture, an input digital code is divided into a plurality of segments, and each segment is converted to an analog signal with a sub-DAC. The segments are scaled and combined to create an overall transfer function. The transfer function of a 2-segment DAC (e.g., the 6-bit DAC of FIG. 5A) is shown in FIG. 5B. The segmented architecture balances the advantages and disadvantages of the LSB binary segment and the thermometer MSB segment and is the most widely used architecture in DAC design. The unit element may be a current source, a capacitor or a resistor or a combination.

The output spectrum of a nyquist DAC with a single-tone sine wave input is shown in fig. 6. As shown in the drawing, harmonics are present at integer multiples of the fundamental frequency and at myriad other frequency components due to the non-linearity of the DAC (INL and DNL). The magnitude and location of the DNL spurs are unpredictable and depend on the input magnitude and frequency. Thus, non-linearity may be a key performance metric for DAC designs.

Over the past several decades, much research has been devoted to improving the nonlinear performance of DACs. It is well known that unit cell mismatch leads to unequal step sizes (DNL) of the DAC transfer function and to spurs in the output spectrum. Dynamic Element Matching (DEM) is a well-known and widely used technique for linearizing thermometer DACs and eliminating DNLs in the presence of mismatch.

For DEM, thermometer code T_1：NRepresenting a natural number w, w 1 s followed by N-w zeros. The thermometer coded DAC may include or, in some embodiments, be comprised of N identical unit elements U_1：NWhich may be turned on (activated) or off (deactivated) by N thermometer codes representing the digital input word x. In the unsigned representation x-w and in the signed representation x-2 w-N. An example of a thermometer representation of a 3-bit natural number is shown in table 1. The outputs of the N unit elements are combined together in a DAC output network.

Table 1: 3-bit thermometer code representation

For a thermometer code with weight w, the w unit elements are turned on or off by the thermometer code representing an input x ═ w. The minimum output occurs when all unit elements are turned off, and the maximum output value occurs when all unit elements are turned on. In general, the unit cells will not be the same and may be represented as U_k＝U+ΔU_k＝U(1+∈_k) Where U is the nominal value, Δ U_kIs a deviation from a nominal value and e_kIs the relative mismatch Δ U_k/U。

In a single-ended DAC, each thermometer code represents either a '1' or a '0', and each unit cell is switched to either a load resistor or ground, as shown in fig. 7. In the ideal case, all unit cells are identical and U is the same for all k, U_kU. In the absence of mismatch, the single ended output is given by:

the input-output transfer function is a linear function.

For the complementary output DAC shown in fig. 8, each thermometer code represents a '1' when activated or a '-1' when deactivated, and the corresponding unit element is switched to a positive or negative load resistor. The complementary output is given by:

in the ideal case, the complementary output is also a linear function of the input.

In DEM, different thermometer codes with the same weight w are used to represent successive occurrences of the same input in a random manner. In other words, a different set of w elementsActivated on consecutive occurrences of the same numeric input code. As shown in fig. 9, like numeralsThe input may have multiple analog output values because there are (N) ways to activate w elements of the N elements. Scrambling ensures that the permutation is uniformly selected in a random manner. The overall average output of the arrangement approximates and resembles a perfectly linear DAC. DEM linearizes the average transfer function by decorrelating errors in the DAC output and input. The average transfer function determines the spurs in the output spectrum. Although DEM results in a slight drop in SNR, the improvement in SFDR can be very significant.

A 4-bit DEM DAC is shown in fig. 10. 4-bit digital code is converted to 15-bit thermometer code T_1∶15. The number of elements activated by the thermometer bits is proportional to the input digital code. The thermometer code is scrambled (permutation operation) which randomizes the position of the active elements, but keeps the number of active elements unchanged. The scrambled thermometer code activates and deactivates the corresponding unit element. The unit elements are combined in a DAC output network to create an output.

The average transfer function of the DEM DAC will be described. Simple combinatorial analysis showed thatOne method activates w elements of the N elements. By first calculating the probability P of activating a bit at the kth position_w(T_k1) and probability P of deactivating the bit of the k-th position_w(T_k0) to find the expected value that is output when the w unit elements are activated. For thermometer code with weight w, there areOne method activates the element at the kth position. Since w elements always need to be activated, this is equivalent to activating the additional w-1 elements of the remaining N-1 potential locations once the kth location is activated. Similarly, there areA method deactivates an element at a kth position of a thermometer code. This amounts to activating w elements of N-1 potential locations after deactivating the kth location. Thus, the probability of activating or deactivating the kth bit can be calculated as:

and

the output of the DAC is given by:

by findingThe expected, average complementary output of the values is:

from equation (1)&(2) Substitution probability P_w(T_k1) and P_w(T_k0) (found below) and note U_k＝U(1+∈_k) To account for unit cell mismatch, thus obtaining:

wherein

Or

Here, α is the average mismatch of the unit elements and the mismatch profile is constant for a given unit element. The average output of the DEM DAC is linearly proportional to its input x-2 w-N. The scaling factor of (1+ α) is the gain error when compared to the output of an ideal DAC. The ideal and DEM transfer functions for a 3-bit DAC are shown in fig. 11. Since it is a linear system, the error is also proportional to the input. It is assumed without loss of generality that the unit element U is 1.

A fully thermometer coded DAC with DEM is always linear. B-bit thermometer DAC requires 2^B1 unit cell. The cost and power of a fully thermometer coded DAC grows exponentially with the number of bits. Therefore, a full thermometer implementation rarely uses more than 8 bits. In a segmented DAC, a B-bit input digital word x is decomposed to have bits B₁，B₂，...，B_mM segments x of₁，x₂，...，x_mSo that B is B₁+B₂+…+B_m. The first sub-DAC processes the first B₁Bit, second sub-DAC processes the next B₂Bits, and the mth sub-DAC processes the last B_mA bit. The segmented DAC need only beA unit cell. Thus, segmentation may result in a significant reduction in complexity. A higher resolution DAC is achieved by combining the outputs of several smaller sub-DACs as shown in fig. 12.

The B-bit digital input x is associated with the m-segment input as a binary weighted sum:

wherein the content of the first and second substances,and the output of the DAC is a weighted combination of the outputs of the m sub-DACs:

when there is no mismatch, the output of each sub-DAC is equal to its input, anThe output of an ideal DAC is equal to its B-bit digital input x:

in case of non-ideal implementation, each sub-DAC employs DEM for linearization. The average output of the ith sub-DAC is represented by y_i＝x_i·(1+α_i) Is given by_iIs the average mismatch of the unit elements in the ith sub-DAC. The output of the DAC is given by:

due to alpha of each segment_iIn contrast, the error term ε is not linearly dependent on the input x, that is, ε is true for any k_xNot equal kx, therefore, the output is not a linear function of x.

In the presence of mismatch, combining the outputs of the sub-DACs after segmentation re-introduces non-linearity into the transfer function. Even if the individual thermometer segments are linearized by DEM, the output of the combined linear sub-DAC will not be linear. Thus, for higher resolution DACs, the segmented architecture is a compromise that balances accuracy, speed, cost and power at the expense of non-linearity.

The output of the DAC can also be written as:

each segment is scaled and combined with the segment preceding it. Therefore, it is useful to analyze the performance of a two-stage DAC in the presence of mismatch. The results can be extended to multiple segments by the nested nature of the calculations in equation (6).

In a two-stage DAC, the most significant B₁The bit is associated with the first segment and the remaining least significant B₂A bit is associated with the second segment. In the case of mismatch, the output of the linearized sub-DAC is represented by y₁＝x₁(1+β₁) And y₂＝x₂(1+β₂) Given, where β s represents the average unit cell mismatch in each segment. N'₂＝N₂(1+γ₂) Is a mismatched scaling factor, where gamma₂Representing the deviation from the ideal power-of-2 value. The output of the DAC can be written as:

wherein alpha is₂Is a parameter that integrates the effects of all mismatches. (1+ beta)₁) Is a gain factor that changes the full scale of the DAC but does not affect the linearity of the DAC. The transfer function of the two-stage DAC is shown in fig. 13.

The problem with segmenting the bits into sub-DACs is a design tradeoff between complexity and performance. While a perfectly linear DAC may be achieved by using only one segment and DEM, it may be impractical for a high resolution DAC. More bits in the DEM thermometer MSB sub-DAC improve linearity but also increase complexity. Due to intersegment unit cell mismatch (beta)_i≠β_j) Inter-stage shrinkageError of puttingNon-linearity is introduced and the benefit of using multiple thermometer sections with the DEM is greatly reduced. The most common topology is therefore a two-segment DAC with a thermometer-coded MSB segment and a binary-coded LSB segment. It may be difficult to implement a high-speed DAC with non-linearity better than 12 bits.

Referring to fig. 14-20, a system, apparatus and method according to features of the present embodiment will be described.

This embodiment introduces perfect linearity using non-ideal component design (zeroDNL)^TM) An innovative method of DAC. This approach may eliminate the non-linearity of the DAC and remove the traditional trade-off between performance and complexity.

In a two-segment DAC, the input x is decomposed into two segments (x)₁，x₂) And is

If it is not

Then (x'₁，x′₂) Is a redundant representation of the input x

Consider a mapping (x)₁，x₂)→(x′₁，x′₂) Is defined as

x′₁＝x₁+δx₁·sgn(x₂)

x′₂＝(|x₂|-N₂·δx₁)·sgn(x₂)

(6)

Substitute into x'₁And x'₂Note that we obtain

x₁taking-N by step length of 2₁+1 and N₁-a value between 1. By selecting δ x₁2, (x) mapping₁，x₂)→x′₁Is an increment or decrement operation. For N₂8 and N₂·δx₁3-bit sub-DAC of 16, with x 'shown in Table 2'₂To (3) is performed. Due to | x₂|＜N₂·δx₁So x₂And x'₂Always with opposite signs.

x2	-7	-7	-3	-1	1	3	5	7
									x′2	9	11	13	15	-15	-13	-11	-9
x′1	x1-2	x1-2	x1-2	x1-2	x1+2	x1+2	x1+2	x1+2

Table 2: redundancy mapping

In the DAC output for redundant input, for input x → (x)₁，x₂) The output of DAC of (a) is given by:

for redundancy, x → (x'₁，x′₂) The output of the DAC is given by:

the transfer functions of y 1400 and y'1500 are shown in fig. 14 and 15, respectively. Clearly, in a DAC with mismatch, y '≠ y ≠ x, although x' ═ x.

Let p be a selection representationAnd p 'is 1-p is the selection redundancy representation (x'₁，x′₂) The probability of (c). For any input x, the output of the DAC can be assumed to be the value of y with probability p or the value of y 'with probability p'. The average value of the DAC output is given by the desired value of y

As previously mentioned, x₂And x'₂Always of opposite polarity, hence sgn (x'₂)＝-sgn(x₂). Thus, a set of non-negative weights w and w' can be found such that the weighted sum w · x₂+w′·x′₂0. It is easy to see that by selecting w ═ x'₂| and w' ═ x₂And using the identity x ═ x |, sgn (x), the weighted sum becomes | x always zero₂|·|x′₂|·[sgn(x₂)+sgn(x′₂)]. Further, the weights are normalized toAnda zero weighted sum results, and w is 1-w'.

By choosing the probabilities p and p' as:

sum p.x₂+p′·x′₂Is always zero and

y_avg＝E[y]＝(1+β₁)·x

thus, by selecting (x) with a probability of p 1610₁，x₂) And selecting (x ' having a probability of p ' 1620 '₁，x′₂) Averaging of DACsThe output 1600 may be perfectly linear as shown in fig. 16. DAC errors e and e' with x₂And x'₂And (4) in proportion. Therefore, a zero weighted sum also results in a zero average DAC error. Linearization is achieved by a combination of redundancy mapping and probability assignment. The architecture of a 2-segment DAC that achieves this linearization is shown in fig. 17 and will be discussed below.

The probability p depends only on x₂And does not depend on the sub-DAC mismatch. Substituting x, we obtain:

the probabilities p and p' for a 3-bit DAC are shown in table 3.

x2	-7	-5	-3	-1	1	3	5	7
									x′2	9	11	13	15	-15	-13	-11	-1
p	9/16	11/16	13/16	15/16	15/16	13/16	11/16	9/16
									p′	7/16	5/16	3/16	1/16	1/16	3/16	5/16	7/16

Table 3: probability distribution for 3-bit sub-DACs

The redundancy map and probability assignment are given by:

pseudo-random numbers are generated using a Linear Feedback Shift Register (LFSR). The L bits in the L-bit LFSR represent "states," and for a properly designed feedback polynomial, the LFSR will cycle through 2L-1 states in sequence before repeating itself. Typically, all-zero or all-one states are not allowed. By selecting a sufficiently large L, each bit in the LFSR is assumed to be either a '0' or a '1' with a probability of 1/2. Thus, a uniformly distributed random number may be generated by grouping together several bits of the LFSR. For example, the 4 bits of the LFSR together represent a uniformly distributed random integer variable R ∈ [ 0: 15 ]]The coincidence probability is 1/16. That is, Prob (R)<1)＝1/16，Prob(R<3)＝3/16，Prob(R<5)＝5/16，Prob(R<7) 7/16, and so on. Probability assignment of probabilities p and p' can be achieved by matching the choices with random integers R and | x₂The comparison results between | are correlated to achieve the following:

the peak amplitude of the input should be reduced so that the binary codes of all zeros and all ones are never encountered in the MSB sub-DAC. This ensures x₁And x'₁All can be formed by B₁The bit words indicate no overflow. The ranges before and after mapping are given by:

x₁∈[-N₁+2：2：N₁-2]

x′₁∈[-N₁+1：2：N₁-1]

and

x₂∈[-N₂+1：2：N₂-1]

x′₂∈[-2N₂+1：2：-N₂-1]∪[N₂+1：2：2N₂-1]

for a 3-bit sub-DAC, as shown in FIG. 17, x₂∈[-7，-5，-3，-1，1，3，5，7]And x'₂∈[-15，-13，-11，-9]∪[9，11，13，15]. Normal and redundant representationThere is no overlap. But the range of x is doubled. x is the number of₂And x'₂All can use 2N₂-1 unit cell (B)₂+1) bit sub-DAC.

Extensions to a multi-section DAC are described below. In an m-segment DAC, an input digital word x is decomposed into m segments x₁，x₂，...x_m. The mapping is defined as:

x→(x₁，x₂，...，x_m)

the redundancy map is given by:

x→(v₁，v₂，...，v_m)

variables are first defined as:

x_k，m→(x_k，x_k+1，…，x_m)

x_k，mis determined by the segments k to m. That is to say:

based on the nested nature of the computations defined in equation (6), the redundancy mapping can be performed sequentially on the paired segments, from the last segment x_mStarting and in a first segment x₁The end is as follows.

The calculation of segments (m-1) to m is:

wherein

And u is_m-1Is an intermediate value to be used in the calculation.

x′_m-1＝x_m-1+δx_m-1·sgn(x_m)

x′_m＝x_m-N_m·δx_m-1·sgn(x_m)

The calculation of segments (k-1) to k is:

wherein

And is

x′_k-1＝x_k-1+δx_k-1·sgn(x_k，m)

u′_k＝u_k-N_k·δx_k-1·sgn(s_k，m)

When k is 2 and v₁＝u₁The recursive process ends.

The sequential paired operation is shown in fig. 18. Each intermediate segment 1810 undergoes two mappings x_k→u_k→v_kThe first mapping 1802 is as the MSB segment 1806 and the second mapping 1804 is as the LSB segment of the two segment pair 1806.

The resolution of main MSB sub-DAC 1812 remains unchanged. However, the resolution of all other sub-DACs 1814, 1816, 1818 is increased by one bit. Based on the binary nature of the input decomposition, the unit elements of all LSB sub-DACs 1814, 1816, 1818 add up to one LSB of MSB sub-DAC 1812. Thus, the increase in complexity is equivalent to only one LSB of MSB sub-DAC 1812. For example, for a design with a 4-bit MSB sub-DAC, the increase in hardware complexity is only 6.25%.

Extensions to the binary DAC will now be discussed. A B-bit binary DAC requires B binary weighted elements. To achieve perfect linearity, the ratio between the weighted elements needs to be a power of 2. Any deviation from a power of 2 will result in DNL and INL errors.

A B-bit binary DAC may be viewed as having a B segment x₁，x₂，…，x_BThe segmented DAC of (1). Each segment having 1 bit, where x_iThe values are-1 and 1. The B-bit digital input x may be represented as x_iBinary weighted sum of (c):

the output of the DAC may be expressed as follows:

in the case of a non-ideal implementation,wherein alpha is_iIs the ratio error for segment i. The output of the DAC is given by:

in the zeroDNL implementation, each 1-bit segment is replaced with a 2-bit thermometer coded segment. With section B v₁，v₂，...v_B. Each segment comprises or alternatively consists of 3 unit elements, where v_iValues of-3, -1, 1 and 3. Segment v₁，v₂，...v_BCan be divided into a plurality of sections by dividing the last section v_bThe initial recursive process is determined as follows.

The calculation of the segments (B-1) to B is:

wherein

And u is_B-1Is the intermediate value used in the next calculation:

x′_B-1＝x_B-1+2·sgn(x_B)

x′_B＝x_B-4·sgn(x_B)

the calculation of segments (k-1) to k is:

wherein

And u is_k-1Is the intermediate value used in the next alternative:

x′_k-1＝x_k-1+2·sgn(u_k+v_k+1，B)

u′_k＝u_k-4·sgn(u_k+v_k+1，B)

when k is 2 and v_k-1＝u_k-1The recursive process ends.

To summarize: 1) the redundant mapping probability assignment results in a perfect linear DAC; 2) linearization does not depend on component mismatch and the DAC is linear by design. Thus, no information about the mismatch is needed. However, the mismatch is converted to random noise, evenly distributed over the nyquist band; 3) linearization is feed forward and occurs in the digital domain; and 4) maintain linearity over process, temperature and voltage variations.

The method of the present embodiment includes the application of a Successive Approximation Register (SAR) ADC. SAR ADCs represent an important segment of the mid-to-high resolution ADC market. Typical resolutions range from 10 to 18 bits with speeds up to 20 MS/s. The SAR architecture results in low power consumption and small area and is the preferred architecture for many applications. Recently, lower resolution time interleaved SAR has resulted in very efficient multi-gigabit sample ADCs.

A B-bit flash ADC uses linear voltage steps with comparators at each of the N "steps" of the steps to simultaneously compare an input voltage with a set of equidistant reference voltages. The outputs of these comparators are fed to a digital encoder that generates binary values. Flash architectures are highly parallel architectures with a fast transition time of one cycle. The main drawback is that the complexity increases exponentially with the number of bits, since a B-bit ADC requires N reference voltages and N comparators.

At the other end of the spectrum is a digital ramp (counter) B-bit ADC, which takes up to N cycles for conversion. The ramp counter increments by one LSB at each count. The B bit count drives the DAC, the output of which is compared to the analog input. The counting process terminates when the DAC output exceeds the analog input. Although this architecture is highly sequential and requires only one comparator and DAC, the sequential nature results in an exponential slow down in the conversion rate of a high resolution ADC.

The basic architecture of a B-bit SAR ADC as an improvement to a digital ramp ADC is shown in fig. 19. The analog input voltage Vin 1902 is sampled and held 1904 for the duration of the transition. The decision directed search algorithm 1908 sequentially selects the B-bit digital input 1910 that drives the output 1912 of the DAC 1904 to the value closest to the input voltage Vin. It is well known that binary search algorithms are likely to be the most efficient search and find the closest code in the B log2(N) step.

The successive approximation register is initialized so that only the Most Significant Bit (MSB) equals the number 1. The code is fed to a DAC which converts the analog equivalent of the digital codeSupplied to a comparator for comparison with the sampled input voltage. If the analog voltage exceeds Vin, the comparator causes the SAR to reset the bit; otherwise, the bit is reserved as 1. The next bit is then set to 1 and the DAC supplies the analog equivalent of the digital code as 1OrAs shown in fig. 20. Thus, in each cycle, the ADC compares Vin to the most recent analog estimate and directs the search according to the polarity of the comparison. The binary search continues until every bit in the SAR is used. The resulting code is a digital approximation of the sampled input voltage.

Two important components of a SAR ADC are the comparator and the DAC. The sample and hold block may typically be embedded in the DAC (e.g., in a capacitive DAC) and may not be an explicit circuit. Noise in the comparator can be considered white and is not a source of non-linearity. However, without amplification, the comparator needs to maintain the accuracy of the B bits, so the input referred noise of the comparator is designed to be less than the LSB.

SAR creates a "virtual" voltage reference ladder, where each voltage step is generated sequentially by the DAC. If the voltages generated by the DAC are not uniformly spaced, this results in unequal steps (or bins), and the signal is non-uniformly quantized. DNL is a measure of the difference from each of the nominal steps.

Typically, the DAC output is monitored as a function of time, and all possible trajectories are mapped. These traces form a "time grid" as shown in fig. 20. The last stage of the time trellis diagram may include or, in some embodiments, consist of a set of voltages that are uniformly spaced over the input voltage range. The linearity of the ADC is a function of how accurately the DAC can generate the set of equidistant voltages. Thus, the linearity of the ADC is determined only by the linearity of the DAC.

High resolution SAR ADCs tend to occupy large areas if the DAC unit cell size is determined by matching linearity requirements rather than thermal noise. High resolution SAR DACs require trimming based on limitations on component matching (capacitors, resistors, current sources). However, trimming cannot compensate for changes in voltage and temperature. Therefore, on-line continuous calibration is required during normal operation.

A DAC employing a zeroDNL architecture with redundant mapping and probability assignment may be perfectly linear. Thus, the zeroDNL DAC generates a set of reference voltages that are uniformly spaced apart, which results in a perfectly linear ADC. The zeroDNL architecture also maintains linearity continuously over process, temperature and voltage variations.

The components may be implemented by one or more processors or computers. It is to be understood that the systems and/or methods described herein may be implemented in various forms of hardware, firmware, or a combination of hardware and software. The actual specialized control hardware or software code used to implement these systems and/or methods is not limiting of implementations. Thus, the operation and behavior of the systems and/or methods were described herein without reference to the specific software code-it being understood that software and hardware may be designed to implement the systems and/or methods based on the description herein.

As also used herein, the terms "processor," "module," "processing circuit," and/or "processing unit" (e.g., including various modules and/or circuitry, such as may operate, implement, and/or be used for encoding, for decoding, for baseband processing, etc.) may be a single processing device or multiple processing devices. Such a processing device may be a microprocessor, microcontroller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding and/or operational instructions for the circuitry. The processing module, processing circuit, and/or processing unit may have associated memory and/or integrated memory elements, which may be a single memory device, multiple memory devices, and/or embedded circuitry of the processing module, processing circuit, and/or processing unit. Such a memory device may be read-only memory (ROM), random-access memory (RAM), volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module, processing circuit, and/or processing unit includes more than one processing device, the processing devices may be centrally located (e.g., directly coupled together via a wired and/or wireless bus structure) or may be distributively located (e.g., via indirectly coupled cloud computing via a local area network and/or a wide area network). It is further noted that if the processing module, processing circuit, and/or processing unit implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory elements storing the corresponding operational instructions may be embedded within or external to the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. It is still further noted that the memory elements may store, and the processing modules, processing circuits and/or processing units execute, hard-coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the figures. Such memory devices or memory elements may be included in an article of manufacture.

The invention has been described above with the aid of method steps illustrating the execution of specified functions and relationships thereof. Boundaries and sequences of these functional building blocks and method steps have been arbitrarily defined herein for the convenience of the description. Alternate boundaries and sequences may be defined so long as the specified functions and relationships are appropriately performed. Accordingly, any such alternative boundaries or sequences are within the scope and spirit of the claimed invention. Furthermore, the boundaries of these functional building blocks have been arbitrarily defined for the convenience of the description. Alternate boundaries may be defined so long as certain important functions are appropriately performed. Similarly, flow diagram blocks are also arbitrarily defined herein to illustrate certain important functions. To the extent used, flow diagram block boundaries and sequences may be defined in other ways and still perform some important functions. Accordingly, such alternative definitions of both functional building blocks and flowchart blocks and sequences are within the scope and spirit of the claimed invention. Those of ordinary skill in the art will also recognize that the functional building blocks and other illustrative blocks, modules, and components herein may be implemented as shown or by discrete components, application specific integrated circuits, processors executing appropriate software, etc., or combinations thereof.

The invention may also be described, at least in part, in terms of one or more embodiments. Embodiments of the invention are used herein to illustrate the invention, aspects thereof, features thereof, concepts thereof and/or examples thereof. Physical embodiments of devices, articles of manufacture, machines and/or processes embodying the invention may include one or more aspects, features, concepts, examples, etc. described with reference to one or more embodiments discussed herein. Further, from figure to figure, embodiments may incorporate the same or similarly named functions, steps, modules, etc. that may use the same or different reference numbers, and such functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or may be different.

The above description provides specific details such as material types and processing conditions in order to provide a thorough description of example embodiments. However, it will be understood by those of ordinary skill in the art that the embodiments may be practiced without these specific details.

Some illustrative aspects of the invention may be beneficial in solving the problems described herein and other problems not discussed, which may be discoverable by a skilled artisan. While the above description contains multiple specificities, these should not be construed as limitations on the scope of any embodiments, but rather as exemplifications of the embodiments presented thereof. Many other consequences and variations are possible within the teachings of various embodiments. While the invention has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best or only mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. Furthermore, in the drawings and the description, there have been disclosed exemplary embodiments of the invention and, although specific terms may have been employed, they are unless otherwise stated used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention therefore not being so limited. Moreover, the use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another. Furthermore, the use of the terms a, an, etc. do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item. The scope of the invention should, therefore, be determined by the appended claims and their legal equivalents, rather than by the examples given.