阅读说明：本技术 显示装置及其制造方法 (Display device and method for manufacturing the same ) 是由 金璱基 崔升夏 金承来 金贤 尹甲洙 李光洙 李在贤 赵正京 于 2021-04-30 设计创作，主要内容包括：本发明为了一种显示装置及其制造方法,其防止配置有像素电极的绝缘层的表面损坏,防止发生薄膜封装层损坏引起的发光元件的劣化,保护焊盘部表面并防止焊盘部的表面损坏,提供一种显示装置,具备：基板,包括显示区域以及围绕所述显示区域的周边区域；薄膜晶体管,配置于与所述显示区域对应的所述基板上；焊盘部,配置于与所述周边区域对应的所述基板上；第一绝缘层,包括配置于所述薄膜晶体管上的第一部分和从所述第一部分延伸的第二部分,所述第一绝缘层暴露所述焊盘部；以及发光元件,配置于所述第一绝缘层的所述第一部分上,并与所述薄膜晶体管电连接,所述第一绝缘层的上面具有所述第一部分和所述第二部分之间的台阶。(The present invention provides a display device and a method for manufacturing the same, which prevents the surface damage of an insulating layer provided with a pixel electrode, prevents the deterioration of a light emitting element caused by the damage of a thin film encapsulation layer, protects the surface of a pad portion, and prevents the surface damage of the pad portion, the display device comprising: a substrate including a display area and a peripheral area surrounding the display area; a thin film transistor disposed on the substrate corresponding to the display region; a pad part disposed on the substrate corresponding to the peripheral region; a first insulating layer including a first portion disposed on the thin film transistor and a second portion extending from the first portion, the first insulating layer exposing the pad part; and a light emitting element disposed on the first portion of the first insulating layer and electrically connected to the thin film transistor, wherein a step is formed between the first portion and the second portion on the first insulating layer.)

1. A display device is provided with:

a substrate including a display area and a peripheral area surrounding the display area;

a thin film transistor disposed on the substrate corresponding to the display region;

a pad part disposed on the substrate corresponding to the peripheral region;

a first insulating layer including a first portion disposed on the thin film transistor and a second portion extending from the first portion, the first insulating layer exposing the pad part; and

a light emitting element disposed on the first portion of the first insulating layer and electrically connected to the thin film transistor,

the first insulating layer has a step thereon between the first portion and the second portion.

2. The display device according to claim 1,

the vertical distance from the substrate to the upper face of the first portion is longer than the vertical distance from the substrate to the upper face of the second portion.

3. The display device according to claim 1,

the display device further includes:

a second insulating layer disposed in the peripheral region and containing the same material as the first insulating layer,

the pad part includes: a pad electrode; and a pad connection electrode disposed on the pad electrode and contacting at least a part of the pad electrode,

the second insulating layer is disposed between the pad electrode and the pad connection electrode, and overlaps at least a portion of the pad connection electrode.

4. The display device according to claim 3,

the surface of the second insulating layer overlapping the pad connection electrode has an inclination.

5. The display device according to claim 3,

the display device further includes:

a third insulating layer disposed between the second insulating layer and the pad electrode and having a contact hole partially exposing the pad electrode,

a portion of the pad connection electrode is in contact with the pad electrode within the contact hole,

the pad connection electrode has a width in one direction wider than a width of the pad electrode exposed through the contact hole.

6. The display device according to claim 3,

the pad part further includes:

and a pad protective layer disposed between the pad electrode and the pad connection electrode.

7. The display device according to claim 3,

the light emitting element includes a pixel electrode, an intermediate layer, and a counter electrode,

at least a part of the pad connection electrode and the pixel electrode contain the same substance.

8. The display device according to claim 7,

the pixel electrode has a three-layer film, and the pad connection electrode has a single-layer film.

9. A display device is provided with:

a substrate including a display area and a peripheral area surrounding the display area;

a thin film transistor disposed on the substrate corresponding to the display region;

a pad part disposed on the substrate corresponding to the peripheral region;

a first insulating layer disposed on the thin film transistor and exposing the pad portion;

a light emitting element disposed on the first insulating layer, electrically connected to the thin film transistor, and including a pixel electrode, an intermediate layer, and a counter electrode; and

and the pixel defining film is configured on the first insulating layer and covers the edge of the pixel electrode, and the side surface of the first insulating layer and the side surface of the pixel defining film are positioned on the same etching surface.

10. The display device according to claim 9,

the first insulating layer includes a first portion and a second portion extending from the first portion,

the first insulating layer has a step thereon between the first portion and the second portion.

11. The display device according to claim 10,

the side face of the first portion and the outer side face of the pixel defining film are located on the same etched face.

12. The display device according to claim 10,

the pixel electrode and the pixel defining film are disposed corresponding to the first portion.

13. The display device according to claim 9,

the display device further includes:

a second insulating layer disposed in the peripheral region and containing the same material as the first insulating layer,

the pad part includes: a pad electrode; and a pad connection electrode disposed on the pad electrode and contacting at least a part of the pad electrode,

the second insulating layer is disposed between the pad electrode and the pad connection electrode, and overlaps at least a portion of the pad connection electrode.

14. The display device according to claim 13,

the surface of the second insulating layer overlapping the pad connection electrode has an inclination.

15. The display device according to claim 13,

the display device further includes:

a third insulating layer disposed on the pad electrode and having a contact hole exposing a portion of the pad electrode,

a part of the pad connection electrode is in contact with an upper face of the third insulating layer.

16. The display device according to claim 15,

the pad connection electrode has a width in one direction wider than a width of the pad electrode exposed through the contact hole.

17. The display device according to claim 13,

the pixel electrode has a three-layer film, and the pad connection electrode has a single-layer film.

18. The display device according to claim 9,

the display device further includes:

the dam portion is arranged corresponding to the peripheral region and comprises a first peripheral insulating layer, a second peripheral insulating layer arranged on the first peripheral insulating layer and a peripheral electrode layer arranged between the first peripheral insulating layer and the second peripheral insulating layer.

19. The display device according to claim 18,

the side surface of the first peripheral insulating layer and the side surface of the second peripheral insulating layer are located on the same etched surface.

20. A display device is provided with:

a substrate including a display area and a peripheral area surrounding the display area;

a thin film transistor disposed on the substrate corresponding to the display region;

a pad part disposed on the substrate corresponding to the peripheral region;

an inorganic insulating layer disposed on the thin film transistor and the pad portion and having an opening exposing an upper surface of the pad portion; and

and a light emitting element disposed on the inorganic insulating layer, electrically connected to the thin film transistor, and including a pixel electrode, an intermediate layer, and a counter electrode.

21. The display device according to claim 20,

the width of the upper face of the pad portion along one direction is smaller than or equal to the width of the opening.

22. The display device according to claim 20,

the pad part includes: a pad electrode; and a pad protective layer disposed on the pad electrode,

an upper face of the pad protection layer is exposed through the opening.

23. The display device according to claim 22,

the width of the upper face of the pad protection layer along a direction is smaller than or equal to the width of the opening.

24. The display device according to claim 22,

the side surface of the pad electrode is exposed at least partially through the opening.

25. The display device according to claim 20,

the display device further includes:

the electrode layer is configured on the thin film transistor and is electrically connected with the thin film transistor;

an insulating layer disposed on the inorganic insulating layer; and

a pixel defining film disposed on the insulating layer with the pixel electrode interposed therebetween,

the inorganic insulating layer further has a first contact hole exposing a portion of the electrode layer,

the insulating layer has a second contact hole corresponding to the first contact hole,

the pixel electrode is electrically connected to the electrode layer through the first contact hole and the second contact hole.

26. The display device according to claim 25,

a side surface of the insulating layer adjacent to the peripheral region is aligned with a side surface of the pixel defining film.

27. The display device according to claim 25,

the insulating layer includes: a first portion; and a second portion extending from the first portion to the peripheral region side,

the insulating layer has a step thereon between the first portion and the second portion.

28. The display device according to claim 20,

the display device further includes:

and the dam part is arranged corresponding to the peripheral area and comprises a first peripheral insulating layer and a second peripheral insulating layer arranged on the first peripheral insulating layer.

29. The display device according to claim 28,

the side faces of the first peripheral insulating layer and the second peripheral insulating layer are aligned.

Technical Field

The present invention relates to a display device and a method of manufacturing the same.

Background

A display device is a device that visually displays data. The display device is used as a display for small products such as a mobile phone and a display for large products such as a television.

Such a display device includes a substrate divided into a display area in which gate lines and data lines are formed to be insulated from each other and a non-display area. The display region defines a plurality of pixel regions, and pixels respectively arranged in the plurality of pixel regions receive electric signals from gate lines and data lines intersecting each other to display an image to the outside and emit light. Each pixel region (each pixel region) includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor, and the pixel regions commonly include a counter electrode. The non-display area may include: various wirings for transmitting electrical signals to the pixels in the display region; a gate driving section; and a pad which can connect the data driving part and the control part.

Recently, the use of display devices has become diversified. In addition, the display device is thin in thickness and light in weight, so that the range of use thereof tends to become wide. Recently, various designs for improving the quality of the display device have been attempted.

Disclosure of Invention

The present invention has been made to solve various problems, and an object thereof is to provide a display device and a method of manufacturing the same, which prevent damage to a surface of an insulating layer provided with a pixel electrode, prevent deterioration of a light emitting element due to damage to a thin film encapsulation layer, and protect a surface of a pad portion by forming an opening exposing the pad portion after an etching process for forming the pixel electrode, and prevent damage to the surface of the pad portion. However, such a problem is exemplary, and the scope of the present invention is not limited thereto.

According to an aspect of the present invention, there is provided a display device including: a substrate including a display area and a peripheral area surrounding the display area; a thin film transistor disposed on the substrate corresponding to the display region; a pad part disposed on the substrate corresponding to the peripheral region; a first insulating layer including a first portion disposed on the thin film transistor and a second portion extending from the first portion, the first insulating layer exposing the pad part; and a light emitting element disposed on the first portion of the first insulating layer and electrically connected to the thin film transistor, wherein a step is formed between the first portion and the second portion on the first insulating layer.

According to an example, a vertical distance from the substrate to an upper surface of the first portion may be longer than a vertical distance from the substrate to an upper surface of the second portion.

According to an example, the display device may further include: a second insulating layer disposed in the peripheral region and containing the same material as the first insulating layer, the pad part including: a pad electrode; and a pad connecting electrode disposed on the pad electrode and contacting at least a portion of the pad electrode, wherein the second insulating layer is disposed between the pad electrode and the pad connecting electrode and overlaps at least a portion of the pad connecting electrode.

According to an example, a surface of the second insulating layer overlapping with the pad connection electrode may have an inclination.

According to an example, the display device may further include: and a third insulating layer disposed between the second insulating layer and the pad electrode and having a contact hole partially exposing the pad electrode, wherein a portion of the pad connection electrode is in contact with the pad electrode in the contact hole.

According to an example, a width of the pad connection electrode along one direction may be wider than a width of the pad electrode exposed through the contact hole.

According to an example, the pad part may further include: and a pad protective layer disposed between the pad electrode and the pad connection electrode.

According to one example, the light-emitting element may include a pixel electrode, an intermediate layer, and a counter electrode, and the pad connection electrode and at least a part of the pixel electrode may include the same material.

In one example, the pixel electrode may have a three-layer film, and the pad connection electrode may have a single-layer film.

According to an example, the pixel electrode may be disposed to overlap only the first portion.

According to another aspect of the present invention, there is provided a method of manufacturing a display device, including: preparing a substrate including a display region and a peripheral region surrounding the display region; a step of forming a thin film transistor on the display region; a step of forming a pad electrode on the peripheral region; forming an inorganic protective layer and a first insulating layer to cover the thin film transistor and the pad electrode; a step of patterning the first insulating layer with a first mask; forming a first contact hole partially exposing the thin film transistor and a second contact hole partially exposing the pad electrode in the inorganic protective layer using the first insulating layer; a step of forming a pixel electrode layer electrically connected to the thin film transistor through the first contact hole on a first portion of the first insulating layer; a step of forming a first photoresist pattern on the pixel electrode layer; etching the pixel electrode layer using the first photoresist pattern; and a step of partially etching a second portion extending from the first portion of the first insulating layer using the first photoresist pattern.

For example, the first mask may be a half-tone mask (half-tone mask) or a slit mask (slit mask).

According to an example, the method of manufacturing a display device may further include: a step of forming a pad connection electrode electrically connected to the pad electrode through the second contact hole; a step of forming a second photoresist pattern on the pad connection electrode; and a step of etching the pad connection electrode using the second photoresist pattern.

According to an example, the method of manufacturing a display device may further include: a step of partially etching a third portion of the first insulating layer corresponding to the peripheral region using the second photoresist pattern.

According to an example, the method of manufacturing a display device may further include removing the second photoresist pattern, wherein the removing the second photoresist pattern and the partially etching the third portion are simultaneously performed.

According to one example, a surface of a remaining portion of the third portion of the first insulating layer other than the etched portion may have an inclination.

According to an example, the step of forming the first photoresist pattern and the step of forming the second photoresist pattern may be simultaneously performed using a second mask.

For example, the second mask may be a half-tone mask (half-tone mask) or a slit mask (slit mask).

According to one example, the first photoresist pattern may have a thickness greater than that of the second photoresist pattern.

According to an example, the method of manufacturing a display device may further include: and a step of forming the pad connection electrode into a three-layer film, and removing the remaining two films except for the film adjacent to the pad electrode in the three-layer film of the pad connection electrode.

According to still another aspect of the present invention, there is provided a display device including: a substrate including a display area and a peripheral area surrounding the display area; a thin film transistor disposed on the substrate corresponding to the display region; a pad part disposed on the substrate corresponding to the peripheral region; a first insulating layer disposed on the thin film transistor and exposing the pad portion; a light emitting element disposed on the first insulating layer, electrically connected to the thin film transistor, and including a pixel electrode, an intermediate layer, and a counter electrode; and a pixel defining film disposed on the first insulating layer and covering an edge of the pixel electrode, a side surface of the first insulating layer and a side surface of the pixel defining film being located on a same etching surface.

According to one example, the first insulating layer may include a first portion and a second portion extending from the first portion, and the first insulating layer may have a step between the first portion and the second portion on an upper surface thereof.

According to an example, a vertical distance from the substrate to an upper surface of the first portion may be longer than a vertical distance from the substrate to an upper surface of the second portion.

According to an example, a side surface of the first portion may be located on the same etched surface as an outer side surface of the pixel defining film.

In one example, the pixel electrode and the pixel defining film may be disposed to correspond to the first portion.

According to an example, the pad part may include: a pad electrode; and a pad connection electrode disposed on the pad electrode and contacting at least a portion of the pad electrode.

According to an example, the display device may further include: and a second insulating layer disposed in the peripheral region and including the same substance as the first insulating layer, the second insulating layer being disposed between the pad electrode and the pad connection electrode and overlapping at least a part of the pad connection electrode.

According to an example, a surface of the second insulating layer overlapping with the pad connection electrode may have an inclination.

According to an example, the display device may further include: and a third insulating layer disposed on the pad electrode and having a contact hole exposing a portion of the pad electrode, wherein a portion of the pad connection electrode is in contact with an upper surface of the third insulating layer.

According to an example, a width of the pad connection electrode along one direction may be wider than a width of the pad electrode exposed through the contact hole.

In one example, the pixel electrode may have a three-layer film, and the pad connection electrode may have a single-layer film.

According to an example, the display device may further include: the dam portion is arranged corresponding to the peripheral region and comprises a first peripheral insulating layer, a second peripheral insulating layer arranged on the first peripheral insulating layer and a peripheral electrode layer arranged between the first peripheral insulating layer and the second peripheral insulating layer.

According to an example, a side surface of the first peripheral insulating layer and a side surface of the second peripheral insulating layer may be located on the same etched surface.

According to still another aspect of the present invention, there is provided a method of manufacturing a display device, including: preparing a substrate including a display region and a peripheral region surrounding the display region; a step of forming a thin film transistor on the display region; sequentially forming a first insulating layer, a pixel electrode material layer and a pixel defining film material layer on the thin film transistor; a step of patterning the pixel defining film substance layer with a first mask to form a preliminary pixel defining film on a first portion of the first insulating layer; a step of forming a pixel electrode by etching the pixel electrode material layer using the preliminary pixel defining film; and a step of locally etching a second portion extending from the first portion of the first insulating layer with the preliminary pixel defining film.

According to an example, the method of manufacturing a display device may further include: a step of forming a pad electrode on the peripheral region; a step of forming an inorganic protective layer having a contact hole exposing a portion of the pad electrode on the pad electrode; and a step of forming a pad connection electrode electrically connected to the pad electrode through the contact hole.

According to an example, the step of forming the pad connection electrode may include: forming a pad connecting electrode substance layer on the pad electrode; a step of forming a photoresist pattern on the pad connection electrode substance layer; and etching the pad connection electrode substance layer using the photoresist pattern.

In one example, the photoresist pattern may be formed by patterning the pixel defining film material layer corresponding to the peripheral region using the first mask.

According to an example, the preliminary pixel defining film may have a thickness greater than a thickness of the photoresist pattern.

According to an example, the method of manufacturing a display device may further include: a step of partially etching a third portion of the first insulating layer corresponding to the peripheral region using the photoresist pattern.

According to an example, the method of manufacturing a display device may further include removing the photoresist pattern, and partially etching the third portion at the same time.

According to an example, the method of manufacturing a display device may further include: and a step of forming the pad connection electrode into a three-layer film, and removing the remaining two films except for the film adjacent to the pad electrode in the three-layer film of the pad connection electrode.

According to an example, the preliminary pixel defining film may include: a first preliminary pixel defining film covering an edge of the pixel electrode; and a second preliminary pixel defining film surrounded by the first preliminary pixel defining film, a thickness of the first preliminary pixel defining film being thicker than a thickness of the second preliminary pixel defining film.

According to an example, the method of manufacturing a display device may further include: a step of removing the second preliminary pixel defining film to form a pixel defining film.

According to an example, the method of manufacturing a display device may further include: a step of forming the preliminary pixel defining film in contact with a side face of the pixel electrode.

For example, the first mask may be a half-tone mask (half-tone mask) or a slit mask (slit mask).

According to still another aspect of the present invention, there is provided a display device including: a substrate including a display area and a peripheral area surrounding the display area; a thin film transistor disposed on the substrate corresponding to the display region; a pad part disposed on the substrate corresponding to the peripheral region; an inorganic insulating layer disposed on the thin film transistor and the pad portion and having an opening exposing an upper surface of the pad portion; and a light emitting element disposed on the inorganic insulating layer, electrically connected to the thin film transistor, and including a pixel electrode, an intermediate layer, and a counter electrode.

According to an example, a width of an upper surface of the pad portion along one direction may be less than or equal to a width of the opening.

According to an example, the pad part may include: a pad electrode; and a pad protective layer disposed on the pad electrode, an upper surface of the pad protective layer being exposed through the opening.

According to an example, a width of an upper surface of the pad protection layer along one direction may be less than or equal to a width of the opening.

According to an example, a side surface of the pad electrode may be aligned with a side surface of the pad protective layer.

According to one example, a side surface of the pad electrode may be partially exposed through the opening.

According to an example, the display device may further include: an electrode layer disposed on the thin film transistor and electrically connected to the thin film transistor, the inorganic insulating layer further having a first contact hole exposing a portion of the electrode layer,

according to an example, the display device may further include: an insulating layer disposed on the inorganic insulating layer and having a second contact hole corresponding to the first contact hole; and a pixel defining film disposed on the insulating layer with the pixel electrode interposed therebetween, the pixel electrode being electrically connected to the electrode layer through the first contact hole and the second contact hole.

According to one example, a side surface of the insulating layer adjacent to the peripheral region may be aligned with a side surface of the pixel defining film.

According to one example, the insulating layer may include: a first portion; and a second portion extending from the first portion to the peripheral region side, the insulating layer having a step therebetween on an upper surface thereof.

According to an example, a vertical distance from the substrate to an upper surface of the first portion may be longer than a vertical distance from the substrate to an upper surface of the second portion.

According to an example, the display device may further include: and the dam part is correspondingly configured with the peripheral area and comprises a first peripheral insulating layer and a second peripheral insulating layer correspondingly configured with the first peripheral insulating layer.

According to one example, a side surface of the first peripheral insulating layer and a side surface of the second peripheral insulating layer may be aligned.

According to still another aspect of the present invention, there is provided a method of manufacturing a display device, including: preparing a substrate including a display region and a peripheral region surrounding the display region; a step of forming a thin film transistor on the display region; a step of forming a pad portion on the peripheral region; a step of forming an inorganic insulating layer on the pad portion; a step of forming, on the inorganic insulating layer, a preliminary pixel defining film having a first opening exposing at least a part of the inorganic insulating layer on the pad portion; and a step of etching a first portion of the inorganic insulating layer exposed through the first opening, using the preliminary pixel defining film.

According to an example, the step of forming the pad part may include; a step of forming a pad electrode on the peripheral region; and a step of forming a pad protective layer on the pad electrode.

According to an example, the step of etching the first portion of the inorganic insulating layer may be a step of exposing an upper surface of the pad protective layer.

According to an example, the method of manufacturing a display device may further include: a step of removing the preliminary pixel defining film corresponding to the peripheral area.

According to an example, the method of manufacturing a display device may further include: forming an electrode layer disposed on the thin film transistor and electrically connected to the thin film transistor; a step of forming a preliminary insulating layer interposed between the electrode layer and the preliminary pixel defining film and having a first contact hole corresponding to a portion of the electrode layer; and a step of etching a second portion of the inorganic insulating layer corresponding to the first contact hole using the preliminary insulating layer.

According to an example, the method of manufacturing a display device may further include: a step of removing the preliminary insulating layer corresponding to the peripheral region.

According to an example, the method of manufacturing a display device may further include: the step of removing the preliminary pixel defining film corresponding to the peripheral region, and the step of removing the preliminary insulating layer corresponding to the peripheral region are simultaneously realized.

Other aspects, features, and advantages than those described above will become apparent from the following detailed description, the claims, and the accompanying drawings.

(effect of the invention)

According to an embodiment of the present invention configured as described above, it is possible to realize a display device and a method of manufacturing the same, which prevent damage of a surface of an insulating layer provided with a pixel electrode, prevent deterioration of a light emitting element caused by damage of a thin film encapsulation layer, and form an opening exposing a pad portion to protect a surface of the pad portion and prevent damage of the surface of the pad portion after an etching process for forming the pixel electrode. Of course, the scope of the present invention is not limited by such effects.

Drawings

Fig. 1 is a plan view briefly showing a display device according to an embodiment of the present invention.

Fig. 2 is a plan view briefly illustrating a display panel according to an embodiment of the present invention.

Fig. 3 is an equivalent circuit diagram schematically showing any one pixel of the display panel according to an embodiment of the present invention.

Fig. 4 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 5 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 6a is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 6b is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 7a to 7g are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention.

Fig. 8a to 8g are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention.

Fig. 9 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 10 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 11 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 12a to 12h are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention.

Fig. 13a to 13g are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention.

Fig. 14a to 14i are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention.

Fig. 15a to 15g are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention.

Fig. 16 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 17 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 18 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 19 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 20a is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 20b is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 21 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 22a to 22j are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention.

Fig. 23a to 23d are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention.

Fig. 24 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Fig. 25 is a sectional view briefly showing a display device according to an embodiment of the present invention.

(description of reference numerals)

1: the display device 10: display panel

117: planarization layer 117 p: preliminary planarization layer

117 a: first portion 117 b: the second part

117 c: third portion 118: insulating layer

119: pixel defining film 119 p: preliminary pixel defining film

ST: step PR: photoresist pattern

OP: opening PVX: inorganic protective layer

M1, M2, M3, M4, M5, M6: first to sixth masks

Detailed Description

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. Effects and features of the present invention and a method for realizing them will become apparent by referring to embodiments described in detail later together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when the description is made with reference to the drawings, the same or corresponding constituent elements will be given the same reference numerals, and repeated description thereof will be omitted.

In the following embodiments, the terms first, second, and the like are not used in a limiting sense, but are used for the purpose of distinguishing one constituent element from other constituent elements.

In the following embodiments, the singular expressions include plural expressions unless the context clearly dictates otherwise.

In the following embodiments, the terms including, having, etc. mean that there are features or constituent elements described in the specification, and do not exclude the possibility of adding one or more other features or constituent elements.

In the following embodiments, when a part such as a film, a region, or a component is referred to as being on or above another part, the part includes not only a case where the part is directly on the other part but also a case where another film, a region, or a component is interposed therebetween.

In the drawings, the sizes of constituent elements may be enlarged or reduced for convenience of explanation. For example, the dimensions and thicknesses of the respective members shown in the drawings are arbitrarily illustrated for convenience of explanation, and thus the present invention is not necessarily limited to the illustrations.

Where an embodiment may be implemented differently, the particular process sequence may also be performed differently than illustrated. For example, two processes described in succession may be executed substantially concurrently, or may be executed in reverse order to the order described.

In the present specification, "A and/or B" means A or B, or A and B. Further, "at least one of a and B" represents a case of a, or B, or a and B.

In the following embodiments, when a film, a region, a component or the like is referred to as being connected, the film, the region, the component or the like is directly connected, or/and the film, the region, the component or the like is indirectly connected via another film, region, or component. For example, in the present specification, when a film, a region, a component, or the like is electrically connected, the film, the region, the component, or the like is directly electrically connected, or/and the film, the region, the component, or the like is indirectly electrically connected via another film, region, component, or the like.

The x-axis, y-axis, and z-axis are not limited to three axes on a rectangular coordinate system, and may be construed to include the broad meaning thereof. For example, the x-axis, the y-axis, and the z-axis may be orthogonal to each other, but may also be referred to as different directions from each other that are not orthogonal to each other.

Fig. 1 is a plan view briefly showing a display device according to an embodiment of the present invention.

Referring to fig. 1, the display device 1 includes a display area DA for displaying an image and a peripheral area PA disposed around the display area DA. The display device 1 can provide an image to the outside by using light emitted from the display area DA. Of course, since the display device 1 includes the substrate 100, the substrate 100 may be said to have the display area DA and the peripheral area PA.

The substrate 100 may be made of various materials such as glass, metal, or plastic. According to an embodiment, the substrate 100 may comprise a flexible material. Herein, a flexible material refers to a substrate that can be easily bent, and folded or rolled. Such a substrate 100 of a flexible material may be made of ultra-thin glass, metal, or plastic.

Pixels PX having various display elements (OLEDs) such as organic light-emitting diodes (OLEDs) may be disposed in the display area DA of the substrate 100. The plurality of pixels PX may be arranged in various forms such as a stripe arrangement, a five-grid arrangement, and a mosaic arrangement, and may realize an image.

When the display area DA is viewed in a planar shape, the display area DA may have a rectangular shape as shown in fig. 1. As still another example, the display area DA may have a polygonal shape such as a triangle, a pentagon, and a hexagon, or a circular shape, an elliptical shape, an irregular shape, and the like.

The peripheral area PA of the substrate 100 may be an area where no image is displayed as an area disposed around the display area DA. The peripheral area PA may surround the display area DA entirely or partially. Various wirings for transmitting an electric signal to be applied to the display area DA, and a PAD portion PAD to which a printed circuit substrate or a driver IC chip is attached may be provided in the peripheral area PA.

Fig. 2 is a plan view briefly illustrating a display panel according to an embodiment of the present invention.

Referring to fig. 2, the display panel 10 includes a display area DA and a peripheral area PA, and includes a plurality of pixels PX disposed in the display area DA. The plurality of pixels PX may each include a display element such as an organic light emitting diode OLED. Each pixel PX may emit light of, for example, red, green, blue, or white through the organic light emitting diode OLED. Hereinafter, in the present specification, each Pixel PX may mean Sub-pixels (Sub-pixels) each emitting light of a different color from each other, and each Pixel PX may be, for example, one of a red (R) Sub-Pixel, a green (G) Sub-Pixel, and a blue (B) Sub-Pixel. The display area DA may be covered with an encapsulation member to protect it from external gas or moisture, etc.

Each pixel PX may be electrically connected to a peripheral circuit disposed in the peripheral area PA. The first gate driving circuit 130, the second gate driving circuit 140, the PAD portion PAD, the data driving circuit 150, the first power supply wiring 160, and the second power supply wiring 170 may be disposed in the peripheral area PA.

The first gate driving circuit 130 and the second gate driving circuit 140 may each include a scan driving circuit and a light emission control driving circuit. The scan driving circuit included in the first gate driving circuit 130 and the second gate driving circuit 140 may supply a scan signal to each pixel PX through the scan line SL. In addition, the light emission control driving circuit included in the first gate driving circuit 130 and the second gate driving circuit 140 may supply a light emission control signal to each pixel PX through the light emission control line EL.

The second gate driving circuit 140 may be disposed side by side with the first gate driving circuit 130 with the display area DA interposed therebetween. A portion of the pixels PX disposed in the display area DA may be electrically connected to the first gate driving circuit 130, and the rest may be connected to the second gate driving circuit 140. As another embodiment, the second gate driving circuit 140 may be omitted.

The PAD portion PAD may be disposed at one side of the substrate 100. The PAD portion PAD may be exposed without being covered by the insulating layer so as to be electrically connected with the printed circuit substrate PCB. The terminal portion PCB-P of the printed circuit substrate PCB may be electrically connected with the PAD portion PAD of the display panel 10. The printed circuit board PCB transmits a signal or power of a control part (not shown) to the display panel 10.

The control signal generated in the control part may be transmitted to the first and second gate driving circuits 130 and 140 through the printed circuit board PCB, respectively. The control part may supply the first and second power supply voltages to the first and second power supply wirings 160 and 170 through the first and second connection wirings 161 and 171, respectively. The first power supply voltage may be supplied to each pixel PX through a driving voltage line PL connected to the first power supply wiring 160, and the second power supply voltage may be supplied to a counter electrode 330 of each pixel PX connected to the second power supply wiring 170 (see fig. 5 described later).

The data driving circuit 150 is electrically connected to the data lines DL. The data signal of the data driving circuit 150 may be supplied to each pixel PX through a connection wiring 151 connected to the PAD portion PAD and a data line DL connected to the connection wiring 151. Fig. 2 shows that the data driving circuit 150 is disposed on the printed circuit substrate PCB, but as another embodiment, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the PAD portion PAD and the first power supply wiring 160.

The first power supply wiring 160 may include a first sub-wiring 162 and a second sub-wiring 163 extending side by side along the x-direction with the display area DA interposed therebetween. The second power supply wiring 170 may partially surround the display area DA in a ring shape with one side open.

Fig. 3 is an equivalent circuit diagram schematically showing any one pixel of the display panel according to an embodiment of the present invention.

Referring to fig. 3, each pixel PX includes: a pixel circuit PC connected to the scan line SL and the data line DL; and an organic light emitting diode OLED connected to the pixel circuit PC.

The pixel circuit PC includes a driving thin film transistor (driving TFT) T1, a switching thin film transistor (switching TFT) T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to the scan line SL and the data line DL, and transmits a data signal Dm input through the data line DL to the driving thin film transistor T1 according to a scan signal Sn input through the scan line SL.

The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between the voltage received from the switching thin film transistor T2 and the driving voltage ELVDD supplied to the driving voltage line PL.

The driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and controls a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED corresponding to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a predetermined luminance by driving a current.

The case where the pixel circuit PC includes two thin film transistors and one storage capacitor is illustrated in fig. 3, but the present invention is not limited thereto. For example, the pixel circuit PC may include three or more thin film transistors and/or two or more storage capacitors. As an embodiment, the pixel circuit PC may also include seven thin film transistors and one storage capacitor.

Fig. 4 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Referring to fig. 4, the display device 1 (see fig. 1) includes a display unit DU and a color filter unit CU disposed opposite to the display unit DU. The display unit DU may include a first pixel PX1, a second pixel PX2, and a third pixel PX3 disposed on a substrate 100 (hereinafter, referred to as a lower substrate). The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be pixels that emit light of colors different from each other, respectively, on the lower substrate 100. For example, the first pixel PX1 may emit red light Lr, the second pixel PX2 may emit green light Lg, and the third pixel PX3 may emit blue light Lb.

The first pixel PX1, the second pixel PX2, and the third pixel PX3 may respectively include a first light emitting element 300a, a second light emitting element 300b, and a third light emitting element 300c including an organic light emitting diode OLED. As an example, the first light emitting element 300a, the second light emitting element 300b, and the third light emitting element 300c may emit blue light. As another example, the first light emitting element 300a, the second light emitting element 300b, and the third light emitting element 300c may emit red light Lr, green light Lg, and blue light Lb, respectively.

The color filter unit CU may include filter parts 500a, 500b, 500 c. The light emitted from the first light-emitting element 300a, the second light-emitting element 300b, and the third light-emitting element 300c can pass through the filter portions 500a, 500b, and 500c and be emitted as red light Lr, green light Lg, and blue light Lb, respectively.

The filter parts 500a, 500b, and 500c may be directly located on the upper substrate 200. The filter portions 500a, 500b, and 500c may include a first quantum dot layer 220a and a first filter layer 210a, a second quantum dot layer 220b and a second filter layer 210b, and a transmission layer 220c and a third filter layer 210c, respectively, which will be described later in fig. 18.

In this case, the phrase "directly on the upper substrate 200" may mean that the first filter layer 210a, the second filter layer 210b, and the third filter layer 210c are directly formed on the upper substrate 200 to manufacture the color filter unit CU. After that, the display unit DU and the color filter unit CU may be joined with the first, second, and third filter layers 210a, 210b, and 210c facing the first, second, and third pixels PX1, PX2, and PX3, respectively.

In fig. 4, the display unit DU and the color filter unit CU are shown joined by an adhesive layer ADH. The Adhesive layer ADH may be, for example, an Optically Clear Adhesive (OCA), but is not necessarily limited thereto. As another embodiment, the adhesive layer ADH may be omitted.

Although fig. 4 shows that the filter units 500a, 500b, and 500c are disposed on the upper substrate 200, the filter units 500a, 500b, and 500c may be disposed on the display unit DU.

For example, the filter portions 500a, 500b, and 500c may be disposed on a film sealing layer 400 shown in fig. 18 described later. The thin film encapsulation layer 400 may be provided with a first quantum dot layer 220a, a second quantum dot layer 220b, a transmission layer 220c, a first filter layer 210a, a second filter layer 210b, and a third filter layer 210 c. First, the first quantum dot layer 220a, the second quantum dot layer 220b, and the transmission layer 220c are disposed on the thin film encapsulation layer 400, and then the first filter layer 210a, the second filter layer 210b, and the third filter layer 210c are disposed on the first quantum dot layer 220a, the second quantum dot layer 220b, and the transmission layer 220c, respectively.

As shown in fig. 4, the display device 1 may include a lower substrate 100 and an upper substrate 200. The number of substrates included in the display device 1 may be two. As another example, the display device 1 may include only the lower substrate 100 without including the upper substrate 200. In this case, the filter portions 500a, 500b, and 500c may be disposed on the lower substrate 100. The number of substrates included in the display device 1 may be one.

Fig. 5 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Referring to fig. 5, the display device 1 (refer to fig. 1) includes: a thin film transistor TFT disposed on the substrate 100 corresponding to the display area DA; and a PAD portion PAD disposed on the substrate 100 corresponding to the peripheral area PA. As an insulating layer which is disposed on the thin film transistor TFT and exposes the PAD portion PAD, a planarization layer 117 is included, and the planarization layer 117 includes a first portion 117a and a second portion 117b which extends from the first portion 117a to one side. At this time, the planarization layer 117 may have a step (step) ST between the first and second portions 117a and 117b on the upper surface.

Hereinafter, referring to fig. 5, the structure included in the display device 1 will be described more specifically based on the stacked structure.

The substrate 100 may include a glass material, a ceramic material, a metal material, or a substance having a flexible or bendable characteristic. In the case where the substrate 100 has a flexible or bendable characteristic, the substrate 100 may include a polymer resin such as polyethersulfone (polyethersulfone), polyacrylate (polyacrylate), polyetherimide (polyetherimide), polyethylene naphthalate (polyethylene naphthalate), polyethylene terephthalate (polyethylene terephthalate), polyphenylene sulfide (polyphenylene sulfide), polyarylate (polyarylate), polyimide (polyimide), polycarbonate (polycarbonate), or cellulose acetate propionate (cellulose acetate propionate).

The substrate 100 may have a single layer or a multi-layer structure of the substance, and may further include an inorganic layer in the case of the multi-layer structure. In some embodiments, the substrate 100 may have an organic/inorganic/organic structure.

The buffer layer 111 may reduce or prevent penetration of foreign substances, moisture, or external gas from below the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic substance such as an oxide or a nitride, an organic substance, or an organic-inorganic composite, and may have a single-layer or multi-layer structure of an inorganic substance and an organic substance.

A barrier layer (not shown) may be further included between the substrate 100 and the buffer layer 111. The barrier layer may function to prevent or minimize the penetration of impurities from the substrate 100 or the like into the semiconductor layer a. The barrier layer may include an inorganic substance such as an oxide or a nitride, an organic substance, or an organic-inorganic composite, and may be formed in a single layer or a multilayer structure of an inorganic substance and an organic substance.

The semiconductor layer a may be disposed on the buffer layer 111. The semiconductor layer a may include an oxide semiconductor material. The semiconductor layer a may include, for example, an oxide of one or more substances selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

For example, the semiconductor layer a may be an ITZO (InSnZnO; indium tin zinc oxide) semiconductor layer, an IGZO (InGaZnO; indium gallium zinc oxide) semiconductor layer, or the like. Since an oxide semiconductor has a wide band gap (about 3.1eV), high carrier mobility (high carrier mobility), and low leakage current, there is an advantage that a voltage drop is not large even if a driving time is long, and a luminance change due to the voltage drop is not large even in low-frequency driving.

The semiconductor layer a may include a channel region C and source and drain regions S and D respectively disposed at one side and the other side of the channel region C. The semiconductor layer a may be formed in a single layer or a plurality of layers.

A conductive layer BML may be disposed between the substrate 100 and the buffer layer 111. The conductive layer BML may be configured to overlap the channel region C of the semiconductor layer a. The conductive layer BML may include a conductive substance containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or a single layer including the material. For example, the conductive layer BML may have a multilayer structure of Ti/Al/Ti.

The conductive layer BML may be provided so as to overlap with the semiconductor layer a including an oxide semiconductor material. Since the semiconductor layer a containing the oxide semiconductor material has a characteristic of being hardly sensitive to light, the conductive layer BML can prevent the element characteristics of the thin film transistor TFT containing the oxide semiconductor material from changing due to a photocurrent induced in the semiconductor layer a by external light incident from the substrate 100 side. In addition, the conductive layer BML may be connected to the drain region D. Although the conductive layer BML is shown in fig. 5 as being connected to the drain region D, the conductive layer BML may be connected to the source region S.

A gate insulating layer 113 may be disposed on the semiconductor layer a. The gate insulating layer 113 may include silicon oxide (SiO)₂) Silicon nitride (SiN)_X) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO)₂) And the like.

As shown in fig. 5, the gate insulating layer 113 may be patterned to overlap a portion of the semiconductor layer a. That is, the gate insulating layer 113 may be patterned to expose the source and drain regions S and D.

A region where the gate insulating layer 113 and the semiconductor layer a overlap may be understood as a channel region C. The source region S and the drain region D are subjected to a conductor-making process using plasma treatment or the like, and at this time, a portion overlapping with the gate insulating layer 113 in the semiconductor layer a (i.e., the channel region C) has different properties from those of the source region S and the drain region D without being exposed to the plasma treatment. That is, by using the gate electrode G located above the gate insulating layer 113 at the time of plasma treatment of the semiconductor layer a as a self-alignment (self alignment) mask, a channel region C where no plasma treatment is performed may be formed at a position overlapping with the gate insulating layer 113, and a source region S and a drain region D where plasma treatment is performed may be formed on both sides of the channel region C, respectively.

As another embodiment, the gate insulating layer 113 may be disposed on the entire surface of the substrate 100 so as to cover the semiconductor layer a without being patterned to overlap a portion of the semiconductor layer a.

A gate electrode G may be disposed on the gate insulating layer 113 to overlap at least a portion of the semiconductor layer a. In addition, the first electrode CE1 of the storage capacitor Cst and the auxiliary pad electrode SPE may be disposed on the gate insulating layer 113. The gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE may be formed in a single layer or a plurality of layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

In an embodiment, the storage capacitor Cst may be disposed with the first electrode CE1 and the second electrode CE2 and exist separately without overlapping the thin film transistor TFT as shown in fig. 5. Unlike this, the storage capacitor Cst may overlap the thin film transistor TFT. For example, the gate electrode G of the thin film transistor TFT may perform a function as the first electrode CE1 of the storage capacitor Cst.

An interlayer insulating layer 115 may be provided to cover the semiconductor layer a, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE. The interlayer insulating layer 115 may include silicon oxide (SiO)₂) Silicon nitride (SiN)_X) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO)₂) And the like.

A source electrode, a drain electrode, a data line (not shown), a second electrode CE2 of the storage capacitor Cst, a pad electrode PE, and the like may be disposed above the interlayer insulating layer 115.

The source electrode, the drain electrode, the data line, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multi-layer or a single layer including the material. As an example, the source electrode, the drain electrode, the data line, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be formed in a multi-layer structure of Ti/Al/Ti. As another example, the source electrode, the drain electrode, the data line, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be formed in a multilayer structure of Ti/Cu.

The source electrode and the drain electrode can be connected to the source region S or the drain region D of the semiconductor layer a through the contact hole. In addition, the conductive layer BML and the source region S or the drain region D of the semiconductor layer a may be connected through contact holes formed in the buffer layer 111 and the interlayer insulating layer 115.

The second electrode CE2 of the storage capacitor Cst interposes the interlayer insulating layer 115 to overlap the first electrode CE1, and forms a capacitance. In this case, the interlayer insulating layer 115 may function as a dielectric layer of the storage capacitor Cst.

The pad electrode PE may be connected to the auxiliary pad electrode SPE through a contact hole formed in the interlayer insulating layer 115. The contact holes connecting the pad electrode PE and the auxiliary pad electrode SPE are shown as three in fig. 5, but may be more or less than this. In addition, the auxiliary pad electrode SPE is illustrated in fig. 5, but the auxiliary pad electrode SPE may be omitted.

An electrode protection layer EPL may be disposed on the source electrode, the drain electrode, and the second electrode CE2 of the storage capacitor Cst, and a pad protection layer PPL may be disposed on the pad electrode PE.

The electrode protection layer EPL and the pad protection layer PPL may be made of a material selected from the group consisting of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), and Indium Oxide (In)₂O₃(ii) a indium oxide), indium gallium oxide (IGO; indium gallium oxide) and zinc aluminum oxide (AZO; aluminum zinc oxide).

The source electrode, the drain electrode, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Thereby, a separate mask for patterning the electrode protection layer EPL and the pad protection layer PPL is not required, and thus the number of masks can be reduced.

The source electrode, the drain electrode, the data line, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be covered by an inorganic protective layer PVX. The inorganic protective layer PVX may be an inorganic insulating film formed with an inorganic material. As the inorganic material, polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, or the like can be used. In addition, the inorganic protective layer PVX may be silicon nitride (SiN)_X) And silicon oxide (SiO)_X) The monolayer film or the multilayer film of (1). The inorganic protection layer PVX may be disposed on the interlayer insulating layer 115 for covering and protectingPartially routed.

The planarization layer 117 is configured to cover the source electrode, the drain electrode, the data line, and the second electrode CE2 of the storage capacitor Cst, and the planarization layer 117 includes a contact hole for connecting the thin film transistor TFT and the pixel electrode 310.

The planarization layer 117 may be formed of a film formed of an organic substance in a single layer or a plurality of layers, and provides a flat upper surface. Such a planarization layer 117 may include Benzocyclobutene (BCB), polyimide (polyimide), Hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or Polystyrene (PS), a general-purpose polymer such as a phenol group-containing polymer derivative, an acrylic polymer, an imide polymer, an aryl ether group polymer, an amide group polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol group polymer, or a mixture thereof, and the like.

The planarization layer 117 may include a first portion 117a disposed on the thin film transistor TFT and a second portion 117b extending to one side from the first portion 117 a. At this time, the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b on the upper surface. That is, the vertical distance d1 from the substrate 100 to the upper face of the first portion 117a and the vertical distance d2 from the substrate 100 to the upper face of the second portion 117b may be different. As an example, as shown in fig. 5, a vertical distance d1 from the substrate 100 to the upper surface of the first portion 117a may be farther than a vertical distance d2 from the substrate 100 to the upper surface of the second portion 117 b.

The planarization layer 117 may be configured to expose the PAD portion PAD. That is, the planarization layer 117 may not be disposed in the peripheral area PA and may not overlap the PAD portion PAD.

As a comparative example, the planarization layer may remain and be disposed in the peripheral region of the display panel. In this case, the remaining planarizing layer in the peripheral region of the display panel may function as a moisture permeation path from the outside, and there is a risk of causing reliability problems such as deterioration of the light emitting element.

Light-emitting element 300 is disposed on planarization layer 117. The light emitting element 300 includes a pixel electrode 310, an intermediate layer 320 including an organic light emitting layer, and a counter electrode 330.

The pixel electrode 310 may be a (semi-) transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 310 may have a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or semitransparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may be formed of a material selected from the group consisting of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), and Indium Oxide (In)₂O₃(ii) a indium oxide), indium gallium oxide (IGO; indium gallium oxide) and zinc aluminum oxide (AZO; aluminum zinc oxide). In some embodiments, as shown in fig. 5, the pixel electrode 310 may have three layers of films. For example, the three-layer film of the pixel electrode 310 may be ITO/Ag/ITO.

In an embodiment, the pixel electrode 310 may be configured to overlap only the first portion 117a of the planarization layer 117. The planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b extending from the first portion 117a on the upper side as previously described. As shown in fig. 5, a step ST may be formed not only in the second portion 117b extending toward the peripheral region PA but also between the second portion 117b and the first portion 117a of the planarization layer 117 extending toward the display region DA. That is, the first portion 117a may correspond to a portion of the planarization layer 117 that is relatively distant in vertical distance from the substrate 100 to the upper surface of the planarization layer 117, and the pixel electrode 310 may be disposed above such first portion 117 a.

A pixel defining film 119 may be disposed on the planarization layer 117. In addition, the pixel defining film 119 may function to prevent an arc or the like from being generated at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310.

The pixel defining film 119 may be formed by spin coating or the like using one or more organic insulating substances selected from the group consisting of polyimide, Polyamide (Polyamide), acrylic resin, benzocyclobutene, and phenol resin.

The intermediate layer 320 may be disposed in an opening formed through the pixel defining film 119 and include an organic light emitting layer. The organic light emitting layer may include an organic material containing a fluorescent or phosphorescent substance emitting red, green, blue or white light. The organic light emitting layer may be a low molecular organic substance or a high molecular organic substance, and functional layers such as a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), and an Electron Injection Layer (EIL) may be selectively disposed under and over the organic light emitting layer.

The counter electrode 330 may be a light transmissive electrode or a reflective electrode. In some embodiments, the counter electrode 330 may be a transparent or semi-transparent electrode and may be formed with a metal thin film having a small work function including Li, Ca, LiF/Al, Ag, Mg, or a compound thereof. Further, ITO, IZO, ZnO or In may be further provided on the metal thin film₂O₃And Transparent Conductive Oxide (TCO) films. The counter electrode 330 may be disposed across the display area DA, and disposed above the intermediate layer 320 and the pixel defining film 119. The counter electrode 330 may be integrally formed in the plurality of light emitting elements 300 to correspond to the plurality of pixel electrodes 310.

Since such organic light emitting elements may be easily damaged by moisture, oxygen, or the like from the outside, an encapsulating layer (not shown) may cover such organic light emitting elements to protect them. Such encapsulation layers may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

Fig. 6a and 6b are sectional views schematically showing a display device according to an embodiment of the present invention. In fig. 6a and 6b, the same reference numerals as in fig. 5 denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 6a, the display device 1 includes: a thin film transistor TFT and a storage capacitor Cst disposed on the substrate 100 corresponding to the display area DA; and a PAD portion PAD disposed on the substrate 100 corresponding to the peripheral area PA.

Different from FIG. 5As shown in fig. 6a, a pad connection electrode PCE may be disposed on the pad electrode PE. The pad connection electrode PCE may include Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), and Indium Oxide (In)₂O₃(ii) a indium oxide), indium gallium oxide (IGO; indium gallium oxide) and zinc aluminum oxide (AZO; aluminum zinc oxide). The pad connection electrode PCE may contain the same substance as at least a portion of the pixel electrode 310. In one embodiment, the pixel electrode 310 may have a three-layer film, and the pad connecting electrode PCE may have a single-layer film. For example, the three-layer film of the pixel electrode 310 may be ITO/Ag/ITO, and the single-layer film of the pad connecting electrode PCE may be ITO.

The pad connection electrode PCE may be in contact with at least a portion of the pad electrode PE. The inorganic protective layer PVX may be formed with a contact hole CNT exposing at least a part of the pad electrode PE, and a part of the pad connection electrode PCE may be in contact with the pad electrode PE in the contact hole CNT. In an embodiment, as shown in fig. 6a, the width W2 of the pad connection electrode PCE along one direction may be wider than the width W1 of the pad electrode PE exposed through the contact hole CNT.

As described in fig. 2, the PAD portion PAD and the terminal portion PCB-P of the printed circuit substrate PCB may be electrically connected. In this case, the contact width of the PAD portion PAD and the terminal portion PCB-P is increased from the width W1 of the PAD electrode PE exposed through the contact hole CNT to the width W2 of the PAD connection electrode PCE. That is, an area where the PAD portion PAD and the terminal portion PCB-P can contact increases. Therefore, the contact failure between the PAD portion PAD and the terminal portion PCB-P can be reduced, and the risk of the occurrence of failure when the display device 1 is driven can be reduced.

An insulating layer 118 disposed on the inorganic protective layer PVX corresponding to the peripheral area PA and including the same material as the planarization layer 117 may be further included.

The insulating layer 118 may be disposed between the pad electrode PE and the pad connection electrode PCE, and may overlap at least a portion of the pad connection electrode PCE. The surface of the insulating layer 118 overlapping the pad connection electrode PCE may have an inclination. The surface of the inorganic protective layer PVX parallel to the substrate 100 and the surface of the insulating layer 118 may have a certain angle. In addition, the surface of the pad connection electrode PCE overlapping with the insulating layer 118 may also have an inclination along the insulating layer 118.

Although the electrode protection layer EPL and the PAD protection layer PPL are omitted in fig. 6a, the PAD portion PAD may further include the PAD protection layer PPL disposed between the PAD electrode PE and the PAD connection electrode PCE, as described in fig. 5, with reference to fig. 6 b. In addition, an electrode protection layer EPL may be disposed on the source electrode, the drain electrode, and the second electrode CE2 of the storage capacitor Cst.

The main description has been made only for the display device, but the present invention is not limited to this. For example, a display device manufacturing method for manufacturing such a display device also falls within the scope of the present invention.

Fig. 7a to 7g are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention. Specifically, a cross-sectional view sequentially showing a method of manufacturing a display device according to an embodiment of the present invention is based on fig. 5. In fig. 7a to 7g, the same reference numerals as in fig. 5 denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 7a, first, a conductive layer BML, a buffer layer 111, a semiconductor layer a, a gate insulating layer 113, a gate electrode G, first and second electrodes CE1 and CE2 of a storage capacitor Cst, an auxiliary pad electrode SPE, an interlayer insulating layer 115, an electrode layer E, a pad electrode PE, an electrode protection layer EPL, a pad protection layer PPL, and an inorganic protection layer PVX are sequentially formed on a substrate 100.

The conductive layer BML may be formed by patterning a preliminary-conductive layer (not shown). The pre-conductive layer may include a conductive substance containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or a single layer including the material.

The buffer layer 111 may be made of silicon oxide (SiO)₂) Or silicon nitride (SiN)_X) The film can be formed by a Vapor Deposition method such as Chemical Vapor Deposition (CVD) or sputtering.

The semiconductor layer a may be disposed on the buffer layer 111. The semiconductor layer a may be formed by patterning a preliminary-semiconductor layer (not shown). The preliminary semiconductor layer may be formed of an oxide semiconductor, and may be evaporated by a chemical vapor deposition method.

The gate insulating layer 113 and the gate electrode G may be disposed on the semiconductor layer a, and the gate insulating layer 113, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE may be disposed on the buffer layer 111.

The gate insulating layer 113, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE may be formed by patterning a preliminary-gate insulating layer (not shown) and a preliminary-metal layer (not shown).

The pre-gate insulating layer may be formed of silicon oxide (SiO)₂) Silicon nitride (SiN)_X) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO)₂) And the like, and may be formed by a Vapor Deposition method such as Chemical Vapor Deposition (CVD) or sputtering (sputtering), but is not limited thereto.

The pre-metal layer may be formed in a single layer or a plurality of layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed by a vapor deposition method such as a Chemical Vapor Deposition (CVD), a Plasma Enhanced CVD (PECVD), a Low Pressure CVD (LPCVD), a Physical Vapor Deposition (PVD), a sputtering, or an Atomic Layer Deposition (ALD), but is not limited thereto.

In patterning the preliminary-gate insulating layer, plasma treatment is performed, and a portion of the semiconductor layer a, which is not overlapped with the gate electrode G and is exposed, is subjected to a conductor formation process using the plasma treatment. As a result, the source region S and the drain region D exposed during the plasma treatment become conductive, and the channel region C overlapping with the gate electrode G has a property different from that of the source region S and the drain region D.

An interlayer insulating layer 115 is formed on the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE. After the interlayer insulating layer 115 is formed, contact holes that penetrate the interlayer insulating layer 115 and expose portions of the conductive layer BML, the semiconductor layer a, and the auxiliary pad electrode SPE, respectively, are formed.

An electrode layer E, a second electrode CE2 of the storage capacitor Cst, and a pad electrode PE are formed on the interlayer insulating layer 115. In addition, an electrode protection layer EPL and a pad protection layer PPL are formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE. The electrode layer E, the second electrode CE2 of the storage capacitor Cst, the pad electrode PE, the electrode protection layer EPL, and the pad protection layer PPL may be formed by sequentially depositing a pre-electrode layer (not shown) and a pre-protection layer (not shown) on the entire interlayer insulating layer 115 through a mask process and an etching process. That is, the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Thus, a separate mask for patterning the electrode protection layer EPL and the pad protection layer PPL is not required, and thus the number of masks can be reduced.

An inorganic protective layer PVX is formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE. The inorganic protective layer PVX may be an inorganic insulating film formed using an inorganic material, and may be formed by a vapor deposition method such as a chemical vapor deposition method, a Plasma Enhanced CVD (PECVD), a Low Pressure CVD (LPCVD), a Physical Vapor Deposition (PVD), a sputtering (sputtering), or an Atomic Layer Deposition (ALD), without being limited thereto.

Referring to fig. 7b, a planarization material layer 117' may be disposed on the inorganic protective layer PVX. The planarizing layer 117' may be formed of a film formed of an organic substance or an inorganic substance in a single layer or a plurality of layers. After the formation of the planarized material layer 117', a chemical mechanical polishing may be performed in order to provide a planar upper surface.

The planarizing layer 117 'may include a positive (positive) photoresist, and the planarizing layer 117' may be formed by applying a positive photoresist solution (not shown) on the inorganic protective layer PVX by various methods such as Spin-coating (Spin-coating), spraying, or dipping. Before the planarization material layer 117 'is applied on the upper surface of the inorganic protective layer PVX, a process of polishing (polising) the upper surface of the inorganic protective layer PVX to which the planarization material layer 117' is applied may be additionally performed.

A first mask M1 may be disposed on the planarized material layer 117'. The first mask M1 can adjust the exposure amount applied to the planarized material layer 117' for each region. For example, the fourth area AR4 of the first mask M1 may adjust the amount of exposure (light exposure) applied to the planarized material layer 117' to be small as compared with the second area AR2 and the fifth area AR5 of the first mask M1. In addition, the sixth area AR6 of the first mask M1 can adjust the exposure amount applied to the planarized object layer 117' to be smaller than the second area AR2 and the fifth area AR5 of the first mask M1. For example, the first mask M1 may be a half-tone mask (half-tone mask) or a slit mask (slit mask). In some embodiments, the first area AR1 and the third area AR3 of the first mask M1 may be shielded from exposing the planarized material layer 117'.

The planarized material layer 117 'may be exposed by the first mask M1 with a different exposure amount for each region, and a portion of the planarized material layer 117' may be removed by a developing process (leveling). Since the amount of the removed planarizing layer 117' differs depending on the exposure amount, the planarizing layer 117 having a different thickness for each region can be formed at once. That is, as shown in fig. 7c, the thickness of the planarization layer 117 corresponding to the display area DA may be thicker than the thickness of the planarization layer 117 corresponding to the peripheral area PA. Thereafter, the adhesion degree with the inorganic protective layer PVX may be increased by the hardening and drying process of the planarization layer 117. At this time, the hardening and drying process may include a heat treatment process.

In fig. 7b, the planarized material layer 117 'is exemplified to include a positive photoresist, but the planarized material layer 117' may include a negative photoresist. In this case, the more the exposure amount applied to the planarized substance layer 117 'is, the thicker the thickness of the planarized layer 117 remaining after the developing process is, in contrast to when the planarized substance layer 117' includes a positive photoresist.

Referring to fig. 7c and 7d, a first contact hole CNT1 partially exposing the electrode layer E and a second contact hole CNT2 partially exposing the pad electrode PE are formed in the inorganic protective layer PVX using the patterned planarization layer 117. The first contact hole CNT1 and the second contact hole CNT2 are formed by an etching process of partially etching the inorganic protective layer PVX. As an example, the etching process for partially etching the inorganic protective layer PVX may be dry etching (dry etch). Although not shown in fig. 7d, a portion of the planarization layer 117 may also be removed together to reduce the thickness of the planarization layer 117 as a whole.

Referring to fig. 7e, a pixel electrode 310 is formed over the planarization layer 117. The pixel electrode 310 may be formed by patterning the preliminary-pixel electrode layer 310' (see fig. 8 b). Alternatively, the pre-pixel electrode layer 310' may be entirely evaporated on the planarization layer 117, and after a photoresist pattern PR is formed on the pre-pixel electrode layer 310', the pre-pixel electrode layer 310' may be etched using the photoresist pattern PR. That is, the pixel electrode 310 may be formed by evaporating the preliminary pixel electrode layer 310' and performing a mask process or an etching process. As an example, the etching process may be wet etching (wet etch).

A third contact hole CNT3 partially exposing the electrode layer E is formed in the planarization layer 117, and the pixel electrode 310 may be connected to the thin film transistor TFT through the first contact hole CNT1 and the third contact hole CNT 3.

After the pixel electrode 310 is formed, an etching process for removing the planarization layer 117 of the peripheral area PA may be performed using the photoresist pattern PR without removing the photoresist pattern PR. As an example, the etching process may be dry etching (dry etch).

Referring to fig. 7f, it can be known that the first portion 117a of the planarization layer 117 corresponds to a portion protected by the photoresist pattern PR during the etching process, and the second portion 117b of the planarization layer 117 corresponds to a portion not protected by the photoresist pattern PR during the etching process. The planarization layer 117 may have a step ST between the first and second portions 117a and 117b on the upper surface thereof by the photoresist pattern PR. That is, the vertical distance d1 from the substrate 100 to the upper face of the first portion 117a may be farther than the vertical distance d2 from the substrate 100 to the upper face of the second portion 117 b. In addition, through the etching process, a portion of the photoresist pattern PR may be etched and the thickness t of the photoresist pattern PR is also thinned.

On the other hand, as shown in fig. 7e, the pixel electrode 310 is formed using the photoresist pattern PR as an etching mask, and as shown in fig. 7f, the first portion 117a of the planarization layer 117 is also formed using the photoresist pattern PR as an etching mask, so that the planar shape of the pixel electrode 310 and the planar shape of the first portion 117a all substantially correspond to the planar shape of the photoresist pattern PR. In addition, as shown in fig. 7f, the edge of the pixel electrode 310 and the sidewall of the first portion 117a also correspond to each other.

As a comparative example, an etching process for removing the planarization layer of the peripheral region may be performed before the pixel electrode is formed. In the case where impurities exist on the surface of the planarization layer, a step may be formed between a portion where the impurities exist and a portion where the impurities do not exist at the time of the etching process. When a light-emitting element is disposed on the surface of the planarization layer having a step, a short circuit (short) between the pixel electrode and the counter electrode may be induced, and a dark spot (dark spot) may be generated on the display panel. In addition, the surface of the planarization layer is not protected during the etching process, and thus the surface roughness of the planarization layer may increase. If the pixel electrode is disposed on the surface of the planarization layer having increased roughness, a decrease in reflectance due to external light may occur, and the light emission efficiency may be decreased.

However, as in an embodiment of the present invention, after the pixel electrode 310 is formed, an etching process for removing the planarization layer 117 of the peripheral area PA may be performed without removing the photoresist pattern PR. In this case, the surface of the planarization layer 117 provided with the pixel electrode 310 may be protected by the photoresist pattern PR. Therefore, a step due to the surface impurity of the planarizing layer 117 is not formed, and the surface roughness of the planarizing layer 117 is not increased. That is, dark spots do not occur in the display panel, and the reduction in reflectance due to external light does not occur, so that the light emission efficiency does not decrease. In addition, since the planarizing layer 117 remains in the peripheral region PA by the etching process, a moisture permeation path from the outside is blocked, and the risk of causing reliability problems such as deterioration of the light-emitting element is reduced.

Referring to fig. 7g, after removing the photoresist pattern PR, a pixel defining film 119 covering an edge of the pixel electrode 310 and having an opening exposing a central portion is integrally formed on the planarization layer 117. The pixel defining film 119 may be formed by spin coating or the like using one or more organic insulating substances selected from the group consisting of polyimide, Polyamide (Polyamide), acrylic resin, benzocyclobutene, and phenol resin.

An intermediate layer 320 is formed on the pixel electrode 310, i.e., inside the opening of the pixel defining film 119. The intermediate layer 320 may comprise a low molecular or polymeric substance. The intermediate layer 320 may be formed by a vacuum evaporation method, a screen printing or inkjet printing method, a Laser Induced Thermal Imaging (LITI) method, or the like.

The intermediate layer 320 of the light emitting element 300 may include an organic light emitting layer. The organic light emitting layer may include an organic material containing a fluorescent or phosphorescent substance emitting red, green, blue or white light. The organic light emitting layer may be a low molecular organic substance or a high molecular organic substance, and functional layers such as a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), and an Electron Injection Layer (EIL) may be selectively disposed under and over the organic light emitting layer. The intermediate layer 320 may be configured corresponding to each of the plurality of pixel electrodes 310. However, it is not limited thereto. The intermediate layer 320 may include a layer integrated across the plurality of pixel electrodes 310, and the like, and various modifications may be made.

After that, the counter electrode 330 is formed to correspond to the plurality of light emitting elements 300. The counter electrode 330 may be formed to cover the display area DA of the substrate 100 through an opening mask. The counter electrode 330 can be formed by a vapor deposition method such as a chemical vapor deposition method, a Plasma Enhanced CVD (PECVD), a Low Pressure CVD (LPCVD), a Physical Vapor Deposition (PVD), a sputtering (sputtering), or an Atomic Layer Deposition (ALD).

Fig. 8a to 8g are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention. Specifically, a cross-sectional view sequentially showing a method of manufacturing a display device according to an embodiment of the present invention is based on fig. 5. In fig. 8a to 8g, the same reference numerals as those in fig. 7a to 7g denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 8a, as described in fig. 7b, the planarized material layer 117 'may be exposed by the first mask M1 with an exposure amount different for each region, and a portion of the planarized material layer 117' may be removed by a developing process. Since the amount of the removed planarizing layer 117' differs depending on the exposure amount, the planarizing layer 117 having a different thickness for each region can be formed at once. That is, the planarization layer 117 may be patterned. The first contact hole CNT1 partially exposing the electrode layer E and the second contact hole CNT2 partially exposing the pad electrode PE may be formed on the inorganic protective layer PVX using the patterned planarization layer 117.

Referring to fig. 8b, a pre-pixel electrode layer 310 'and a photoresist layer PR' are sequentially formed on the planarization layer 117.

The photoresist layer PR ' may include a positive photoresist, and the photoresist layer PR ' may be formed by coating a positive photoresist (not shown) on the pre-pixel electrode layer 310' by various methods such as Spin-coating, spraying, or dipping.

A second mask M2 may be disposed on the photoresist layer PR'. The second mask M2 can adjust the exposure amount applied to the photoresist layer PR' for each region. For example, the fourth region AR4 of the second mask M2 may adjust the exposure amount applied to the photoresist layer PR' to be small as compared to the first, third, and fifth regions AR1, AR3, and AR5 of the second mask M2. For example, the second mask M2 may be a half-tone mask (half-tone mask) or a slit mask (slit mask). In some embodiments, the second area AR2 of the second mask M2 may be masked so as not to expose the photoresist layer PR'.

The photoresist layer PR 'may be exposed by the second mask M2 with a different exposure amount per region, and a portion of the photoresist layer PR' may be removed by a developing process. The amount of the photoresist layer PR' removed is different according to the exposure amount, and thus the first photoresist pattern PR1 and the second photoresist pattern PR2 having different thicknesses per region may be formed at one time. That is, as shown in fig. 8c, the thickness t1 of the first photoresist pattern PR1 corresponding to the display area DA may be thicker than the thickness t2 of the second photoresist pattern PR2 corresponding to the peripheral area PA.

In fig. 8b, the photoresist layer PR 'is exemplified to include a positive photoresist, but the photoresist layer PR' may include a negative photoresist. In this case, the more the exposure amount applied to the photoresist layer PR ', the thicker the thickness of the photoresist layer PR ' remaining after the developing process, in contrast to when the photoresist layer PR ' includes a positive photoresist.

Referring to fig. 8c and 8d, a pixel electrode 310 and a pad connection electrode PCE are formed over the planarization layer 117. The pixel electrode 310 and the pad connection electrode PCE may be formed by patterning the preliminary-pixel electrode layer 310'. The pre-pixel electrode layer 310 'is entirely evaporated on the planarization layer 117, and a first photoresist pattern PR1 and a second photoresist pattern PR2 are formed on the pre-pixel electrode layer 310'. At this time, the first photoresist pattern PR1 is disposed in the display area DA, and the second photoresist pattern PR2 is disposed in the peripheral area PA.

Thereafter, the pre-pixel electrode layer 310' is etched using the first and second photoresist patterns PR1 and PR2, respectively, to form the pixel electrode 310 and the pad connecting electrode PCE. That is, the pixel electrode 310 and the pad connecting electrode PCE may be formed by evaporating the preliminary pixel electrode layer 310' through a mask process and an etching process. As an example, the etching process may be wet etching (wet etch).

After the pixel electrode 310 and the pad connection electrode PCE are formed, an etching process for removing the planarization layer 117 of the peripheral area PA is performed using the first and second photoresist patterns PR1 and PR2 without removing the first and second photoresist patterns PR1 and PR 2. As an example, the etching process may be dry etching (dry etch).

Referring to fig. 8e, it can be appreciated that the first portion 117a of the planarization layer 117 corresponds to a portion protected by the first photoresist pattern PR1 during the etching process, and the second portion 117b of the planarization layer 117 corresponds to a portion not protected by the first photoresist pattern PR1 or the second photoresist pattern PR2 during the etching process. The planarization layer 117 may have a step ST between the first and second portions 117a and 117b thereon by the first photoresist pattern PR 1. That is, the vertical distance d1 from the substrate 100 to the upper face of the first portion 117a may be farther than the vertical distance d2 from the substrate 100 to the upper face of the second portion 117 b. In addition, a portion of the first photoresist pattern PR1 is etched through the etching process, and the thickness t1 of the first photoresist pattern PR1 may also be thinned.

A portion of the third portion 117c of the planarization layer 117 corresponding to the peripheral area PA, which is not protected by the second photoresist pattern PR2, is removed. In contrast, a portion of the third portion 117c of the planarization layer 117 corresponding to the peripheral area PA, which is protected by the second photoresist pattern PR2, remains. In addition, as shown in fig. 8e, the second photoresist pattern PR2 may be entirely etched and removed during the etching process. That is, the step of partially etching the third portion 117c of the planarization layer 117 and the step of removing the second photoresist pattern PR2 may be simultaneously performed.

As a comparative example, an etching process for removing the planarization layer of the peripheral region may be performed before the pixel electrode is formed. In the case where the impurity exists on the surface of the planarization layer, a step may be formed between a portion where the impurity exists and a portion where the impurity does not exist at the time of the etching process. When a light-emitting element is disposed on the surface of the planarization layer having a step, a short circuit (short) between the pixel electrode and the counter electrode may be induced, and a dark spot (dark spot) may be generated on the display panel. In addition, the surface of the planarization layer is not protected during the etching process, and thus the surface roughness of the planarization layer may increase. If the pixel electrode is disposed on the surface of the planarization layer having increased roughness, a decrease in reflectance due to external light may occur, and the light emission efficiency may be decreased.

However, as in an embodiment of the present invention, after the pixel electrode 310 is formed, an etching process for removing the planarization layer 117 in the peripheral area PA may be performed without removing the first and second photoresist patterns PR1 and PR 2. In this case, the surface of the planarization layer 117 where the pixel electrode 310 is disposed may be protected by the first photoresist pattern PR 1. Therefore, a step due to the surface impurity of the planarizing layer 117 is not formed, and the surface roughness of the planarizing layer 117 is not increased. That is, dark spots do not occur in the display panel, and the reduction in reflectance due to external light does not occur, so that the light emission efficiency does not decrease. In addition, since the planarizing layer 117 remains in the peripheral region PA by the etching process, a moisture permeation path from the outside is blocked, and the risk of causing reliability problems such as deterioration of the light-emitting element is reduced.

Thereafter, the etching process may be performed in a state where the first photoresist pattern PR1 is not removed. As an example, the etching process may be wet etching (wet etch).

Referring to fig. 8f, the remaining two films of the pad connecting electrode PCE formed as a three-layered film except for the film adjacent to the pad electrode PE may be removed by an etching process. The pad connection electrode PCE may be a single-layer film.

As a comparative example, the pad connection electrode may be held as a three-layer film. In the case where the pad connection electrode is a three-layer film, it may be formed of ITO/Ag/ITO. The pad connection electrode may be exposed without being covered by the insulating layer. In this case, silver (Ag) having a high reaction rate is exposed to risk of short-circuiting with an adjacent electrode.

However, in the case of removing two of the three films of the pad connection electrode PCE as in one embodiment of the present invention, only ITO is present in the exposed pad connection electrode PCE, and the risk of short-circuiting with the adjacent electrode disappears.

In an embodiment, as shown in fig. 8f, the width W2 of the pad connection electrode PCE along one direction may be wider than the width W1 of the pad electrode PE exposed through the second contact hole CNT 2. In this case, as described in fig. 6a, an area where the PAD portion PAD and the terminal portion PCB-P can contact is increased. Therefore, the contact failure between the PAD portion PAD and the terminal portion PCB-P can be reduced, and the risk of the occurrence of failure during driving of the display device 1 can be reduced.

Referring to fig. 8g, after removing the first photoresist pattern PR1, a pixel defining film 119 covering an edge of the pixel electrode 310 and having an opening exposing a central portion is integrally formed on the planarization layer 117. The pixel defining film 119 may be formed by spin coating or the like using one or more organic insulating substances selected from the group consisting of polyimide, Polyamide (Polyamide), acrylic resin, benzocyclobutene, and phenol resin.

An intermediate layer 320 is formed on the pixel electrode 310, i.e., inside the opening of the pixel defining film 119. The intermediate layer 320 may comprise a low molecular or polymeric substance. The intermediate layer 320 may be formed by a vacuum evaporation method, a screen printing or inkjet printing method, a Laser Induced Thermal Imaging (LITI) method, or the like.

The intermediate layer 320 of the light emitting element 300 may include an organic light emitting layer. The organic light emitting layer may include an organic material containing a fluorescent or phosphorescent substance emitting red, green, blue or white light. The organic light emitting layer may be a low molecular organic substance or a high molecular organic substance, and functional layers such as a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), and an Electron Injection Layer (EIL) may be selectively disposed under and over the organic light emitting layer. The intermediate layer 320 may be configured corresponding to each of the plurality of pixel electrodes 310. However, it is not limited thereto. The intermediate layer 320 may include a layer integrated across the plurality of pixel electrodes 310, and the like, and various modifications may be made.

After that, the counter electrode 330 is formed to correspond to the plurality of light emitting elements 300. The counter electrode 330 may be formed to cover the display area DA of the substrate 100 through an opening mask. The counter electrode 330 can be formed by a vapor deposition method such as a chemical vapor deposition method, a Plasma Enhanced CVD (PECVD), a Low Pressure CVD (LPCVD), a Physical Vapor Deposition (PVD), a sputtering (sputtering), or an Atomic Layer Deposition (ALD).

Fig. 9 is a sectional view briefly showing a display device according to an embodiment of the present invention.

Referring to fig. 9, the display device 1 (refer to fig. 1) includes: a thin film transistor TFT disposed on the substrate 100 corresponding to the display area DA; and a PAD portion PAD disposed on the substrate 100 corresponding to the peripheral area PA. As an insulating layer which is disposed on the thin film transistor TFT and exposes the PAD portion PAD, a planarization layer 117 is included, and the planarization layer 117 includes a first portion 117a and a second portion 117b which extends from the first portion 117a to one side. At this time, the planarization layer 117 may have a step (step) ST between the first and second portions 117a and 117b on the upper surface.

A pixel defining film 119 may be disposed on the planarization layer 117. At this time, the side of the planarization layer 117 and the side of the pixel defining film 119 may be etched surfaces of the same plane. The side of the first portion 117a of the planarization layer 117 and the side of the pixel defining film 119 may be the same etched face.

Hereinafter, referring to fig. 9, the structure included in the display device 1 will be described more specifically based on the stacked structure.

The substrate 100 may include a glass material, a ceramic material, a metal material, or a substance having a flexible or bendable characteristic. The substrate 100 may have a single layer or a multi-layer structure, and may further include an inorganic layer in the case of the multi-layer structure. In some embodiments, the substrate 100 may have an organic/inorganic/organic structure.

The buffer layer 111 may reduce or prevent penetration of foreign substances, moisture, or external gas from below the substrate 100, and may provide a flat surface on the substrate 100.

A barrier layer (not shown) may be further included between the substrate 100 and the buffer layer 111. The barrier layer may function to prevent or minimize the penetration of impurities from the substrate 100 or the like into the semiconductor layer a.

The semiconductor layer a may be disposed on the buffer layer 111. The semiconductor layer a may include an oxide semiconductor material. The semiconductor layer a may include, for example, an oxide of one or more substances selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

For example, the semiconductor layer a may be an itzo (insnzno) semiconductor layer, an igzo (ingazno) semiconductor layer, or the like. Since an oxide semiconductor has a wide band gap (about 3.1eV), high carrier mobility (high carrier mobility), and low leakage current, there is an advantage that a voltage drop is not large even if a driving time is long, and a luminance change due to the voltage drop is not large even in low-frequency driving.

The semiconductor layer a may include a channel region C and source and drain regions S and D respectively disposed at one side and the other side of the channel region C. The semiconductor layer a may be formed in a single layer or a plurality of layers.

A conductive layer BML may be disposed between the substrate 100 and the buffer layer 111. The conductive layer BML may be configured to overlap the channel region C of the semiconductor layer a.

The conductive layer BML may be provided so as to overlap with the semiconductor layer a including an oxide semiconductor material. Since the semiconductor layer a containing the oxide semiconductor material has a characteristic of being hardly sensitive to light, the conductive layer BML can prevent the element characteristics of the thin film transistor TFT containing the oxide semiconductor material from changing due to a photocurrent induced in the semiconductor layer a by external light incident from the substrate 100 side. In addition, the conductive layer BML may be connected to the drain region D. Although the conductive layer BML is shown in fig. 9 as being connected to the drain region D, the conductive layer BML may be connected to the source region S.

A gate insulating layer 113 may be disposed on the semiconductor layer a. The gate insulating layer 113 may include silicon oxide (SiO)₂) Silicon nitride (SiN)_X) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO)₂) And the like.

As shown in fig. 9, the gate insulating layer 113 may be patterned to overlap a portion of the semiconductor layer a. That is, the gate insulating layer 113 may be patterned to expose the source and drain regions S and D.

A region where the gate insulating layer 113 and the semiconductor layer a overlap may be understood as a channel region C. The source region S and the drain region D are subjected to a conductor-making process using plasma treatment or the like, and at this time, a portion overlapping with the gate insulating layer 113 in the semiconductor layer a (i.e., the channel region C) has different properties from those of the source region S and the drain region D without being exposed to the plasma treatment. That is, by using the gate electrode G located above the gate insulating layer 113 at the time of plasma treatment of the semiconductor layer a as a self-alignment (self alignment) mask, a channel region C where no plasma treatment is performed may be formed at a position overlapping with the gate insulating layer 113, and a source region S and a drain region D where plasma treatment is performed may be formed on both sides of the channel region C, respectively.

As another embodiment, the gate insulating layer 113 may be disposed on the entire surface of the substrate 100 so as to cover the semiconductor layer a without being patterned to overlap a portion of the semiconductor layer a.

The gate electrode G may be disposed on the gate insulating layer 113 to overlap at least a portion of the semiconductor layer a. In addition, the first electrode CE1 of the storage capacitor Cst and the auxiliary pad electrode SPE may be disposed on the gate insulating layer 113.

In an embodiment, the storage capacitor Cst may be disposed with the first electrode CE1 and the second electrode CE2 and exist separately without overlapping the thin film transistor TFT as shown in fig. 9. Unlike this, the storage capacitor Cst may overlap the thin film transistor TFT. For example, the gate electrode G of the thin film transistor TFT may perform a function as the first electrode CE1 of the storage capacitor Cst.

An interlayer insulating layer 115 may be provided to cover the semiconductor layer a, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE.

A source electrode, a drain electrode, a data line (not shown), a second electrode CE2 of the storage capacitor Cst, a pad electrode PE, and the like may be disposed above the interlayer insulating layer 115.

The source electrode and the drain electrode can be connected to the source region S or the drain region D of the semiconductor layer a through the contact hole. In addition, the conductive layer BML and the source region S or the drain region D of the semiconductor layer a may be connected through contact holes formed in the buffer layer 111 and the interlayer insulating layer 115.

The second electrode CE2 of the storage capacitor Cst interposes the interlayer insulating layer 115 to overlap the first electrode CE1, and forms a capacitance. In this case, the interlayer insulating layer 115 may function as a dielectric layer of the storage capacitor Cst.

The pad electrode PE may be connected to the auxiliary pad electrode SPE through a contact hole formed in the interlayer insulating layer 115. The contact holes connecting the pad electrode PE and the auxiliary pad electrode SPE are shown as three in fig. 9, but may be more or less than this. In addition, the auxiliary pad electrode SPE is shown in fig. 9, but the auxiliary pad electrode SPE may be omitted.

An electrode protection layer EPL may be disposed on the source electrode, the drain electrode, and the second electrode CE2 of the storage capacitor Cst, and a pad protection layer PPL may be disposed on the pad electrode PE.

The source electrode, the drain electrode, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Thereby, a separate mask for patterning the electrode protection layer EPL and the pad protection layer PPL is not required, and thus the number of masks can be reduced.

The source electrode, the drain electrode, the data line, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be covered by an inorganic protective layer PVX.

The planarization layer 117 is configured to cover the source electrode, the drain electrode, the data line, and the second electrode CE2 of the storage capacitor Cst, and the planarization layer 117 includes a contact hole for connecting the thin film transistor TFT and the pixel electrode 310.

The planarization layer 117 may be formed of a film formed of an organic substance in a single layer or a plurality of layers, and provides a flat upper surface.

The planarization layer 117 may include a first portion 117a disposed on the thin film transistor TFT and a second portion 117b extending to one side from the first portion 117 a. At this time, the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b on the upper surface. That is, the vertical distance d1 from the upper face of the substrate 100 to the upper face of the first portion 117a and the vertical distance d2 from the upper face of the substrate 100 to the upper face of the second portion 117b may be different. As an example, as shown in fig. 9, a vertical distance d1 from the upper surface of the substrate 100 to the upper surface of the first portion 117a may be farther than a vertical distance d2 from the upper surface of the substrate 100 to the upper surface of the second portion 117 b.

The planarization layer 117 may be configured to expose the PAD portion PAD. That is, the planarization layer 117 may not be disposed in the peripheral area PA and may not overlap the PAD portion PAD.

As a comparative example, the planarization layer may remain and be disposed in the peripheral region of the display panel. In this case, the remaining planarizing layer in the peripheral region of the display panel may function as a moisture permeation path from the outside, and there is a risk of causing reliability problems such as deterioration of the light emitting element.

Light-emitting element 300 is disposed on planarization layer 117. The light emitting element 300 includes a pixel electrode 310, an intermediate layer 320 including an organic light emitting layer, and a counter electrode 330.

In an embodiment, the pixel electrode 310 may be configured to overlap only the first portion 117a of the planarization layer 117. The planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b extending from the first portion 117a on the upper side as previously described. As shown in fig. 9, a step ST may be formed not only in the second portion 117b extending toward the peripheral region PA but also between the second portion 117b and the first portion 117a of the planarization layer 117 extending toward the display region DA. That is, the first portion 117a may correspond to a portion of the planarization layer 117 that is relatively distant in vertical distance from the substrate 100 to the upper surface of the planarization layer 117, and the pixel electrode 310 may be disposed above such first portion 117 a.

A pixel defining film 119 may be disposed on the planarization layer 117. The pixel defining film 119 may cover an edge of the pixel electrode 310 and have an opening exposing a portion of the pixel electrode 310. The pixel defining film 119 may function to prevent an arc or the like from being generated at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310.

In one embodiment, as shown in fig. 9, the planarization layer 117 and the pixel defining film 119 may have the same etched surface s, s'. As described later in fig. 12g, the planarization layer 117 and the pixel defining film 119 may be simultaneously formed by the same etching process, and may include the same etched faces s, s'. A portion of the planarization layer 117 may be etched using the pixel defining film 119 as a mask, and the outer side of the pixel defining film 119 and the side of the planarization layer 117 may be located on the same etched face s, s'. The outer side of the pixel defining film 119 and the side of the first portion 117a of the planarization layer 117 may be located on the same etched face s, s'.

The outer side of the pixel defining film 119 and the side of the planarization layer 117 may be located on the same plane. The outer side of the pixel defining film 119 and the side of the first portion 117a of the planarization layer 117 may be located on the same plane. The outer side surface of the pixel defining film 119 and the side surface of the planarization layer 117 may be formed without a step. The outer side surface of the pixel defining film 119 and the side surface of the planarization layer 117 may be formed without a boundary.

The pixel defining film 119 may be disposed to overlap the first portion 117a of the planarization layer 117. In a plane, the boundary of the pixel defining film 119 may correspond to the boundary of the first portion 117a of the planarization layer 117.

In the case where the pixel defining film 119 and the first portion 117a of the planarization layer 117 have the same etching surface s, s', the pixel defining film 119 may be disposed corresponding to the first portion 117 a. The pixel defining film 119 may be disposed corresponding to the first portion 117a and not disposed in the second portion 117 b. The pixel defining film 119 may be removed from a portion corresponding to the second portion 117 b. The insulating layer formed of an organic substance may be removed by a value (t + (d1-d2)) that adds the thickness t of the pixel defining film 119 to the step ST of the planarization layer 117. In this case, the pixel defining film 119 and the planarization layer 117 adjacent to the light emitting element 300 are partially removed, so that the volume (volume) of the organic matter inside the display device 1 is reduced, and outgassing of the organic matter can be minimized. Therefore, even if the display device 1 is exposed to sunlight for a long time, decomposition of organic matter due to sunlight can be prevented or minimized, and thus defects such as pixel shrinkage due to outgassing can be prevented. The reliability of the display device 1 can be improved.

The intermediate layer 320 may be disposed in an opening formed through the pixel defining film 119 and include an organic light emitting layer. The organic light emitting layer may include an organic material containing a fluorescent or phosphorescent substance emitting red, green, blue or white light. The organic light emitting layer may be a low molecular organic substance or a high molecular organic substance, and functional layers such as a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), and an Electron Injection Layer (EIL) may be selectively disposed under and over the organic light emitting layer.

The counter electrode 330 may be a light transmissive electrode or a reflective electrode. In some embodiments, the counter electrode 330 may be a transparent or semi-transparent electrode and may be formed with a metal thin film having a small work function including Li, Ca, LiF/Al, Ag, Mg, or a compound thereof. Further, ITO, IZO, ZnO or In may be further provided on the metal thin film₂O₃And Transparent Conductive Oxide (TCO) films. The counter electrode 330 may be disposed across the display area DA, and disposed above the intermediate layer 320 and the pixel defining film 119. The counter electrode 330 may be integrally formed in the plurality of light emitting elements 300 to correspond to the plurality of pixel electrodes 310.

Since such an organic light emitting element is easily damaged by moisture, oxygen, or the like from the outside, the thin film encapsulation layer 400 may cover the organic light emitting element to protect the organic light emitting element as described later in fig. 18. The thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430. As described above, the insulating layer formed of an organic material may be removed from the portion corresponding to the second portion 117b of the planarization layer 117. The organic encapsulation layer 420 may further configure the amount of the insulating layer removed. The thickness of the organic encapsulation layer 420 can be increased by the amount of the insulating layer removed, and thus foreign substances or the like flowing from the outside hardly reach the counter electrode 330. When foreign substances or the like flowing from the outside reach the counter electrode 330, the light-emitting element 300 may be deteriorated, and the organic encapsulating layer 420 having a large thickness can prevent the light-emitting element 300 from being deteriorated. That is, it is possible to prevent the thin film encapsulation layer 400 from being damaged by foreign substances or the like flowing in from the outside and to prevent the light emitting element 300 from being deteriorated due to the damage of the thin film encapsulation layer 400.

Fig. 10 and 11 are sectional views schematically showing a display device according to an embodiment of the present invention. In fig. 10 and 11, the same reference numerals as in fig. 9 denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 10, the display device 1 includes: a thin film transistor TFT and a storage capacitor Cst disposed on the substrate 100 corresponding to the display area DA; and a PAD portion PAD disposed on the substrate 100 corresponding to the peripheral area PA.

Unlike fig. 9, a pad connection electrode PCE may be disposed on the pad electrode PE as shown in fig. 10. The pad connection electrode PCE may include Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), and Indium Oxide (In)₂O₃(ii) a indium oxide), indium gallium oxide (IGO; indium gallium oxide) and zinc aluminum oxide (AZO; aluminum zinc oxide).

The pad connection electrode PCE may contain the same substance as at least a portion of the pixel electrode 310. In one embodiment, the pixel electrode 310 may have a three-layer film, and the pad connecting electrode PCE may have a single-layer film. For example, the three-layer film of the pixel electrode 310 may be ITO/Ag/ITO, and the single-layer film of the pad connecting electrode PCE may be ITO.

The pad connection electrode PCE may be in contact with at least a portion of the pad electrode PE. In fig. 10, it is shown that the pad connection electrode PCE and the pad electrode PE are electrically connected through the pad protection layer PPL, but the pad protection layer PPL may be omitted and the pad connection electrode PCE and the pad electrode PE may be in direct contact. The inorganic protective layer PVX may be formed with a contact hole CNT exposing at least a part of the pad electrode PE, and a part of the pad connection electrode PCE may be in contact with the pad electrode PE in the contact hole CNT. In an embodiment, as shown in fig. 10, the width W2 of the pad connection electrode PCE along one direction may be wider than the width W1 of the pad electrode PE exposed through the contact hole CNT.

As described in fig. 1, the PAD portion PAD may be attached with a printed circuit substrate or a driver IC chip. In this case, the contact width of the PAD portion PAD with the printed circuit substrate or the driver IC chip is increased from the width W1 of the PAD electrode PE exposed through the contact hole CNT to the width W2 of the PAD connection electrode PCE. That is, the area of the PAD portion PAD that can contact the printed circuit substrate or the driver IC chip is increased. Therefore, contact failure between the PAD portion PAD and the printed circuit board or the driver IC chip can be reduced, and the risk of failure occurring when the display device 1 is driven can be reduced.

In an embodiment, as shown in fig. 10, a portion of the pad connection electrode PCE may be in contact with the upper face of the inorganic protective layer PVX. A part of the pad connection electrode PCE may be formed in a shape of the upper surface of the inorganic protective layer PVX in contact with the upper surface of the inorganic protective layer PVX.

In another embodiment, as shown in fig. 11, the display device 1 may further include an insulating layer 118 disposed on the inorganic protective layer PVX corresponding to the peripheral area PA and including the same material as the planarization layer 117.

The insulating layer 118 may be disposed between the pad electrode PE and the pad connection electrode PCE, and may overlap at least a portion of the pad connection electrode PCE. The surface of the insulating layer 118 overlapping the pad connection electrode PCE may have an inclination. The surface of the inorganic protective layer PVX parallel to the substrate 100 and the surface of the insulating layer 118 may have a certain angle. In addition, the surface of the pad connection electrode PCE overlapping with the insulating layer 118 may also have an inclination along the insulating layer 118.

Although the electrode protection layer EPL and the pad protection layer PPL are shown in fig. 10 and 11, the electrode protection layer EPL and the pad protection layer PPL may be omitted.

The main description has been made only for the display device, but the present invention is not limited to this. For example, a display device manufacturing method for manufacturing such a display device also falls within the scope of the present invention.

Fig. 12a to 12h are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention. Specifically, a sectional view sequentially showing a method of manufacturing a display device according to an embodiment of the present invention is based on fig. 9. In fig. 12a to 12h, the same reference numerals as in fig. 9 denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 12a, first, a conductive layer BML, a buffer layer 111, a semiconductor layer a, a gate insulating layer 113, a gate electrode G, first and second electrodes CE1 and CE2 of a storage capacitor Cst, an auxiliary pad electrode SPE, an interlayer insulating layer 115, an electrode layer E, a pad electrode PE, an electrode protection layer EPL, a pad protection layer PPL, and an inorganic protection layer PVX are sequentially formed on a substrate 100.

The conductive layer BML may be formed by patterning a preliminary-conductive layer (not shown). The pre-conductive layer may include a conductive substance containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or a single layer including the material.

The buffer layer 111 may be made of silicon oxide (SiO)₂) Or silicon nitride (SiN)_X) The film can be formed by a Vapor Deposition method such as Chemical Vapor Deposition (CVD) or sputtering.

The semiconductor layer a may be disposed on the buffer layer 111. The semiconductor layer a may be formed by patterning a preliminary-semiconductor layer (not shown). The preliminary semiconductor layer may be formed of an oxide semiconductor, and may be evaporated by a chemical vapor deposition method.

The gate insulating layer 113 and the gate electrode G may be disposed on the semiconductor layer a, and the gate insulating layer 113, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE may be disposed on the buffer layer 111.

The gate insulating layer 113, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE may be formed by patterning a preliminary-gate insulating layer (not shown) and a preliminary-metal layer (not shown).

The pre-gate insulating layer may be formed of silicon oxide (SiO)₂) Silicon nitride (SiN)_X) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO)₂) And the like, and may be formed by a Vapor Deposition method such as Chemical Vapor Deposition (CVD) or sputtering (sputtering), but is not limited thereto.

The pre-metal layer may be formed in a single layer or a plurality of layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed by a vapor deposition method such as a Chemical Vapor Deposition (CVD), a Plasma Enhanced CVD (PECVD), a Low Pressure CVD (LPCVD), a Physical Vapor Deposition (PVD), a sputtering, or an Atomic Layer Deposition (ALD), but is not limited thereto.

In patterning the preliminary-gate insulating layer, plasma treatment is performed, and a portion of the semiconductor layer a, which is not overlapped with the gate electrode G and is exposed, is subjected to a conductor formation process using the plasma treatment. As a result, the source region S and the drain region D exposed during the plasma treatment become conductive, and the channel region C overlapping with the gate electrode G has a property different from that of the source region S and the drain region D.

An interlayer insulating layer 115 is formed on the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE. After the interlayer insulating layer 115 is formed, contact holes that penetrate the interlayer insulating layer 115 and expose portions of the conductive layer BML, the semiconductor layer a, and the auxiliary pad electrode SPE, respectively, are formed.

An electrode layer E, a second electrode CE2 of the storage capacitor Cst, and a pad electrode PE are formed on the interlayer insulating layer 115. In addition, an electrode protection layer EPL and a pad protection layer PPL are formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE. The electrode layer E, the second electrode CE2 of the storage capacitor Cst, the pad electrode PE, the electrode protection layer EPL, and the pad protection layer PPL may be formed by sequentially depositing a pre-electrode layer (not shown) and a pre-protection layer (not shown) on the entire interlayer insulating layer 115 through a mask process and an etching process. That is, the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Thus, a separate mask for patterning the electrode protection layer EPL and the pad protection layer PPL is not required, and thus the number of masks can be reduced.

An inorganic protective layer PVX is formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE. The inorganic protective layer PVX may be an inorganic insulating film formed using an inorganic material, and may be formed by a vapor deposition method such as a chemical vapor deposition method, a Plasma Enhanced CVD (PECVD), a Low Pressure CVD (LPCVD), a Physical Vapor Deposition (PVD), a sputtering (sputtering), or an Atomic Layer Deposition (ALD), without being limited thereto.

After the inorganic protective layer PVX is formed, the first contact hole CNT1 and the second contact hole CNT2 partially exposing the electrode protective layer EPL and the pad protective layer PPL, respectively, may be formed through a separate mask.

Referring to fig. 12b, a planarization material layer 117' may be disposed on the inorganic protective layer PVX. The planarizing layer 117 'may include a positive (positive) photoresist, and the planarizing layer 117' may be formed by applying a positive photoresist solution (not shown) on the inorganic protective layer PVX by various methods such as Spin-coating (Spin-coating), spraying, or dipping. Before the planarization material layer 117 'is applied on the upper surface of the inorganic protective layer PVX, a process of polishing (polising) the upper surface of the inorganic protective layer PVX to which the planarization material layer 117' is applied may be additionally performed.

A first mask M1 may be disposed on the planarized material layer 117'. The first region AR1 and the third region AR3 of the first mask M1 may be shielded from exposing the planarized material layer 117', and the second region AR2 and the fourth region AR4 of the first mask M1 may be shielded from exposing the planarized material layer 117'.

The planarized material layer 117 'may be exposed by the first mask M1 for each region, and a portion of the planarized material layer 117' may be removed by a developing process (leveling) to form the planarized layer 117. The planarization layer 117 may be formed of a film made of an organic substance or an inorganic substance in a single layer or a plurality of layers. The adhesion degree with the inorganic protective layer PVX may be increased by the hardening and drying process of the planarization layer 117. At this time, the hardening and drying process may include a heat treatment process. After the formation of the planarization layer 117, chemical mechanical polishing may be performed in order to provide a planar upper surface.

In fig. 12b, the planarized material layer 117 'is exemplified to include a positive photoresist, but the planarized material layer 117' may include a negative photoresist. In this case, in contrast to when the planarized substance layer 117 'includes a positive photoresist, the exposed region in the planarized substance layer 117' remains after the developing process.

Referring to fig. 12c, the planarization layer 117 may have a third contact hole CNT3 partially exposing the electrode protection layer EPL corresponding to a portion exposed through the second area AR2 of the first mask M1. The planarization layer 117 may be formed to expose the PAD portion PAD corresponding to a portion exposed through the fourth area AR4 of the first mask M1. After the planarization layer 117 is formed, a pixel electrode material layer 310' is formed over the planarization layer 117.

Referring to fig. 12d, a pixel defining film substance layer 119 'is formed over the pixel electrode substance layer 310'. The pixel defining film substance layer 119' may include a positive (positive) photoresist, and the pixel defining film substance layer 119' may be formed by applying a positive photoresist solution on the pixel electrode substance layer 310' by various methods such as Spin-coating, spraying, or dipping.

A second mask M2 may be disposed on the pixel defining film substance layer 119'. The second mask M2 can adjust the exposure amount applied to the pixel defining film substance layer 119' per region. For example, the third area AR3 of the second mask M2 may adjust the amount of exposure (light exposure) applied to the pixel defining film substance layer 119' to be small as compared with the first area AR1 and the fifth area AR5 of the second mask M2. For example, the second mask M2 may be a half-tone mask (half-tone mask) or a slit mask (slit mask). In some embodiments, the second area AR2 and the fourth area AR4 of the second mask M2 may be masked so as not to expose the pixel defining film substance layer 119'.

The pixel defining film substance layer 119 'may be exposed by the second mask M2 with a different exposure amount per region, and a portion of the pixel defining film substance layer 119' may be removed by a developing process. The amount of the pixel defining film substance layer 119' to be removed differs depending on the exposure amount, and therefore, the preliminary pixel defining film 119p having a different thickness for each region can be formed at once.

For example, as shown in fig. 12e, the preliminary pixel defining film 119p may include a first preliminary pixel defining film 119pa and a second preliminary pixel defining film 119pb surrounded by the first preliminary pixel defining film 119 pa. The first preliminary pixel defining film 119pa corresponds to a portion where the pixel defining film substance layer 119 'is not exposed to light and the pixel defining film substance layer 119' is not removed by the second area AR2 and the fourth area AR4 of the second mask M2. The second preliminary pixel defining film 119pb corresponds to a portion where a portion of the pixel defining film substance layer 119 'is removed by applying the adjusted exposure amount to the pixel defining film substance layer 119' through the third area AR3 of the second mask M2. The thickness t1 of the first preliminary pixel defining film 119pa may be thicker than the thickness t2 of the second preliminary pixel defining film 119 pb.

In fig. 12d, the pixel defining film substance layer 119 'includes a positive photoresist as an example, but the pixel defining film substance layer 119' may include a negative photoresist. In this case, the more the exposure amount applied to the pixel defining film substance layer 119' is, the thicker the thickness of the pixel defining film substance layer 119' remaining after the developing process is, contrary to when the pixel defining film substance layer 119' includes a positive photoresist.

Referring to fig. 12e and 12f, the pixel electrode material layer 310 'is etched using the preliminary pixel defining film 119p formed on the pixel electrode material layer 310' to form the pixel electrode 310. That is, the pixel electrode 310 may be formed by evaporating the pixel electrode material layer 310' through a mask process or an etching process. As an example, the etching process may be wet etching (wet etch).

The number of times the etching process is performed may be changed according to the conditions of the etching process. For example, the etching process may include a primary etching process and a secondary etching process. The etching process may be performed two times in total. After one etching process, the pixel electrode substance layer 310' not protected by the preliminary pixel defining film 119p may remain as a single-layer film or a double-layer film. After the secondary etching process, the pixel electrode substance layer 310' not protected by the preliminary pixel defining film 119p may be removed. As another example, the etching process may be performed only once to remove the pixel electrode material layer 310'.

A third contact hole CNT3 partially exposing the electrode layer E is formed in the planarization layer 117, and the pixel electrode 310 may be electrically connected to the thin film transistor TFT through the first contact hole CNT1 and the third contact hole CNT 3.

Referring to fig. 12f, a curing (curing) process of preparing the pixel defining film 119p may be performed. In fig. 12d, after the preliminary pixel defining film 119p is formed, a primary curing process may be performed, and after the pixel electrode 310 is formed, a secondary curing process may be performed. At this time, the primary curing process condition and the secondary curing process condition may be different.

When the curing process of the preliminary pixel defining film 119p is performed under the one-time curing process condition, the preliminary pixel defining film 119p may also have fluidity after the curing process of the preliminary pixel defining film 119 p. Therefore, after the pixel electrode 310 is patterned, if the preliminary pixel defining film 119p is subjected to the secondary curing process by changing the curing process conditions, the preliminary pixel defining film 119p surrounds the side surface of the pixel electrode 310 as shown in fig. 12 g. Through the curing process, the preliminary pixel defining film 119p is reflowed (reflow) by a portion to surround the side of the pixel electrode 310. The side surface of the pixel electrode 310 is not exposed to the outside through the preliminary pixel defining film 119p, and thus silver (Ag) having strong reducibility included in the pixel electrode 310 can be prevented from reacting with external particles.

Referring to fig. 12g and 12h, in order to expose a portion of the pixel electrode 310, an etching process of removing the second preliminary pixel defining film 119pb is performed. The second preliminary pixel defining film 119pb may be removed from the preliminary pixel defining film 119p to form a pixel defining film 119. As an example, the etching process may be dry etching (dry etch).

It is noted that the first portion 117a of the planarization layer 117 corresponds to a portion protected by the preliminary pixel defining film 119p at the time of the etching process, and the second portion 117b of the planarization layer 117 corresponds to a portion not protected by the preliminary pixel defining film 119p at the time of the etching process. By preparing the pixel defining film 119p, the upper face of the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117 b.

When the second preliminary pixel defining film 119pb is etched, the first preliminary pixel defining film 119pa and the first portion 117a of the planarizing layer 117 may be partially etched together. As a result, the planarization layer 117 and the pixel defining film 119 may have the same etched faces s, s'. The outer side of the pixel defining film 119 and the side of the planarization layer 117 may be located on the same etched face s, s'.

On the other hand, as shown in fig. 12f, the pixel electrode 310 is formed using the preliminary pixel defining film 119p as an etching mask, and as shown in fig. 12g and 12h, the first portion 117a of the planarization layer 117 is also formed using the preliminary pixel defining film 119p as an etching mask, so that the planar shape of the pixel electrode 310 and the planar shape of the first portion 117a all substantially correspond to the planar shape of the pixel defining film 119. In addition, as shown in fig. 12h, the edge of the pixel electrode 310 and the sidewall of the first portion 117a also correspond to each other. The edge of the pixel electrode 310 and the sidewall of the pixel defining film 119 also correspond to each other.

Referring to fig. 12h, an intermediate layer 320 is formed on the pixel electrode 310, i.e., inside the opening of the pixel defining film 119. The intermediate layer 320 may comprise a low molecular or polymeric substance. The intermediate layer 320 may be formed by a vacuum evaporation method, a screen printing or inkjet printing method, a Laser Induced Thermal Imaging (LITI) method, or the like.

The intermediate layer 320 of the light emitting element 300 may include an organic light emitting layer. The organic light emitting layer may include an organic material containing a fluorescent or phosphorescent substance emitting red, green, blue or white light. The organic light emitting layer may be a low molecular organic substance or a high molecular organic substance, and functional layers such as a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), and an Electron Injection Layer (EIL) may be selectively disposed under and over the organic light emitting layer. The intermediate layer 320 may be configured corresponding to each of the plurality of pixel electrodes 310. However, it is not limited thereto. The intermediate layer 320 may include a layer integrated across the plurality of pixel electrodes 310, and the like, and various modifications may be made.

After that, the counter electrode 330 is formed to correspond to the plurality of light emitting elements 300. The counter electrode 330 may be formed to cover the display area DA of the substrate 100 through an opening mask. The counter electrode 330 can be formed by a vapor deposition method such as a chemical vapor deposition method, a Plasma Enhanced CVD (PECVD), a Low Pressure CVD (LPCVD), a Physical Vapor Deposition (PVD), a sputtering (sputtering), or an Atomic Layer Deposition (ALD).

Fig. 13a to 13g are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention. Specifically, a sectional view sequentially showing a method of manufacturing a display device according to an embodiment of the present invention is based on fig. 10. In fig. 13a to 13g, the same reference numerals as in fig. 10 denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 13a, a pixel electrode material layer 310 'and a pixel defining material layer 119' are sequentially formed over the planarization layer 117. Before the pixel electrode material layer 310 'and the pixel defining film material layer 119' are sequentially formed, the formation process of the thin film transistor TFT, the pad electrode PE, the planarization layer 117, and the like may be the same as that of fig. 12a and 12 b.

A third mask M3 may be disposed on the pixel defining film substance layer 119'. The third mask M3 can adjust the exposure amount applied to the pixel defining film substance layer 119' per region. For example, the third area AR3 and the sixth area AR6 of the third mask M3 may adjust the exposure amount applied to the pixel defining film substance layer 119' to be smaller than the first area AR1, the fifth area AR5, and the seventh area AR7 of the third mask M3. The third area AR3 of the third mask M3 can adjust the exposure amount applied to the pixel defining film substance layer 119' to be small as compared with the sixth area AR6 of the third mask M3. The exposure amount applied to the pixel defining film substance layer 119' corresponding to the third area AR3 of the third mask M3 may be minimized. For example, the third mask M3 may be a half-tone mask (half-tone mask) or a slit mask (slit mask). In some embodiments, the second area AR2 and the fourth area AR4 of the third mask M3 may be shielded from exposing the pixel defining film substance layer 119'.

The pixel defining film substance layer 119 'may be exposed by the third mask M3 with a different exposure amount per region, and a portion of the pixel defining film substance layer 119' may be removed by a developing process. The amount of the pixel defining film substance layer 119' to be removed differs depending on the exposure amount, and thus the preliminary pixel defining film 119p having a different thickness for each region and the photoresist pattern PR can be formed at once.

For example, as shown in fig. 13b, a preliminary pixel defining film 119p may be formed in the display area DA, and a photoresist pattern PR may be formed in the peripheral area PA. The preliminary pixel defining film 119p may include a first preliminary pixel defining film 119pa and a second preliminary pixel defining film 119pb surrounded by the first preliminary pixel defining film 119 pa. The photoresist pattern PR may be formed with the pixel defining film substance layer 119' at the same time as the preliminary pixel defining film 119p, and thus may include the same substance as the preliminary pixel defining film 119 p.

The first preliminary pixel defining film 119pa corresponds to a portion where the pixel defining film substance layer 119 'is not exposed to light and the pixel defining film substance layer 119' is not removed by the second area AR2 and the fourth area AR4 of the third mask M3. The second preliminary pixel defining film 119pb corresponds to a portion where the least amount of exposure is applied to the pixel defining film substance layer 119 'through the third area AR3 of the third mask M3 and the pixel defining film substance layer 119' is removed the least. The photoresist pattern PR corresponds to a portion to which more exposure light than the third region AR3 of the third mask M3 is applied to the pixel defining film substance layer 119 'through the sixth region AR6 of the third mask M3, and corresponds to a portion from which the pixel defining film substance layer 119' is removed more than the second preliminary pixel defining film 119 pb.

The thickness t1 of the first preliminary pixel defining film 119pa may be thicker than the thickness t2 of the second preliminary pixel defining film 119 pb. The thickness t2 of the second preliminary pixel defining film 119pb may be thicker than the thickness t3 of the photoresist pattern PR. That is, the thicknesses t1, t2 of the preliminary pixel defining film 119p may be thicker than the thickness t3 of the photoresist pattern PR.

In fig. 13a, the pixel defining film substance layer 119 'includes a positive photoresist as an example, but the pixel defining film substance layer 119' may include a negative photoresist. In this case, the more the exposure amount applied to the pixel defining film substance layer 119' is, the thicker the thickness of the pixel defining film substance layer 119' remaining after the developing process is, contrary to when the pixel defining film substance layer 119' includes a positive photoresist.

Referring to fig. 13b and 13c, the pixel electrode material layer 310 'is etched using the preliminary pixel defining film 119p and the photoresist pattern PR formed on the pixel electrode material layer 310', respectively, to form a pixel electrode 310 and a pad connection electrode PCE. That is, the pixel electrode 310 and the pad connection electrode PCE may be formed by vapor-depositing the pixel electrode material layer 310' through a mask process and an etching process. As an example, the etching process may be wet etching (wet etch).

Referring to fig. 13c and 13d, a curing (curing) process of the preliminary pixel defining film 119p may be performed. After the patterning of the pixel electrode 310, if the curing process of the preliminary pixel defining film 119p is performed, the preliminary pixel defining film 119p surrounds the side of the pixel electrode 310 as shown in fig. 13 d. Through the curing process, the preliminary pixel defining film 119p is reflowed by a portion to surround the side of the pixel electrode 310. The side surface of the pixel electrode 310 is not exposed to the outside through the preliminary pixel defining film 119p, and thus silver (Ag) having strong reducibility included in the pixel electrode 310 can be prevented from reacting with external particles.

Although the preliminary pixel defining film 119p is illustrated as an example, the photoresist pattern PR may also be subjected to a curing process together. A portion of the photoresist pattern PR is reflowed to surround the side of the pad connection electrode PCE.

Referring to fig. 13d and 13e, an etching process for removing the photoresist pattern PR is performed. As an example, the etching process may be dry etching (dry etch).

It is noted that the first portion 117a of the planarization layer 117 corresponds to a portion protected by the preliminary pixel defining film 119p at the time of the etching process, and the second portion 117b of the planarization layer 117 corresponds to a portion not protected by the preliminary pixel defining film 119p at the time of the etching process. By preparing the pixel defining film 119p, the upper face of the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117 b. In addition, by the etching process, a part of the preliminary pixel defining film 119p may be etched while the thickness of the preliminary pixel defining film 119p is also thinned as a whole.

Thereafter, an etching process may be performed in a state where the preliminary pixel defining film 119p is not removed. As an example, the etching process may be wet etching (wet etch).

Referring to fig. 13f, the remaining two films of the pad connecting electrode PCE once formed as a three-layered film, except for the film adjacent to the pad electrode PE, may be removed through an etching process. The pad connection electrode PCE may be a single-layer film.

As a comparative example, the pad connection electrode may be held as a three-layer film. In the case where the pad connection electrode is a three-layer film, it may be formed of ITO/Ag/ITO. The pad connection electrode may be exposed without being covered by the insulating layer. In this case, silver (Ag) having a high reaction rate is exposed to risk of short-circuiting with an adjacent electrode.

However, in the case of removing two of the three films of the pad connection electrode PCE as in one embodiment of the present invention, only ITO is present in the exposed pad connection electrode PCE, and the risk of short-circuiting with the adjacent electrode disappears.

Thereafter, an etching process for removing the second preliminary pixel defining film 119pb to expose a portion of the pixel electrode 310 is performed. The second preliminary pixel defining film 119pb may be removed from the preliminary pixel defining film 119p to form a pixel defining film 119. As an example, the etching process may be dry etching (dry etch).

When the second preliminary pixel defining film 119pb is etched, the first preliminary pixel defining film 119pa and the first portion 117a of the planarizing layer 117 may be partially etched together. As a result, the planarization layer 117 and the pixel defining film 119 may have the same etched faces s, s'. The outer side of the pixel defining film 119 and the side of the planarization layer 117 may be located on the same etched face s, s'.

On the other hand, as shown in fig. 13c, the pixel electrode 310 is formed using the preliminary pixel defining film 119p as an etching mask, and as shown in fig. 13f and 13g, the first portion 117a of the planarization layer 117 is also formed using the preliminary pixel defining film 119p as an etching mask, so that the planar shape of the pixel electrode 310 and the planar shape of the first portion 117a all substantially correspond to the planar shape of the pixel defining film 119. In addition, as shown in fig. 13g, the edge of the pixel electrode 310 and the sidewall of the first portion 117a also correspond to each other. The edge of the pixel electrode 310 and the sidewall of the pixel defining film 119 also correspond to each other.

After that, an intermediate layer 320 is formed inside the opening of the pixel defining film 119, and a counter electrode 330 is formed on the intermediate layer 320.

Fig. 14a to 14i are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention. Specifically, a sectional view sequentially showing a method of manufacturing a display device according to an embodiment of the present invention is based on fig. 9. In fig. 14a to 14i, the same reference numerals as those in fig. 9 and 12a to 12h denote the same components, and redundant description thereof will be omitted.

Referring to fig. 14a, first, a conductive layer BML, a buffer layer 111, a semiconductor layer a, a gate insulating layer 113, a gate electrode G, first and second electrodes CE1 and CE2 of a storage capacitor Cst, an auxiliary pad electrode SPE, an interlayer insulating layer 115, an electrode layer E, a pad electrode PE, an electrode protection layer EPL, a pad protection layer PPL, and an inorganic protection layer PVX are sequentially formed on a substrate 100. The process of forming the inorganic protective layer PVX from the conductive layer BML is the same as described in fig. 12 a. However, after the inorganic protective layer PVX is formed, contact holes that partially expose the electrode protective layer EPL and the pad protective layer PPL, respectively, may be formed by the planarization layer 117, as shown in fig. 14b and 14c, without forming the contact holes through a separate mask. As a result, the contact hole formed in the inorganic protective layer PVX can be formed without a separate mask.

Referring to fig. 14b, a planarization material layer 117' may be disposed on the inorganic protective layer PVX. A fourth mask M4 may be disposed on the planarized material layer 117'. The fourth mask M4 can adjust the exposure amount applied to the planarized material layer 117' for each region. For example, the fourth area AR4 of the fourth mask M4 may adjust the exposure amount applied to the planarized object layer 117' to be small as compared with the second area AR2 and the fifth area AR5 of the fourth mask M4. In addition, the sixth area AR6 of the fourth mask M4 can adjust the exposure amount applied to the planarized object layer 117' to be smaller than the second area AR2 and the fifth area AR5 of the fourth mask M4. For example, the fourth mask M4 may be a half-tone mask (half-tone mask) or a slit mask (slit mask). In some embodiments, the first area AR1 and the third area AR3 of the fourth mask M4 may be shielded from exposing the planarized material layer 117'.

The planarized material layer 117 'may be exposed by the fourth mask M4 with a different exposure amount for each region, and a portion of the planarized material layer 117' may be removed by a developing process (leveling). Since the amount of the removed planarizing layer 117' differs depending on the exposure amount, the planarizing layer 117 having a different thickness for each region can be formed at once. That is, as shown in fig. 14c, the thickness of the planarization layer 117 corresponding to the display area DA may be thicker than the thickness of the planarization layer 117 corresponding to the peripheral area PA. Thereafter, the adhesion degree with the inorganic protective layer PVX may be increased by the hardening and drying process of the planarization layer 117. At this time, the hardening and drying process may include a heat treatment process.

In fig. 14b, the planarized material layer 117 'is exemplified to include a positive photoresist, but the planarized material layer 117' may include a negative photoresist. In this case, the more the exposure amount applied to the planarized substance layer 117 'is, the thicker the thickness of the planarized layer 117 remaining after the developing process is, in contrast to when the planarized substance layer 117' includes a positive photoresist.

Referring to fig. 14c and 14d, a first contact hole CNT1 partially exposing the electrode layer E and a second contact hole CNT2 partially exposing the pad electrode PE are formed in the inorganic protective layer PVX using the patterned planarization layer 117. The first contact hole CNT1 and the second contact hole CNT2 are formed by an etching process of partially etching the inorganic protective layer PVX. As an example, the etching process for partially etching the inorganic protective layer PVX may be dry etching (dry etch). Although not shown in fig. 14d, a portion of the planarization layer 117 may also be removed together to reduce the thickness of the planarization layer 117 as a whole.

Referring to fig. 14e to 14i, a pixel electrode material layer 310 'and a pixel defining film material layer 119' (fig. 14e) are sequentially formed on the planarization layer 117. The preliminary pixel defining film 119p having different thicknesses for each region may be formed at once by the fifth mask M5 disposed on the pixel defining film substance layer 119' (fig. 14 f). Then, the pixel electrode material layer 310 'is etched using the preliminary pixel defining film 119p formed on the pixel electrode material layer 310', thereby forming the pixel electrode 310 (fig. 14f and 14 g). The curing process of the preliminary pixel defining film 119p may be performed to arrange the preliminary pixel defining film 119p to surround the side surface of the pixel electrode 310 (fig. 14g and 14 h). An etching process of removing the second preliminary pixel defining film 119pb for exposing a portion of the pixel electrode 310 is performed (fig. 14 h). The second preliminary pixel defining film 119pb may be etched to form a pixel defining film 119. Since the details have already been described in fig. 12d to 12h, the redundant description is omitted in fig. 14e to 14 i.

It is to be noted that the first portion 117a of the planarization layer 117 corresponds to a portion protected by the preliminary pixel defining film 119p at the time of the etching process of the second preliminary pixel defining film 119pb, and the second portion 117b of the planarization layer 117 corresponds to a portion not protected by the preliminary pixel defining film 119p at the time of the etching process of the second preliminary pixel defining film 119 pb. By preparing the pixel defining film 119p, the upper face of the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117 b. In addition, the planarization layer 117 and the pixel defining film 119 may have the same etched surface. The planarization layer 117 corresponding to the peripheral area PA cannot be protected by the preliminary pixel defining film 119p at the time of the etching process and thus can be removed.

Fig. 15a to 15g are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention. Specifically, a sectional view sequentially showing a method of manufacturing a display device according to an embodiment of the present invention is based on fig. 11. In fig. 15a to 15g, the same reference numerals as those in fig. 11 and 13a to 13g denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 15a, a pixel electrode material layer 310 'and a pixel defining material layer 119' are sequentially formed over the planarization layer 117. Before the pixel electrode substance layer 310 'and the pixel defining film substance layer 119' are sequentially formed, the formation process of the thin film transistor TFT, the pad electrode PE, the planarization layer 117, and the like may be the same as those of fig. 14a to 14 d.

Referring to fig. 15a to 15g, a preliminary pixel defining film 119p having a different thickness for each region and a photoresist pattern PR may be formed at one time through a sixth mask M6 disposed on the pixel defining film substance layer 119' (fig. 15 b). Thereafter, the pixel electrode material layer 310 'is etched using the preliminary pixel defining film 119p and the photoresist pattern PR formed on the pixel electrode material layer 310', respectively, to form the pixel electrode 310 and the pad connecting electrode PCE (fig. 15b and 15 c). A curing process of the preliminary pixel defining film 119p may be performed to arrange the preliminary pixel defining film 119p to surround the side of the pixel electrode 310 (fig. 15c and 15 d). An etching process for removing the photoresist pattern PR is performed (fig. 15 e).

The planarization layer 117 may have a step ST at the time of the etching process. In addition, a portion of the third portion 117c of the planarization layer 117 corresponding to the peripheral area PA, which is not protected by the photoresist pattern PR, is removed. In contrast, a portion of the third portion 117c of the planarization layer 117 corresponding to the peripheral area PA, which is protected by the photoresist pattern PR, remains. In addition, as shown in fig. 15e, the photoresist pattern PR may be entirely etched and removed in the etching process. That is, the step of partially etching the third portion 117c of the planarization layer 117 and the step of removing the photoresist pattern PR may be simultaneously performed.

After that, in a state where the preliminary pixel defining film 119p is not removed, an etching process is performed to make the pad connecting electrode PCE a single-layer film (fig. 15e and 15 f). An etching process for removing the second preliminary pixel defining film 119pb to expose a portion of the pixel electrode 310 is performed (fig. 15f and 15 g). The second preliminary pixel defining film 119pb may be removed to form a pixel defining film 119. Since the description is given in fig. 13a to 13g, details of fig. 15a to 15g are omitted.

Fig. 16 and 17 are sectional views schematically showing a display device according to an embodiment of the present invention. Fig. 16 and 17 correspond to a partial modification of fig. 9 and 11. In fig. 16 and 17, the same reference numerals as in fig. 9 and 11 denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 16, the display device 1 (see fig. 1) includes: a thin film transistor TFT disposed on the substrate 100 corresponding to the display area DA; and a PAD portion PAD disposed on the substrate 100 corresponding to the peripheral area PA. As an insulating layer which is disposed on the thin film transistor TFT and exposes the PAD portion PAD, a planarization layer 117 is included, and the planarization layer 117 includes a first portion 117a and a second portion 117b which extends from the first portion 117a to one side. At this time, the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b on the upper surface.

A pixel defining film 119 may be disposed on the planarization layer 117. At this time, the side of the planarization layer 117 and the side of the pixel defining film 119 may be etched surfaces of the same plane. The side of the first portion 117a of the planarization layer 117 and the side of the pixel defining film 119 may be the same etched face.

Hereinafter, referring to fig. 16, the structure included in the display device 1 will be described more specifically based on the stacked structure.

A buffer layer 111 may be disposed on the substrate 100. A barrier layer may be further included between the substrate 100 and the buffer layer 111. A conductive layer BML, an electrode layer E, a first electrode CE1 of the storage capacitor Cst, and an auxiliary pad electrode SPE may be disposed between the substrate 100 and the buffer layer 111. Unlike those shown in fig. 9 and 11, the electrode layer E and the like are not disposed in different layers from the conductive layer BML. The conductive layer BML, the electrode layer E, the first electrode CE1, and the auxiliary pad electrode SPE are disposed in the same layer, and thus the conductive layer BML, the electrode layer E, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE may be simultaneously formed by patterning one metal layer. Therefore, the number of masks used to manufacture the display device 1 can be reduced.

The semiconductor layer a may be disposed on the buffer layer 111. A gate insulating layer 113 may be disposed on the semiconductor layer a. As shown in fig. 16, the gate insulating layer 113 may be patterned to overlap a portion of the semiconductor layer a.

A gate electrode G may be disposed on the gate insulating layer 113 to overlap at least a portion of the semiconductor layer a. In addition, a first bridge electrode BE1, a second bridge electrode BE2, a second electrode CE2 of the storage capacitor Cst, and a pad electrode PE may BE disposed on the gate insulating layer 113.

The first bridge electrode BE1 may BE connected to the conductive layer BML and the semiconductor layer a through contact holes formed in the gate insulating layer 113 and the buffer layer 111, respectively. The conductive layer BML and the semiconductor layer a may BE electrically connected through a first bridge electrode BE 1.

The second bridge electrode BE2 may BE connected to the electrode layer E and the semiconductor layer a through contact holes formed in the gate insulating layer 113 and the buffer layer 111, respectively. The electrode layer E and the semiconductor layer a may BE electrically connected through a second bridge electrode BE 2.

The first electrode CE1 and the second electrode CE2 of the storage capacitor Cst may overlap each other with the gate insulating layer 113 and the buffer layer 111 interposed therebetween. The gate insulating layer 113 and the buffer layer 111 may function as a dielectric layer of the storage capacitor Cst. The second electrode CE2, which is illustrated as the storage capacitor Cst in fig. 16, contains the same substance as the gate electrode G, but the second electrode CE2 of the storage capacitor Cst may also contain the same substance as the semiconductor layer a. The second electrode CE2 of the storage capacitor Cst may be disposed at the same layer as the semiconductor layer a.

An electrode protection layer EPL may BE disposed on the gate electrode G, the first bridge electrode BE1, the second bridge electrode BE2, and the second electrode CE2 of the storage capacitor Cst, and a pad protection layer PPL may BE disposed on the pad electrode PE.

The gate electrode G, the first bridge electrode BE1, the second bridge electrode BE2, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may BE covered by an inorganic protective layer PVX.

A planarization layer 117 is disposed on the inorganic protective layer PVX, and the planarization layer 117 includes a contact hole for connecting the thin film transistor TFT and the pixel electrode 310. The planarization layer 117 may be configured to expose the PAD portion PAD. That is, the planarization layer 117 may not be disposed in the peripheral area PA and may not overlap the PAD portion PAD.

Light-emitting element 300 is disposed on planarization layer 117. The light emitting element 300 includes a pixel electrode 310, an intermediate layer 320 including an organic light emitting layer, and a counter electrode 330.

A pixel defining film 119 may be disposed on the planarization layer 117. The pixel defining film 119 may cover an edge of the pixel electrode 310 and have an opening exposing a portion of the pixel electrode 310. The planarization layer 117 and the pixel defining film 119 may have the same etched faces s, s'.

In an embodiment, as shown in fig. 17, a pad connection electrode PCE may be disposed on the pad electrode PE. The display device 1 may further include an insulating layer 118 disposed on the inorganic protective layer PVX corresponding to the peripheral area PA and including the same material as the planarization layer 117. The insulating layer 118 may be disposed between the pad electrode PE and the pad connection electrode PCE, and at least partially overlap the pad connection electrode PCE. The surface of the insulating layer 118 overlapping the pad connection electrode PCE may have an inclination.

The method for manufacturing the display device described in fig. 14b to 14i and 15a to 15g can be applied in the same manner when manufacturing the display device 1 according to the embodiment shown in fig. 16 and 17.

Fig. 18 is a sectional view briefly showing a display device according to an embodiment of the present invention. In fig. 18, the same reference numerals as in fig. 9 denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 18, at least one thin film transistor TFT and a display element connected to the thin film transistor TFT may be disposed on the display area DA of the display device 1 (see fig. 1) according to an embodiment of the present invention.

The display area DA of the display device 1 according to the present embodiment is provided with the first to third pixels PX1, PX2, PX 3. Of course, this is exemplary, and the display device 1 may have more pixels. Also, it is shown in fig. 18 that the first to third pixels PX1, PX2, PX3 are adjacent to each other, but the present invention is not limited thereto. That is, other components such as wiring may be interposed between the first to third pixels PX1, PX2, and PX 3. Thus, for example, the first pixel PX1 and the second pixel PX2 may not be pixels arranged adjacent to each other. In addition, the cross sections of the first to third pixels PX1, PX2, PX3 in fig. 18 may not be cross sections in the same direction.

The first to third pixels PX1, PX2, PX3 each include a light emitting region EA. The light emitting region EA may be a region where light is generated and emitted to the outside. The non-light emitting regions NEA may be disposed between the light emitting regions EA, and the light emitting regions EA may be divided by the non-light emitting regions NEA.

The first to third pixels PX1, PX2, PX3 may realize lights different from each other. For example, it may be that the first pixel PX1 realizes red light, the second pixel PX2 realizes green light, and the third pixel PX3 realizes blue light. The light emitting regions EA may have various polygonal or circular shapes when viewed in plan, and may be arranged in various patterns such as stripe arrangement and penta arrangement.

On the other hand, the display device 1 according to the present embodiment may include a first quantum dot layer 220a, a second quantum dot layer 220b, and a transmission layer 220c corresponding to the light emitting region EA. The first, second and transmission layers 220a, 220b and 220c may include Quantum dots (Quantum dots) and metal nanoparticles.

For example, it may be that the first pixel PX1 includes a first quantum dot layer 220a, the second pixel PX2 includes a second quantum dot layer 220b, and the third pixel PX3 includes a transmission layer 220 c.

In the present embodiment, the average sizes of quantum dots included in the first quantum dot layer 220a and the second quantum dot layer 220b may be different from each other.

Hereinafter, a display device 1 according to an embodiment of the present invention will be specifically described according to the stacking sequence shown in fig. 18.

The substrate 100 (hereinafter, referred to as a lower substrate) may include a glass material, a ceramic material, a metal material, or a substance having a flexible or bendable characteristic. A barrier layer (not shown) may be further included between the lower substrate 100 and the buffer layer 111.

The conductive layer BML may be disposed on the lower substrate 100, and the semiconductor layer a may be disposed on the buffer layer 111. The gate electrode G may be disposed on the semiconductor layer a to overlap at least a portion of the semiconductor layer a with the gate insulating layer 113 interposed therebetween.

An interlayer insulating layer 115 may be disposed to cover the gate electrode G. A source electrode, a drain electrode, and the like may be disposed over the interlayer insulating layer 115.

A planarization layer 117 may be disposed on the source electrode and the drain electrode, and the first to third light-emitting elements 300a, 300b, and 300c may be disposed on the planarization layer 117. The first to third light emitting elements 300a, 300b, 300c each commonly include a pixel electrode 310, an intermediate layer 320 including an organic light emitting layer, and a counter electrode 330.

A pixel defining film 119 may be disposed on the planarization layer 117. In one embodiment, as shown in fig. 18, the planarization layer 117 and the pixel defining film 119 may have the same etched surface s, s'. The planarization layer 117 and the pixel defining film 119 may be simultaneously formed through the same etching process and may include the same etched surface s, s'. A portion of the planarization layer 117 may be etched using the pixel defining film 119 as a mask, and the outer side of the pixel defining film 119 and the side of the planarization layer 117 may be located on the same etched face s, s'. The outer side of the pixel defining film 119 and the side of the first portion 117a of the planarization layer 117 may be located on the same etched face s, s'.

In the case where the pixel defining film 119 and the first portion 117a of the planarization layer 117 have the same etching surface s, s', the pixel defining film 119 may be disposed corresponding to the first portion 117 a. The pixel defining film 119 may be disposed corresponding to the first portion 117a and not disposed in the second portion 117 b. The pixel defining film 119 may be removed from a portion corresponding to the second portion 117 b. The insulating layer formed with an organic substance may be removed by a value that adds the thickness t of the pixel defining film 119 to the step ST of the planarization layer 117. In this case, the pixel defining film 119 and the planarization layer 117 adjacent to the light emitting element 300 are partially removed, so that the volume (volume) of the organic matter inside the display device 1 is reduced, and outgassing of the organic matter can be minimized. Therefore, even if the display device 1 is exposed to sunlight for a long time, decomposition of organic matter due to sunlight can be prevented or minimized, and thus defects such as pixel shrinkage due to outgassing can be prevented. The reliability of the display device 1 can be improved.

The first to third light emitting elements 300a, 300b, and 300c may be easily damaged by moisture, oxygen, or the like from the outside, and thus may be covered and protected by the thin film encapsulation layer 400. The thin film encapsulation layer 400 may cover the display area DA and extend to the outside of the display area DA. The thin film encapsulation layer 400 includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

The first inorganic encapsulation layer 410 may cover the counter electrode 330 and include silicon oxide, silicon nitride, and/or silicon oxynitride, etc. Although not shown, another layer such as a cover layer may be interposed between the first inorganic sealing layer 410 and the counter electrode 330 as needed. The first inorganic encapsulation layer 410 is formed along the structure thereunder and thus has an uneven upper surface. The organic encapsulation layer 420 may cover such a first inorganic encapsulation layer 410 and make its upper side substantially flat differently from the first inorganic encapsulation layer 410.

Even if a crack is generated in the thin film encapsulation layer 400, the thin film encapsulation layer 400 may have such a crack that is not connected between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430 by the aforementioned multilayer structure. This can prevent or minimize the formation of a path through which moisture, oxygen, or the like from the outside can penetrate into the display area DA.

As described above, the insulating layer formed of an organic material may be removed from the portion corresponding to the second portion 117b of the planarization layer 117. The organic encapsulation layer 420 may further configure the amount of the insulating layer removed. Since the thickness t4 of the organic encapsulation layer 420 can be increased by the amount of the insulating layer removed, foreign substances or the like flowing from the outside hardly reach the counter electrode 330, and deterioration of the light-emitting element 300 can be prevented. It is possible to prevent the thin film encapsulation layer 400 from being damaged by foreign substances or the like flowing in from the outside and the light emitting element 300 from being deteriorated due to the damage of the thin film encapsulation layer 400.

The upper substrate 200 is positioned above the lower substrate 100 with the counter electrode 330 interposed between the upper substrate 200 and the lower substrate 100. The upper substrate 200 may include glass, metal, or polymer resin. If the upper substrate 200 has a flexible or bendable characteristic, the upper substrate 200 may include a polymer resin such as polyether sulfone (polyethersulfone), polyacrylate (polyacrylate), polyetherimide (polyetherimide), polyethylene naphthalate (polyethylene naphthalate), polyethylene terephthalate (polyethylene terephthalate), polyphenylene sulfide (polyphenylene sulfide), polyarylate (polyarylate), polyimide (polyimide), polycarbonate (polycarbonate), or cellulose acetate propionate (cellulose acetate propionate). Of course, the upper substrate 200 may have a multilayer structure including two layers each including such a polymer resin and a barrier layer including an inorganic substance (silicon oxide, silicon nitride, silicon oxynitride, or the like) interposed between the two layers, and various modifications may be made.

A light-shielding layer 230 is disposed on the lower surface of the upper substrate 200 in the direction of the lower substrate 100. The light-shielding layer 230 includes openings corresponding to the first to third light-emitting elements 300a, 300b, and 300c, respectively, and the first to third filter layers 210a, 210b, and 210c are located in the openings, respectively. The light-shielding layer 230 may be a layer for improving color brightness and contrast as a black matrix. The light-shielding layer 230 may include at least one of a black pigment, a black dye, or black particles. In some embodiments, the light shielding layer 230 may include Cr or CrO_X、Cr/CrO_X、Cr/CrO_X/CrN_YResins (carbon pigments, RGB mixed pigments), Graphite (Graphite), non-Cr-based materials, and the like.

The first filter layer 210a may pass only light having a wavelength of 630nm to 780nm, the second filter layer 210b may pass only light having a wavelength of 495nm to 570nm, and the third filter layer 210c may pass only light having a wavelength of 450nm to 495 nm. The first to third filter layers 210a, 210b, 210c may function to reduce reflection of external light in the display device 1.

A first upper insulating layer 240 is disposed on the light-shielding layer 230. The first upper insulating layer 240 includes 1 st-1 st openings 241a corresponding to the first light emitting elements 300a, 1 st-2 nd openings 241b corresponding to the second light emitting elements 300b, and 1 st-3 rd openings 241c corresponding to the third light emitting elements 300 c. The first quantum dot layer 220a is positioned in the 1 st-1 st opening 241a, the second quantum dot layer 220b is positioned in the 1 st-2 nd opening 241b, and the transmission layer 220c is positioned in the 1 st-3 rd opening 241 c. The first quantum dot layer 220a and the second quantum dot layer 220b may be formed by inkjet printing.

The first upper insulating layer 240 may, for example, include an organic substance. According to circumstances, the first upper insulating layer 240 may include a light blocking substance to function as a light blocking layer. The light-shielding substance may, for example, contain at least one of a black pigment, a black dye, black particles or metal particles. In one embodiment, the first upper insulating layer 240 may be blue.

The first quantum dot layer 220a may convert the light of the first wavelength band generated from the intermediate layer 320 on the pixel electrode 310 into the light of the second wavelength band. For example, if light having a wavelength of 450nm to 495nm is generated from the intermediate layer 320 on the pixel electrode 310, the first quantum dot layer 220a may convert the light into light having a wavelength of 630nm to 780 nm. Thereby, in the first pixel PX1, light having a wavelength of 630nm to 780nm is emitted to the outside through the upper substrate 200.

The second quantum dot layer 220b may convert the light of the first wavelength band generated from the intermediate layer 320 on the pixel electrode 310 into the light of the third wavelength band. For example, if light having a wavelength of 450nm to 495nm is generated from the intermediate layer 320 on the pixel electrode 310, the second quantum dot layer 220b may convert the light into light having a wavelength of 495nm to 570 nm. Thus, in the second pixel PX2, light having a wavelength of 495nm to 570nm is emitted to the outside through the upper substrate 200.

Each of the first and second quantum dot layers 220a and 220b may have a form in which quantum dots are dispersed in a resin. The quantum dots include semiconductor substances such as cadmium sulfide (CdS), cadmium telluride (CdTe), zinc sulfide (ZnS), or indium phosphide (InP). The size of the quantum dot may be several nanometers, and the wavelength of the converted light is different according to the size of the quantum dot. Any resin included in the first quantum dot layer 220a and the second quantum dot layer 220b may be used as long as it is a light-transmissive substance. For example, a polymer resin such as acrylic, Benzocyclobutene (BCB), or Hexamethyldisiloxane (HMDSO) may be used as the substance for forming the first and second quantum dot layers 220a and 220 b.

In the third pixel PX3, the light of the first wavelength generated from the intermediate layer 320 can be emitted to the outside without wavelength conversion. Therefore, the third pixel PX3 may not have a quantum dot layer. In this way, since the quantum dot layer is not required in the 1 st to 3 rd openings 241c, the transmissive layer 220c formed of the light transmissive resin can be disposed. The transmissive layer 220c may include acrylic acid, Benzocyclobutene (BCB; Benzocyclobutene), or Hexamethyldisiloxane (HMDSO). Of course, according to circumstances, it is also possible that the transmissive layer 220c is not present in the 1 st to 3 rd openings 241c, unlike that shown in fig. 18.

In such a display device according to the present embodiment, light of the second wavelength band is externally emitted in the first pixel PX1, light of the third wavelength band is externally emitted in the second pixel PX2, and light of the first wavelength band is externally emitted in the third pixel PX 3. Therefore, the display device 1 according to the present embodiment can display a full color image.

A second upper insulating layer 250 is disposed on the first upper insulating layer 240. The second upper insulating layer 250 includes 2 nd-1 st openings 251a corresponding to the 1 st-1 st openings 241a, 2 nd-2 nd openings 251b corresponding to the 1 st-2 nd openings 241b, and 2 nd-3 rd openings 251c corresponding to the 1 st-3 rd openings 241 c.

The first and second quantum dot layers 220a and 220b respectively positioned in the 1 st-1 st and 1 st-2 nd openings 241a and 241b may be formed in an inkjet printing manner, and the 2 nd-1 st and 2 nd openings 251a and 251b may be channels through which ink ejected through nozzles drops and moves when the inkjet printing is performed. The ink moved through the second upper insulating layer 250 including the 2-1 st opening 251a and the 2-2 nd opening 251b may reach into the 1-1 st opening 241a and the 1-2 nd opening 241b, respectively, and form the first quantum dot layer 220a and the second quantum dot layer 220 b.

The second upper insulating layer 250 may contain a light blocking substance. For example, the light-shielding substance may include at least one of a black pigment, a black dye, a black particle, or a metal particle. In addition, in an embodiment, the second upper insulating layer 250 may be blue. As described above, the first upper insulating layer 240 may contain a light shielding material, but materials constituting the first upper insulating layer 240 and the second upper insulating layer 250 may be different in order to form the first quantum dot layer 220a and the second quantum dot layer 220b by an inkjet printing method.

For example, the second upper insulating layer 250, which is a channel through which ink ejected through a nozzle moves at the time of inkjet printing, may contain a substance having no affinity with the ink. In addition, the first upper insulating layer 240 in which the ink is accumulated to form the first and second quantum dot layers 220a and 220b may contain a substance having affinity with the ink.

In fig. 18, all of the first upper insulating layer 240 and the second upper insulating layer 250 are shown, but the second upper insulating layer 250 may be omitted, or only the first upper insulating layer 240 may be disposed on the upper substrate 200.

A filler 600 may be further disposed between the lower substrate 100 and the upper substrate 200. The filler 600 may play a role of buffering against external pressure or the like. The filler 600 may be formed of an organic material such as methyl silicone, phenyl silicone, or polyimide. However, the filler 600 is not limited thereto, and may be formed of urethane resin, epoxy resin, acrylic resin, or silicon, which is an organic sealant.

Fig. 19 is a sectional view briefly showing a display device according to an embodiment of the present invention. Specifically, fig. 19 is an exemplary sectional view of the display device of fig. 1 taken along I-I 'and II-II'. In fig. 19, the same reference numerals as in fig. 9 denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 19, the display device 1 includes a display area DA and a peripheral area PA. The substrate 100 may have regions corresponding to the display region DA and the peripheral region PA.

Referring to the display area DA of fig. 19, a conductive layer BML, a thin film transistor TFT, and a light emitting element 300 may be disposed on the substrate 100. Details of this are already described in fig. 9.

A thin film encapsulation layer 400 may be disposed on the light emitting element 300. The thin film encapsulation layer 400 may be disposed to cover the entire display area DA and extend to the peripheral area PA side to cover a part of the peripheral area PA. The thin film encapsulation layer 400 may extend to the outside of the common voltage supply line CVL.

The thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, a second inorganic encapsulation layer 430, and an organic encapsulation layer 420 interposed therebetween.

A portion 330a of the counter electrode 330 may extend to the peripheral area PA side to overlap the common voltage supply line CVL. A connection wiring CL may be disposed between a portion 330a of the counter electrode 330 and the common voltage supply line CVL. The connection wiring CL may electrically connect the common voltage supply line CVL and the counter electrode 330 so that the common voltage may be transmitted to the counter electrode 330.

Although not shown in fig. 19, a driving circuit region is arranged on the peripheral region PA. For example, a gate driver circuit portion may be arranged in the driver circuit region. The gate driving circuit part may include a thin film transistor, and include a wiring connected to the thin film transistor.

The buffer layer 111, the interlayer insulating layer 115, and the inorganic protective layer PVX may extend toward the peripheral area PA.

The first DAM1, the second DAM2, and the mask support MS may be disposed on the inorganic protective layer PVX corresponding to the peripheral area PA. The first DAM1, the second DAM2, and the mask holder MS may be configured to surround the periphery of the display area DA in a plane. That is, it may be that the first DAM1 is disposed to surround the periphery of the display area DA, the second DAM2 is disposed to surround the periphery of the first DAM1, and the mask holder MS is disposed to surround the periphery of the second DAM 2.

The first DAM1 and the second DAM2 may function to prevent the organic encapsulation layer 420 of the thin film encapsulation layer 400 from overflowing to the outside of the substrate 100. The mask holder MS may function to support an opening mask used in forming the counter electrode 330 or the like.

The first and second inorganic encapsulation layers 410 and 430 of the thin film encapsulation layer 400 may partially overlap the first and second DAM1 and 2. In contrast, as shown in fig. 19, the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may not overlap the mask holder MS.

The first DAM1, the second DAM2, and the mask holder MS may be provided in a double-layered structure. The first DAM1, the second DAM2, and the mask holder MS may each include a peripheral insulating layer 117s, 119s containing the same substance as the planarization layer 117 and the pixel defining film 119. The peripheral insulating layers 117s and 119s forming the first DAM1, the second DAM2, and the mask frame MS, respectively, may be disposed at the same layer as the planarization layer 117 and the pixel defining film 119.

The peripheral electrode layers 310a, 310b, and 310c may be interposed between the peripheral insulating layers 117s and 119s on which the first DAM1, the second DAM2, and the mask frame MS are formed, respectively. Each of the peripheral electrode layers 310a, 310b, and 310c may contain the same material as the pixel electrode 310. The peripheral electrode layers 310a, 310b, and 310c may be disposed on the same layer as the pixel electrode 310. Each of the peripheral electrode layers 310a, 310b, and 310c may be surrounded by the second peripheral insulating layer 119 s.

The first peripheral insulating layer 117s and the second peripheral insulating layer 119s may have the same etched surface. The side of the first peripheral insulating layer 117s and the side of the second peripheral insulating layer 119s may be located on the same etched face.

The width of the mask holder MS may be wider than the width of the first DAM 1. The width of the mask holder MS may be wider than the width of the second DAM 2. As an example, the width of the mask holder MS may be about 4 to 6 times the width of the first DAM 1.

The pixel defining film 119 and the planarizing layer 117 included in the display device 1 according to an embodiment of the present invention may have the same etched surface. The thickness t4 of the organic encapsulating layer 420 in the thin-film encapsulating layer 400 can be increased by the amount of the pixel defining film 119 and the planarizing layer 117 that are etched and removed, and therefore, foreign substances or the like that flow in from the outside are difficult to reach the counter electrode 330, and the occurrence of degradation of the light-emitting element 300 can be prevented. It is possible to prevent the thin film encapsulation layer 400 from being damaged by foreign substances or the like flowing in from the outside and the light emitting element 300 from being deteriorated due to the damage of the thin film encapsulation layer 400.

In addition, the volume (volume) of the organic matter in the display device 1 can be reduced to minimize the outgassing of the organic matter.

Fig. 20a is a sectional view briefly showing a display device according to an embodiment of the present invention.

Referring to fig. 20a, the display device 1 (see fig. 1) includes: a thin film transistor TFT disposed on the substrate 100 corresponding to the display area DA; and a PAD portion PAD disposed on the substrate 100 corresponding to the peripheral area PA.

The display device 1 includes a planarization layer 117 as an insulating layer disposed on the thin film transistor TFT and exposing the PAD portion PAD, and includes a pixel defining film 119 disposed on the planarization layer 117. At this time, the side of the planarization layer 117 adjacent to the peripheral area PA and the side of the pixel defining film 119 may be aligned. This may mean that the side of the planarization layer 117 adjacent to the peripheral area PA and the side of the pixel defining film 119 are located on the same plane. The side of the planarization layer 117 and the side of the pixel defining film 119 adjacent to the peripheral area PA may be the same-plane etched plane formed by the same etching process.

Hereinafter, the structure included in the display device 1 will be described more specifically based on the stacked structure with reference to fig. 20 a.

The substrate 100 may include a glass material, a ceramic material, a metal material, or a substance having a flexible or bendable characteristic. The substrate 100 may have a single layer or a multi-layer structure of the substance, and may further include an inorganic layer in the case of the multi-layer structure. In some embodiments, the substrate 100 may have an organic/inorganic/organic structure.

The buffer layer 111 may reduce or prevent penetration of foreign substances, moisture, or external gas from below the substrate 100, and may provide a flat surface on the substrate 100.

A barrier layer (not shown) may be further included between the substrate 100 and the buffer layer 111. The barrier layer may function to prevent or minimize the penetration of impurities from the substrate 100 or the like into the semiconductor layer a.

The semiconductor layer a may be disposed on the buffer layer 111. The semiconductor layer a may include an oxide semiconductor material. The semiconductor layer a may include, for example, an oxide of one or more substances selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

For example, the semiconductor layer a may be an itzo (insnzno) semiconductor layer, an igzo (ingazno) semiconductor layer, or the like.

The semiconductor layer a may include a channel region C and source and drain regions S and D respectively disposed at one side and the other side of the channel region C. The semiconductor layer a may be formed in a single layer or a plurality of layers.

A conductive layer BML may be disposed between the substrate 100 and the buffer layer 111. The conductive layer BML may be configured to overlap the channel region C of the semiconductor layer a. The conductive layer BML may include a conductive substance containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or a single layer including the material. For example, the conductive layer BML may have a multilayer structure of Ti/Al/Ti.

The conductive layer BML may be provided so as to overlap with the semiconductor layer a including an oxide semiconductor material. Since the semiconductor layer a containing the oxide semiconductor material has a characteristic of being hardly sensitive to light, the conductive layer BML can prevent the element characteristics of the thin film transistor TFT containing the oxide semiconductor material from changing due to a photocurrent induced in the semiconductor layer a by external light incident from the substrate 100 side. In addition, the conductive layer BML may be connected to the drain region D. Although the conductive layer BML is shown in fig. 20a to be connected to the drain region D, the conductive layer BML may be connected to the source region S.

A gate insulating layer 113 may be disposed on the semiconductor layer a. The gate insulating layer 113 may include silicon oxide (SiO)₂) Nitriding the resulting mixtureSilicon (SiN)_X) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO)₂) And the like.

As shown in fig. 20a, the gate insulating layer 113 may be patterned to overlap a portion of the semiconductor layer a. That is, the gate insulating layer 113 may be patterned to expose the source and drain regions S and D.

A region where the gate insulating layer 113 and the semiconductor layer a overlap may be understood as a channel region C. The source region S and the drain region D are subjected to a conductor-making process using plasma treatment or the like, and at this time, a portion overlapping with the gate insulating layer 113 in the semiconductor layer a (i.e., the channel region C) has different properties from those of the source region S and the drain region D without being exposed to the plasma treatment. That is, by using the gate electrode G located above the gate insulating layer 113 at the time of plasma treatment of the semiconductor layer a as a self-alignment (self alignment) mask, a channel region C where no plasma treatment is performed may be formed at a position overlapping with the gate insulating layer 113, and a source region S and a drain region D where plasma treatment is performed may be formed on both sides of the channel region C, respectively.

As another embodiment, the gate insulating layer 113 may be disposed on the entire surface of the substrate 100 so as to cover the semiconductor layer a without being patterned to overlap a portion of the semiconductor layer a.

A gate electrode G may be disposed on the gate insulating layer 113 to overlap at least a portion of the semiconductor layer a. In addition, the first electrode CE1 of the storage capacitor Cst and the auxiliary pad electrode SPE may be disposed on the gate insulating layer 113.

In an embodiment, the storage capacitor Cst may be disposed with the first electrode CE1 and the second electrode CE2 and exist separately without overlapping the thin film transistor TFT as shown in fig. 20 a. Unlike this, the storage capacitor Cst may overlap the thin film transistor TFT. For example, the gate electrode G of the thin film transistor TFT may perform a function as the first electrode CE1 of the storage capacitor Cst.

An interlayer insulating layer 115 may be provided to cover the semiconductor layer a, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE.

An electrode layer E, a second electrode CE2 of the storage capacitor Cst, a pad electrode PE, and the like may be disposed over the interlayer insulating layer 115. The electrode layer E may be a source electrode, a drain electrode, a data line, etc.

The electrode layer E may be connected to the source region S or the drain region D of the semiconductor layer a through a contact hole. In addition, the conductive layer BML and the source region S or the drain region D of the semiconductor layer a may be connected through contact holes formed in the buffer layer 111 and the interlayer insulating layer 115.

The second electrode CE2 of the storage capacitor Cst interposes the interlayer insulating layer 115 to overlap the first electrode CE1, and forms a capacitance. In this case, the interlayer insulating layer 115 may function as a dielectric layer of the storage capacitor Cst.

The pad electrode PE may be connected to the auxiliary pad electrode SPE through a contact hole formed in the interlayer insulating layer 115. The contact holes connecting the pad electrode PE and the auxiliary pad electrode SPE are shown as three in fig. 20a, but may be more or less than this. In addition, the auxiliary pad electrode SPE is shown in fig. 20a, but the auxiliary pad electrode SPE may be omitted.

An electrode protection layer EPL may be disposed on the electrode layer E and the second electrode CE2 of the storage capacitor Cst, and a pad protection layer PPL may be disposed on the pad electrode PE.

The electrode protection layer EPL and the pad protection layer PPL may be made of a material selected from the group consisting of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), and Indium Oxide (In)₂O₃(ii) a indium oxide), indium gallium oxide (IGO; indium gallium oxide) and zinc aluminum oxide (AZO; aluminum zinc oxide).

The electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Thereby, a separate mask for patterning the electrode protection layer EPL and the pad protection layer PPL is not required, and thus the number of masks can be reduced.

The pad electrode PE and the pad protective layer PPL may be patterned together, and thus a side surface of the pad electrode PE and a side surface of the pad protective layer PPL may be aligned. The pad electrode PE and the pad protective layer PPL may be simultaneously formed by the same etching process and may include the same etched surface. The side of the pad electrode PE and the side of the pad protective layer PPL may be located on the same etched surface. Although the pad electrode PE and the pad protection layer PPL are explained as an example, the electrode layer E and the electrode protection layer EPL, and the second electrode CE2 and the electrode protection layer EPL of the storage capacitor Cst may be applied similarly.

The electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be covered with an inorganic insulating layer (hereinafter, an inorganic protective layer) PVX. The inorganic protective layer PVX may be an inorganic insulating film formed with an inorganic material. As the inorganic material, polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, or the like can be used. In addition, the inorganic protective layer PVX may be silicon nitride (SiN)_X) And silicon oxide (SiO)_X) The monolayer film or the multilayer film of (1). The inorganic protective layer PVX may be used to cover and protect a part of the wiring disposed on the interlayer insulating layer 115.

The inorganic protective layer PVX may include: a first contact hole CNT1 for connecting the thin film transistor TFT and the pixel electrode 310; and an opening OP exposing the PAD portion PAD.

The width W1 of the upper face of the PAD portion PAD in one direction may be the same as the width W2 of the opening OP. Specifically, the width W1 of the upper face of the pad protection layer PPL in the one direction may be the same as the width W2 of the opening OP. The upper surface of the pad protective layer PPL may be exposed through an opening OP formed in the inorganic protective layer PVX. As shown in fig. 20a, the upper surface of the pad protection layer PPL may be entirely exposed through the opening OP.

As described in fig. 1, the PAD portion PAD may be attached with a printed circuit substrate or a driver IC chip. In this case, the contact width of the PAD portion PAD with the printed circuit substrate or the driver IC chip may be changed according to the size of the opening OP formed in the inorganic protective layer PVX. As shown in fig. 20a, in the case where the upper surface of the PAD protection layer PPL is entirely exposed through the opening OP, the area where the PAD portion PAD can contact the printed circuit substrate or the driver IC chip may be maximized. Therefore, contact failure between the PAD portion PAD and the printed circuit board or the driver IC chip can be reduced, and the risk of failure occurring when the display device 1 is driven can be reduced.

The planarization layer 117 is configured to cover the electrode layer E and the second electrode CE2 of the storage capacitor Cst, and the planarization layer 117 includes a second contact hole for connecting the thin film transistor TFT and the pixel electrode 310.

The planarization layer 117 may be formed of a film formed of an organic substance in a single layer or a plurality of layers, and provides a flat upper surface. The planarization layer 117 may be configured to expose the PAD portion PAD. That is, the planarization layer 117 may not be disposed in the peripheral area PA and may not overlap the PAD portion PAD.

As a comparative example, the planarization layer may remain and be disposed in the peripheral region of the display panel. In this case, the remaining planarizing layer in the peripheral region of the display panel may function as a moisture permeation path from the outside, and there is a risk of causing reliability problems such as deterioration of the light emitting element.

Light-emitting element 300 is disposed on planarization layer 117. The light emitting element 300 includes a pixel electrode 310, an intermediate layer 320 including an organic light emitting layer, and a counter electrode 330.

A pixel defining film 119 may be disposed on the planarization layer 117. The pixel defining film 119 may cover an edge of the pixel electrode 310 and have an opening exposing a portion of the pixel electrode 310. In addition, the pixel defining film 119 may function to prevent an arc or the like from being generated at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310.

In one embodiment, as shown in fig. 20a, the planarization layer 117 and the pixel defining film 119 may have the same etched surface s. As described later in fig. 22i and 22j, the planarization layer 117 and the pixel defining film 119 may be simultaneously formed by the same etching process and may include the same etched face s.

The side of the planarization layer 117 adjacent to the peripheral area PA and the outer side of the pixel defining film 119 may be located on the same etched face s. In other words, the side of the planarization layer 117 adjacent to the peripheral area PA and the outer side of the pixel defining film 119 may be located on the same plane. In other words, the side surface of the planarization layer 117 and the outer side surface of the pixel defining film 119 adjacent to the peripheral area PA may be formed without a step and may be formed without a boundary. The side of the planarization layer 117 adjacent to the peripheral area PA and the outer side of the pixel defining film 119 may be aligned.

The intermediate layer 320 may be disposed in an opening formed through the pixel defining film 119 and include an organic light emitting layer.

The counter electrode 330 may be a semitransparent electrode or a reflective electrode. In some embodiments, the counter electrode 330 may be a transparent or semi-transparent electrode and may be formed with a metal thin film having a small work function including Li, Ca, LiF/Al, Ag, Mg, or a compound thereof. Further, ITO, IZO, ZnO or In may be further provided on the metal thin film₂O₃And Transparent Conductive Oxide (TCO) films. The counter electrode 330 may be disposed across the display area DA, and disposed above the intermediate layer 320 and the pixel defining film 119. The counter electrode 330 may be integrally formed in the plurality of light emitting elements 300 to correspond to the plurality of pixel electrodes 310.

Since such an organic light emitting element is easily damaged by moisture, oxygen, or the like from the outside, the thin film encapsulation layer 400 may cover the organic light emitting element to protect the organic light emitting element as described later in fig. 24. The thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

Fig. 20b and 21 are sectional views schematically showing a display device according to an embodiment of the present invention. In fig. 20b and 21, the same reference numerals as in fig. 20a denote the same components, and a repetitive description thereof will be omitted. Fig. 20b is a modified embodiment of fig. 20a, and there is a difference in the structure of the planarization layer 117. In addition, fig. 21 shows a difference in the structure of the inorganic protective layer PVX as a modified example of fig. 20 a. In the following, the description of fig. 20a is used instead of the overlapping description, and the description is mainly given for differences.

Referring to fig. 20b, the planarization layer 117 may include a first portion 117a disposed on the thin film transistor TFT and a second portion 117b extending from the first portion 117a to the peripheral area PA side. At this time, the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b on the upper surface.

The vertical distance d1 from the upper face of the substrate 100 to the upper face of the first portion 117a and the vertical distance d2 from the upper face of the substrate 100 to the upper face of the second portion 117b may be different. As an example, as shown in fig. 20b, a vertical distance d1 from the upper surface of the substrate 100 to the upper surface of the first portion 117a may be farther than a vertical distance d2 from the upper surface of the substrate 100 to the upper surface of the second portion 117 b.

The first portion 117a of the planarization layer 117 and the pixel defining film 119 may have the same etched surface. As described later in fig. 23c and 23d, the first portion 117a of the planarization layer 117 and the pixel defining film 119 may be simultaneously formed by the same etching process and may include the same etched surface.

The side of the first portion 117a of the planarization layer 117 adjacent to the peripheral area PA and the outer side of the pixel defining film 119 may be located on the same etched face. In other words, the side of the first portion 117a of the planarization layer 117 adjacent to the peripheral area PA and the outer side of the pixel defining film 119 may be located on the same plane. In other words, the side surface of the first portion 117a of the planarization layer 117 adjacent to the peripheral area PA and the outer side surface of the pixel defining film 119 may be formed without a step and may be formed without a boundary. The side of the first portion 117a of the planarization layer 117 adjacent to the peripheral area PA and the outer side of the pixel defining film 119 may be aligned.

Referring to fig. 21, a width W1 of an upper face of the PAD portion PAD in one direction may be less than a width W3 of the opening OP. Specifically, the width W1 of the upper face of the pad protection layer PPL in the one direction may be smaller than the width W3 of the opening OP.

The upper surface of the pad protection layer PPL and the side surface of the pad protection layer PPL may be exposed through an opening OP formed in the inorganic protection layer PVX. As shown in fig. 21, the upper surface and the side surface of the pad protection layer PPL may be entirely exposed through the opening OP. In addition, the side surface of the pad electrode PE may be partially exposed through the opening OP.

As described in fig. 1, the PAD portion PAD may be attached with a printed circuit substrate or a driver IC chip. In this case, the contact width of the PAD portion PAD with the printed circuit substrate or the driver IC chip may be changed according to the size of the opening OP formed in the inorganic protective layer PVX. As shown in fig. 21, in the case where the upper surface and the side surface of the PAD protection layer PPL are all exposed through the opening OP, the area where the PAD portion PAD can contact the printed circuit substrate or the driver IC chip may be maximized. Therefore, contact failure between the PAD portion PAD and the printed circuit board or the driver IC chip can be reduced, and the risk of failure occurring when the display device 1 is driven can be reduced.

The main description has been made only for the display device, but the present invention is not limited to this. For example, a display device manufacturing method for manufacturing such a display device also falls within the scope of the present invention.

Fig. 22a to 22j are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention. In fig. 22a to 22j, the same reference numerals as in fig. 20a denote the same members, and a repetitive description thereof will be omitted.

Referring to fig. 22a, first, a conductive layer BML, a buffer layer 111, a semiconductor layer a, a gate insulating layer 113, a gate electrode G, first and second electrodes CE1 and CE2 of a storage capacitor Cst, an auxiliary pad electrode SPE, an interlayer insulating layer 115, an electrode layer E, a pad electrode PE, an electrode protection layer EPL, a pad protection layer PPL, and an inorganic protection layer PVX are sequentially formed on a substrate 100.

The conductive layer BML may be formed by patterning a preliminary-conductive layer (not shown). The pre-conductive layer may include a conductive substance containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or a single layer including the material.

The buffer layer 111 may be made of silicon oxide (SiO)₂) Or silicon nitride (SiN)_X) The film can be formed by a Vapor Deposition method such as Chemical Vapor Deposition (CVD) or sputtering.

The semiconductor layer a may be disposed on the buffer layer 111. The semiconductor layer a may be formed by patterning a preliminary-semiconductor layer (not shown). The preliminary semiconductor layer may be formed of an oxide semiconductor, and may be evaporated by a chemical vapor deposition method.

The gate insulating layer 113 and the gate electrode G may be disposed on the semiconductor layer a, and the gate insulating layer 113, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE may be disposed on the buffer layer 111.

The gate insulating layer 113, the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE may be formed by patterning a preliminary-gate insulating layer (not shown) and a preliminary-metal layer (not shown).

The pre-gate insulating layer may be formed of silicon oxide (SiO)₂) Silicon nitride (SiN)_X) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO)₂) And the like, and may be formed by a Vapor Deposition method such as Chemical Vapor Deposition (CVD) or sputtering (sputtering), but is not limited thereto.

The pre-metal layer may be formed in a single layer or a plurality of layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed by a vapor deposition method such as a Chemical Vapor Deposition (CVD), a Plasma Enhanced CVD (PECVD), a Low Pressure CVD (LPCVD), a Physical Vapor Deposition (PVD), a sputtering, or an Atomic Layer Deposition (ALD), but is not limited thereto.

In patterning the preliminary-gate insulating layer, plasma treatment is performed, and a portion of the semiconductor layer a, which is not overlapped with the gate electrode G and is exposed, is subjected to a conductor formation process using the plasma treatment. As a result, the source region S and the drain region D exposed during the plasma treatment become conductive, and the channel region C overlapping with the gate electrode G has a property different from that of the source region S and the drain region D.

An interlayer insulating layer 115 is formed on the gate electrode G, the first electrode CE1 of the storage capacitor Cst, and the auxiliary pad electrode SPE. After the interlayer insulating layer 115 is formed, contact holes penetrating the interlayer insulating layer 115 and exposing portions of the conductive layer BML, the semiconductor layer a, and the auxiliary pad electrode SPE, respectively, are formed.

An electrode layer E, a second electrode CE2 of the storage capacitor Cst, and a pad electrode PE are formed on the interlayer insulating layer 115. In addition, an electrode protection layer EPL and a pad protection layer PPL are formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE.

The electrode layer E, the second electrode CE2 of the storage capacitor Cst, the pad electrode PE, the electrode protection layer EPL, and the pad protection layer PPL may be formed by sequentially depositing a pre-electrode layer (not shown) and a pre-protection layer (not shown) on the entire interlayer insulating layer 115 through a mask process and an etching process. That is, the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE may be patterned together with the electrode protection layer EPL and the pad protection layer PPL. Thus, a separate mask for patterning the electrode protection layer EPL and the pad protection layer PPL is not required, and thus the number of masks can be reduced.

An inorganic protective layer PVX is formed on the electrode layer E, the second electrode CE2 of the storage capacitor Cst, and the pad electrode PE. The inorganic protective layer PVX may be an inorganic insulating film formed using an inorganic material, and may be formed by a vapor deposition method such as a chemical vapor deposition method, a Plasma Enhanced CVD (PECVD), a Low Pressure CVD (LPCVD), a Physical Vapor Deposition (PVD), a sputtering (sputtering), or an Atomic Layer Deposition (ALD), without being limited thereto.

Referring to fig. 22b, a planarization material layer 117' may be disposed on the inorganic protective layer PVX. A first mask M1 may be disposed on the planarized material layer 117'. The first mask M1 may adjust the amount of exposure (light exposure) applied to the planarized material layer 117' for each region. For example, the fourth region AR4 of the first mask M1 may adjust the exposure amount applied to the planarized object layer 117' to be small as compared with the second region AR2 of the first mask M1. For example, the first mask M1 may be a half-tone mask (half-tone mask) or a slit mask (slit mask). In some embodiments, the first area AR1 and the third area AR3 of the first mask M1 may be shielded from exposing the planarized material layer 117'.

The planarized material layer 117 'may be exposed by the first mask M1 with a different exposure amount for each region, and a portion of the planarized material layer 117' may be removed by a developing process (leveling). Since the amount of the removed planarizing layer 117' differs depending on the exposure amount, a preliminary insulating layer (hereinafter, preliminary planarizing layer) 117p having a different thickness for each region can be formed at once.

Referring to fig. 22c, the preliminary planarization layer 117p may include a first preliminary planarization layer 117PA corresponding to the display area DA and a second preliminary planarization layer 117pb corresponding to the peripheral area PA. The thickness of the first preliminary planarization layer 117pa may be thicker than the thickness of the second preliminary planarization layer 117 pb.

After forming the preliminary planarization layer 117p by removing a portion of the planarization material layer 117', a hardening and drying process of the preliminary planarization layer 117p may be performed. The adhesion to the inorganic protective layer PVX can be increased by a curing and drying process of the preliminary planarization layer 117 p. At this time, the hardening and drying process may include a heat treatment process.

In fig. 22b, the planarized material layer 117 'is exemplified to include a positive photoresist, but the planarized material layer 117' may include a negative photoresist. In this case, the more the exposure amount applied to the planarized substance layer 117 'is, the thicker the thickness of the preliminary planarized layer 117p remaining after the developing process is, in contrast to when the planarized substance layer 117' includes a positive photoresist.

Referring to fig. 22c and 22d, a contact hole CNT partially exposing the electrode layer E is formed in the inorganic protective layer PVX by using the patterned preliminary planarization layer 117 p. The contact hole CNT is formed through an etching process of partially etching the inorganic protective layer PVX. As an example, the etching process for partially etching the inorganic protective layer PVX may be dry etching (dry etch). Although not shown in fig. 22d, a portion of the preliminary planarization layer 117p may also be removed together to reduce the thickness of the preliminary planarization layer 117p as a whole.

Referring to fig. 22e, a pixel electrode material layer 310 'and a photoresist layer PR' are sequentially formed on the preliminary planarization layer 117 p.

The photoresist layer PR ' may include a positive photoresist, and the photoresist layer PR ' may be formed by coating a positive photoresist (not shown) on the pixel electrode material layer 310' by various methods such as Spin-coating (Spin-coating), spraying, or dipping.

A second mask M2 may be disposed on the photoresist layer PR'. The second mask M2 can adjust the exposure amount applied to the photoresist layer PR' for each region. For example, the second area AR2 of the second mask M2 may be masked so as not to expose the photoresist layer PR'. The first and third areas AR1 and AR3 of the second mask M2 may not be masked to expose the photoresist layer PR'.

The photoresist layer PR 'corresponding to the first and third regions AR1 and AR3 may be exposed through the second mask M2 and a portion of the photoresist layer PR' may be removed through a developing process, as shown in fig. 22f, and a photoresist pattern PR may be formed.

In fig. 22e, the photoresist layer PR 'is exemplified to include a positive photoresist, but the photoresist layer PR' may include a negative photoresist. In this case, contrary to when the photoresist layer PR 'includes a positive photoresist, a portion of the photoresist layer PR' that is not exposed to light corresponds to a portion removed after the developing process.

Referring to fig. 22f and 22g, the pixel electrode material layer 310 'is etched using the photoresist pattern PR formed on the pixel electrode material layer 310' to form the pixel electrode 310. That is, the pixel electrode 310 may be formed by evaporating the pixel electrode material layer 310' through a mask process or an etching process. As an example, the etching process may be wet etching (wet etch).

Contact holes partially exposing the electrode layer E are formed in the preliminary planarization layer 117p and the inorganic protective layer PVX, and the pixel electrode 310 may be electrically connected to the thin film transistor TFT through the contact holes.

As a comparative example, when a contact hole electrically connecting the pixel electrode and the thin film transistor is formed, an opening partially exposing the pad portion may be formed. After forming the opening partially exposing the pad part, wet etching for forming the pixel electrode may be performed. In this case, the pad portion exposed through the opening is affected by the wet etching and a portion of the surface of the pad portion may be cracked (crack) or form a fine boundary line (seam). A part of the surface of the pad portion may be damaged. When the surface of the pad portion is finely cracked, copper (Cu) or the like constituting the pad portion is corroded, and there is a possibility that contact failure of the pad portion occurs.

However, as shown in fig. 22f, when the etching process for forming the pixel electrode 310 is performed, the PAD protection layer PPL and the PAD electrode PE are protected by the preliminary planarization layer 117p, and thus the surface of the PAD portion PAD can be safely protected. Therefore, the contact failure of the PAD portion PAD can be improved. In addition, since the PAD protection layer PPL and the PAD electrode PE are protected by the preliminary planarization layer 117p, the PAD portion PAD can be protected regardless of whether the etching process for forming the pixel electrode 310 is performed once, twice, or only once.

Referring to fig. 22g, after the pixel electrode 310 is formed, a pixel defining film substance layer 119' is formed over the pixel electrode 310 and the preliminary planarization layer 117 p. The pixel defining film substance layer 119 'may include a positive (positive) photoresist, and the pixel defining film substance layer 119' may be formed by applying a positive photoresist solution on the pixel electrode 310 and the preliminary planarization layer 117p by various methods such as Spin-coating, spraying, or dipping.

A third mask M3 may be disposed on the pixel defining film substance layer 119'. The third mask M3 can adjust the exposure amount applied to the pixel defining film substance layer 119' per region. For example, the second area AR2, the fourth area AR4, and the sixth area AR6 of the third mask M3 may adjust the exposure amount applied to the pixel defining film substance layer 119' to be small as compared with the fifth area AR5 of the third mask M3. For example, the third mask M3 may be a half-tone mask (half-tone mask) or a slit mask (slit mask). In some embodiments, the first area AR1 and the third area AR3 of the third mask M3 may be shielded from exposing the pixel defining film substance layer 119'.

The pixel defining film substance layer 119 'may be exposed by the third mask M3 with a different exposure amount per region, and a portion of the pixel defining film substance layer 119' may be removed by a developing process. The amount of the pixel defining film substance layer 119' to be removed differs depending on the exposure amount, and therefore, the preliminary pixel defining film 119p having a different thickness for each region can be formed at once.

For example, as shown in fig. 22h, the preliminary pixel defining film 119p may include: the first preliminary pixel defining film 119 pa; a second preliminary pixel defining film 119pb surrounded by the first preliminary pixel defining film 119 pa; and a third preliminary pixel defining film 119pc corresponding to the peripheral area PA.

At this time, the second preliminary pixel defining film 119pb may function to protect the surface of the pixel electrode 310 in a subsequent process. As another example, the second preliminary pixel defining film 119pb may be omitted. The second region AR2 of the third mask M3 is opened and the maximum amount of exposure is applied to the pixel defining film substance layer 119', so that the pixel defining film substance layer 119' corresponding to the second region AR2 of the third mask M3 can be entirely removed.

The first preliminary pixel defining film 119pa corresponds to a portion where the pixel defining film substance layer 119 'is not exposed to light and the pixel defining film substance layer 119' is not removed by the first area AR1 and the third area AR3 of the third mask M3. The second preliminary pixel defining film 119pb corresponds to a portion where a portion of the pixel defining film substance layer 119 'is removed by applying a regulated exposure amount to the pixel defining film substance layer 119' through the second area AR2 of the third mask M3. The third preliminary pixel defining film 119pc corresponds to a portion where a portion of the pixel defining film substance layer 119 'is removed by applying the adjusted exposure amount to the pixel defining film substance layer 119' through the fourth area AR4 and the sixth area AR6 of the third mask M3.

The thickness of the first preliminary pixel defining film 119pa may be thicker than the thickness of the second preliminary pixel defining film 119 pb. The thickness of the first preliminary pixel defining film 119pa may be thicker than that of the third preliminary pixel defining film 119 pc. The thickness of the second preliminary pixel defining film 119pb and the thickness of the third preliminary pixel defining film 119pc may be the same or different. For example, as shown in fig. 22h, the thickness of the third preliminary pixel defining film 119pc may be thicker than that of the second preliminary pixel defining film 119 pb.

The preliminary pixel defining film 119p may have a first opening OP1 corresponding to the PAD portion PAD. The first opening OP1 corresponds to a portion where the pixel defining film substance layer 119 'is removed entirely by applying the maximum exposure amount to the pixel defining film substance layer 119' through the fifth area AR5 of the third mask M3.

In fig. 22g, the pixel defining film material layer 119 'includes a positive photoresist as an example, but the pixel defining film material layer 119' may include a negative photoresist. In this case, the more the exposure amount applied to the pixel defining film substance layer 119' is, the thicker the thickness of the pixel defining film substance layer 119' remaining after the developing process is, contrary to when the pixel defining film substance layer 119' includes a positive photoresist.

Referring to fig. 22h and 22i, a second opening OP2 and a third opening OP3 exposing an upper surface of the PAD portion PAD are formed in the preliminary planarization layer 117p and the inorganic protective layer PVX, respectively, using the patterned preliminary pixel defining film 119 p. The second opening OP2 and the third opening OP3 are formed by an etching process of partially etching the preliminary planarization layer 117p and the inorganic protective layer PVX. As an example, the etching process for partially etching the preliminary planarization layer 117p and the inorganic protective layer PVX may be dry etching (dry etch). Although not shown in fig. 22i, a part of the preliminary pixel defining film 119p may also be removed together to reduce the thickness of the preliminary pixel defining film 119p as a whole.

Referring to fig. 22i and 22j, an etching process of removing the second preliminary pixel defining film 119pb, the third preliminary pixel defining film 119pc, and the second preliminary planarization layer 117pb is performed. As an example, the etching process may be dry etching (dry etch).

The second preliminary planarization layer 117pb may be removed from the preliminary planarization layer 117p to form the planarization layer 117.

The second preliminary pixel defining film 119pb and the third preliminary pixel defining film 119pc may be removed from the preliminary pixel defining film 119p to form a pixel defining film 119. A portion of the pixel electrode 310 may be exposed by removing the second preliminary pixel defining film 119 pb. The pixel defining film 119 may have an opening exposing a portion of the pixel electrode 310.

When the etching process of removing the second preliminary pixel defining film 119pb, the third preliminary pixel defining film 119pc, and the second preliminary planarization layer 117pb is performed, a portion of the first preliminary pixel defining film 119pa and a portion of the first preliminary planarization layer 117pa may also be etched together. For example, as shown in fig. 22i, a portion of the first preliminary pixel defining film 119PA on the peripheral area PA side on the virtual plane s' and a portion of the first preliminary planarization layer 117PA may be etched together.

As shown in fig. 22j, the planarization layer 117 and the pixel defining film 119 may have the same etched face s. The outer side of the pixel defining film 119 adjacent to the peripheral area PA and the side of the planarization layer 117 may be located on the same etched plane s. The same etched surface s can correspond to the virtual surface s' described above in fig. 22 i.

On the other hand, as shown in fig. 22i, the planarization layer 117 is formed using the preliminary pixel defining film 119p as an etching mask, and therefore the planar shape of the planarization layer 117 substantially corresponds to the planar shape of the pixel defining film 119. In addition, as shown in fig. 22j, the side wall of the planarization layer 117 and the side wall of the pixel defining film 119 adjacent to the peripheral area PA also correspond to each other.

Referring to fig. 22j, an intermediate layer 320 is formed on the pixel electrode 310, i.e., inside the opening of the pixel defining film 119. The intermediate layer 320 may comprise a low molecular or polymeric substance. The intermediate layer 320 may be formed by a vacuum evaporation method, a screen printing or inkjet printing method, a Laser Induced Thermal Imaging (LITI) method, or the like.

The intermediate layer 320 of the light emitting element 300 may include an organic light emitting layer. The organic light emitting layer may include an organic material containing a fluorescent or phosphorescent substance emitting red, green, blue or white light.

After that, the counter electrode 330 is formed to correspond to the plurality of light emitting elements 300. The counter electrode 330 may be formed to cover the display area DA of the substrate 100 through an opening mask. The counter electrode 330 can be formed by a vapor deposition method such as a chemical vapor deposition method, a Plasma Enhanced CVD (PECVD), a Low Pressure CVD (LPCVD), a Physical Vapor Deposition (PVD), a sputtering (sputtering), or an Atomic Layer Deposition (ALD).

Fig. 23a to 23d are sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention. Fig. 23a to 23d are variations of the modified embodiments of fig. 22g to 22j, and there is a difference in the structure of the planarization layer 117. In the following, the description of fig. 22g to 22j is replaced with the description of the overlapping contents, and the description is mainly given with differences.

Referring to fig. 23a, after the pixel electrode 310 is formed, a pixel defining film substance layer 119' is formed over the pixel electrode 310 and the preliminary planarization layer 117 p. The pixel defining film substance layer 119 'may include a positive (positive) photoresist, and the pixel defining film substance layer 119' may be formed by applying a positive photoresist solution on the pixel electrode 310 and the preliminary planarization layer 117p by various methods such as Spin-coating, spraying, or dipping.

A fourth mask M4 may be disposed on the pixel defining film substance layer 119'. The fourth mask M4 can adjust the exposure amount applied to the pixel defining film substance layer 119' per region. For example, the fourth mask M4 may be a half-tone mask (half-tone mask) or a slit mask (slit mask). In some embodiments, the first area AR1 and the third area AR3 of the fourth mask M4 may be shielded from exposing the pixel defining film substance layer 119'.

The pixel defining film substance layer 119 'may be exposed by the fourth mask M4 with a different exposure amount per region, and a portion of the pixel defining film substance layer 119' may be removed by a developing process. The amount of the pixel defining film substance layer 119' to be removed differs depending on the exposure amount, and therefore, the preliminary pixel defining film 119p having a different thickness for each region can be formed at once.

For example, as shown in fig. 23b, the preliminary pixel defining film 119p may include: the first preliminary pixel defining film 119 pa; a second preliminary pixel defining film 119pb surrounded by the first preliminary pixel defining film 119 pa; and a third preliminary pixel defining film 119pc corresponding to the peripheral area PA.

The thickness of the first preliminary pixel defining film 119pa may be thicker than the thickness of the second preliminary pixel defining film 119 pb. The thickness of the first preliminary pixel defining film 119pa may be thicker than that of the third preliminary pixel defining film 119 pc. The thickness of the second preliminary pixel defining film 119pb and the thickness of the third preliminary pixel defining film 119pc may be the same or different. For example, as shown in fig. 23b, the thickness of the third preliminary pixel defining film 119pc may be thicker than that of the second preliminary pixel defining film 119 pb.

A step ST' may be formed at a boundary of the first and third preliminary pixel defining films 119pa and 119 pc. By the preliminary planarization layer 117p, a distance from the upper face of the substrate 100 to the upper face of the first preliminary pixel defining film 119pa and a distance from the upper face of the substrate 100 to the upper face of the third preliminary pixel defining film 119pc may be different, and a step ST' may be formed between the first preliminary pixel defining film 119pa and the third preliminary pixel defining film 119 pc.

Referring to fig. 23b and 23c, a second opening OP2 and a third opening OP3 exposing an upper surface of the PAD portion PAD are formed in the preliminary planarization layer 117p and the inorganic protective layer PVX, respectively, using the patterned preliminary pixel defining film 119 p. The second opening OP2 and the third opening OP3 are formed by an etching process of partially etching the preliminary planarization layer 117p and the inorganic protective layer PVX. As an example, the etching process for partially etching the preliminary planarization layer 117p and the inorganic protective layer PVX may be dry etching (dry etch). Although not shown in fig. 23c, it is also possible to remove a part of the preliminary pixel defining film 119p together to reduce the thickness of the preliminary pixel defining film 119p as a whole.

Referring to fig. 23c and 23d, an etching process of removing the second preliminary pixel defining film 119pb, the third preliminary pixel defining film 119pc, and the second preliminary planarization layer 117pb is performed. As an example, the etching process may be dry etching (dry etch).

When the etching process of removing the second preliminary pixel defining film 119pb, the third preliminary pixel defining film 119pc, and the second preliminary planarization layer 117pb is performed, a portion of the first preliminary pixel defining film 119pa and a portion of the first preliminary planarization layer 117pa may also be etched together.

As shown in fig. 23d, the planarization layer 117 includes a first portion 117a disposed on the thin film transistor TFT and a second portion 117b extending from the first portion 117a to the peripheral area PA side. At this time, the planarization layer 117 may have a step ST between the first portion 117a and the second portion 117b on the upper surface.

The first portion 117a of the planarization layer 117 and the pixel defining film 119 may have the same etched surface. The outer side of the pixel defining film 119 adjacent to the peripheral area PA and the side of the first portion 117a of the planarization layer 117 may be aligned.

Referring to fig. 23d, an intermediate layer 320 is formed on the pixel electrode 310, i.e., inside the opening of the pixel defining film 119. The intermediate layer 320 of the light emitting element 300 may include an organic light emitting layer. After that, the counter electrode 330 is formed to correspond to the plurality of light emitting elements 300. The counter electrode 330 may be formed to cover the display area DA of the substrate 100 through an opening mask.

Fig. 24 is a sectional view briefly showing a display device according to an embodiment of the present invention. In fig. 24, the same reference numerals as in fig. 20a denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 24, at least one thin film transistor TFT and a display element connected to the thin film transistor TFT may be disposed on the display area DA of the display device 1 (see fig. 1) according to an embodiment of the present invention.

The display area DA of the display device 1 includes the first to third pixels PX1, PX2, PX 3. Of course, this is exemplary, and the display device 1 may have more pixels. Also, it is shown in fig. 24 that the first to third pixels PX1, PX2, PX3 are adjacent to each other, but the present invention is not limited thereto. That is, other components such as wiring may be interposed between the first to third pixels PX1, PX2, and PX 3. Thus, for example, the first pixel PX1 and the second pixel PX2 may not be pixels arranged adjacent to each other. In addition, the cross sections of the first to third pixels PX1, PX2, PX3 in fig. 24 may not be cross sections in the same direction.

The first to third pixels PX1, PX2, PX3 each include a light emitting region EA. The light emitting region EA may be a region where light is generated and emitted to the outside. The non-light emitting regions NEA may be disposed between the light emitting regions EA, and the light emitting regions EA may be divided by the non-light emitting regions NEA.

The first to third pixels PX1, PX2, PX3 may realize lights different from each other. For example, it may be that the first pixel PX1 realizes red light, the second pixel PX2 realizes green light, and the third pixel PX3 realizes blue light. The light emitting regions EA may have various polygonal or circular shapes when viewed in plan, and may be arranged in various patterns such as stripe arrangement and penta arrangement.

On the other hand, the display device 1 may include a first quantum dot layer 220a, a second quantum dot layer 220b, and a transmission layer 220c corresponding to the light emitting region EA. The first, second and transmission layers 220a, 220b and 220c may include Quantum dots (Quantum dots) and metal nanoparticles.

For example, it may be that the first pixel PX1 includes a first quantum dot layer 220a, the second pixel PX2 includes a second quantum dot layer 220b, and the third pixel PX3 includes a transmission layer 220 c.

In the present embodiment, the average sizes of quantum dots included in the first quantum dot layer 220a and the second quantum dot layer 220b may be different from each other.

Hereinafter, a display device 1 according to an embodiment of the present invention will be specifically described according to the stacking sequence shown in fig. 24.

The substrate 100 (hereinafter, referred to as a lower substrate) may include a glass material, a ceramic material, a metal material, or a substance having a flexible or bendable characteristic. A barrier layer (not shown) may be further included between the lower substrate 100 and the buffer layer 111.

The conductive layer BML may be disposed on the lower substrate 100, and the semiconductor layer a may be disposed on the buffer layer 111. The gate electrode G may be disposed on the semiconductor layer a to overlap at least a portion of the semiconductor layer a with the gate insulating layer 113 interposed therebetween.

An interlayer insulating layer 115 may be disposed to cover the gate electrode G. A source electrode, a drain electrode, and the like may be disposed over the interlayer insulating layer 115.

A planarization layer 117 may be disposed on the source electrode and the drain electrode, and the first to third light-emitting elements 300a, 300b, and 300c may be disposed on the planarization layer 117. The first to third light emitting elements 300a, 300b, 300c each commonly include a pixel electrode 310, an intermediate layer 320 including an organic light emitting layer, and a counter electrode 330. A pixel defining film 119 may be disposed on the planarization layer 117.

The first to third light emitting elements 300a, 300b, 300c may be easily damaged by moisture, oxygen, or the like from the outside, and thus may be covered and protected with the thin film encapsulation layer 400. The thin film encapsulation layer 400 may cover the display area DA and extend to the outside of the display area DA. The thin film encapsulation layer 400 includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

The first inorganic encapsulation layer 410 may cover the counter electrode 330 and include silicon oxide, silicon nitride, and/or silicon oxynitride, etc. Although not shown, another layer such as a cover layer may be interposed between the first inorganic sealing layer 410 and the counter electrode 330 as needed. The first inorganic encapsulation layer 410 is formed along the structure thereunder and thus has an uneven upper surface. The organic encapsulation layer 420 may cover such a first inorganic encapsulation layer 410 and make its upper side substantially flat differently from the first inorganic encapsulation layer 410.

Even if a crack is generated in the thin film encapsulation layer 400, the thin film encapsulation layer 400 may have such a crack that is not connected between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430 by the aforementioned multilayer structure. This can prevent or minimize the formation of a path through which moisture, oxygen, or the like from the outside can penetrate into the display area DA.

The upper substrate 200 is positioned above the lower substrate 100 with the counter electrode 330 interposed between the upper substrate 200 and the lower substrate 100.

A light-shielding layer 230 is disposed on the lower surface of the upper substrate 200 in the direction of the lower substrate 100. The light-shielding layer 230 includes openings corresponding to the first to third light-emitting elements 300a, 300b, and 300c, respectively, and the first to third filter layers 210a, 210b, and 210c are located in the openings, respectively. The light-shielding layer 230 may be a layer for improving color brightness and contrast as a black matrix. The light-shielding layer 230 may include at least one of a black pigment, a black dye, or black particles. In some embodiments, the light shielding layer 230 may include Cr or CrO_X、Cr/CrO_X、Cr/CrO_X/CrN_YResins (carbon pigments, RGB mixed pigments), Graphite (Graphite), non-Cr-based materials, and the like.

The first filter layer 210a may pass only light having a wavelength of 630nm to 780nm, the second filter layer 210b may pass only light having a wavelength of 495nm to 570nm, and the third filter layer 210c may pass only light having a wavelength of 450nm to 495 nm. The first to third filter layers 210a, 210b, 210c may function to reduce reflection of external light in the display device 1.

A first upper insulating layer 240 is disposed on the light-shielding layer 230. The first upper insulating layer 240 includes 1 st-1 st openings 241a corresponding to the first light emitting elements 300a, 1 st-2 nd openings 241b corresponding to the second light emitting elements 300b, and 1 st-3 rd openings 241c corresponding to the third light emitting elements 300 c. The first quantum dot layer 220a is positioned in the 1 st-1 st opening 241a, the second quantum dot layer 220b is positioned in the 1 st-2 nd opening 241b, and the transmission layer 220c is positioned in the 1 st-3 rd opening 241 c. The first quantum dot layer 220a and the second quantum dot layer 220b may be formed by inkjet printing.

The first upper insulating layer 240 may, for example, include an organic substance. According to circumstances, the first upper insulating layer 240 may include a light blocking substance to function as a light blocking layer. The light-shielding substance may, for example, contain at least one of a black pigment, a black dye, black particles or metal particles. In one embodiment, the first upper insulating layer 240 may be blue.

The first quantum dot layer 220a may convert the light of the first wavelength band generated from the intermediate layer 320 on the pixel electrode 310 into the light of the second wavelength band. For example, if light having a wavelength of 450nm to 495nm is generated from the intermediate layer 320 on the pixel electrode 310, the first quantum dot layer 220a may convert the light into light having a wavelength of 630nm to 780 nm. Thereby, in the first pixel PX1, light having a wavelength of 630nm to 780nm is emitted to the outside through the upper substrate 200.

The second quantum dot layer 220b may convert the light of the first wavelength band generated from the intermediate layer 320 on the pixel electrode 310 into the light of the third wavelength band. For example, if light having a wavelength of 450nm to 495nm is generated from the intermediate layer 320 on the pixel electrode 310, the second quantum dot layer 220b may convert the light into light having a wavelength of 495nm to 570 nm. Thus, in the second pixel PX2, light having a wavelength of 495nm to 570nm is emitted to the outside through the upper substrate 200.

Each of the first and second quantum dot layers 220a and 220b may have a form in which quantum dots are dispersed in a resin. The quantum dots include semiconductor substances such as cadmium sulfide (CdS), cadmium telluride (CdTe), zinc sulfide (ZnS), or indium phosphide (InP). The size of the quantum dot may be several nanometers, and the wavelength of the converted light is different according to the size of the quantum dot. Any resin included in the first quantum dot layer 220a and the second quantum dot layer 220b may be used as long as it is a light-transmissive substance. For example, a polymer resin such as acrylic, Benzocyclobutene (BCB), or Hexamethyldisiloxane (HMDSO) may be used as the substance for forming the first and second quantum dot layers 220a and 220 b.

In the third pixel PX3, the light of the first wavelength generated from the intermediate layer 320 can be emitted to the outside without wavelength conversion. Therefore, the third pixel PX3 may not have a quantum dot layer. In this way, since the quantum dot layer is not required in the 1 st to 3 rd openings 241c, the transmissive layer 220c formed of the light transmissive resin can be disposed. The transmissive layer 220c may include acrylic acid, Benzocyclobutene (BCB; Benzocyclobutene), or Hexamethyldisiloxane (HMDSO). Of course, according to circumstances, it is also possible that the transmissive layer 220c is not present in the 1 st to 3 rd openings 241c, unlike that shown in fig. 24.

In such a display device according to the present embodiment, light of the second wavelength band is externally emitted in the first pixel PX1, light of the third wavelength band is externally emitted in the second pixel PX2, and light of the first wavelength band is externally emitted in the third pixel PX 3. Therefore, the display device 1 according to the present embodiment can display a full color image.

A second upper insulating layer 250 is disposed on the first upper insulating layer 240. The second upper insulating layer 250 includes 2 nd-1 st openings 251a corresponding to the 1 st-1 st openings 241a, 2 nd-2 nd openings 251b corresponding to the 1 st-2 nd openings 241b, and 2 nd-3 rd openings 251c corresponding to the 1 st-3 rd openings 241 c.

The first and second quantum dot layers 220a and 220b respectively positioned in the 1 st-1 st and 1 st-2 nd openings 241a and 241b may be formed in an inkjet printing manner, and the 2 nd-1 st and 2 nd openings 251a and 251b may be channels through which ink ejected through nozzles drops and moves when the inkjet printing is performed. The ink moved through the second upper insulating layer 250 including the 2-1 st opening 251a and the 2-2 nd opening 251b may reach into the 1-1 st opening 241a and the 1-2 nd opening 241b, respectively, and form the first quantum dot layer 220a and the second quantum dot layer 220 b.

The second upper insulating layer 250 may contain a light blocking substance. For example, the light-shielding substance may include at least one of a black pigment, a black dye, a black particle, or a metal particle. In addition, in an embodiment, the second upper insulating layer 250 may be blue. As described above, the first upper insulating layer 240 may contain a light shielding material, but materials constituting the first upper insulating layer 240 and the second upper insulating layer 250 may be different in order to form the first quantum dot layer 220a and the second quantum dot layer 220b by an inkjet printing method.

For example, the second upper insulating layer 250, which is a channel through which ink ejected through a nozzle moves at the time of inkjet printing, may contain a substance having no affinity with the ink. In addition, the first upper insulating layer 240 in which the ink is accumulated to form the first and second quantum dot layers 220a and 220b may contain a substance having affinity with the ink.

In fig. 24, all of the first upper insulating layer 240 and the second upper insulating layer 250 are shown, but the second upper insulating layer 250 may be omitted, or only the first upper insulating layer 240 may be disposed on the upper substrate 200.

A filler 600 may be further disposed between the lower substrate 100 and the upper substrate 200. The filler 600 may play a role of buffering against external pressure or the like. The filler 600 may be formed of an organic material such as methyl silicone, phenyl silicone, or polyimide. However, the filler 600 is not limited thereto, and may be formed of urethane resin, epoxy resin, acrylic resin, or silicon, which is an organic sealant.

Fig. 25 is a sectional view briefly showing a display device according to an embodiment of the present invention. Specifically, fig. 25 is an exemplary sectional view of the display device of fig. 1 taken along I-I 'and II-II'. In fig. 25, the same reference numerals as in fig. 20a denote the same components, and a repetitive description thereof will be omitted.

Referring to fig. 25, the display device 1 includes a display area DA and a peripheral area PA. The substrate 100 may have regions corresponding to the display region DA and the peripheral region PA.

Referring to the display area DA of fig. 25, a conductive layer BML, a thin film transistor TFT, and a light emitting element 300 may be disposed on the substrate 100. Details of this are already described in fig. 20 a.

A thin film encapsulation layer 400 may be disposed on the light emitting element 300. The thin film encapsulation layer 400 may be disposed to cover the entire display area DA and extend to the peripheral area PA side to cover a part of the peripheral area PA. The thin film encapsulation layer 400 may extend to the outside of the common voltage supply line CVL.

The thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, a second inorganic encapsulation layer 430, and an organic encapsulation layer 420 interposed therebetween.

A portion 330a of the counter electrode 330 may extend to the peripheral area PA side to overlap the common voltage supply line CVL. A connection wiring CL may be disposed between a portion 330a of the counter electrode 330 and the common voltage supply line CVL. The connection wiring CL may electrically connect the common voltage supply line CVL and the counter electrode 330 so that the common voltage may be transmitted to the counter electrode 330.

Although not shown in fig. 25, a driving circuit region is arranged on the peripheral region PA. For example, a gate driver circuit portion may be arranged in the driver circuit region. The gate driving circuit part may include a thin film transistor, and include a wiring connected to the thin film transistor.

The buffer layer 111, the interlayer insulating layer 115, and the inorganic protective layer PVX may extend toward the peripheral area PA.

The first DAM1, the second DAM2, and the mask support MS may be disposed on the inorganic protective layer PVX corresponding to the peripheral area PA. The first DAM1, the second DAM2, and the mask holder MS may be configured to surround the periphery of the display area DA in a plane. That is, it may be that the first DAM1 is disposed to surround the periphery of the display area DA, the second DAM2 is disposed to surround the periphery of the first DAM1, and the mask holder MS is disposed to surround the periphery of the second DAM 2.

The first DAM1 and the second DAM2 may function to prevent the organic encapsulation layer 420 of the thin film encapsulation layer 400 from overflowing to the outside of the substrate 100. The mask holder MS may function to support an opening mask used in forming the counter electrode 330 or the like.

The first and second inorganic encapsulation layers 410 and 430 of the thin film encapsulation layer 400 may partially overlap the first and second DAM1 and 2. In contrast, as shown in fig. 25, the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may not overlap the mask holder MS.

The first DAM1, the second DAM2, and the mask holder MS may be provided in a double-layered structure. The first DAM1, the second DAM2, and the mask holder MS may each include a first peripheral insulating layer 117s containing the same substance as the planarization layer 117 and a second peripheral insulating layer 119s containing the same substance as the pixel defining film 119. The first and second peripheral insulating layers 117s and 119s forming the first and second DAM1 and DAM2 and the mask holder MS, respectively, may be disposed at the same layer as the planarization layer 117 and the pixel defining film 119, respectively.

The first peripheral insulating layer 117s and the second peripheral insulating layer 119s may have the same etched surface. The side of the first peripheral insulating layer 117s and the side of the second peripheral insulating layer 119s may be located on the same etched face. In other words, the side of the first peripheral insulating layer 117s and the side of the second peripheral insulating layer 119s may be aligned. The side surface of the first peripheral insulating layer 117s and the side surface of the second peripheral insulating layer 119s may be located on the same plane. In other words, the side surface of the first peripheral insulating layer 117s and the side surface of the second peripheral insulating layer 119s may be formed without steps and may be formed without a boundary.

The width of the mask holder MS may be wider than the width of the first DAM 1. The width of the mask holder MS may be wider than the width of the second DAM 2. As an example, the width of the mask holder MS may be about 4 to 6 times the width of the first DAM 1.

The invention has been described with reference to the embodiments shown in the drawings, which are intended to be illustrative only, since various modifications and equivalent other embodiments are possible, as would be understood by those of ordinary skill in the art. Therefore, the true technical scope of the present invention should be determined by the technical idea of the appended claims.