Semiconductor element and manufacturing method thereof
阅读说明：本技术 半导体元件及其制作方法 (Semiconductor element and manufacturing method thereof ) 是由 黄世贤 刘昇旭 谈文毅 于 2020-05-29 设计创作，主要内容包括：本发明公开一种半导体元件及其制作方法,其中该制作半导体元件的方法为先形成一栅极结构于基底上,然后形成一间隙壁于栅极结构旁,形成凹槽于间隙壁旁,修整部分间隙壁,再形成一外延层于凹槽内。半导体元件又包含第一突起部设于外延层一侧以及第二突起部设于外延层另一侧,其中第一突起部包含一V形设于间隙壁下方且V形的夹角大于30度以及小于90度。(The invention discloses a semiconductor element and a manufacturing method thereof, wherein the method for manufacturing the semiconductor element comprises the steps of firstly forming a grid structure on a substrate, then forming a gap wall beside the grid structure, forming a groove beside the gap wall, trimming part of the gap wall, and then forming an epitaxial layer in the groove. The semiconductor element also comprises a first protrusion part arranged on one side of the epitaxial layer and a second protrusion part arranged on the other side of the epitaxial layer, wherein the first protrusion part comprises a V-shaped structure arranged below the gap wall, and the included angle of the V-shaped structure is larger than 30 degrees and smaller than 90 degrees.)
1. A method of fabricating a semiconductor device, comprising:
forming a gate structure on a substrate;
forming a spacer beside the gate structure;
forming a first groove beside the gap wall;
trimming a portion of the spacer; and
a first epitaxial layer is formed in the first groove.
2. The method of claim 1, further comprising:
performing a first etching process to remove the substrate to form a second groove;
performing a second etching process to trim the spacer;
performing a third etching process to enlarge the second groove to form the first groove; and
forming the first epitaxial layer in the first groove.
3. The method of claim 2, wherein said first etch process comprises a dry etch process.
4. The method of claim 2, wherein said second etch process comprises a dry etch process.
5. The method of claim 2, wherein said third etch process comprises a wet etch process.
6. The method of claim 2, further comprising:
carrying out a fourth etching manufacturing process to remove the first epitaxial layer;
forming a second epitaxial layer comprising in-situ dopants on the first epitaxial layer; and
a third epitaxial layer is formed on the second epitaxial layer.
7. The method of claim 6, wherein said first epitaxial layer and said second epitaxial layer comprise opposite dopants.
8. The method of claim 6, wherein the second epitaxial layer comprises a first V-shape.
9. The method of claim 1, further comprising:
forming a first protrusion on one side of the first epitaxial layer; and
and forming a second protrusion part on the other side of the first epitaxial layer.
10. The method of claim 9, wherein the first protrusion comprises a second V-shape disposed below the spacer.
11. The method of claim 10, wherein the included angle of the second V-shape is greater than 30 degrees and less than 90 degrees.
12. A semiconductor device, comprising:
the grid structure is arranged on the substrate;
a spacer disposed beside the gate structure; and
and the epitaxial layer is arranged beside the gap wall, wherein the epitaxial layer comprises a protrusion part which is positioned below the gap wall and has an included angle larger than 30 degrees.
13. The semiconductor device of claim 12, further comprising:
a first protrusion portion provided on one side of the epitaxial layer; and
and a second protrusion portion provided on the other side of the epitaxial layer.
14. The semiconductor device as defined in claim 13, wherein the first protrusion comprises a V-shape under the spacer.
15. The semiconductor device as defined in claim 14, wherein the included angle of the V-shape is greater than 30 degrees and less than 90 degrees.
16. The semiconductor device as defined in claim 13, wherein the first protrusion depth is less than one fifth of the thickness of the epitaxial layer.
17. A semiconductor device, comprising:
the grid structure is arranged on the substrate;
a spacer disposed beside the gate structure;
the first epitaxial layer is arranged beside the gap wall;
a second epitaxial layer disposed on the first epitaxial layer, wherein the second epitaxial layer comprises a V-shape; and
and the third epitaxial layer is arranged on the second epitaxial layer.
18. The semiconductor device of claim 17, wherein said first epitaxial layer and said second epitaxial layer comprise opposite dopants.
19. The semiconductor device of claim 17, wherein said second epitaxial layer and said third epitaxial layer comprise opposite dopants.
20. The semiconductor device as defined in claim 17, wherein the V-shape is located directly below the spacer.
Technical Field
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for trimming a spacer by an etching process before forming an epitaxial layer.
Background
In order to increase the carrier mobility of the semiconductor structure, the gate channel may be selectively stressed in a compressive or tensile manner. For example, if compressive stress is required, the prior art often uses a Selective Epitaxial Growth (SEG) technique to form an epitaxial structure, such as a silicon germanium (SiGe) epitaxial structure, having the same lattice arrangement as the silicon substrate. By utilizing the characteristic that the lattice constant (lattice constant) of the silicon germanium epitaxial structure is larger than that of the silicon substrate lattice, the channel region of the P-type metal oxide semiconductor transistor is stressed, the carrier mobility (carrier mobility) of the channel region is increased, and the silicon germanium epitaxial structure is used for increasing the speed of the metal oxide semiconductor transistor. On the contrary, if the N-type semiconductor transistor is used, a silicon carbide (SiC) epitaxial structure may be formed in the silicon substrate to generate a tensile stress on the gate channel region.
In the epitaxial growth process of forming a MOS transistor having an epitaxial layer, a lightly doped ion implantation process is usually used to form a lightly doped drain in the substrate on both sides of the spacer before the epitaxial layer is grown, however, the formation of the lightly doped drain by the ion implantation process is not easy to precisely control the concentration distribution of the lightly doped drain and is prone to cause a leakage and Short Channel Effect (SCE). Therefore, how to improve the existing manufacturing process technology to solve the existing bottleneck is an important issue today.
Disclosure of Invention
The embodiment of the invention discloses a method for manufacturing a semiconductor element, which mainly comprises the steps of forming a grid structure on a substrate, forming a gap wall beside the grid structure, forming a groove beside the gap wall, trimming part of the gap wall and forming an epitaxial layer in the groove. The semiconductor element also comprises a first protrusion part arranged on one side of the epitaxial layer and a second protrusion part arranged on the other side of the epitaxial layer, wherein the first protrusion part comprises a V-shaped structure arranged below the gap wall, and the included angle of the V-shaped structure is larger than 30 degrees and smaller than 90 degrees.
In another embodiment of the present invention, a semiconductor device is disclosed, which mainly comprises a gate structure disposed on a substrate, a spacer disposed beside the gate structure, and an epitaxial layer disposed beside the spacer, wherein the epitaxial layer comprises a protrusion having an included angle greater than 30 degrees and disposed below the spacer.
In another embodiment of the present invention, a semiconductor device is disclosed, which mainly includes a gate structure disposed on a substrate, a spacer disposed beside the gate structure, a first epitaxial layer disposed beside the spacer, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer, wherein the second epitaxial layer has a V-shape.
Drawings
Fig. 1 to 6 are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the invention;
fig. 7 is a schematic structural diagram of a semiconductor device according to an embodiment of the invention.
Description of the main elements
12 base
14 gate structure
16: gate structure
18 gate dielectric layer
20 layer of gate material
Hard mask 22
24 lightly doped drain
26 pocket doped region
28 spacer wall
30, spacer wall
32: groove
34 holes
36: groove
38 buffer layer
40 epitaxial layer
42 first projecting part
44 second protrusion
46 source/drain regions
48 covering layer
54 interlayer dielectric layer
56 dielectric layer
58 high dielectric constant dielectric layer
60 work function metal layer
62 low resistance metal layer
64 metal gate
66 metal gate
68 hard mask
70 contact plug
72 first epitaxial layer
74 second epitaxial layer
76 third epitaxial layer
Detailed Description
Referring to fig. 1 to 6, fig. 1 to 6 are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the invention. As shown in fig. 1, a substrate 12 is provided, and gate structures 14 and 16 are formed on the substrate 12. In the present embodiment, the gate structures 14, 16 are preferably formed by sequentially forming a gate dielectric layer, a gate material layer and a hard mask on the substrate 12, performing a pattern transfer process using a patterned photoresist (not shown) as a mask to remove a portion of the hard mask, a portion of the gate material layer and a portion of the gate dielectric layer by a single etching step or a sequential etching step, and then stripping the patterned photoresist to form the gate structures 14, 16 at least comprising the patterned gate dielectric layer 18, the patterned gate material layer 20 and the patterned hard mask 22 on the substrate 12, wherein the gate dielectric layer 18 and the gate material layer 20 preferably form gate electrodes. It should be noted that, in order to highlight the steps related to forming the epitaxial layer between the gate structures 14 and 16, the embodiment mainly takes the formation of two transistors on the substrate 12 as an example and only shows a portion of the two transistors and the region between the two gate structures 14 and 16.
In the present embodiment, the substrate 12 is a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. The gate dielectric layer 18 may comprise silicon dioxide (SiO)2) Silicon nitride (SiN) or high dielectric constant (high-k) materials; the gate material layer 20 may include a conductive material such as a metal material, polysilicon, or metal silicide (silicide); the hard mask 22 may be selected from the group consisting of silicon oxide, silicon nitride, silicon carbide (SiC), and silicon oxynitride (SiON), but is not limited thereto.
In addition, in one embodiment, a plurality of doped wells (not shown) or a plurality of Shallow Trench Isolations (STI) for electrical isolation may be formed in the substrate 12 in advance. Moreover, although the present embodiment is illustrated with a planar transistor, in other variations, the semiconductor fabrication process of the present invention may be applied to a non-planar transistor, such as a Fin-FET (Fin-FET), where the substrate 12 as indicated in fig. 1 is correspondingly represented as a Fin structure formed on a substrate 12.
Then, at least one spacer is formed on the sidewalls of the gate structures 14 and 16, and an ion implantation process is performed, for example, by implanting dopants into the substrate 12 at two sides of the gate structures 14 and 16 by oblique angle ion implantation to form pocket implantation regions (pocket implantation) 26. In the present embodiment, the spacer is preferably a composite spacer, which may be detailed as a spacer 28 disposed on the sidewalls of the gate structures 14, 16 or the gate electrodes and a spacer 30 disposed on the sidewalls of the spacer 28, wherein the inner spacer 28 and the outer spacer 30 preferably comprise I-shaped cross-sections. In the present embodiment, the inner spacer 28 may comprise the same or different material as the outer spacer 30 and both spacers 28, 30 may comprise silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride. In addition, the pocket-shaped doped region 26 preferably comprises a different conductivity type than the MOS device to be fabricated. Taking the fabrication of the pmos transistor of this embodiment as an example, the pocket doping region 26 preferably includes N-type dopants, but is not limited thereto.
Next, as shown in FIG. 2, a first etching process is performed to form initial recesses 32 in the substrate 12 on both sides of the spacers 30. In the present embodiment, the first etching process preferably includes a dry etching process, and the first etching process may further include a three-stage etching process, wherein the first stage etching process includes performing a vertical etching process to remove a portion of the substrate 12, the second stage etching process includes performing a horizontal etching process to remove a portion of the substrate 12, and the third stage etching process includes performing another vertical etching process to remove a portion of the substrate 12 and form the recess 32.
For details, the first-stage etching process preferably includes hydrogen bromide (HBr) and/or helium (He), wherein the flow rate of the HBr and the helium in the first-stage etching process is about 200/20 standard milliliters per minute (sccm) and the process time is about 11 seconds. The second etching process preferably comprises chlorine (Cl)2) And/or ammonia (NH)3) WhereinThe flow rates of chlorine and ammonia in the second stage etching process are about 50/10 standard milliliters per minute (sccm) for a process time of about 15 seconds. The third-stage etching process preferably comprises hydrogen bromide (HBr) and/or helium (He), wherein the flow rate of the HBr and the helium is about 200/20 standard milliliters per minute (sccm) and the process time is about 6-10 seconds.
A second etch process is then performed to trim or thin the spacers 30 and reduce the thickness of the spacers 30 slightly, as shown in fig. 3. In the present embodiment, the second etching process preferably includes trifluoromethane (CHF)3) Carbon tetrafluoride (CF)4) Or a combination thereof, wherein the flow rate of the trifluoromethane and the carbon tetrafluoride in the second etching process is about 35/60 standard milliliters per minute (sccm) and the process time is about 0.05 nanoseconds. It should be noted that, in this stage, the etching gas composition used in the second etching process for trimming the spacers 30 is preferably used to simultaneously remove a portion of the substrate 12 on both sides of the spacers 30 to form the holes 34 directly below the spacers 30, wherein although the thickness of the sidewalls of the spacers 30 is slightly reduced in the second etching process, the bottoms of the spacers 30 are preferably aligned with the surface of the substrate 12, so that the tops of the formed holes 34 are preferably aligned with the surface of the substrate 12 directly below the gate structures 14 and 16 or the bottoms of the spacers 28, and the holes 34, except for exposing a portion or all of the bottoms of the spacers 30, may extend inward or even expose the bottoms of the spacers 28 according to the process requirements, which is also encompassed by the present invention.
As shown in fig. 4, a third etching process is then performed to isotropically enlarge the initial recess 32 to form another recess 36. In an embodiment of the present invention, the third etching process preferably includes a wet etching process, wherein the wet etching process may selectively use, for example, ammonium hydroxide (NH)4OH) or tetramethylammonium hydroxide (TMAH). It should be noted that the manner of forming the groove 36 is not limited to the manner of wet etching, and may be formed by dry etching and/or wet etching once or several times. For example, in one embodiment, the grooves 36 may have different cross-sectional shapesThe shape of the cross section is, for example, a circular arc, a hexagonal (also called sigma Σ), or an octagonal (octagon), etc., the embodiment is described with the hexagonal cross section as an implementation, but not limited thereto.
Subsequently, as shown in fig. 5, a Selective Epitaxial Growth (SEG) process is performed to sequentially form the buffer layer 38 and the epitaxial layer 40 in the recess 36 and fill the hole 34. In the present embodiment, the overall shape of the buffer layer 38 and the epitaxial layer 40 preferably exhibits a substantially hexagonal shape (sigma) and the top surface of the epitaxial layer 40 is preferably slightly higher than the surface of the substrate 12. Taking the epitaxial layer 40 between one side of the gate structure, such as the gate structures 14 and 16, as an example, two protrusions are preferably formed on the sidewalls of the epitaxial layer 40 at the bottom of the spacer 30, which fills the hole 34, and even connects the hole, wherein the two protrusions include a first protrusion 42 and a second protrusion 44, and each of the first protrusion 42 and the second protrusion 44 includes a V-shape located right below the spacer 30, and the included angle of the V-shape is a V-shapePreferably greater than 30 degrees and less than 90 degrees, and the depth D of each of the first protrusions 42 and the second protrusions 44 is less than one fifth of the thickness of the epitaxial layer 40, such as, but not limited to, 5 nm to 30 nm.
In a preferred embodiment of the present invention, the epitaxial layer 40 may have different materials according to different Metal Oxide Semiconductor (MOS) transistor types, for example, if the MOS transistor is a P-type MOS transistor (PMOS), the epitaxial layer 40 may optionally comprise germanium silicide (SiGe), boron silicide (SiGeB) or tin silicide (SiGeSn). In another embodiment of the present invention, if the MOS transistor is an N-type metal oxide semiconductor (NMOS), the epitaxial layer 40 may optionally comprise silicon carbide (SiC), silicon carbon phosphide (SiCP) or silicon phosphide (SiP). In addition, the selective epitaxial process may be formed in a single layer or multiple layers, and the hetero atoms (e.g., germanium atoms or carbon atoms) may be changed in a graded manner, but it is preferable that the surface of the epitaxial layer 40 be light or free of germanium atoms for the formation of the metal silicide layer. To be provided withIn the case of fabricating a PMOS transistor in this embodiment, the germanium content in the epitaxial layer 40 is preferably between 30% and 50% and the boron concentration is preferably between 1.0 × 1020Atoms/cubic centimeter to 1.0 x 1021Atoms per cubic centimeter.
It should be noted that, compared to the existing lightly doped drain formed by ion implantation, the present embodiment mainly omits the means of forming the lightly doped drain by ion implantation process and utilizes in-situ doping to form the doped region with uniform concentration distribution while forming the epitaxial layer 40, wherein the doped regions at the positions of the first protrusion 42 and the second protrusion 44 are preferably used as the lightly doped drain 24. An ion implantation process may then be performed to form source/drain regions 46 in the substantially central portion of the epitaxial layer 40, particularly outside the first and second protrusions 42, 44 or on both sides of the spacer 30 rather than directly under the spacer 30, wherein the dopant concentration of the source/drain regions 46 is preferably greater than the dopant concentration of the lightly doped drains 24 of the first and second protrusions 42, 44 and has the same conductivity type. A cap layer 48 is then formed over the epitaxial layer 40, wherein the cap layer 48 preferably comprises silicon grown to extend upwardly from the sidewalls of the spacers 30 and the top of the cap layer 48 preferably comprises a planar upper surface.
As shown in fig. 6, a contact hole etch stop layer (not shown) and an interlayer dielectric layer 54 are sequentially formed on each gate structure 14, 16, and then a planarization process is performed, such as using Chemical Mechanical Polishing (CMP) to remove a portion of the interlayer dielectric layer 54 and a portion of the contact hole etch stop layer and expose the gate material layer 20 made of polysilicon material, so that the upper surface of each hard mask 22 is flush with the upper surface of the interlayer dielectric layer 54.
A metal gate replacement process is then performed to convert the gate structures 14, 16 into metal gates. For example, a selective dry or wet etching process, such as ammonia (NH), may be performed4OH) or Tetramethylammonium Hydroxide (TMAH), etc., to sequentially remove the hard mask 22, the gate material layer 20, and even the hard mask 22 in the gate structures 14 and 16Gate dielectric 18 is formed to form a recess (not shown) in ild 54. A selective dielectric layer 56 or a gate dielectric layer (not shown), a high-k dielectric layer 58, a work function metal layer 60, and a low-resistance metal layer 62 are sequentially formed in each recess, and a planarization process is performed, such as CMP, to remove a portion of the low-resistance metal layer 62, a portion of the work function metal layer 60, and a portion of the high-k dielectric layer 58 to form the gate structures 14 and 16 formed by the metal gates 64 and 66. Taking the gate structure fabricated by the post-high-k dielectric layer fabrication process of the present embodiment as an example, each of the gate structures 14, 16 preferably includes a dielectric layer 56 or gate dielectric layer (not shown), a U-shaped high-k dielectric layer 58, a U-shaped work function metal layer 60, and a low-resistance metal layer 62.
In the present embodiment, the high-k dielectric layer 58 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO)2) Hafnium silicate oxide (HfSiO)4) Hafnium silicate oxynitride (HfSiON), aluminum oxide (Al)2O3) Lanthanum oxide (La)2O3) Tantalum oxide (Ta), and a process for producing the same2O5) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) Strontium titanate (SrTiO), strontium titanate oxide (srf)3) Zirconium silicate oxide (ZrSiO)4) Hafnium zirconate (HfZrO) oxide4) Strontium bismuth tantalum oxide (SrBi)2Ta2O9SBT), lead zirconate titanate (PbZr)xTi1-xO3PZT), barium strontium titanate (Ba)xSr1-xTiO3BST), or combinations thereof.
The work function metal layer 60 is preferably used to adjust the work function of the metal gate formed, making it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 60 may be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 60 may be made of a metal material having a work function of 4.8eV to 5.2eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 60 and the low resistance metal layer 62, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and the like. The low resistance metal layer 62 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), and combinations thereof.
Then, a portion of the high-k dielectric layer 58, a portion of the work function metal layer 60, and a portion of the low-resistance metal layer 62 may be selectively removed to form a recess (not shown), and then a hard mask 68 is filled into the recess such that the hard mask 68 is flush with the surface of the interlayer dielectric layer 54, wherein the hard mask 68 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
A contact plug formation process may then be performed to form contact plugs 70 electrically connecting the source/drain regions 46, respectively. In the present embodiment, the contact plug 70 is formed by removing a portion of the interlayer dielectric layer 54 and a portion of the contact hole etch stop layer to form a contact hole (not shown), and then sequentially depositing a barrier layer (not shown) and a metal layer (not shown) on the substrate 12 to fill the contact hole. Then, a planarization process, such as CMP, is used to remove a portion of the metal layer, a portion of the barrier layer, or even a portion of the inter-layer dielectric 54, so as to form the contact plug 70 in the contact hole, wherein the upper surface of the contact plug 70 is preferably aligned with the upper surface of the inter-layer dielectric 54. In the present embodiment, the barrier layer is preferably selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride and tungsten nitride, and the metal layer is preferably selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum and copper, but not limited thereto.
Referring to fig. 6 again, fig. 6 further discloses a structural schematic diagram of a semiconductor device according to an embodiment of the invention. As shown in fig. 6, the semiconductor device mainly includes a gate structure 14 formed by a metal gate 64 disposed on a substrate 12, spacers 28 and 30 disposed beside the gate structure 14, pocket-shaped doped regions 26 respectively disposed in the substrate 12 at two sides of the gate structure 14, and an epitaxial layer 40 disposed in the substrate 12 beside the spacers 30, wherein each epitaxial layer 40 includes two protrusions and each protrusion has an included angle greater than 30 degrees and is located below each spacer 30.
Taking the example of the epitaxial layer 40 on one side of the gate structure, e.g., between the gate structures 14 and 16, the semiconductor device includes a first protrusion 42 disposed on one side of the epitaxial layer 40 and a second protrusion 44 disposed on the other side of the epitaxial layer 40, wherein the first protrusion 42 is disposed in the substrate 12 on one side of the gate structure 14 and the second protrusion 44 is disposed in the substrate 12 on one side of the gate structure 16. In detail, the first protrusion 42 directly contacts the bottom of the spacer 30 beside the gate structure 14, the second protrusion 44 directly contacts the bottom of the spacer 30 beside the gate structure 16, and the first protrusion 42 and the second protrusion 44 each include a V-shape below the spacer 30, and the included angle of the V-shapePreferably greater than 30 degrees and less than 90 degrees, and the depth D of each of the first protrusions 42 and the second protrusions 44 is less than one fifth of the thickness of the epitaxial layer 40, such as, but not limited to, 5 nm to 15 nm.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a semiconductor device according to an embodiment of the invention. As shown in fig. 7, after the buffer layer 38 is formed in fig. 5, a first epitaxial layer 72 is formed in the recess 32 and the hole 34 may be filled or not filled, and then a fourth etching process is performed to remove a portion of the first epitaxial layer 72 by using, for example, hydrochloric acid (HCl), so as to form a second epitaxial layer 74 having a V-shaped cross section on the first epitaxial layer 72, form a third epitaxial layer 76 on the second epitaxial layer 74, and form a cap layer 48 on the third epitaxial layer 76.
It is noted that, in order to improve the leakage current of the device, the present embodiment may implant dopants into the first epitaxial layer 72 and the third epitaxial layer 76 as the source/drain regions 46 by in-situ doping, and implant dopants into the second epitaxial layer 74 as the lightly doped drain 24 by in-situ doping having a conductivity type opposite to that of the first epitaxial layer 72 or the source/drain regions 46. Taking the PMOS transistor of this embodiment as an example, the source/drain regions 46 in the first epitaxial layer 72 and the third doped region 76 preferably comprise P-type dopants and the second epitaxial layer 74 preferably comprises N-type dopants, but are not limited thereto.
As a whole, the second epitaxial layer 74 itself has a substantially V-shaped cross section, and like the epitaxial layer 40 of the previous embodiment, two protrusions are preferably formed on two sides of the second epitaxial layer 74 at the positions where the holes 34 are filled up, including the first protrusion 42 and the second protrusion 44 as the lightly doped drain 24, wherein the first protrusion 42 and the second protrusion 44 each include a V-shape located right below the spacer 30, and the included angle of the V-shape is the same as that of the first protrusion 42 and the second protrusion 44Preferably greater than 30 degrees and less than 90 degrees, and the depth D of each of the first and second protrusions 42 and 44 is less than one fifth of the thickness of the first to third epitaxial layers 72 to 76, for example, but not limited to, 5 nm to 30 nm. In the present embodiment, the germanium content of the first epitaxial layer 72 and/or the third epitaxial layer 76 is preferably between 30% and 50% and the concentration of the P-type dopant, such as boron, contained therein is preferably between 1.0 × 1020Atoms/cubic centimeter to 1.0 x 1021The germanium content of the second epitaxial layer 74 is preferably between 30% and 50% and the concentration of the N-type dopant, such as phosphorus, contained therein is preferably between 1.0 x 10 atoms/cc16Atoms/cubic centimeter to 1.0 x 1021Atoms per cubic centimeter.
Generally, after the pocket doping region 26 is formed by the ion implantation process and before the recess 32 is formed by the first etching process, a lightly doped ion implantation process is usually additionally performed to form a lightly doped drain in the substrate on both sides of the spacer. Considering that the formation of the lightly doped drain by the ion implantation process is not easy to precisely control the concentration distribution of the lightly doped drain and is easy to cause the leakage and Short Channel Effect (SCE), the present invention mainly omits the means of forming the lightly doped drain by the ion implantation process and forms the lightly doped drain 24 (such as the first protrusion 42 and the second protrusion 44) with uniform concentration distribution while forming the epitaxial layer (such as the second epitaxial layer 74 in the foregoing embodiments) by using in-situ doping. In addition, another embodiment of the present invention can also choose to perform an additional etching process to trim or thin the outermost spacer 30 after forming the recess 32 in the substrate, so that the lightly doped drain and the epitaxial layer formed by the subsequent synchronous doping method are closer to the gate structure to improve the overall performance of the device.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.