阅读说明：本技术 处理器核、处理器、片上系统和调试系统 (Processor core, processor, system on chip and debugging system ) 是由 刘畅 夏天一 赵彬广 郭世晟 于 2021-07-06 设计创作，主要内容包括：提供一种处理器核、处理器、片上系统和调试系统。该处理器核包括：调试单元,用于持续接收第一调试请求,并在第一调试请求表征在第一程序指令之后进入调试模式时,根据第一调试请求产生第二调试请求；取指令单元,用于读取程序指令；指令译码单元,用于对程序指令进行译码,根据第一调试请求将第一程序指令的译码结果发送给普通执行单元,根据第二调试请求将第二程序指令的译码结果发送给特殊执行单元；指令执行单元,包括特殊执行单元和普通执行单元；指令提交单元,用于提交第一程序指令的执行结果,并根据第二程序指令的指令信息进入调试模式或响应调试异常。该方案减少处理器核内为了实现调试功能的逻辑判断元件的数量,有助于降低制造成本。(A processor core, a processor, a system on a chip, and a debug system are provided. The processor core includes: the debugging unit is used for continuously receiving the first debugging request and generating a second debugging request according to the first debugging request when the first debugging request is characterized and enters a debugging mode after the first program instruction; an instruction fetching unit for reading a program instruction; the instruction decoding unit is used for decoding the program instruction, sending a decoding result of the first program instruction to the common execution unit according to the first debugging request, and sending a decoding result of the second program instruction to the special execution unit according to the second debugging request; the instruction execution unit comprises a special execution unit and a common execution unit; and the instruction submitting unit is used for submitting the execution result of the first program instruction and entering a debugging mode or responding to debugging exception according to the instruction information of the second program instruction. The scheme reduces the number of logic judgment elements for realizing debugging functions in the processor core, and is beneficial to reducing the manufacturing cost.)

1. A processor core, comprising:

the debugging unit is used for continuously receiving a first debugging request, and generating a second debugging request according to the first debugging request when the first debugging request is characterized to enter a debugging mode after a first program instruction, wherein the second debugging request is characterized to enter the debugging mode before a second program instruction, and the second program instruction is the next instruction of the first program instruction;

an instruction fetch unit to read program instructions, the program instructions including the first program instruction and the second program instruction;

the instruction decoding unit is used for decoding a program instruction, sending a decoding result of the first program instruction to the common execution unit according to the first debugging request when the first debugging request represents that the program instruction enters a debugging mode after the first program instruction, and sending a decoding result of the second program instruction to a special execution unit according to the second debugging request;

the instruction execution unit comprises the special execution unit and the ordinary execution unit, the special execution unit does not execute the program instruction but sends instruction information, and the ordinary execution unit executes the program instruction and generates an execution result;

and the instruction submitting unit is used for submitting the execution result of the first program instruction when the first debugging request representation enters a debugging mode after the first program instruction, and entering the debugging mode or responding to debugging exception according to the instruction information of the second program instruction.

2. The processor core of claim 1, wherein the instruction decoding unit is to send a decoding result of the first program instruction to a special execution unit when the first debug request indicates that a debug mode is entered before the first program instruction, and the instruction committing unit is to enter the debug mode or respond to a debug exception according to instruction information of the first program instruction.

3. The processor core of claim 2, wherein the instruction commit unit cancels or prevents committing the execution result of the first program instruction prior to entering the debug mode if it is determined that the first debug request characterizes entering the debug mode prior to the first program instruction, which has been executed by the normal execution unit.

4. The processor core of claim 3, wherein the instruction commit unit determines based on the execution results of the normal execution unit and a first debug request received from the debug unit.

5. The processor core of claim 1, wherein the instruction commit unit is to send an indication to the debug unit if it is determined that the first debug request is characterized as entering a debug mode after a first program instruction that has been executed by the normal execution unit, the debug unit to generate a second debug request based on the first debug request based on the indication.

6. The processor core of claim 1 or 2, wherein the instruction fetch unit obtains the first and second debug requests from the debug unit, identifies the first and second program instructions accordingly, and informs the instruction decode unit of the identification result; or, the instruction decoding unit obtains the first debugging request and the second debugging request from the debugging unit or the instruction fetching unit, and accordingly identifies the first program instruction and the second program instruction.

7. The processor core of claim 1, wherein the second debug request is configured as any other debug request having a priority greater than any execution results of the second program instruction, and also having a priority greater than the second program instruction set.

8. The processor core of claim 1, wherein the second debug request is configured such that the second program instructions are unable to respond to interrupts and exceptions.

9. A processor, comprising:

one or more processor cores as claimed in any one of claims 1 to 8,

and the debugging module is used for selecting one of the one or more processor cores and sending the first debugging request.

10. The processor of claim 9, further comprising: and the protocol interface module is used for receiving a debugging command, converting the debugging command and sending the converted debugging command to the debugging module.

11. A system on a chip, comprising:

one or more processor cores as claimed in any one of claims 1 to 8,

the debugging module is used for selecting one of the one or more processor cores and sending the first debugging request;

and the protocol interface module is used for receiving a debugging command, converting the debugging command and sending the converted debugging command to the debugging module.

12. A debugging system, comprising:

the host comprises a debugging tool and a converter, wherein the debugging tool receives user operation and converts the user operation into a debugging command through the converter;

debugging transmission hardware for transmitting the debugging command;

a processor according to claim 9 or 10.

13. A debugging system, comprising:

the host comprises a debugging tool and a debugging converter, wherein the debugging tool receives user operation and converts the user operation into a debugging command through the debugging converter;

debugging transmission hardware for transmitting the debugging command;

the system on a chip of claim 11.

Technical Field

The present disclosure relates to the field of chips, and in particular, to a processor core, a processor, a system on a chip, and a debug system.

Background

In the process from design to hardware implementation of the processor, a good debugging system is of great importance, and the good debugging system can help software and hardware developers to quickly identify and correct the causes of errors. A good debugging system cannot be realized by hardware, so various debugging components are built in a processor or a processor core, and the various debugging components cooperate to complete debugging commands sent by users or other parts. Before the product is unmolded, a hardware developer can continuously improve the debugging component so as to improve the product performance and reduce the product cost.

Disclosure of Invention

In view of the above, an object of the present disclosure is to provide a processor core, a processor, a system on chip, and a debugging system, in which a hardware structure for realizing a debugging function is simplified.

In a first aspect, an embodiment of the present disclosure provides a processor core, including:

the debugging unit is used for continuously receiving a first debugging request, and generating a second debugging request according to the first debugging request when the first debugging request is characterized to enter a debugging mode after a first program instruction, wherein the second debugging request is characterized to enter the debugging mode before a second program instruction, and the second program instruction is the next instruction of the first program instruction;

an instruction fetch unit to read program instructions, the program instructions including the first program instruction and the second program instruction;

the instruction decoding unit is used for decoding a program instruction, sending a decoding result of the first program instruction to the common execution unit according to the first debugging request when the first debugging request represents that the program instruction enters a debugging mode after the first program instruction, and sending a decoding result of the second program instruction to a special execution unit according to the second debugging request;

the instruction execution unit comprises the special execution unit and the ordinary execution unit, the special execution unit does not execute the program instruction but sends instruction information, and the ordinary execution unit executes the program instruction and generates an execution result;

and the instruction submitting unit is used for submitting the execution result of the first program instruction when the first debugging request representation enters a debugging mode after the first program instruction, and entering the debugging mode or responding to debugging exception according to the instruction information of the second program instruction.

Optionally, when the first debug request indicates that the first program instruction enters the debug mode before the first program instruction, the instruction decoding unit sends a decode result of the first program instruction to the special execution unit, and the instruction submitting unit enters the debug mode or responds to a debug exception according to the instruction information of the first program instruction.

Optionally, if the instruction submitting unit determines that the first debugging request indicates that the debugging mode is entered before the first program instruction and the first program instruction is executed by the normal execution unit, the instruction submitting unit cancels or prevents the execution result of the first program instruction from being submitted before the debugging mode is entered.

Optionally, the instruction submitting unit determines according to the execution result of the normal execution unit and the first debug request received from the debug unit.

Optionally, if the instruction submitting unit determines that the first debug request is characterized by entering a debug mode after a first program instruction, and the first program instruction is executed by the normal execution unit, the instruction submitting unit sends instruction information to the debug unit, and the debug unit generates a second debug request according to the first debug request according to the instruction information.

Optionally, the instruction fetching unit obtains the first debugging request and the second debugging request from the debugging unit, identifies the first program instruction and the second program instruction accordingly, and informs the instruction decoding unit of an identification result; or, the instruction decoding unit obtains the first debugging request and the second debugging request from the debugging unit or the instruction fetching unit, and accordingly identifies the first program instruction and the second program instruction.

Optionally, the second debug request is configured as any other debug request whose priority is greater than any execution result of the second program instruction, while its priority is greater than the second program instruction setting.

Optionally, the second debug request is configured such that the second program instruction is unable to respond to interrupts and exceptions.

In a second aspect, an embodiment of the present disclosure provides a processor, including:

one or more processor cores of any of the above,

and the debugging module is used for selecting one of the one or more processor cores and sending the first debugging request.

Optionally, the processor further comprises: and the protocol interface module is used for receiving a debugging command, converting the debugging command and sending the converted debugging command to the debugging module.

In a third aspect, an embodiment of the present disclosure provides a system on a chip, including:

one or more processor cores of any of the above,

the debugging module is used for selecting one of the one or more processor cores and sending the first debugging request;

and the protocol interface module is used for receiving a debugging command, converting the debugging command and sending the converted debugging command to the debugging module.

In a fourth aspect, an embodiment of the present disclosure provides a debugging system, including:

the host comprises a debugging tool and a converter, wherein the debugging tool receives user operation and converts the user operation into a debugging command through the converter;

debugging transmission hardware for transmitting the debugging command;

the processor described above.

In a fifth aspect, an embodiment of the present disclosure provides a debugging system, including:

the host comprises a debugging tool and a debugging converter, wherein the debugging tool receives user operation and converts the user operation into a debugging command through the debugging converter;

debugging transmission hardware for transmitting the debugging command;

the system on chip is described above.

According to the processor core provided by the embodiment of the disclosure, when the first debugging request representation enters the debugging mode after the first program instruction, the second debugging request representation enters the debugging mode before the second program instruction, so that the processor core enters the debugging mode according to the second debugging request but not the first debugging request, namely, the processor core always enters the debugging mode according to the debugging request representing the debugging mode before a certain program instruction.

Drawings

The foregoing and other objects, features, and advantages of the disclosure will be apparent from the following description of embodiments of the disclosure, which refers to the accompanying drawings in which:

FIG. 1 shows a schematic diagram of a system implementing a debug function;

FIG. 2 is an exemplary diagram of a graphical interface of programming software for an embedded debug tool;

FIG. 3 is a block diagram of a processor core provided by an embodiment of the disclosure;

fig. 4 and 5 are flowcharts of a debugging function implemented based on the processor core shown in fig. 3 according to an embodiment of the present disclosure;

FIG. 6 is a block diagram of a general-purpose computer system to which an embodiment of the present disclosure is applied;

fig. 7 is a schematic structural diagram of an embedded system to which an embodiment of the present disclosure is applied.

Detailed Description

The present disclosure is described below based on examples, but the present disclosure is not limited to only these examples. In the following detailed description of the present disclosure, some specific details are set forth in detail. It will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. Well-known methods, procedures, and procedures have not been described in detail so as not to obscure the present disclosure. The figures are not necessarily drawn to scale.

Before describing the various embodiments of the present disclosure, some terms or concepts used by the present disclosure are explained and clarified.

Instruction pipelining, which is a way to increase the efficiency of a processor executing instructions, divides the operation of an instruction into multiple tiny steps, each of which is done by specialized circuitry. Currently, the mainstream instruction pipeline technology includes three-stage, four-stage, five-stage, seven-stage, super instruction pipelines, and the like. The five-stage instruction pipeline of the example textbook, for example, includes fetch, decode, execute, access, and write-back.

Debugging system

It should be noted that, since the purpose of the embodiments of the present disclosure is to describe improvements in relation to debugging functionality in a processor, components related to debugging functionality will be described with emphasis in the figures and text. Fig. 1 shows a schematic diagram of a system implementing a debugging function.

As shown in the figure, the system includes a debug host 101, debug transfer hardware 102, and a debug system 103. The debugging host 101 is an electronic product such as a notebook computer, a desktop computer, a palm computer, etc., on which a debugging tool (e.g., gdb)1011 and a translator 1012 are deployed. The debug tool 1011 communicates with a translator 1012, and the translator 1012 (e.g., OpenOCD, including hardware drivers) communicates with the debug transfer hardware (e.g., Olimex USB-JTAG adapter) 102. Debug transfer hardware 102 establishes communication between debug host 101 and debug system 103.

Debug system 103 includes a Debug Transport Module (DTM) 1031, a Debug Module Interface (DMI)1032, a Debug Module (DM) 1033, a program cache 1034, a system bus 1035, and one or more processor cores 1036. The transport implementation module 1031 accesses the debug module 1033 using one or more transport interface modules 1032. The transmission implementation module 1031 implements the access debugging module 1032 based on a transmission element (e.g., JTAG or USB component). The debug system 103 may support a plurality of transport implementation modules 1031 to allow access to the debug module 1033 by one of the transport implementation modules 1031, provided that the transport implementation module 1031 has access to the transport interface module 1032.

The transport interface module 1032 may be a secondary bus with a master-slave or a more fully functional bus similar to a TileLink or AMBA advanced peripheral bus, for implementing a translation interface between user-provided abstract debug commands and concrete implementations. As such, the debug module 1033 is slaved to a bus referred to as a Debug Module Interface (DMI) 1032.

The transmission implementation module 1031 and the transmission interface module 1032 may be understood as a whole, that is, two components constitute a protocol interface module, and the protocol interface module is configured to receive a debug command from the outside, convert the debug command, and send the converted debug command to the debug module 1033.

Debug module 1033 may control one or more processor cores 1036. Multiple processor cores 1036 may be heterogeneous or homogeneous, and are not limiting. There may be a plurality of debug modules, and the mapping between the plurality of processor cores 1036 and the plurality of debug modules is not further limited, but typically all processor cores within a single processor (or system on a chip) are controlled by the same debug module. When a user activates a debugging tool 1011, the debugging module 1033 selects a processor core for debugging, and then various commands inputted by the user through the debugging tool 1011 are executed by the processor core. Meanwhile, the user may input various control commands for the processing core, such as pause (halt), resume (resume), reset (reset), and the like, through the debugging tool 1011.

Debug module 1033 in the figure illustrates only three types of functions: reset/halt control 10331, abstract command set 10332, and bus access 10333. Reset/halt control (reset/halt control)10331 refers to a concrete functional implementation of control commands to one or more processor cores, abstract command set 10332 is a set of commands to one or more processing cores, and bus access 10333 is a bus access interface. Debug module 1033 defines a plurality of states for one or more processor cores and can continuously track changes in its state through specific commands in abstract command set 10332.

Abstract command set 10332 includes a functional implementation of a series of abstract commands, most of which are optional. One or several of these abstract commands may be supported by different debug tools 101. In operation, a user may send an abstract command through a debugging tool in a debugging state and then execute an error check command to determine whether the execution of the command was successful, in this way, it may be determined which abstract commands the user may use in the debugging tool. In addition, each abstract command has its own supported options, and when an abstract command is provided with an option that it does not support, the abstract command generates error information that is also viewed using the error-checking command.

In some embodiments, the set of abstract commands 10332 includes three types of abstract commands. The first type of abstract command drives the debug tool to access the registers and allow it to execute program instructions within program buffer 1034. The second type of abstract command drives the processor core into debug mode and then executes the program instructions in program buffer 1034. The third class of abstract commands allows the debug tool to perform memory accesses with exactly the same memory view and the permissions that the selected processor core has.

Bus access 10333 is used to implement memory access not via the processor core. Thus, the debug tool 1011 can access memory via bus access 10333 using program buffers or abstract access memory commands (contained in abstract command set 10332). A necessity of the bus access 10333 exists in that, depending on the microarchitecture, the memory data accessed via the bus access 10333 may not always be so consistent with the memory data observed at each processor core, e.g., data is written to a particular region of the memory map via the bus access 10333 but cannot be written by the processor core. Bus access 10333 is optional and the chip designer will determine whether to include bus access 10333 in the processor core based on actual product requirements.

To support execution of commands on selected processing cores, system 103 also includes a program caching mechanism that drives selected processor cores to execute a piece of program code (typically a debug instruction) by writing the piece of code to a program cache 1034. The specific operation is as follows: the debugging tool 1011 writes the program instruction into the buffer, and then the processor core accesses the buffer through a specific command in the abstract command set 10332 to execute the program instruction of the buffer, in order to return to process the command sent by the debugging module 1033 after the program instruction of the program buffer 1034 is executed, the program instruction in the program buffer needs to be ended with ebeak or c.ebeak, and when the processor core executes ebeak or c.ebeak, the instruction execution in the program buffer 1034 will be skipped. With this feature, a program buffer of only 32 bits can provide efficient debugging. As described above, the user can control and observe the process executed by the target program on the server through the debugging tool 1011. Some programming software may embed a debugging tool 1011, and the program may be run into a debugging mode (the program running mode includes a debugging mode and a normal operating mode) through the debugging tool 1011. The corresponding operation of the debugging tool by the user is converted by the converter 1012 into an activation command, which is sent via the debug transfer hardware 102 to the debugging module 1033 in the debugging system 103, during which it is passed via the transfer function module 1031 and the transfer interface module 1032. The debugging module 1033 determines which processor core the program to be debugged runs on, and a subsequent user can input various commands to view the running condition of the program to be debugged on the processor core.

Processor core 1036 is a core component for computing, accepting/storing commands, and processing data. Processor core 1036 has a complex hardware and software architecture. As shown, processor core 1036 may include an instruction fetch unit 10361, an instruction decode unit 10362, an instruction execution unit 10363, and an instruction commit unit 10364, divided according to an instruction set architecture. The instruction fetch unit 3021 may fetch a physical address and an instruction packet according to a program pointer (program PC) from an instruction cache (not shown) coupled inside the processor core 302 or an external memory. The instruction decoding unit 10362 decodes the current instruction according to an instruction set packaged in the processor core, and obtains an opcode, a source register, a destination register, and an immediate of the current instruction by decoding. The instruction execution unit 10363 includes various hardware execution units for performing various operations according to the decoding result of the instruction decoding unit 10362 and sending the execution result to the instruction issue unit 10364. Instruction commit unit 10364 is used to write execution results (e.g., calculation results of various operations stored in registers) to a data cache internal to the processor core or to memory external to the processor core.

On the basis, the processor core is also used for processing the debugging request, switching from the normal working mode to the debugging mode according to the debugging request, and entering debugging response exception if the switching from the normal working mode to the debugging mode fails. The processor core provides two response modes for the debugging request: the first is that after the processor core receives the debugging request, the processor core enters the debugging mode (or responds to the debugging exception) after the program instruction responding to the debugging request is executed; the second is that the processor core, after receiving a debug request, does not execute or cancel instructions within the program instructions in response to the debug request, and then enters debug mode (or responds to a debug exception). The specific response mode adopted by the processor core depends on the information carried by the debugging request.

FIG. 2 is an exemplary diagram of a graphical interface for programming software for an embedded debug tool. The following continues with the example of fig. 2 showing how processor core 1036 may implement debugging.

The target program debugged in the figure is a.out, the enabled debugging tool is kDbg, and referring to the figure, the user sets a debugging breakpoint on the program instruction "str [ i ] ═ a'". When the debug tool kDbg is started, the kDbg sends a debug request to the processor core 1036, after the processor core 1036 receives the debug request, it first determines a program instruction responding to the debug request, that is, a program instruction "str [ i ] ═ a'" in fig. 3, and then reads a debug time in the debug request, where the debug time may be set by the debug tool 1011 or the debug module 1033. There are two assignments for the present embodiment when setting debug time: a first value (e.g., 0) and a second value (e.g., 1), when the debug opportunity is equal to the first value, determining whether the program instruction responding to the debug request has been executed, if so, canceling the execution result of the program instruction responding to the debug request, and if not, preventing the execution of the program instruction; when the debugging opportunity is equal to the second value, judging whether the program instruction responding to the debugging request is executed completely, if so, submitting the execution result of the program instruction responding to the debugging request, if not, waiting for the execution of the program instruction to be completed, then the processor core enters a debugging mode or responds to the debugging abnormity, and continuously explaining by taking the example of fig. 2 as follows: processor core 1036 determines whether the instruction of "str [ i ] ═ a ' ″ has been executed completely when the debug time (corresponding to field timing in the debug request) is equal to a first value (for example, 0), and if so, cancels the execution result of the instruction of" str [ i ] ═ a ' ″, and if not, prevents the execution of the instruction of "str [ i ] ═ a ' ″; if the debug opportunity is equal to a second value (e.g., 1), the execution result of the instruction "str [ i ] ═ a'" is committed, and the processor core then enters debug mode or responds to a debug exception.

However, the processor core of the above scheme for processing the debug request needs more logic judgment elements, and the hardware structure is more complex.

Fig. 3 is a structural block diagram of a system for implementing debugging functions provided by the embodiment of the disclosure on the basis of fig. 1. Among other things, debug system 301 may include one or more processor cores 302 as provided by embodiments of the present disclosure.

The processor core 302 performs instruction fetching, decoding, execution, etc. of the program code according to an instruction set encapsulated within the processor core. Processor core 302 generally includes an instruction fetch unit 3021, an instruction decode unit 3022, a general execution unit 30243023, a special execution unit 3024, an instruction commit unit 3025, and a debug unit 3026.

The instruction fetch unit 3021 may fetch a physical address and an instruction packet from an instruction cache (not shown) coupled to the inside of the processor core 302 or from an external memory according to a program pointer (program PC). In some embodiments, the instruction fetch unit 3021 may also include a predecode unit to predecode instructions within an instruction packet to determine the instruction type of each instruction. For example, the instruction type may be one of a general instruction and a memory access instruction, where the memory access instruction includes a store instruction and a load instruction, and the general instruction may be other than the memory access instruction, including a branch instruction, a data transfer instruction, and the like. The pre-decoding module performs different operations according to the instruction type.

The instruction decoding unit 3022 decodes the current instruction according to the instruction set packaged in the processor core, and obtains the opcode, the source register, the destination register, and the immediate of the current instruction by decoding. The instruction set encapsulated within the processor core is determined by the manufacturer of the processor, and in the compilation stage, the source code is compiled by the compiler into program instructions that are supported by the various instruction sets. However, if the compiled program instruction is not supported by the current instruction set, the instruction decoding unit 202 cannot understand the meaning of the program instruction expression, and the instruction decoding fails.

Instruction commit unit 3025 is used to write execution results (e.g., calculation results of various operations stored in registers) to a data cache inside the processor core or to a memory outside.

The instruction execution unit includes a special execution unit 3023 and a normal execution unit 3024, the special execution unit 3023 does not generate an execution result, but the special execution unit 3023 sends instruction information to the instruction commit unit 3025, and the normal execution unit 3024 normally executes a program instruction and sends an execution result to the instruction commit unit 3025.

On the basis of the above-described processor components, the processor core 302 further includes a debug unit 3026. Debug unit 3026 is coupled to instruction fetch unit 3021 and instruction commit unit 3025, respectively. The debug unit 3026 is configured to continuously receive a first debug request from the external debug module 1033, where the debug unit 3026 determines the first debug request, and if it is determined that the first debug request indicates that the debug mode is entered after the first program instruction is executed, generates a second debug request according to the first debug request, where the second debug request indicates that the debug mode is entered before the second program instruction, and the second program instruction is a next instruction of the first program instruction, and then may send both the first debug request and the second debug request to the instruction fetch unit 3021, but if it is determined that the first debug request indicates that the debug mode is entered before the first program instruction is executed, does not generate the second debug request according to the first debug request, but directly sends the first debug request to the instruction fetch unit 3021. In some embodiments, debug unit 3026 generates the second debug request by calling a hardware trigger module built into it.

The instruction fetch unit 3021 fetches a packet from a cache coupled to the instruction fetch unit 3021, and thus the instruction fetch unit 3021 sends a first program instruction and a second program instruction and a first debug request or a second debug request to the instruction decode unit 3022.

The instruction decoding unit 3022 decodes the program instructions, provides the decoded result of the first program instruction to the special execution unit 3024 if it is determined that the first debug request indicates entry into the debug mode before execution of the first program instruction is completed, provides the decoded result of the first program instruction to the normal execution unit 3023 if it is determined that the first debug request indicates entry into the debug mode after execution of the first program instruction is completed, or provides the decoded result of the second program instruction to the special execution unit 3024 if it is determined that the second debug request indicates entry into the debug mode before execution of the second program instruction is completed.

The special execution unit 3023 does not generate execution results, but the special execution unit 3023 sends instruction information to the instruction issue unit 3025, and the normal execution unit 3024 executes program instructions normally and sends execution results to the instruction issue unit 3025.

The instruction commit unit 3025 commits the execution result sent by the normal execution unit 3024, that is, commits the execution result of the result register of the instruction execution unit 503 to the memory, and then enters a debug mode or responds to a debug exception according to instruction information or the execution result.

It should be understood that when the debug unit 3026 receives a first debug request from the outside, the program instruction specified by the request may have been decoded, executed, or even completed execution in the instruction pipeline (i.e., committed to memory via the instruction commit unit 3025), and therefore, optionally, the debug unit 3026 sends the first debug request to the instruction commit unit 3025, and after the instruction commit unit 3025 receives the first debug request, it is determined that if the first debug request indicates that debug mode was entered before the first program instruction executed, but in fact, the first program instruction has been executed via the normal execution unit 3024 as found by the execution results returned from the normal execution unit 3024, then the execution result of the first program instruction may be cancelled or prevented from being committed (both cancelling and preventing commit are intended to not commit the execution results of the result register generated by the instruction execution unit 503 to memory, and may clear the result register). Before entering debug mode, the processor core may clear the instruction flow line so that the processor core may receive the debug instruction from debug module 1033 again and process it. Taking into account that in some cases (e.g. a delay), causing the normal execution unit 3024 to process the first program instruction that would have been processed by the special execution unit 3023, results in the execution result of the first program instruction being sent to the instruction issue unit, so cancelling the issue or preventing the issue by the instruction issue unit 3025 enables the processor core to return to a state in which the first program instruction is not executed.

Fig. 4 and 5 are flowcharts of a debugging function implemented based on the processor core shown in fig. 3 according to an embodiment of the present disclosure. The flowchart specifically includes the following steps.

In step S401, the debug unit 3026 sends a debug request to the instruction fetch unit 3021. The debug request may include the first debug request and the second debug request described above, and the debug request includes a debug opportunity (timing) and program instructions to respond to the debug request. If timing of the debug request is equal to 0 and the program instruction responding to the debug request is designated as a first program instruction, entering a debug mode before the execution of the first program instruction is completed; if timing of the debug request is equal to 1 and the program instruction responding to the debug request is the first program instruction, it indicates that debug mode is entered after the execution of the first program instruction is completed.

In step S402, the instruction fetch unit 3021 determines whether the instruction has received a debug request. If so, step S403 is performed, otherwise step S404 is performed.

In step S403, the instruction fetch unit 3021 sends the instruction and the debug request information to the instruction decode unit 3022.

In step S404, the instruction fetch unit 3021 sends the instruction to the instruction decode unit 3022.

In step S405, the instruction decoding unit 3022 determines whether the instruction has a debug request, and if so, performs step S406, otherwise performs step S411.

In step S406, the instruction decoding unit 3022 determines timing of the debug request, and if it is equal to 0, performs step S407, and if it is equal to 1, performs step S409.

In step S407, the instruction decode unit 3022 sends the decode result of the corresponding instruction to the special execution unit 3023.

In step S408, the special execution unit 3023 does not generate an execution result, and sends instruction information to the instruction issue unit 3025.

In step S409, the instruction decode unit 3022 sends the decode result of the corresponding instruction to the normal execution unit 3024.

In step S410, the normal execution unit 3024 generates an execution result, and sends the execution result to the instruction issue unit 3025.

In step S411, the instruction decode unit 3022 sends the decoded result to the normal execution unit 3024.

In step S412, the normal execution unit 3024 generates an execution result, and sends the execution result to the instruction issue unit 3025.

In step S413, the debug unit 3026 sends a debug request to the instruction commit unit 3025. The debug request may be a debug request with timing equal to 0 or equal to 1. Specifically, initially, the debug unit 3026 issues one copy of each of the instruction fetch unit 3021 and the instruction commit unit 3025 for any received debug request (timing is 0 or 1), and the debug unit 3026 newly constructs a debug request with timing equal to 0 for a debug request with timing equal to 1, and the newly constructed response program instruction with timing equal to 0 is the next instruction, and also issues a debug request with timing equal to 0 to the instruction fetch unit 3021.

In step S414, the instruction issue unit 3025 determines whether the instruction issue unit 3025 has a debug request, and if so, performs step S419, otherwise performs step S415.

In step S415, the instruction commit unit 3025 commits the execution result.

In step S416, the instruction fetch unit 3021 fetches a new instruction. Then, the execution continues to jump to step S402.

In step S417, the instruction issue unit 3025 determines whether the instruction has an execution result, and if so, performs step S418, otherwise performs step S423.

In step S418, the instruction issue unit 3025 cancels (discards) the execution result.

In step S419, the instruction issue unit 3025 determines Timing of the debug request, and if it is equal to 1, performs step S420, and if it is equal to 0, performs step S417.

In step S420, the instruction commit unit 3025 commits the execution result.

In step S421, the instruction commit unit 3025 sends information in response to the debug request with Timing of 1 to the debug unit 3026.

In step S422, the debug unit 3026 generates a pending debug request with Timing of 0 to the next instruction. Then, the execution continues to jump to step S402.

The Pending debug request (the second debug request referred to above, i.e., the Pending debug request) is a newly added request type. In the Pending debug request, the debug time is set to 0, the request type is set to 'Pending', the request is a request defined by the system and not performing any actual operation, and the function of the request is to enable the processor core to enter a debug mode or respond to a debug exception. And in order for the processor core to enter debug mode or respond to a debug exception before the next instruction executes, the request may also be prioritized over any results generated during the execution of the next instruction, even if those results (e.g., generating a non-debug exception, or responding to an interrupt, etc.) have priority over a debug request whose timing is the first value. Similarly, pending debug requests are also prioritized over other debug requests for the next instruction. The Pending debug request is supplied to the instruction commit unit 3025 via step S413.

In step S423, the instruction commit unit 3025 enters the debug mode or responds to a debug exception, and notifies the debug tool.

In some embodiments, the processor core needs to record the type of the debug request in response to the debug request entering the debug mode, and the processor needs to record exception information in response to the debug request triggering the debug exception.

The technical effect of the present embodiment is described by taking fig. 2 as an example and is not different from the prior art. In fig. 2, the program instruction responding to the debug request is an instruction "str [ i ] ═ a '", when the timing of the debug request is equal to 1, the processor core completes the execution of the instruction "str [ i ] ═ a'", and submits the execution result, and then the debug unit 3026 sends a debug request whose timing is 0 at the next instruction "for (i ═ 0; i < 9; i + +"). According to the above-mentioned flowchart, the processor core enters the debug mode when the instruction "str [ i ] ═ a '" completes execution and commits but the next instruction "for (i ═ 0; i < 9; i + +") is not executed, while the prior art also enters the debug mode when the instruction "str [ i ] ═ a'" completes execution and commits but the next instruction "for (i ═ 0; i < 9; i + +") is not executed.

The embodiments of the present disclosure are described in more detail below based on an example.

According to the debugging time timing of the debugging request, there are two types of debugging requests: (a) debugging requests with timing of 0; (b) debug request with timing of 1. There are also two ways to inform the debug request: I. and (ii) informing of the debug request in an instruction fetch stage and informing of the debug request in an instruction commit stage. Four processing scenarios of debug requests are thus constructed:

scene one: (a) timing is 1 debugging request, and I, the debugging request is informed in the instruction fetching stage. The following instruction sequences are illustrated as examples:

instruction A: add (add) instruction;

and instruction B: a sub (subtract) instruction.

Debug unit 3026 indicates that a debug request with timing of 1 is generated on the A instruction. The response process is as follows:

1. instruction fetch unit 3021 fetches an A instruction, and debug unit 3026 informs instruction fetch unit 3021 that a debug request at timing 1 should be responded to on instruction A.

2. Instruction fetch unit 3021 sends the a instruction to instruction decode unit 3022, and instruction decode unit 3022 still sends the instruction to normal execution unit 3024 (i.e., ALU, arithmetic operation).

3. After the normal execution unit 3024 completes the execution of the a instruction, the execution result is sent to the instruction issue unit 3025.

4. Instruction commit unit 3025 commits the execution result of instruction a and informs debug unit a that the instruction responded to the debug request with timing of 1. The debug unit will generate a pending debug request with timing 0 on instruction B next to instruction a.

5. Instruction fetch unit 3021 fetches a B instruction, and debug unit 3026 signals instruction fetch unit 3021 to respond to a (pending) debug request with timing 0 on instruction B.

6. Instruction fetch unit 3021 sends the B instruction to instruction decode unit 3022, and instruction decode unit 3022 sends the B instruction to a special instruction execution unit, instead of normal execution unit 3024.

7. The special instruction execution unit does not generate the execution (subtraction) result of the B instruction, but still sends B instruction information to the instruction issue unit 3025.

8. Instruction commit unit 3025 does not commit the execution result of the B instruction and informs debug unit 3026 that a debug request of timing 0 is responded to, and then enters debug mode or responds to a debug exception.

Scene two: (a) timing is 1 debug request, II, the debug request is informed in the instruction submission stage.

Similar to the steps 1-8, the difference lies in:

1. instruction fetch unit 3021 fetches an A instruction and debug unit does not tell instruction fetch unit 3021 that a debug request with timing of 1 should be responded to on instruction A.

2. Instruction fetch unit 3021 sends the a instruction to instruction decode unit 3022, and instruction decode unit 3022 still sends the instruction to normal execution unit 3024.

3. After the instruction execution unit 503 completes the execution of the a instruction, the execution result is sent to the instruction issue unit 3025.

4. When the instruction submitting unit 3025 submits the execution result of the a instruction, the debugging unit notifies the a instruction that the debugging request with timing 1 should be responded, the instruction submitting unit 3025 further makes a series of determinations to determine whether the a instruction responds to the debugging request, and after determining that the a instruction responds, notifies the debugging unit 3026 that the a instruction has responded to the debugging request, that is, the instruction submitting unit 3025 notifies the debugging unit 3026 that the a instruction responds to the debugging request with timing 1. The debug unit will generate a pending debug request with timing 0 on instruction B next to instruction a.

5. Instruction fetch unit 3021 fetches a B instruction, and debug unit tells instruction fetch unit 3021 to respond to a (pending) debug request with timing 0 on instruction B.

6. Instruction fetch unit 3021 sends the B instruction to instruction decode unit 3022, and instruction decode unit 3022 sends the B instruction to special instruction execution unit 503 instead of normal execution unit 3024.

7. The special instruction execution unit does not generate the execution (subtraction) result of the B instruction, but still sends B instruction information to the instruction issue unit 3025.

8. Instruction commit unit 3025 does not commit the execution result of the B instruction and informs debug unit 3026 that a debug request of timing 0 is responded, and then enters a debug mode or generates a debug exception.

Scene three: (b) debug requests with timing of 0 (such as pending debug requests and other types of debug requests), i. Similar to the steps 5-8. The following instruction sequences are examples: instruction A: add (add) instruction.

The debug unit indicates that a debug request with timing of 0 is generated on the A instruction. The response process is as follows:

1. instruction fetch unit 3021 fetches an A instruction and debug unit tells instruction fetch unit 3021 to respond to a debug request with timing of 0 on instruction A.

2. The instruction fetch unit 3021 sends an a instruction to the instruction decode unit 3022, and the instruction decode unit 3022 sends an a instruction to the special instruction execution unit 503 instead of the normal execution unit 3024.

3. The special instruction execution unit 503 does not generate the execution (addition) result of the a instruction, but still sends a instruction information to the instruction issue unit 3025.

4. Instruction commit unit 3025 does not commit the execution result of the a instruction and informs the debug unit to respond to the debug request with timing of 0 and then enters debug mode or generates a debug exception.

Scene four: (b) debug requests with timing of 0 (such as pending debug requests and other types of debug requests), ii.

1. Instruction fetch unit 3021 fetches an A instruction and debug unit does not tell instruction fetch unit 3021 to respond to a debug request with timing 0 on instruction A.

2. Instruction fetch unit 3021 sends the a instruction to instruction decode unit 3022, and instruction decode unit 3022 still sends the instruction to normal execution unit 3024.

3. After the instruction execution unit 503 completes the execution of the a instruction, the execution result is sent to the instruction issue unit 3025.

4. Instruction commit unit 3025, when committing the execution result of instruction a, the debug unit informs instruction a that it should respond to a debug request with timing of 1. Instruction commit unit 3025 cancels the execution result of instruction a and informs the debug unit that a debug request of timing 0 was responded to, and then enters debug mode or generates a debug exception.

To sum up, according to the processor core provided by the embodiment of the present disclosure, when the first debug request is characterized to enter the debug mode after the first program instruction, the second debug request is generated, and the second debug request is characterized to enter the debug mode before the second program instruction, so that the processor core enters the debug mode according to the second debug request instead of the first debug request, that is, the processor core always enters the debug mode according to the debug request which is characterized to enter the debug mode before a certain program instruction.

Specific application of processor provided by the embodiment of the disclosure

FIG. 6 illustrates a general computer architecture to which embodiments of the disclosure may be applied. As shown, computer system 600 may include one or more processors 12, and memory 14. The processor provided in the above embodiment may be used as the processor 12.

The memory 14 in the computer system 600 may be a main memory (referred to simply as main memory or memory). For storing instruction information and/or data information represented by data signals, such as data provided by the processor 12 (e.g., operation results), and for implementing data exchange between the processor 12 and an external storage device 16 (or referred to as an auxiliary memory or an external memory).

In some cases, processor 12 may need to access memory 14 to retrieve data in memory 14 or to make modifications to data in memory 14. To alleviate the speed gap between processor 12 and memory 14 due to the slow access speed of memory 14, computer system 600 further includes a cache memory 18 coupled to bus 11, cache memory 18 being used to cache some data in memory 14, such as program data or message data, that may be repeatedly called. The cache Memory 18 is implemented by a storage device such as a Static Random Access Memory (SRAM). The Cache memory 18 may have a multi-level structure, such as a three-level Cache structure having a first-level Cache (L1 Cache), a second-level Cache (L2 Cache), and a third-level Cache (L3 Cache), or may have a Cache structure with more than three levels or other types of Cache structures. In some embodiments, a portion of the cache memory 18 (e.g., a level one cache, or a level one cache and a level two cache) may be integrated within the processor 12 or in the same system on a chip as the processor 12.

In this regard, the processor 12 may include an instruction execution unit 121, a memory management unit 122, and so on. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory, where the write access request specifies write data and a corresponding physical address that need to be written into the memory; the memory management unit 122 is configured to translate the virtual addresses specified by the instructions into the physical addresses mapped by the virtual addresses, and the physical addresses specified by the write access request may be consistent with the physical addresses specified by the corresponding instructions.

The information exchange between the memory 14 and the cache 18 is typically organized in blocks. In some embodiments, the cache 18 and the memory 14 may be divided into data blocks by the same spatial size, and a data block may be the smallest unit of data exchange (including one or more data of a preset length) between the cache 18 and the memory 14. For the sake of brevity and clarity, each data block in the cache memory 18 will be referred to below simply as a cache block (which may be referred to as a cacheline or cache line), and different cache blocks have different cache block addresses; each data block in the memory 14 is referred to as a memory block, and different memory blocks have different memory block addresses. The cache block address comprises, for example, a physical address tag for locating the data block.

Due to space and resource constraints, the cache memory 18 cannot cache the entire contents of the memory 14, i.e., the storage capacity of the cache memory 18 is generally smaller than that of the memory 14, and the cache block addresses provided by the cache memory 18 cannot correspond to the entire memory block addresses provided by the memory 14. When the processor 12 needs to access the memory, firstly, the cache memory 18 is accessed through the bus 11 to judge whether the content to be accessed is stored in the cache memory 18, if so, the cache memory 18 hits, and at the moment, the processor 12 directly calls the content to be accessed from the cache memory 18; if the content that the processor 12 needs to access is not in the cache memory 18, the processor 12 needs to access the memory 14 via the bus 11 to look up the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, the efficiency of the processor 12 can be significantly improved when the cache memory 18 hits, thereby also improving the performance and efficiency of the overall computer system 600.

In addition, computer system 600 may also include input/output devices such as storage device 16, display device 13, audio device 19, mouse/keyboard 15, and the like. The storage device 16 is a device for information access such as a hard disk, an optical disk, and a flash memory coupled to the bus 11 via corresponding interfaces. The display device 13 is coupled to the bus 11, for example via a corresponding graphics card, for displaying in accordance with display signals provided by the bus 11.

The computer system 600 also typically includes a communication device 17 and thus may communicate with a network or other devices in a variety of ways. The communication device 17 may comprise, for example, one or more communication modules, by way of example, the communication device 17 may comprise a wireless communication module adapted for a particular wireless communication protocol. For example, the communication device 17 may include a WLAN module for implementing Wi-FiTM communication in compliance with 602.11 standards set by the Institute of Electrical and Electronics Engineers (IEEE); the communication device 17 may also include a WWAN module for implementing wireless wide area communication conforming to a cellular or other wireless wide area protocol; the communication device 17 may also include a communication module using other protocols, such as a bluetooth module, or other custom type communication modules; the communication device 17 may also be a port for serial transmission of data.

Of course, the structure of different computer systems may vary depending on the motherboard, operating system, and instruction set architecture. For example, many computer systems today have an input/output control hub coupled between the bus 11 and various input/output devices, and the input/output control hub may be integrated within the processor 12 or separate from the processor 12.

Fig. 7 is a block diagram of an embedded system to which an embodiment of the present disclosure is applied. The processor provided by the above-described embodiment may be used as the processor 701.

Although the embedded system has a high similarity to a computer system in terms of hardware structure, the application characteristics of the embedded system cause the embedded system to be greatly different from a general computer system in terms of the composition and implementation form of hardware.

First, in order to meet the requirements of the embedded system 700 on speed, volume and power consumption, data that needs to be stored for a long time, such as an operating system, application software, and special data, is usually not used in a storage medium with a large capacity and a low speed, such as a magnetic disk, but a random access Memory 702 or a Flash Memory (Flash Memory)703 is mostly used.

In addition, in the embedded system 700, an a/D (analog/digital conversion) interface 705 and a serial interface 706 are required for the need of measurement and control, which is rarely used in a general-purpose computer. The a/D interface 705 mainly performs conversion of an analog signal to a digital signal and conversion of a digital signal to an analog signal, which are required in the test. Embedded system 700 often requires testing when applied to industrial production. Because the single chip generates digital signals, which need to be converted into analog signals for testing, unlike general purpose computers, an a/D (analog/digital conversion) interface 705 is required to complete the relevant conversion. In addition, the industry often requires multiple embedded systems to be connected in series to perform related functions, and therefore a serial interface 706 for connecting multiple embedded systems in series is required, which is not required in general purpose computers.

In addition, the embedded system 700 is a basic processing unit, and a plurality of embedded systems 700 are often required to be networked in industrial design, so that a network interface 707 for networking the embedded system 700 is required. This is also mostly not required in general purpose computers. In addition, some embedded systems 700 employ an external bus 704, depending on the application and size. With the rapid expansion of the application field of the embedded system 700, the embedded system 700 tends to be personalized more and more, and the types of buses adopted according to the characteristics of the embedded system 700 are more and more. In addition, in order to test the internal circuits of the embedded processor 701, the boundary scan test technology is commonly used for processor chips. To accommodate this testing, a debug interface 708 is employed.

With the rapid development of Very Large Scale integrated circuits (Very Large Scale Integration) and semiconductor processes, part or all of the embedded system can be implemented on a silicon chip, i.e., an embedded system on a chip (SoC).

Furthermore, the present application also discloses an electronic device comprising means for implementing the processor core or processor of the embodiments described herein.

Commercial value of the disclosed embodiments

The embodiment of the disclosure can reduce the number of logic judgment elements in a processor (or a processor core), thereby reducing the cost of the processor. Similar processors are available for end devices such as notebooks and cell phones, as well as certain consumer electronics, and thus embodiments of the present disclosure have commercial and economic value.

It should be understood that the above-described are only preferred embodiments of the present invention, and are not intended to limit the present invention, and that many variations of the embodiments described herein will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

It should be understood that the embodiments in this specification are described in a progressive manner, and that the same or similar parts in the various embodiments may be referred to one another, with each embodiment being described with emphasis instead of the other embodiments. In particular, as for the method embodiments, since they are substantially similar to the methods described in the apparatus and system embodiments, the description is simple, and the relevant points can be referred to the partial description of the other embodiments.

It should be understood that the above description describes particular embodiments of the present specification. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

It should be understood that an element described herein in the singular or shown in the figures only represents that the element is limited in number to one. Furthermore, modules or elements described or illustrated herein as separate may be combined into a single module or element, and modules or elements described or illustrated herein as single may be split into multiple modules or elements.

It is also to be understood that the terms and expressions employed herein are used as terms of description and not of limitation, and that the embodiment or embodiments of the specification are not limited to those terms and expressions. The use of such terms and expressions is not intended to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications may be made within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims should be looked to in order to cover all such equivalents.