阅读说明：本技术 晶体管装置及形成晶体管装置的方法 (Transistor device and method of forming a transistor device ) 是由 B·W·文 J·M·具 于 2021-05-14 设计创作，主要内容包括：本申请涉及晶体管装置及形成晶体管装置的方法。可提供一种LDMOS晶体管装置,包括其中设有导电区的衬底,设于该衬底内的第一隔离结构,设于该导电区内的源区与漏区,设于该源区与该漏区之间的第二隔离(局部隔离)结构,以及至少部分设于该第二隔离结构内的栅极结构。该第一隔离结构可沿该导电区的边界的至少一部分延伸,且该第二隔离结构的深度可小于该第一隔离结构的深度。在使用期间,可沿设于该第二隔离(局部隔离)结构内的该栅极结构的侧面的至少一部分形成电子流的沟道。(The present application relates to transistor devices and methods of forming transistor devices. An LDMOS transistor device may be provided comprising a substrate having a conductive region disposed therein, a first isolation structure disposed within the substrate, a source region and a drain region disposed within the conductive region, a second isolation (local isolation) structure disposed between the source region and the drain region, and a gate structure at least partially disposed within the second isolation structure. The first isolation structure may extend along at least a portion of a boundary of the conductive region, and the second isolation structure may have a depth less than a depth of the first isolation structure. During use, a channel for electron flow may be formed along at least a portion of a side of the gate structure disposed within the second isolation (local isolation) structure.)

1. A transistor device, comprising:

a substrate having a conductive region disposed therein;

a first isolation structure disposed within the substrate, wherein the first isolation structure extends along at least a portion of a boundary of the conductive region;

a source region and a drain region disposed in the conductive region;

the second isolation structure is arranged between the source region and the drain region, wherein the depth of the second isolation structure is smaller than that of the first isolation structure; and

and the grid structure is at least partially arranged in the second isolation structure.

2. The transistor device of claim 1, wherein the transistor device is an LDMOS transistor device and the second isolation structure is a local isolation structure.

3. The transistor device of claim 1, further comprising a body region disposed between the first isolation structure and the gate structure, wherein the source region is disposed within the body region.

4. The transistor device of claim 3, wherein the gate structure abuts the body region along a side of the gate structure.

5. The transistor device of claim 3, wherein a depth of the body region is between a depth of the second isolation structure and a depth of the gate structure disposed within the second isolation structure.

6. The transistor of claim 3, further comprising a body contact disposed within the body region, wherein the body contact abuts the source region.

7. The transistor device of claim 1, further comprising a drift region disposed within the conductive region, wherein the drain region and the second isolation region are disposed within the drift region.

8. The transistor device of claim 1, wherein the first isolation structure is partially disposed within the conductive region.

9. The transistor device of claim 1, wherein a depth of the second isolation structure is less than or equal to 120 nm.

10. The transistor device of claim 1, wherein a depth of the second isolation structure ranges from one third of a depth of the first isolation structure to two thirds of a depth of the first isolation structure.

11. The transistor device of claim 1, wherein the second isolation structure is an ultra shallow trench isolation structure.

12. The transistor device of claim 1, wherein a side of the gate structure facing the source region is aligned with a side of the second isolation structure.

13. The transistor device of claim 1, wherein a portion of the second isolation structure extends from the gate structure toward the drain region.

14. The transistor device of claim 1, wherein a first portion of the gate structure is disposed within the second isolation structure and a second portion of the gate structure is disposed above the substrate.

15. The transistor device of claim 14, further comprising a silicide block layer extending from over the second portion of the gate structure toward a top surface of the substrate.

16. The transistor device of claim 1, wherein the gate structure is disposed entirely within the second isolation structure.

17. A method of forming a transistor device, the method comprising:

providing a substrate;

forming a conductive region in the substrate;

forming a first isolation structure within the substrate, wherein the first isolation structure extends along at least a portion of a boundary of the conductive region;

forming a second isolation structure in the conductive region, wherein the depth of the second isolation structure is less than the depth of the first isolation structure;

forming a gate structure at least partially within the second isolation structure; and

and forming a source region and a drain region in the conductive region, so that the second isolation structure is arranged between the source region and the drain region.

18. The method of claim 17, further comprising forming a body region between said first isolation structure and said gate structure.

19. The method of claim 18, wherein said body region is formed after forming said gate structure.

20. The method of claim 18, wherein forming the body region comprises depositing a dopant in the substrate at an angle substantially perpendicular to a top surface of the substrate.

Technical Field

The present application relates generally to transistor devices, and methods of forming the same.

Background

Transistor devices are widely used in many applications to amplify or switch electrical signals. One type of transistor device is a laterally-diffused metal-oxide semiconductor (LDMOS) device, which is commonly used in Radio Frequency (RF) power amplifiers for mobile networks. LDMOS devices typically include a source, a drain, and a gate therebetween, wherein the source and drain are disposed in respective wells (wells) having different conductivity types. When a sufficiently large gate voltage is applied to the gate of the LDMOS device, a channel may be formed in the well where the source is disposed, allowing current flow between the source and the drain.

Conventional LDMOS devices often suffer from high on-resistance, low breakdown voltage, and high switching loss. To date, several techniques have been developed to address these issues. For example, an electrically insulating structure may be included within the well in which the drain is disposed to enhance the breakdown voltage of the device. However, the breakdown voltage may not be boosted enough and the on-resistance and switching losses of such LDMOS devices are still high. In addition, the fabrication of conventional LDMOS devices often involves several etching processes. These processes are time consuming and often introduce errors that may affect the performance of the resulting LDMOS device.

Disclosure of Invention

According to various non-limiting embodiments, a transistor device may be provided. The transistor device may include: a substrate having a conductive region disposed therein; a first isolation structure disposed within the substrate, wherein the first isolation structure may extend along at least a portion of a boundary of the conductive region; a source region and a drain region disposed in the conductive region; a second isolation structure disposed between the source region and the drain region, wherein a depth of the second isolation structure may be less than a depth of the first isolation structure; and a gate structure at least partially disposed within the second isolation structure.

According to various non-limiting embodiments, a method of forming a transistor device may be provided. The method can comprise the following steps: providing a substrate; forming a conductive region in the substrate; forming a first isolation structure within the substrate, wherein the first isolation structure may extend along at least a portion of a boundary of the conductive region; forming a second isolation structure in the conductive region, wherein the second isolation structure may have a depth less than that of the first isolation structure; forming a gate structure at least partially within the second isolation structure; and forming a source region and a drain region in the conductive region such that the second isolation structure can be disposed between the source region and the drain region.

Drawings

In the drawings, like reference numerals generally refer to the same parts throughout the different views. Additionally, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. Non-limiting embodiments of the present invention will now be described, by way of example only, with reference to the following drawings, in which:

FIGS. 1A and 1B show simplified top and simplified cross-sectional views, respectively, of a transistor device according to various non-limiting embodiments;

FIGS. 2A-2L show simplified cross-sectional views of a method of forming the transistor device of FIGS. 1A and 1B, in accordance with various non-limiting embodiments;

FIG. 3 shows a simplified cross-sectional view of the transistor device of FIGS. 1A and 1B during use of the transistor device;

FIG. 4 is a graph illustrating drain current versus gate voltage for the transistor devices of FIGS. 1A and 1B, as well as for another transistor device;

FIG. 5 shows a simplified cross-sectional view of a transistor device in accordance with an alternative non-limiting embodiment;

FIG. 6 shows a simplified cross-sectional view of a transistor device in accordance with an alternative non-limiting embodiment; and

fig. 7 shows a Transmission Electron Microscope (TEM) cross-sectional image of an example isolation structure that may be used in the transistor devices of fig. 1A and 1B, 5 or 6.

Detailed Description

Embodiments are generally related to semiconductor devices. In particular, some embodiments relate to transistor devices. For example, some embodiments may relate to LDMOS transistor devices. For example, the transistor device may be included in a power amplifier and a switch.

Embodiments of the invention and their specific features, advantages and details are explained more fully below with reference to the non-limiting examples that are illustrated in the accompanying drawings. Descriptions of well-known materials, manufacturing tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the present invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the present invention, are given by way of illustration only, not limitation. Various alternatives, modifications, additions and/or arrangements will become apparent to those skilled in the art from this disclosure, which are within the spirit and/or scope of the basic inventive concept.

Approximating language, as used herein in the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as "about" or "approximately", are not to be limited to the precise value specified. In some cases, the approximating language may correspond to the precision of an instrument for measuring the value. Additionally, a direction modified by a term or terms, such as "substantially", refers to a direction that will apply within the ordinary tolerances of the semiconductor industry. For example, "substantially parallel" refers to extending generally in the same direction within the ordinary tolerances of the semiconductor industry, and "substantially perpendicular" refers to an angle of ninety degrees plus or minus the ordinary tolerances of the semiconductor industry.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" (and any form of comprising, such as "comprises" and "comprising"), "having" (and any form of having, such as "has" and "having"), "including" (and any form of including, such as "includes" and "including"), and "containing" (and any form of including, such as "contains" and "containing") are open-ended linking verbs. Thus, a method or apparatus that "comprises," "has," "includes" or "contains" one or more steps or elements possesses those one or more steps or elements, but is not limited to only those one or more steps or elements. Likewise, a method step or device element that "comprises," "has," "includes" or "contains" one or more features possesses those one or more features, but is not limited to only those one or more features. Moreover, a device or structure configured in a particular manner is configured in at least that manner, but may also be configured in ways not listed.

The term "connected," when used in reference to two physical elements, as used herein, refers to a direct connection between the two physical elements. The term "coupled," however, may refer to a connection either directly or through one or more intervening elements.

The terms "may" and "may" as used herein mean that it may occur within a set of circumstances; possess a specified attribute, characteristic or function; and/or qualify another verb (by expressing one or more capabilities, functions, or possibilities associated with the qualified verb). Thus, use of "may" and "may" means that the modified term is clearly suited, capable, or suitable for the indicated performance, function, or use, while taking into account that in some cases the modified term may not be suited, capable, or suitable for use at times. For example, in some cases an event or property may be expected, while in other cases the event or property may not occur, and so such distinction is made by the terms "may" and "may".

Fig. 1A shows a simplified top view of a transistor device 100 in accordance with various non-limiting embodiments. Fig. 1B shows a simplified cross-sectional view of the transistor device 100 along line a-a' of fig. 1A. The transistor device 100 may be an LDMOS transistor device.

The transistor device 100 may include a substrate 102. The substrate 102 may be a semiconductor substrate. For example, the substrate 102 may include a semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or combinations thereof.

The substrate 102 may include a conductive region 104 disposed therein. Conductive region 104 may be a hvw region. Body regions 106 and drift regions 108 may also be provided in the substrate 102, and in particular in the conductive region 104. As shown in fig. 1B, drift region 108 may abut body region 106. The drift region 108 and the body region 106 may be disposed along the top surface 102t of the substrate 102. Furthermore, the depth D of the body region 106₁₀₆May be less than the depth D of the drift region 108₁₀₈. Depth D of drift region 108₁₀₈May be configured based on the voltage (Vdd) to be supplied to the transistor device 100.

Transistor device 100 may also include a source region 110 and a drain region 112. Source region 110 may be disposed within conductive region 104 (particularly, body region 106), and drain region 112 may be disposed within conductive region 104 (particularly, drift region 108). Furthermore, the transistor device 100 may comprise a body contact (body contact)114 disposed within the body region 106, wherein the body contact 114 may abut the source region 110. Source regions 110, drain regions 112, and body contacts 114 may be disposed along a top surface 102t of substrate 102.

The transistor device 100 may be a positive (positive) channel metal oxide semiconductor (PMOS) device. In particular, the substrate 102, the drift region 108, the source region 110, and the drain region 112 may have the first conductivity type, or in other words, may include dopants having the first conductivity type. The conductive regions 104, body regions 106, and body contacts 114 may have a second conductivity type different from the first conductivity type, or in other words, may include dopants having the second conductivity type. For example, the substrate 102, drift region 108, source region 110, and drain region 112 may have p-type conductivity, while the conductive region 104, body region 106, and body contact 114 may have n-type conductivity. The p-type dopant may include boron (B), indium (In), or a combination thereof; and the n-type dopant may include phosphorus (p), arsenic (As), antimony (Sb), or a combination thereof.

The transistor device 100 may also include a first isolation structure 116 disposed within the substrate 102. The first isolation structure 116 may extend along at least a portion of the boundary of the conductive region 104. As used herein, "border" refers to a surface of the conductive region 104 facing the first isolation structure 116. This "boundary" is indicated by a dotted line in fig. 1A. For example, as shown in fig. 1A, the first isolation structure 116 may surround the conductive region 104. In other words, the first isolation structure 116 may extend along the entire boundary of the conductive region 104. However, the first isolation structure 116 may alternatively extend along only a portion of the boundary of the conductive region 104. For example, the first isolation structure 116 may be disposed along at least 50% of the boundary of the conductive region 104; alternatively, the first isolation structure 116 may be disposed along at least 70% of the boundary of the conductive region 104, or may even be disposed along at least 90% of the boundary of the conductive region 104.

As shown more clearly in fig. 1B, the first isolation structure 116 may be partially disposed within the conductive region 104. However, the first isolation structure 116 may alternatively be provided entirely outside of the conductive region 104, but abutting a boundary of the conductive region 104, e.g., contacting a surface of the conductive region 104 facing the first isolation structure 116. Additionally, as shown in fig. 1B, the first isolation structure 116 may adjoin the body region 106 and the drift region 108. Although in fig. 1B the transistor device 100 is shown with a portion of the body region 106 between the body contact 114 and the first isolation structure 116, and with a portion of the drift region 108 between the drain region 112 and the first isolation structure 116, the first isolation structure 116 may alternatively abut one or both of the drain region 112 and the body contact 114. The first isolation structure 116 may be a Shallow Trench Isolation (STI) structure and may include an isolation material. The isolation material may be a dielectric material or a gap-fill oxide such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Depth D of first isolation structure 116₁₁₆May be approximately equal to the depth of the isolation structures of a typical isolation device and may be equal to or greater than 300 nanometers when the transistor device 100 is fabricated using 180 nanometer (nm) to 130 nanometer technology nodes. For example, the depth D of the first isolation structure 116₁₁₆May be about 320 nanometers. However, if other technology nodes are used to fabricate the transistor device 100, the depth D of the first isolation structure 116₁₁₆May be different.

The transistor device 100 may also include a second isolation structure 120 disposed within the substrate 102. The second isolation structure 120 may be completely disposed within the conductive region 104, and particularly within the drift region 108. In other words, the second isolation structure 120 may be a local isolation structure. As shown in fig. 1B, a second isolation structure 120 may be disposed between the source region 110 and the drain region 112. The second isolation structure 120 may be laterally spaced from the drain region 112, or in other words, a portion of the drift region 108 may be provided at the second isolation structure 120 and the drain region 112Between drain regions 112. In particular, the second isolation structure 120 may be an ultra-shallow trench isolation (USTI) structure and may similarly include an isolation material such as a dielectric material or a gap-fill oxide (such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof). Additionally, the top surface 120t of the second isolation structure 120 may be substantially laterally aligned with the top surface 116t of the first isolation structure 116 and the top surface 102t of the substrate 102. Depth D of the second isolation structure 120₁₂₀Less than the depth D of the first isolation structure 116₁₁₆. For example, the depth D of the second isolation structure 120₁₂₀May range from a depth D of the first isolation structure 116₁₁₆To a depth D of the first isolation structure 116₁₁₆Two thirds. In particular, when the transistor device 100 is fabricated using a 180 nm to 130 nm technology node, the depth D of the second isolation structure 120₁₂₀May be equal to or less than 120 nanometers. For example, the depth D of the second isolation structure 120₁₂₀May be about 120 nanometers. However, if other technology nodes are used to fabricate the transistor device 100, the depth D of the second isolation structure 120₁₂₀May be different.

The transistor device 100 may further include a gate structure 122 at least partially disposed within the second isolation structure 120. The gate structure 122 may be a vertical gate structure. In particular, as shown in FIG. 1B, a first portion 122 of a gate structure 122₁May be disposed in the second isolation structure 120 and the second portion 122 of the gate structure 122₂May be provided over the substrate 102. In FIG. 1B, a second portion 122 of the gate structure 122 is shown₂Having a first portion 122 located at the gate structure 122₁An upper trench 1222R, but in an alternative non-limiting embodiment, this trench 1222R may not be present.

Referring to fig. 1B, a side 122a of the gate structure 122 facing the source region 110 may be vertically aligned with a side 120a of the second isolation structure 120, and a portion 120 of the second isolation structure 120₁May extend from gate structure 122 toward drain region 112. As shown in FIG. 1B, a portion 120 of the second isolation structure 120₁May extend beyond the gate structure 122. The body region 106 may be disposed at the first isolation structure 116 and the gate junctionBetween the structures 122. The gate structure 122 may adjoin the body region 106 along a side 122a of the gate structure 122, and the second isolation structure 120 may adjoin the body region 106 along a side 120a of the second isolation structure 120. As shown in fig. 1B, source regions 110 may be disposed within body regions 106 and may be spaced apart from gate structures 122. In other words, a portion of body region 106 may be disposed between source region 110 and gate structure 122. As will be described in detail below with reference to fig. 3, a vertical channel region may be formed in the body region 106 along at least a portion of the side 122a of the gate structure 122. In addition, the depth D of the body region 106₁₀₆May be at a depth D of the second isolation structure 120₁₂₀And a depth D of the gate structure 122 disposed in the second isolation structure 120₁₂₂₁(in other words, the first portion 122 of the gate structure 122₁Depth D of₁₂₂₁) In the meantime. In particular, depth D₁₀₆May be less than depth D₁₂₀But greater than depth D₁₂₂₁。

Referring to fig. 1B, the gate structure 122 may include a gate oxide layer 124 and a gate element 126. The gate oxide layer 124 may extend along the top surface 102t of the substrate 102 over the body region 106, along the body region 106 and the second isolation structure 120, and further along the top surface 102t of the substrate 102 over the second isolation structure 120. A gate element 126 may be disposed over the gate oxide layer 124. Gate oxide layer 124 may include a gate oxide material such as, but not limited to, silicon dioxide; however, the gate element 126 may comprise a conductive material such as, but not limited to, polysilicon or a metal (e.g., titanium nitride, tantalum nitride, tungsten, alloys thereof, or combinations thereof).

The transistor device 100 may also include spacers 127a, 127b, 127c, 127d disposed along the sides of the gate element 126. The spacers 127a, 127b, 127c, 127d may comprise a dielectric material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. For clarity of illustration, the spacers 127a, 127b, 127c, 127d are not shown in FIG. 1A.

The transistor device 100 may also include a second portion 122 of the slave gate structure 122₂A silicide block layer 128 extending over the top surface 102t of the substrate 102. As shown in fig. 1B, the silicide block layer 128 may also extend along the gate structure 122 and the drainThe top surface 102t of the substrate 102 between the regions 112 extends. Additionally, the silicide block layer 128 may overlap the drain region 112. The silicide block layer 128 may be a Silicide Alignment Block (SAB) oxide layer and may include a blocking material such as, but not limited to, silicon oxide, silicon nitride, or a combination thereof.

As shown in fig. 1B, the transistor device 100 may also include an insulating layer 130 disposed over the substrate 102. Second portion 122 of gate structure 122₂And a silicide block layer 128 may be disposed within the insulating layer 130. The insulating layer 130 may be an inter-layer dielectric (ILD) layer and may include an insulating material such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, or a combination thereof.

As shown in fig. 1A, the transistor device 100 may further include a plurality of first contacts 150 disposed over and in contact with the body region 114 and the source region 110, a plurality of second contacts 152 disposed over and in contact with the gate structure 122, a plurality of third contacts 154 disposed over and in contact with the drain region 112, and a plurality of fourth contacts 156 (which may be ground region contacts) disposed over and in contact with the substrate 102. The first, second, third, and fourth contacts 150, 152, 154, 156 may be conductive contacts comprising a conductive material, such as, but not limited to, aluminum, copper, tungsten, alloys thereof, or combinations thereof.

Fig. 2A-2L show simplified cross-sectional views of a method of forming a transistor device 100 according to various non-limiting embodiments. For clarity of illustration, certain reference numerals have been omitted from fig. 2A to 2L.

Referring to fig. 2A and 2B, the method may include providing a substrate 102 and forming a first isolation structure 116 and a second isolation structure 120 within the substrate 102. To form the first isolation structure 116, the substrate 102 may be etched to form an opening and the opening filled with an isolation material. Subsequently, the second isolation structure 120 may be similarly formed by etching the substrate 102 to form an opening and filling the opening with an isolation material. Alternatively, the openings of both the first and second isolation structures 116, 120 may be filled with isolation material simultaneously. Additionally, after filling the openings with the isolation material, a smoothing process (e.g., a Chemical Mechanical Polishing (CMP) process) may be performed to remove the isolation material outside the substrate 102 so that the top surfaces 116t, 120t of the isolation structures 116, 120 may be aligned with each other and with the top surface 102t of the substrate 102.

Referring to fig. 2C, the method may further include forming a conductive region 104 in the substrate 102 and forming a drift region 108 in the conductive region 104. The conductive region 104 and the drift region 108 may be formed by depositing dopants in respective regions of the substrate 102.

Referring to fig. 2D-2H, the method may further include forming a gate structure 122 at least partially within the second isolation structure 120. As shown in fig. 2D, a mask 202 having an opening 202a may be formed over the substrate 102. As shown in fig. 2E, the substrate 102 may be etched through the opening 202a of the mask 202 to form a trench 204 extending into the second isolation structure 120. As shown in fig. 2F, a layer of gate oxide material 206 may be formed over the substrate 102, a portion of which is formed within the trench 204. The gate oxide material layer 206 may be a thermal oxide formed by oxidizing the surface of the substrate 102. As shown in fig. 2G, a layer of conductive material 208 may then be formed over the gate oxide material 206, a portion of which is similarly formed within the trench 204. As shown in fig. 2H, a portion of gate oxide material 206 and a portion of conductive material 208 may be removed (e.g., by a single etch process using another mask) to form gate structure 122. In particular, the remaining gate oxide material 206 may form the gate oxide layer 124, and the remaining conductive material 208 may form the gate element 126.

Referring to fig. 2I, the method may further include forming a body region 106 within the conductive region 104. To form body region 106, another mask 210 having an opening 210a may be formed over substrate 102 and over gate structure 122. Next, dopants may be deposited in the substrate 102 through the openings 210a of the other mask 210. The dopant may be deposited into the substrate 102 at an angle substantially perpendicular to the top surface 102t of the substrate 102, as indicated by arrow 250.

Referring to fig. 2J, the method may further include forming spacers 127a, 127b, 127c, 127d along the sides of the gate device 126. The spacers 127a, 127b, 127c, 127d may be formed by depositing a dielectric material over the substrate 102 and the gate elements 126 and etching the dielectric material.

Referring to fig. 2K, the method may further include forming a source region 110, a drain region 112, and a body contact 114. The source region 110, drain region 112, and body contact 114 may be formed by implanting dopants into the respective regions 106, 108 using, for example, ion implantation. Alternatively, the source region 110, the drain region 112, and the body contact 114 may be formed by forming masks over the substrate 102 and doping the corresponding regions of the substrate 102 through openings of the masks.

Referring to fig. 2L, the method may further include forming a silicide block layer 128. To form the silicide block layer 128, a block material may be deposited over the gate structure 122 and the substrate 102, and the block material may be etched. The method may further include forming an insulating layer 130 by depositing an insulating material over the substrate 102.

The above-described order for the method is intended to be illustrative only, and the method is not limited to the order specifically described above unless otherwise specifically indicated.

Fig. 3 shows the transistor device 100 during use, the substrate 102, the drift region 108, the source region 110 and the drain region 112 having p-type conductivity, while the conductive region 104, the body region 106 and the body contact 114 have n-type conductivity. Also, for clarity of illustration, certain reference numerals have been omitted from FIG. 3.

As shown in FIG. 3, a gate Voltage (VG) may be applied to the gate structure 122 sufficiently large to form a vertical channel region C within a portion of the body region 106 beneath the gate structure 122 and along the sides 122a of the gate structure 122 when the transistor device 100 is in use₁₀₆. As shown in fig. 3, the vertical channel region C₁₀₆Length L of_C106May be approximately equal to the first portion 122 of the gate structure 122₁Depth D of₁₂₂₁. By further applying a voltage difference (drain Voltage (VD) — source Voltage (VS)) between the source region 110 and the drain region 112, electrons may flow from the source region 110 to the drain region 112 (as indicated by arrow 302). As shown in FIG. 3, the electrons may flow through the vertical channel region C₁₀₆And flows through the drift region 108 located below the second isolation structure 120. Can utilizeThe source voltage VS, the gate voltage VG, and the drain voltage VD are applied by first, second, and third contacts 150, 152, 154 disposed over the source region 110, the gate structure 122, and the drain region 112, respectively. Since the first contact 150 may be disposed over both the body contact 114 and the source region 110, the body contact 114 and the source region 110 may be connected to the same voltage VS. It should be appreciated that if the first conductivity type and the second conductivity type are n-type and p-type, respectively, the flow of electrons may be in opposite directions, particularly from drain region 112 to source region 110.

The transistor device 100 may have a higher Breakdown Voltage (BV), a lower on-resistance (Ron), and improved switching performance, such as lower switching losses, as compared to prior art transistor devices. In other words, the transistor device 100 may have improved performance parameters, such as an improved figure-of-merit (FOM ═ Ron × BV), an improved Baliga figure-of-merit (BFOM ═ BV)²/Ron) and modified Ron × Qgg parameters, where Qgg represents the gate charge of the transistor device 100.

For example, by using a lens having a smaller depth D₁₂₀The doped region of the drift region 108 may be larger and may reduce the electric field within the drift region 108. Accordingly, the second isolation structure 120 may help to reduce the on-resistance of the device 100. Fig. 4 shows graphs (plot)402, 404, which illustrate drain current-gate voltage (ID-VG) relationships, respectively, for the transistor device 100 and a transistor device similar to the transistor device 100 but having the second isolation structure 120 replaced by an isolation structure similar to the first isolation structure 116. The graphs 402, 404 were obtained with the drain Voltage (VD) set to 0.05V. As shown in fig. 4, with the second isolation structure 120 in the drift region 108 where the drain region 112 may be disposed, the on-resistance of the transistor device 100 may be reduced and the linear drain current ID may be improved_Lin。

Moreover, partially extending the gate structure 122 into the second isolation structure 120 may allow for the formation of a vertical (rather than a horizontal) channel region C when a sufficiently large gate voltage is applied to the gate structure 122₁₀₆. This may help to reduce the channel region C₁₀₆Is longAnd accordingly, the on-resistance of the transistor device 100 may be reduced. Additionally, the silicide block layer 128 may help reduce over-voltage stress in the transistor device 100 under high current conditions. In addition, the body region 106 may help to reduce the on-resistance of the device 100. In addition, due to the portion 120 of the second isolation structure 120₁Extending from gate structure 122 toward drain region 112, a thicker gate-to-drain oxide layer may be provided in transistor device 100 as compared to prior art devices. This may help to reduce the gate to drain capacitance (Cgd) of the transistor device 100.

The fabrication of the transistor device 100 may also include fewer etching processes. For example, the formation of the body region 106 of the transistor device 100 may be a self-controlled/self-aligned process (thus, the body region 106 may be referred to as a self-aligned body implant). In particular, as described above with reference to fig. 2A-2L, body region 106 may be formed after gate structure 122 is formed. Since the gate structure 122 may extend partially into the second isolation structure 120, the deposition of dopants in the substrate 102 may be guided by the gate structure 122 to achieve an overlap between the body region 106 and the gate structure 122 along the side 122 a. Thus, after depositing the gate oxide material 206 and the conductive material 208, a single etch of these materials 206, 208 (rather than two separate etch processes) may be sufficient to form the gate structure 122 and expose a portion of the substrate 102 to form the body region 106.

Fig. 5 shows a transistor device 500 in accordance with an alternative non-limiting embodiment. The transistor device 500 is similar to the transistor device 100 and, therefore, common features are denoted with the same reference numerals and need not be discussed.

In contrast to the transistor device 100, in the transistor device 500, the transistor device 500 may comprise a further conductive region 502 provided within the substrate 102, in particular within the conductive region 104. Another conductive region 502 may be a hvw region. The body region 106 and the drift region 108 may be disposed within another conductive region 502. In other words, the source region 110, the drain region 112 and the body contact 114 may be provided within the further conductive region 502. The transistor device 500 may be a negative (negative) channel metal oxide semiconductor (NMOS) device. In particular, the substrate 102, the further conductive region 502, the body region 106 and the body contact 114 may have a first conductivity type; and the conductive region 104, the drift region 108, the source region 110, and the drain region 112 may have a second conductivity type. For example, the substrate 102, the further conductive region 502, the body region 106 and the body contact 114 may have p-type conductivity, while the conductive region 104, the drift region 108, the source region 110 and the drain region 112 may have n-type conductivity.

Fig. 6 shows a transistor device 600 in accordance with an alternative non-limiting embodiment. The transistor device 600 is similar to the transistor device 100 and, therefore, common features are denoted with the same reference numerals and need not be discussed.

In the transistor device 600, the gate structure 122 may be completely disposed within the second isolation structure 120, as compared to the transistor device 100. The top surface 122t of the gate structure 122 may be substantially aligned with the top surface 102t of the substrate 102 and the depth D of the gate structure 122 within the second isolation structure 120₁₂₂May be approximately equal to the depth D in the transistor device 100₁₂₂₁. Additionally, the silicide block layer 128 may not be present in the transistor device 600. To form the gate structure 122 of the transistor device 600, a smoothing process (e.g., a CMP process) may be performed to remove the conductive material 208 and the gate oxide material 206 located above the substrate 102, instead of the etching process described above with reference to fig. 2H. A deoxidation process, such as a poly-deoxidation process, may also be performed to more completely remove the conductive material 208 located above the substrate 102.

In fig. 1, 5 and 6, the first and second isolation structures 116, 120 are shown having sides substantially perpendicular to their respective top surfaces 116t, 120 t. However, alternatively, the sides of these isolation structures 116, 120 may be inclined at an angle relative to their top surfaces 116t, 120 t. When the transistor device 100 comprises such isolation structures 116, 120, the side 122a of the gate structure 122 facing the source region 110 may also be angled such that it may be aligned with the angled side of the second isolation structure 120 to adjoin the body region 106. Additionally, although the first and second isolation structures 116, 120 are shown in fig. 1, 5, and 6 as being completely disposed within the substrate 102, these isolation structures 116, 120 may alternatively extend beyond the top surface 102t of the substrate 102. For example, FIG. 7 showsA Transmission Electron Microscope (TEM) cross-sectional image of an example first and second isolation structures 116, 120 that may be used in the transistor device 100 is shown, wherein these isolation structures 116, 120 may have sloped sides and may extend beyond the top surface 102t of the substrate 102. As shown in fig. 7, the top surface 116t of the first isolation structure 116 and the top surface 120t of the second isolation structure 120 may be substantially laterally aligned with each other over the top surface 102t of the substrate 102. Depth D of the second isolation structure 120₁₂₀May be smaller (from its top surface 120t) than the depth D of the first isolation structure 116₁₁₆(from its top surface 116 t).

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The embodiments described above are therefore to be considered in all respects as illustrative and not restrictive on the invention described herein. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.