阅读说明：本技术 半导体器件及其制备方法 (Semiconductor device and method for manufacturing the same ) 是由 肖魁 方冬 于 2020-05-18 设计创作，主要内容包括：本申请涉及一种半导体器件及其制备方法,器件包括：漂移区和形成于漂移区上表层的体区；形成于体区上表层第一掺杂区；第一沟槽,自体区内延伸至漂移区内,第二沟槽,贯穿第一掺杂区、体区并延伸至漂移区内,第一沟槽的侧壁和第二沟槽的侧壁均形成有氧化层,第一沟槽内填充有第一导电结构,第二沟槽填充有第二导电结构；第一扩展区,包围第一沟槽的底部；栅极与第二导电结构接触；第一电极延伸至第一沟槽顶部并与第一掺杂区、体区和第一沟槽接触；第二电极与半导体衬底接触。漂移区、第一掺杂区、具有第一导电类型,体区、第一扩展区具有第二导电类型。通过第一沟槽和扩展区的作用,可增强漂移区的耗尽,提高器件耐压。(The application relates to a semiconductor device and a preparation method thereof, wherein the device comprises: the drift region and the body region formed on the upper surface layer of the drift region; a first doped region formed on the upper surface layer of the body region; the self-body region of the first groove extends into the drift region, the second groove penetrates through the first doped region and the body region and extends into the drift region, oxide layers are formed on the side wall of the first groove and the side wall of the second groove, the first groove is filled with a first conductive structure, and the second groove is filled with a second conductive structure; a first extension region surrounding a bottom of the first trench; the grid electrode is contacted with the second conductive structure; the first electrode extends to the top of the first groove and is in contact with the first doping region, the body region and the first groove; the second electrode is in contact with the semiconductor substrate. The drift region, the first doped region and the body region have a first conductivity type, and the first extension region and the body region have a second conductivity type. Through the action of the first groove and the extension region, the depletion of the drift region can be enhanced, and the withstand voltage of the device is improved.)

1. A semiconductor device, comprising:

a drift region having a first conductivity type formed on the semiconductor substrate;

the body region is provided with a second conduction type and is formed on the upper surface layer of the drift region;

the first doped region is provided with a first conductive type and is formed on the upper surface layer of the body region;

a first trench and a second trench, wherein the first trench extends from the inside of the body region to the inside of the drift region, the second trench penetrates through the first doped region and the body region and extends into the drift region, oxide layers are formed on the side walls of the first trench and the second trench, the first trench is filled with a first conductive structure, and the second trench is filled with a second conductive structure;

a first extension region of a second conductivity type formed in the drift region under the first trench and surrounding the bottom of the first trench;

a gate in contact with the second conductive structure;

a first electrode extending to a top of the first trench and contacting the first doped region, the body region and the first trench;

a second electrode in contact with the semiconductor substrate.

2. The semiconductor device of claim 1, wherein a bottom depth of the first trench is greater than a bottom depth of the second trench.

3. The semiconductor device of claim 1, wherein the oxide layer is not formed at the bottom of the first trench, and the first extension region is in contact with the first conductive structure.

4. The semiconductor device of claim 1, wherein inner walls of the first trenches are each formed with the oxide layer, the first extension regions being isolated from the first conductive structures.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first conductive structure is in contact with the first electrode.

6. The semiconductor device according to any one of claims 1 to 4, wherein an isolation layer is further formed in the first trench on top of the first conductive structure, the first conductive structure being isolated from the first electrode by the isolation layer.

7. The semiconductor device according to claim 1, further comprising:

the heavily doped region is of the second conduction type, is formed in the body region and is arranged at intervals with the second groove, the doping concentration of the heavily doped region is higher than that of the body region, the first groove extends into the drift region from the inside of the heavily doped region, and the part, which is not covered by the first groove, of the bottom of the first electrode is surrounded by the heavily doped region.

8. The semiconductor device of claim 1, wherein the semiconductor device is a VDMOS field effect transistor, the first doped region is a source region, the semiconductor substrate has a first conductivity type, the first electrode is a source, and the second electrode is a drain.

9. The semiconductor device according to claim 1, wherein the semiconductor device is an IGBT device, the first doped region is an emitter region, the semiconductor substrate has a second conductivity type, a buffer region is further formed between the semiconductor substrate and the drift region, the buffer region has the first conductivity type, the first electrode is an emitter, and the second electrode is a collector.

10. A method for manufacturing a semiconductor device, comprising:

forming a drift region on a semiconductor substrate, the drift region having a first conductivity type;

forming a first groove on the drift region, and forming an oxide layer on the inner wall of the first groove;

injecting second conductive type doping ions into the drift region through the first groove to form a first expansion region which is in contact with the bottom of the first groove;

filling a first conductive structure into the first groove;

forming a second groove isolated from the first groove on the drift region, forming an oxide layer on the inner wall of the second groove, and filling a second conductive structure into the second groove;

doping the upper surface layer of the drift region with a second conductive type to form a body region in contact with the first groove and the second groove, and doping the upper surface layer of the body region with a first conductive type to form a first doped region in contact with the first groove and the second groove;

and cutting the heights of the first conductive structure and the oxide layer in the first groove to the body region, forming a first electrode which penetrates through the first doped region and part of the body region and extends to be in contact with the top of the first groove, forming a grid electrode in contact with the second conductive structure, and forming a second electrode in contact with the semiconductor substrate.

Technical Field

The present disclosure relates to the field of semiconductors, and particularly to a semiconductor device and a method for manufacturing the same.

Background

In a MOS (Metal Oxide Semiconductor) transistor and other Semiconductor devices having a MOS structure, since a certain on-resistance exists when the device is turned on, the larger the on-resistance is, the larger the power consumption of the device is, and therefore, it is necessary to reduce the on-resistance as much as possible. At present, a trench gate structure is usually adopted, and a conduction channel is changed from a transverse direction to a longitudinal direction by forming the trench gate structure, so that the density of the conduction channel is greatly improved, and the conduction resistance is reduced. However, in order to further reduce the on-resistance of the trench gate structure, the doping concentration of the drift region needs to be increased, and the increase in the doping concentration will reduce the voltage endurance of the device.

Disclosure of Invention

Therefore, it is necessary to provide a new semiconductor device and a method for manufacturing the same, aiming at the technical problem that it is difficult to further reduce the on-resistance of the conventional semiconductor device.

A semiconductor device, comprising:

a drift region having a first conductivity type formed on the semiconductor substrate;

the body region is provided with a second conduction type and is formed on the upper surface layer of the drift region;

the first doped region is provided with a first conductive type and is formed on the upper surface layer of the body region;

a first trench and a second trench, wherein the first trench extends from the inside of the body region to the inside of the drift region, the second trench penetrates through the first doped region and the body region and extends into the drift region, oxide layers are formed on the side walls of the first trench and the second trench, the first trench is filled with a first conductive structure, and the second trench is filled with a second conductive structure;

a first extension region of a second conductivity type formed in the drift region under the first trench and surrounding the bottom of the first trench;

a gate in contact with the second conductive structure;

a first electrode extending to a top of the first trench and contacting the first doped region, the body region and the first trench;

a second electrode in contact with the semiconductor substrate.

In one embodiment, the depth of the bottom of the first trench is greater than the depth of the bottom of the second trench.

In one embodiment, the oxide layer is not formed at the bottom of the first trench, and the first extension region is in contact with the first conductive structure.

In one embodiment, the oxide layer is formed on the inner wall of the first trench, and the first extension region is isolated from the first conductive structure.

In one embodiment, the first conductive structure is in contact with the first electrode.

In one embodiment, an isolation layer is further formed in the first trench on top of the first conductive structure, and the first conductive structure is isolated from the first electrode by the isolation layer.

In one embodiment, the method further comprises the following steps:

the heavily doped region is formed in the body region and is arranged at intervals with the second groove, the doping concentration of the heavily doped region is higher than that of the body region, the first groove penetrates through the heavily doped region and extends into the drift region, and the part, not covered by the first groove, of the bottom of the first electrode is surrounded by the heavily doped region.

In one embodiment, the semiconductor device is a VDMOS field effect transistor, the first doped region is a source region, the semiconductor substrate has a first conductivity type, the first electrode is a source, and the second electrode is a drain.

In one embodiment, the semiconductor device is an IGBT device, the first doped region is an emitter region, the semiconductor substrate has a second conductivity type, a buffer region is further formed between the semiconductor substrate and the drift region, the buffer region has the first conductivity type, the first electrode is an emitter, and the second electrode is a collector.

A semiconductor device manufacturing method includes:

forming a drift region on a semiconductor substrate, the drift region having a first conductivity type;

forming a first groove on the drift region, and forming an oxide layer on the inner wall of the first groove;

injecting second conductive type doping ions into the drift region through the first groove to form a first expansion region which is in contact with the bottom of the first groove;

filling a first conductive structure into the first groove;

forming a second groove isolated from the first groove on the drift region, forming an oxide layer on the inner wall of the second groove, and filling a second conductive structure into the second groove;

doping the upper surface layer of the drift region with a second conductive type to form a body region in contact with the first groove and the second groove, and doping the upper surface layer of the body region with a first conductive type to form a first doped region in contact with the first groove and the second groove;

and cutting the heights of the first conductive structure and the oxide layer in the first groove to the body region, forming a first electrode which penetrates through the first doped region and part of the body region and extends to be in contact with the top of the first groove, forming a grid electrode in contact with the second conductive structure, and forming a second electrode in contact with the semiconductor substrate.

According to the semiconductor device and the preparation method thereof, the second groove is formed in the cellular region, the second conductive structure and the oxide layer are formed in the second groove, the second conductive structure is connected with the grid electrode, so that the groove grid structure is formed, the longitudinal conduction channel is formed through the groove grid structure, the density of the conduction channel is improved, and the conduction resistance is reduced.

Meanwhile, a first groove is formed in the cell area, on one hand, a first conductive structure and an oxide layer are formed in the first groove, the first conductive structure can obtain a certain electric potential from the first electrode, an inner field plate is formed between the first conductive structure and the oxide layer, the electric field of the drift area is adjusted, and depletion of the drift area is enhanced. On the other hand, a first extension region is formed in the cell region to surround the bottom of the trench, and the conductivity type of the first extension region is opposite to that of the drift region, so that the first extension region can also enhance the depletion of the drift region. In the application, the inner field plate and the first expansion region are formed on the basis of the traditional trench gate structure, so that the depletion of the drift region is increased under the combined action of the inner field plate and the first expansion region, and the breakdown voltage of the drift region is improved. Therefore, under the condition of equal breakdown voltage, the drift region of the semiconductor device in the application can increase the doping concentration, so that the on-resistance is reduced, namely, under the condition of equal breakdown voltage, the semiconductor device in the application has lower on-resistance.

Drawings

Fig. 1 is a cross-sectional view of a semiconductor device in a first embodiment;

fig. 2 is a cross-sectional view of a semiconductor device in a second embodiment;

fig. 3 is a cross-sectional view of a semiconductor device in a third embodiment;

fig. 4 is a cross-sectional view of a semiconductor device in a fourth embodiment;

FIG. 5 is a flowchart illustrating steps in a method for fabricating a semiconductor device according to one embodiment;

fig. 6a to 6h are cross-sectional views of structures corresponding to the steps related to the method for manufacturing a semiconductor device according to an embodiment.

Description of the reference symbols

A 100 drift region; a 110 body region; 111 a first doped region; 112 heavily doped region; 121 a first trench; 122 a second trench; 131 an oxide layer; 131a an isolation oxide layer; 131b a gate oxide layer; 141 a first conductive structure; 142 a second conductive structure; 150 a first extension area; 160 an isolation layer; 200 dielectric layers; 310 a first electrode; 320 a second electrode; 410 a semiconductor substrate.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, the semiconductor device includes a drift region 100, the drift region 100 is formed on a front surface of a semiconductor substrate 410, and the drift region 100 may be formed by epitaxially growing the semiconductor substrate 410. The drift region 100 has a body region 110 formed on an upper surface thereof, and the body region 110 has a first doped region 111 formed on an upper surface thereof. The first doped region 111 is connected to the first electrode 310, the semiconductor substrate 410 is connected to the second electrode 320, and the first electrode 310 and the second electrode 320 form a current path through the body region 110 and the drift region 100.

The semiconductor device further has a first trench 121 and a second trench 122 therein, wherein the first trench 121 extends from within the body region 110 to within the drift region 100, i.e., a top end and a bottom end of the first trench 121 are within the body region 110 and within the drift region 100, respectively; the second trench 122 penetrates the source region 111, the body region 110 and extends into the drift region 100. An oxide layer 131 is formed on both sidewalls of the first trench 121 and the second trench 122, wherein the oxide layer formed in the first trench 121 is an isolation oxide layer 131a, and the oxide layer formed in the second trench 122 is a gate oxide layer 131 b. Meanwhile, the first trench 121 is further filled with a first conductive structure 141, and the second trench 122 is further filled with a second conductive structure 142. Further, a gate (not shown) is in contact with the second conductive structure 142; the first electrode 310 extends to the top of the first trench 121 and contacts the first doped region 111, the body region 110 and the first trench, respectively, so that the first doped region 111, the body region 110 and the first conductive structure 141 in the first trench 121 can all obtain the potential of the first electrode 310. Specifically, the first conductive structure 141 and the second conductive structure 142 may be polysilicon.

A first extension region 150 is further formed in the drift region 100, and the first extension region 150 is located below the first trench 121 and surrounds the bottom of the first trench 121.

The drift region 100 and the first doped region 111 have a first conductivity type, and the body region 110 and the first extension region 150 have a second conductivity type. Specifically, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

In the semiconductor device, the second conductive structure 142 and the gate oxide layer 131b in the second trench 122 form a trench gate structure and are connected to a gate (not shown), so that a vertical conductive channel is formed in the body region 110 through the trench gate structure. Further, only the second conductive structure 142 may be filled in the second trench 122, so as to form the ordinary trench gate structure as shown in fig. 1.

Meanwhile, on the one hand, the first conductive structure 141 in the first trench 121 can obtain a potential from the first electrode 310, so that the first conductive structure 141 and the isolation oxide layer 131a in the first trench 121 constitute an inner field plate to adjust an electric field of the drift region 110, and enhance depletion of the drift region 110. On the other hand, the first extension region 150 at the bottom of the first trench 121 has a conductivity type opposite to that of the drift region 110, which can further enhance the depletion of the drift region 110. In the application, the withstand voltage of the device can be effectively improved by adding the inner field plate and the first extension region, so that the drift region of the semiconductor device can improve the doping concentration under the condition of equal breakdown voltage, and the on-resistance is reduced. In addition, in the conventional trench gate structure, the breakdown position is an interface between the trench gate and the drift region, and in the present application, because the first trench 121 and the first extension region 150 surrounding the bottom of the first trench 121 are disposed in the drift region 100, the breakdown position is transferred from the trench gate to the interface between the first extension region 150 and the drift region 100, so that the breakdown is more stable.

In an embodiment, a second extension region surrounding the second trench 122 may also be formed in the drift region 100 at the bottom of the second trench 122, and the second extension region has the same properties and functions as the first extension region, which may further enhance the depletion of the drift region.

In an embodiment, the depths of the bottoms of the first trench 121 and the second trench 122 are different, and in particular, the depth of the bottom of the first trench 121 is greater than the depth of the bottom of the second trench 122, so that the three-dimensional depletion of the drift region 100 is optimized.

In an embodiment, the semiconductor device further includes a heavily doped region 112, the heavily doped region 112 is formed in the body region 110 and spaced apart from the second trench 122, and the heavily doped region 112 has the second conductivity type, i.e., the conductivity type of the heavily doped region 112 is the same as that of the body region 110, but the doping concentration of the heavily doped region 112 is higher than that of the body region 110. At this time, the first trench 121 sequentially penetrates through the heavily doped region 112 and the body region 110 and extends into the drift region 100, a portion of the bottom of the first electrode 310 contacts the first trench 121 and is covered by the first trench 121, and another portion is surrounded by the heavily doped region 112, so as to reduce the contact resistance between the first electrode 310 and the body region 110. It should be noted that the first electrode 310 here includes a metal layer located at the top layer shown in the figure and a first lead-out structure extending from the metal layer to the first trench 121.

In one embodiment, the first doped region 111 and the second trench 122 are covered with a dielectric layer 200, and the first lead-out structure of the first electrode 310 penetrates through the dielectric layer 200, the first doped region 111 and extends to the top of the first trench 121 to contact the first trench 121.

Specifically, in an embodiment, no oxide layer is formed at the bottom of the first trench 121, so that the first extension region 150 is in direct contact with the first conductive structure 141. In another embodiment, the oxide layer 131 is formed on the inner walls of the first trenches 121, so that the first extension regions 150 are isolated from the first conductive structures 141.

Specifically, in one embodiment, the first electrode 310 extends to the top of the first trench 121 and contacts the first trench 121, and the first conductive structure 141 fills the first trench 121 and directly contacts the first electrode 310 to obtain an electric potential. In another embodiment, the first conductive structure 141 does not fill the first trench 121, an isolation layer is further disposed on the top of the first conductive structure, the first conductive structure 141 is isolated from the first electrode 310 by the isolation layer, and the thickness of the isolation layer is required to satisfy the requirement that the first conductive structure 141 can obtain the induced potential from the first electrode 310.

To describe the semiconductor structure in detail, four embodiments are further described below.

The first embodiment:

fig. 1 is a schematic structural view of a semiconductor device in the first embodiment.

With continued reference to fig. 1, the first electrode 310 extends to the top of the first trench 121 and directly contacts the first conductive structure 141 in the first trench 121, so that the first conductive structure 141 directly obtains the potential of the first electrode 310, and the first conductive structure 141 and the oxide layer 131 act as an inner field plate, thereby adjusting the electric field of the drift region 100 and enhancing the depletion of the drift region 100.

Specifically, in the first trench 121, the oxide layer 131 is formed only on the sidewall of the first trench 121, that is, the oxide layer 131 is formed on the sidewall of the first trench 121, but no oxide layer is formed on the bottom of the first trench 121, the first extension region 150 is in contact with the first conductive structure 141 in the first trench 121, and after the first conductive structure 141 obtains a potential from the first electrode 310, the first extension region 150 can also obtain a potential through the first conductive structure 141, thereby enhancing the depletion of the first extension region 150 on the drift region 100.

In the embodiment, the first conductive structure 141 is directly contacted with the first electrode 310, and the first extension region 150 is directly contacted with the first conductive structure 141, so that the first extension region 150 and the first conductive structure 141 both have a stronger potential, and the depletion of the drift region 100 can be improved.

Second embodiment:

fig. 2 is a schematic structural view of a semiconductor device in the second embodiment.

The second embodiment is different from the first embodiment only in that the coverage area of the oxide layer 131 is different in the second embodiment. In the present embodiment, the oxide layer 131 is formed on the inner wall of the first trench 121, that is, the oxide layer 131 is formed on the sidewall and the bottom of the first trench 121, and the first extension region 150 is isolated from the first conductive structure 141, so that the leakage path of the first electrode 310, the first conductive structure 141 and the first extension region 150 is cut off, and the leakage is reduced.

The third embodiment:

fig. 3 is a schematic structural view of a semiconductor device in a third embodiment.

The third embodiment is different from the first embodiment only in that an isolation layer 160 is further formed between the first conductive structure 141 and the first electrode 310 in the third embodiment, the first conductive structure 141 is isolated from the first electrode 310 by the isolation layer 160, and the thickness of the isolation layer 160 is required to satisfy that the first conductive structure 141 can obtain the induced potential from the first electrode 310. Specifically, the isolation layer 160 may be silicon oxide.

In this embodiment, the isolation layer 160 is disposed between the first electrode 310 and the first conductive structure 141, and the leakage path of the first electrode 310, the first conductive structure 141 and the first extension region 150 is cut off by the isolation layer 160, so as to reduce the leakage. Meanwhile, the first conductive structure 141 may acquire an induced potential of the first electrode 310, and therefore, in the present embodiment, the first conductive structure 141 and the first extension region 150 have a certain induced potential, which may enhance the depletion of the drift region 100.

The fourth embodiment:

fig. 4 is a schematic structural view of a semiconductor device in a fourth embodiment.

The fourth embodiment is different from the first embodiment only in that an isolation layer 160 is disposed between the first conductive structure 141 and the first electrode 310 in the first trench 121, and an oxide layer 131 is formed on the inner wall of the first trench 121 to isolate the first extension region 150 from the first conductive structure 141.

In the embodiment, the first electrode 310 is isolated from the first conductive structure 141 by the isolation structure 160, and the first conductive structure 141 is isolated from the first extension region 150 by the oxide layer 131, so as to further cut off the leakage path of the first electrode 310, the first conductive structure 141 and the oxide layer 131, thereby avoiding leakage, at this time, the first conductive structure 141 can obtain the induced potential of the first electrode 310, and the first extension region 150 has no potential.

In a specific embodiment, the Semiconductor device may be a VDMOS (Vertical Double diffusion Metal Oxide Semiconductor) field effect transistor. The first doped region 111 is a source region, and the semiconductor substrate 410 has a first conductivity type. The first electrode 310 is a source and the second electrode 320 is a drain.

In another specific embodiment, the semiconductor device may also be an IGBT (Insulated Gate Bipolar Transistor), wherein the first doped region 111 is an emitter region, the semiconductor substrate 410 has the second conductivity type, a buffer region is further formed between the semiconductor substrate 410 and the drift region 100, the buffer region has the first conductivity type, the first electrode 310 is an emitter, and the second electrode 320 is a collector.

The present application also relates to a method of manufacturing a semiconductor device, as shown in fig. 5, the method comprising the steps of:

step S510: a drift region is formed on a semiconductor substrate, the drift region having a first conductivity type.

As shown in fig. 6a, a semiconductor substrate 410 is provided, the semiconductor substrate 410 having a drift region 100 formed thereon.

Step S520: and forming a first groove on the drift region, and forming an oxide layer on the inner wall of the first groove.

As shown in fig. 6b, a first trench 121 is opened in the drift region 100, and an oxide layer 131 is formed on an inner wall of the first trench 121. Specifically, the oxide layer 131 may be formed on the inner wall of the first trench 121 through a thermal oxidation process.

Step S530: and injecting second conductive type doping ions into the drift region through the first groove to form a first extension region which is in contact with the bottom of the first groove.

As shown in fig. 6c, second conductive type dopant ions are implanted into the drift region 100 through the first trench 121 to form a first extension region 150 contacting the bottom of the first trench 121.

Step S540: and filling a first conductive structure into the first groove.

As shown in fig. 6e, the first conductive structure 141 is filled into the first trench 121. Specifically, the first conductive structure 141 may be polysilicon.

In an embodiment, between step S530 and step S540, the method further includes:

and etching the oxide layer at the bottom of the first groove to expose the first expansion region.

As shown in fig. 6d, an opening exposing the first extension region 150 is formed by dry etching the oxide layer 131 at the bottom of the first trench 121. At this time, in step S540, after the first conductive structures 141 are filled, the first conductive structures 141 are in contact with the first extension regions 150.

Step S550: and opening a second groove isolated from the first groove on the drift region, forming an oxide layer on the inner wall of the second groove, and filling a second conductive structure into the second groove.

As shown in fig. 6f, the second trench 122 is opened on the drift region 100, and the first trench 121 and the second trench 122 are isolated from each other. An oxide layer 131 is formed on the inner wall of the second trench 122, and a second conductive structure 142 is filled in the second trench 122. At this time, the oxide layer formed in the first trench 121 is the isolation oxide layer 131a, and the oxide layer formed in the second trench 122 is the gate oxide layer 131 b. Specifically, the second conductive structure 142 may be polysilicon.

Step S560: and doping the upper surface layer of the drift region with a second conductive type to form a body region in contact with the first groove and the second groove, and doping the upper surface layer of the body region with a first conductive type to form a first doped region in contact with the first groove and the second groove.

As shown in fig. 6g, after the first trench 121 and the second trench 122 are formed, the formation of the body region and the first doping region is continued. Specifically, the upper surface layer of the drift region 100 is doped with the second conductive type, and the body region 110 in contact with the first trench 121 and the second trench 122 is formed. The first conductive type doping of the upper surface of the body region 110 is continued to form the first doping region 111 in contact with the first trench 121 and the second trench 122.

In an embodiment, the process of forming the body region 110 is specifically a high temperature drive-in process, wherein the temperature and time of the high temperature drive-in process can be adjusted according to the doping depth and the doping concentration of the body region, specifically, the temperature range of the high temperature drive-in process can be controlled between 900 ℃ and 1200 ℃, and the time range of the high temperature drive-in process can be controlled between 10min and 180 min. While the high temperature drive-in forms the body region 110, the dopant ions of the first extension region 150 are out-diffused, causing the first extension region 150 to extend outward, thereby increasing the volume of the first extension region 150.

Step S570: and cutting the heights of the first conductive structure and the oxide layer in the first groove to the body region, forming a first electrode which penetrates through the first doped region and part of the body region and extends to be in contact with the top of the first groove, forming a grid electrode in contact with the second conductive structure, and forming a second electrode in contact with the semiconductor substrate.

As shown in fig. 6h, the heights of the first conductive structure 141 and the oxide layer 131 in the first trench are reduced, so that the height of the top surface of the first trench 121 and the internal filling structure thereof is reduced to the body region, and the first trench 121 penetrates through the first doped region 111 and extends to the first lead-out structure of the body region 110, which is already in contact with the first trench, so that the first lead-out structure is also in contact with the first doped region 111 and the body region 110. The top of the first lead-out structure is connected to the first metal layer, and the first lead-out structure and the first metal layer together serve as a first electrode 310. Specifically, the width of the first lead-out structure in the cross section of fig. 6h is greater than the width of the first trench 121, and the first lead-out structure covers the first trench 121.

At the same time, a gate electrode is also formed in contact with the second conductive structure 142.

When the semiconductor device is a VDMOS field effect transistor, the first doped region 111 is a source region, and the semiconductor substrate 410 has a first conductivity type. When the semiconductor device is an IGBT, the first doped region 111 is an emitter region, the semiconductor substrate 410 has the second conductivity type, and a first conductivity type buffer region is further formed between the semiconductor substrate 410 and the drift region 100.

The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.