阅读说明：本技术 阵列基板及显示面板 (Array substrate and display panel ) 是由 李波 于 2021-08-06 设计创作，主要内容包括：本申请实施例公开了一种阵列基板及显示面板,阵列基板包括自下而上层叠设置的基底、第一半导体层、第一金属层、第二金属层、第二半导体层、第三金属层,第一半导体层包括各第一类晶体管的有源层,第二半导体层包括各第二类晶体管的有源层；其中,第一金属层包括各第一类晶体管的顶栅极,第二金属层包括第一主扫描线和第二主扫描线,第三金属层包括第一次扫描线和第二次扫描线,第一主扫描线包括复位晶体管的底栅极,第一次扫描线包括复位晶体管的顶栅极,第二主扫描线包括补偿晶体管的底栅极,第二次扫描线包括补偿晶体管的顶栅极。可以最大程度降低多晶硅晶体管的像素电路的漏电流大小,使得发光元件电流更加稳定,避免显示面板出现的闪烁现象。(The embodiment of the application discloses an array substrate and a display panel, wherein the array substrate comprises a substrate, a first semiconductor layer, a first metal layer, a second semiconductor layer and a third metal layer which are stacked from bottom to top, the first semiconductor layer comprises active layers of various first transistors, and the second semiconductor layer comprises active layers of various second transistors; the first metal layer comprises top gates of the first transistors, the second metal layer comprises a first main scanning line and a second main scanning line, the third metal layer comprises a first secondary scanning line and a second secondary scanning line, the first main scanning line comprises a bottom gate of the reset transistor, the first secondary scanning line comprises a top gate of the reset transistor, the second main scanning line comprises a bottom gate of the compensation transistor, and the second secondary scanning line comprises a top gate of the compensation transistor. The leakage current of the pixel circuit of the polysilicon transistor can be reduced to the greatest extent, so that the current of the light-emitting element is more stable, and the flicker phenomenon of the display panel is avoided.)

1. An array substrate is characterized by comprising a plurality of pixels arranged in an array, wherein each pixel comprises a driving transistor, a data writing transistor, a reset transistor, a compensation transistor and a light-emitting element, the driving transistor and the data writing transistor are first-class transistors, and the reset transistor and the compensation transistor are second-class transistors;

the array substrate comprises a substrate, a first semiconductor layer, a first metal layer, a second semiconductor layer and a third metal layer which are stacked from bottom to top, wherein the first semiconductor layer comprises active layers of various first transistors, and the second semiconductor layer comprises active layers of various second transistors;

wherein, first metal level includes the top grid of each first class transistor, the second metal level includes first main scanning line and second main scanning line, the third metal level includes first scanning line and second scanning line, first main scanning line includes the bottom gate of reset transistor, first scanning line includes the top grid of reset transistor, second main scanning line includes the bottom gate of compensation transistor, the second scanning line includes the top gate of compensation transistor.

2. The array substrate of claim 1, wherein the first type of transistors are polysilicon transistors and the second type of transistors are oxide transistors.

3. The array substrate of claim 2, wherein an orthographic projection of the first main scanning line on the substrate and an orthographic projection of the first sub-scanning line on the substrate at least partially overlap;

the orthographic projection of the second main scanning line on the substrate and the orthographic projection of the second secondary scanning line on the substrate are at least partially overlapped.

4. The array substrate of claim 3, wherein the active layer of the compensation transistor and the active layer of the reset transistor are of an integral structure connected to each other, and a material of the second semiconductor layer between the compensation transistor and the reset transistor is conductized.

5. The array substrate of claim 4, further comprising a storage capacitor electrically connected to the drive transistor;

the first metal layer includes a first capacitor electrode of a storage capacitor, and the second metal layer includes a second capacitor electrode of the storage capacitor.

6. The array substrate of claim 5, further comprising a fourth metal layer disposed on a side of the third metal layer away from the substrate, the fourth metal layer including a data line and a first power line.

7. The array substrate of claim 6, further comprising a fifth metal layer disposed on a side of the fourth metal layer away from the substrate, wherein the fifth metal layer comprises a second power line electrically connected to the first power line, an extending direction of the second power line is the same as an extending direction of the first power line, and an orthographic projection of the second power line on the substrate at least partially overlaps an orthographic projection of the first power line on the substrate.

8. The array substrate of claim 7, wherein the second power line further comprises a protrusion, and an orthographic projection of the protrusion on the substrate covers orthographic projections of the driving transistor, the compensating transistor and the reset transistor on the substrate.

9. The array substrate of claim 8, wherein the pixel further comprises:

the light emitting diode comprises a reset transistor, a first light emitting control transistor and a second light emitting control transistor, wherein the reset transistor, the first light emitting control transistor and the second light emitting control transistor are transistors of a first type.

10. A display panel comprising the array substrate according to any one of claims 1 to 9, wherein the array substrate further comprises a pixel defining layer, the light emitting device is disposed in the opening of the pixel defining layer, and the display panel further comprises an encapsulation layer disposed on the light emitting device.

Technical Field

The application relates to the field of display, in particular to an array substrate and a display panel.

Background

With the development of multimedia, display devices become more and more important. Accordingly, the demand for various types of display devices is increasing, especially in the field of smart phones, and ultrahigh frequency driving display, low power consumption driving display, and low frequency driving display are the development demand directions at present and in the future.

Because Low Temperature Polysilicon (LTPS) has high mobility and strong driving capability, LTPS thin film transistors are widely used in pixel circuits in OLED display panels (organic light emitting display panels), but the LTPS thin film transistors have large leakage currents, and gate voltages are easily unstable due to the large leakage currents, especially during Low frequency display, so that the potential difference between the gate and the source is unstable, the current of the OLED light emitting device is unstable, and the display panel flickers.

Disclosure of Invention

The embodiment of the application provides an array substrate and a display panel, and can solve the problems that an OLED light-emitting element current is unstable and a display panel flickers due to the fact that a pixel circuit adopting a polycrystalline silicon thin film transistor has large leakage current of the transistor.

The embodiment of the application provides an array substrate, which comprises a plurality of pixels arranged in an array, wherein each pixel comprises a driving transistor, a data writing transistor, a reset transistor, a compensation transistor and a light-emitting element;

the array substrate comprises a substrate, a first semiconductor layer, a first metal layer, a second semiconductor layer and a third metal layer which are stacked from bottom to top, wherein the first semiconductor layer comprises active layers of various first transistors, and the second semiconductor layer comprises active layers of various second transistors;

wherein, first metal level includes the top grid of each first class transistor, the second metal level includes first main scanning line and second main scanning line, the third metal level includes first scanning line and second scanning line, first main scanning line includes the bottom gate of reset transistor, first scanning line includes the top grid of reset transistor, second main scanning line includes the bottom gate of compensation transistor, the second scanning line includes the top gate of compensation transistor.

Optionally, in some embodiments of the present application, the first type transistor is a polysilicon transistor, and the second type transistor is an oxide transistor.

Optionally, in some embodiments of the present application, an orthographic projection of the first main scan line on the substrate and an orthographic projection of the first sub scan line on the substrate at least partially overlap;

the orthographic projection of the second main scanning line on the substrate and the orthographic projection of the second secondary scanning line on the substrate are at least partially overlapped.

Optionally, in some embodiments of the present application, the active layer of the compensation transistor and the active layer of the reset transistor are of an integral structure connected to each other, and a material of the second semiconductor layer between the compensation transistor and the reset transistor is conductized.

Optionally, in some embodiments of the present application, the display device further includes a storage capacitor, and the storage capacitor is electrically connected to the driving transistor;

the first metal layer includes a first capacitor electrode of a storage capacitor, and the second metal layer includes a second capacitor electrode of the storage capacitor.

Optionally, in some embodiments of the present application, a fourth metal layer disposed on a side of the third metal layer away from the substrate is further included,

the fourth metal layer includes a data line and a first power line.

Optionally, in some embodiments of the present application, the method further includes providing a fifth metal layer on one side of the substrate away from the fourth metal layer, where the fifth metal layer includes a second power line, the second power line is electrically connected to the first power line, an extending direction of the second power line is the same as an extending direction of the first power line, and the second power line is in the orthographic projection on the substrate and the orthographic projection on the substrate of the first power line at least partially overlap.

Optionally, in some embodiments of the present application, the second power line further includes a protrusion, and an orthographic projection of the protrusion on the substrate covers an orthographic projection of the driving transistor, the compensation transistor, and the reset transistor on the substrate.

Optionally, in some embodiments of the present application, the pixel further includes:

the light emitting diode comprises a reset transistor, a first light emitting control transistor and a second light emitting control transistor, wherein the reset transistor, the first light emitting control transistor and the second light emitting control transistor are transistors of a first type.

Correspondingly, the embodiment of the application provides a display panel, which comprises the array substrate, the array substrate further comprises a pixel definition layer, the light-emitting element is arranged in the opening of the pixel definition layer, and the display panel further comprises an encapsulation layer arranged on the light-emitting element.

In the embodiment of the application, the array substrate and the display panel are provided, the oxidation transistor with the double-grid structure is used as the reset transistor and the compensation transistor, the leakage current of a pixel circuit of the polycrystalline silicon transistor can be reduced to the greatest extent, the current of an OLED light-emitting element is more stable, and the flicker phenomenon of the display panel is avoided.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of an equivalent circuit of a pixel on an array substrate according to an embodiment of the present disclosure;

fig. 2 is a timing diagram of an equivalent circuit of a pixel on an array substrate according to an embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional film structure of a pixel on an array substrate according to an embodiment of the present disclosure;

fig. 4 is a schematic layout diagram of a pixel on an array substrate according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a pattern of a first semiconductor layer in a pixel layout according to an embodiment of the present application;

fig. 6 is a schematic diagram of a pattern of a first metal layer in a pixel layout according to an embodiment of the present application;

fig. 7 is a schematic diagram of a pattern of a second metal layer in a pixel layout according to an embodiment of the present application;

fig. 8 is a schematic diagram of a pattern of a second semiconductor layer in a pixel layout according to an embodiment of the present application;

fig. 9 is a schematic diagram of a third metal layer in a pixel layout according to an embodiment of the present application;

fig. 10 is a schematic diagram of a pattern of a fourth metal layer in a pixel layout according to an embodiment of the present application;

fig. 11 is a schematic diagram of a pattern of a fifth metal layer in a pixel layout according to an embodiment of the present application;

fig. 12 is a schematic diagram of a stacking structure from a first semiconductor layer to a first metal layer in a pixel layout according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.

The embodiment of the application provides an array substrate, which comprises a plurality of pixels arranged in an array, wherein each pixel comprises a driving transistor, a data writing transistor, a reset transistor, a compensation transistor and a light-emitting element;

the array substrate comprises a substrate, a first semiconductor layer, a first metal layer, a second semiconductor layer and a third metal layer which are stacked from bottom to top, wherein the first semiconductor layer comprises active layers of various first transistors, and the second semiconductor layer comprises active layers of various second transistors;

the first metal layer comprises top gates of the first transistors, the second metal layer comprises a first main scanning line and a second main scanning line, the third metal layer comprises a first secondary scanning line and a second secondary scanning line, the first main scanning line comprises a bottom gate of the reset transistor, the first secondary scanning line comprises a top gate of the reset transistor, the second main scanning line comprises a bottom gate of the compensation transistor, and the second secondary scanning line comprises a top gate of the compensation transistor.

The embodiment of the application provides an array substrate and a display panel. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.

The first embodiment,

Referring to fig. 1, fig. 2, fig. 3, and fig. 4, fig. 1 is a schematic diagram of an equivalent circuit of a pixel on an array substrate according to an embodiment of the present application, fig. 2 is a timing diagram of an equivalent circuit of a pixel on an array substrate according to an embodiment of the present application, fig. 3 is a schematic diagram of a cross-sectional film structure of a pixel on an array substrate according to an embodiment of the present application, and fig. 4 is a schematic diagram of a layout of a pixel on an array substrate according to an embodiment of the present application.

The embodiment of the application provides an array substrate 100, which comprises a plurality of pixels 200 arranged in an array, wherein the pixels 200 comprise a driving transistor T1, a data writing transistor T2, a reset transistor T4, a compensation transistor T3 and a light-emitting element OL, the driving transistor T1 and the data writing transistor T2 are transistors of a first type, and the reset transistor T4 and the compensation transistor T3 are transistors of a second type;

the array substrate 100 comprises a substrate 11, a first semiconductor layer 13, a first metal layer 15, a second metal layer 17, a second semiconductor layer 19 and a third metal layer 21 which are stacked from bottom to top, wherein the first semiconductor layer 13 comprises an active layer of each first transistor, and the second semiconductor layer 19 comprises an active layer of each second transistor;

the first metal layer 15 includes a top gate of each first-type transistor, the second metal layer 17 includes a first main scan line Sn (11) and a second main scan line Sn (vt1), the third metal layer 21 includes a first sub-scan line Sn (12) and a second sub-scan line Sn (vt2), the first main scan line Sn (11) includes a bottom gate of the reset transistor T4, the first sub-scan line Sn (12) includes a top gate of the reset transistor T4, the second main scan line Sn (vt1) includes a bottom gate of the compensation transistor T3, and the second sub-scan line Sn (vt2) includes a top gate of the compensation transistor T3.

Further, in the array substrate 100 of some embodiments, the first type of transistors are polysilicon transistors, and the second type of transistors are oxide transistors.

Further, in the array substrate 100 of some embodiments, an orthogonal projection of the first main scan line Sn (11) on the substrate 11 and an orthogonal projection of the first sub scan line Sn (12) on the substrate 11 at least partially overlap;

the orthographic projection of the second main scanning line Sn (vt1) on the substrate 11 and the orthographic projection of the second secondary scanning line Sn (vt2) on the substrate 11 at least partially overlap.

Further, in the array substrate 100 of some embodiments, the active layer of the compensation transistor T3 and the active layer of the reset transistor T4 are integrated structures connected to each other, and the material of the second semiconductor layer between the compensation transistor T3 and the reset transistor T4 is conducted.

Further, in the array substrate 100 of some embodiments, a storage capacitor Cst is further included, and the storage capacitor Cst is electrically connected to the driving transistor T1;

the first metal layer 15 includes a first capacitance electrode Cst11 of the storage capacitance Cst, and the second metal layer 17 includes a second capacitance electrode Cst12 of the storage capacitance Cst.

Further, in the array substrate 100 of some embodiments, a fourth metal layer 23 is further included on a side of the third metal layer 21 away from the substrate 11, and the fourth metal layer 23 includes a Data line Data and a first power line VDD 1.

Further, in the array substrate 100 of some embodiments, a fifth metal layer 25 is further included on a side of the fourth metal layer 23 away from the base 11, the fifth metal layer 25 includes a second power line VDD2, the second power line VDD2 is electrically connected to the first power line VDD1, an extending direction of the second power line VDD2 is the same as an extending direction of the first power line VDD1, and an orthographic projection of the second power line VDD2 on the base 11 at least partially overlaps an orthographic projection of the first power line VDD1 on the base 11.

Further, in the array substrate 100 of some embodiments, the second power line VDD2 further includes a protrusion 301, and an orthographic projection of the protrusion 301 on the substrate 11 covers an orthographic projection of the driving transistor T1, the compensating transistor T3 and the reset transistor T4 on the substrate 11.

Further, in the array substrate 100 of some embodiments, the pixel further includes: the reset transistor T7, the first light emission controlling transistor T5, and the second light emission controlling transistor T6, and the reset transistor T7, the first light emission controlling transistor T5, and the second light emission controlling transistor T6 are first type transistors.

The structure and connection relationship of the above embodiments are further described below.

Referring to fig. 3 and 4, the pixels 200 are disposed on the array substrate 100, and the layer structure of the array substrate 100 may be, but is not limited to, the following number and order of the layer structures, and the layer structure of the array substrate 100 includes: a substrate 11; a buffer layer 12 provided on the substrate 11, and a first semiconductor layer 13 provided on the buffer layer 12; a first gate insulating layer 14 provided on the first semiconductor layer 13; a first metal layer 15 provided on the first gate insulating layer 14; a capacitor insulating layer 16 provided on the first metal layer 15; a second metal layer 17 provided on the capacitor insulating layer 16; a second gate insulating layer 18 disposed on the second metal layer 17; a second semiconductor layer 19 provided on the second gate insulating layer 18; a third gate insulating layer 20 provided on the second semiconductor layer 19; a third metal layer 21 disposed on the third gate insulating layer 20; an interlayer insulating layer 22 provided on the third metal layer 21; a fourth metal layer 23 provided on the interlayer insulating layer 22; a first planarization layer 24 disposed on the fourth metal layer 23; a fifth metal layer 25 provided on the first flat layer 24; a second planarization layer 26 disposed on the fifth metal layer 25; an anode 27 provided on the second flat layer; a pixel defining layer 28 disposed on the anode 27.

Referring to fig. 3, 4, 5, 6, 7, 8, 9, 10, 11 and 12, fig. 5 is a schematic diagram of a pattern of a first semiconductor layer in a pixel layout provided in the embodiment of the present application, fig. 6 is a schematic diagram of a pattern of a first metal layer in a pixel layout provided in an embodiment of the present application, fig. 7 is a schematic diagram of a pattern of a second metal layer in a pixel layout provided in an embodiment of the present application, fig. 8 is a schematic diagram of a pattern of a second semiconductor layer in a pixel layout provided in an embodiment of the present application, fig. 9 is a schematic diagram of a pattern of a third metal layer in a pixel layout provided in the embodiment of the present application, fig. 10 is a schematic diagram of a pattern of a fourth metal layer in a pixel layout provided in the embodiment of the present application, fig. 11 is a schematic diagram of a pattern of a fifth metal layer in a pixel layout provided in the embodiment of the present application, fig. 12 is a schematic diagram of a stacking structure from a first semiconductor layer to a first metal layer in a pixel layout according to an embodiment of the present application.

Referring to fig. 3, 4, 5 and 12, the first semiconductor layer 13 includes an active layer T1B, a source T1S and a drain T1D of the driving transistor T1, the first semiconductor layer 13 includes an active layer T2B, a source T2S and a drain T2D of the data writing transistor T2, the first semiconductor layer 13 includes an active layer T5B, a source T5S and a drain T5D of the first light emission controlling transistor T5, the first semiconductor layer 13 includes an active layer T6B, a source T6S and a drain T6D of the second light emission controlling transistor T6, the first semiconductor layer 13 includes an active layer T7B, a source T7S and a drain T7D of the reset transistor T7, the active layers of the transistors are connected to each other, and the material of the first semiconductor layer between the different transistors is made conductive so that the source or the drain serves as an electrode for electrical connection. That is, the first semiconductor layer 13 includes an active layer of each of the first-type transistors.

Specifically, the first type of transistor is a polysilicon transistor, which uses a polysilicon material as a semiconductor layer, such as Low Temperature Polysilicon (LTPS).

Specifically, the reset signal source may include a first reset signal source VI1 and a second reset signal source VI2, the first semiconductor layer 13 includes a second reset signal source VI12, and the first semiconductor layer 13 includes a second reset signal source VI12 formed by being conducted.

Referring to fig. 3, 4, 6 and 12, the first metal layer 15 includes a third scan line sn (d), a fourth scan line sn (x), a light-emitting control signal line EM, and a gate T1G of a driving transistor T1, wherein a gate T2G of a data writing transistor T2 is a portion of the third scan line sn (d), a gate T7G of a reset transistor T7 is a portion of the fourth scan line sn (x), a gate T5G of a first light-emitting control transistor T5 and a gate T6G of a second light-emitting control transistor T6 are portions of the light-emitting control signal line EM, and a gate T1G of the driving transistor T1 is multiplexed as a first capacitor electrode C11 of the storage capacitor Cst. That is, the first metal layer 15 is patterned to form the top gate of the first type transistor.

Referring to fig. 3, 4 and 7, the second metal layer 17 includes a trace of the reset signal source VI, a first main scan line Sn (11), a second main scan line Sn (vt1) and a second capacitor electrode C12 of the storage capacitor Cst, the bottom gate T4G1 of the reset transistor T4 is a portion of the first main scan line Sn (11), and the bottom gate T3G1 of the compensation transistor T3 is a portion of the second main scan line Sn (vt 1). That is, the second metal layer 17 is patterned to form the bottom gate of the second type transistor.

Specifically, the reset signal source VI may include a first reset signal source VI1 and a second reset signal source VI2, the second metal layer 17 includes a first reset signal source VI11, the first semiconductor layer 13 includes a second reset signal source VI12, and the second reset signal source VI12 may be arranged to reduce the impedance of the reset signal source VI, so as to improve the potential uniformity of the reset signal source VI in each pixel.

Referring to fig. 3, 4 and 8, the second semiconductor layer 19 includes an active layer T3B, a source T3S and a drain T3D of the compensation transistor T3, and the second semiconductor layer 19 includes an active layer T4B, a source T4S and a drain T4D of the reset transistor T4. That is, the second semiconductor layer 19 is patterned to form the active layer of each of the second type transistors.

Specifically, the second type of transistor is an oxide transistor, and a metal oxide is used as a semiconductor material, such as an IGZO (indium gallium zinc oxide) material.

Specifically, the active layer of the compensation transistor T3 and the active layer of the reset transistor T4 are connected to each other to form an integrated structure, the material of the second semiconductor layer between the compensation transistor T3 and the reset transistor T4 is conducted, the parts of the conducted second semiconductor layer serve as the source T3S and the drain T3D of the compensation transistor T3 and the source T4S and the drain T4D of the reset transistor T4, and no additional metal layer is required to be manufactured to serve as the source and the drain of the second type of transistor, so that the layer structure complexity of the array substrate 100 can be reduced and the manufacturing process can be simplified.

Referring to fig. 3, 4 and 9, the third metal layer 21 includes a first sub-scanning line Sn (12) and a second sub-scanning line Sn (vt2), a top gate T4G2 of the reset transistor T4 is a portion of the first sub-scanning line Sn (12), and a top gate T3G2 of the compensation transistor T3 is a portion of the second sub-scanning line Sn (vt 2). That is, the third metal layer 21 is patterned to form the top gate of the second type transistor.

In particular, in the polysilicon pixel, the leakage current of the polysilicon thin film transistor is large, especially, when displaying at low frequency, the leakage current is large, which easily causes unstable gate voltage, thereby causing unstable gate and source potential difference, which causes unstable current of the OLED light emitting element, and the display panel has a flicker phenomenon, in the embodiment of the present application, the compensation transistor T3 and the reset transistor T4, which are electrically connected to the first capacitor electrode Cst11, are implemented by using an oxide transistor, the leakage current of the oxide transistor is small, which can improve unstable gate and source potential difference of the driving transistor T1, thereby preventing the display panel from having a flicker phenomenon, further, the compensation transistor T3 and the reset transistor T4 both use a dual-gate structure, the compensation transistor T3 includes a bottom gate T3G1 and a top gate T3G2, the reset transistor T4 includes a bottom gate T4G1 and a top gate T4G2, the dual-gate structure can better turn off the compensation transistor T3 and the reset transistor T4, the leakage currents of the compensation transistor T3 and the reset transistor T4 are minimized to make the gate and source potential differences of the driving transistor T1 reach the most stable state, thereby preventing the flicker phenomenon of the display panel.

Specifically, the orthographic projection of the first main scanning line Sn (11) on the substrate 11 and the orthographic projection of the first secondary scanning line Sn (12) on the substrate 11 are at least partially overlapped, that is, the bottom gate T3G1 and the top gate T3G2 of the compensation transistor T3 are at least partially overlapped, and the overlapped portions of the double gates of the compensation transistor T3 jointly function to simultaneously turn on and off the compensation transistor T3, so that the mobility of the compensation transistor T3 in the on state can be improved, and the leakage current of the compensation transistor T3 in the off state can be reduced. The orthographic projection of the second main scanning line Sn (vt1) on the substrate 11 and the orthographic projection of the second secondary scanning line Sn (vt2) on the substrate 11 are at least partially overlapped, that is, the bottom gate T4G1 and the top gate T4G2 of the reset transistor T4 are at least partially overlapped, and the overlapped portions of the double gates of the reset transistor T4 jointly play a role of simultaneously turning on and off the reset transistor T4, so that the mobility of the reset transistor T4 in the on state can be improved, and the leakage current of the reset transistor T4 in the off state can be reduced.

Referring to fig. 3, 4 and 10, the fourth metal layer 23 includes a Data line Data, a first power line VDD1, a first connection electrode 201, a second connection electrode 202, a third connection electrode 203 and a fourth connection electrode 204, wherein the first connection electrode 201, the second connection electrode 202, the third connection electrode 203 and the fourth connection electrode 204 function as a bridge electrode for transmitting signals, and are specifically connected to other layers through various vias described later.

Referring to fig. 3, 4 and 11, the fifth metal layer 25 includes a second power line VDD2, and the second power line VDD2 is electrically connected to the first power line VDD1 and supplies the same signal, so as to reduce the voltage drop (IRDrop) on the first power line VDD1 to the maximum, thereby improving the voltage uniformity and stability of the first power line VDD1 on the entire array substrate 100, and improving the display quality.

Specifically, the second power line VDD2 further includes a protrusion 301, an orthographic projection of the protrusion 301 on the substrate 11 covers an orthographic projection of the driving transistor T1, the compensating transistor T3 and the reset transistor T4 on the substrate 11, that is, the protrusion 301 of the second power line VDD2 functions to shield the driving transistor T1, the compensating transistor T3 and the reset transistor T4, so as to prevent an electrode such as an anode of the light emitting element OL above the protrusion 301 from affecting the operation stability of the driving transistor T1, the compensating transistor T3 and the reset transistor T4 through capacitive coupling or the like, the protrusion 301 may also function to shield the storage capacitor Cst, prevent an electrode such as an anode of the light emitting element OL above the protrusion 301 from affecting the voltage stability of the storage capacitor Cst through capacitive coupling or the like, and therefore, the protrusion 301 may improve the voltage stability of the storage capacitor Cst, the driving transistor T1, the compensating transistor T3 and the reset transistor T4, thereby avoiding the display panel from flickering.

Specifically, the second power line VDD2 is electrically connected to the first power line VDD1, the extending direction of the second power line VDD2 is the same as the extending direction of the first power line VDD1, the orthographic projection of the second power line VDD2 on the substrate 11 at least partially overlaps the orthographic projection of the first power line VDD1 on the substrate 11, and since the second power line VDD2 is electrically connected to the first power line VDD1 and supplies the same electrical signal, after the orthographic projection of the second power line VDD2 on the substrate 11 overlaps the orthographic projection of the first power line VDD1 on the substrate 11, the space occupied by the second power line VDD2 and the first power line VDD1 on the layout (layout) can be reduced, and the pixel resolution of the array substrate 100 can be improved.

The connection relationship of the transistors will be described in detail below.

The array substrate 100 provided by the embodiment of the present application includes pixels 200 arranged in an array, the pixels 200 include a pixel circuit and a light emitting element OL, a first electrode of the light emitting element OL is electrically connected to a first power line VDD1, a second electrode of the light emitting element OL is electrically connected to a third power line VSS, the pixel circuit is coupled between the first power line VDD1 and the first electrode of the light emitting element OL, and the pixel circuit includes a driving transistor T1, a data writing transistor T2, a storage capacitor Cst, a compensation transistor T3, a reset transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, and a reset transistor T7.

A gate T1G of the driving transistor T1 is electrically connected to the first node a, a source T1S of the driving transistor T1 is electrically connected to the second node B, and a drain T1D of the driving transistor T1 is electrically connected to the third node C;

the gate T2G of the Data writing transistor T2 is electrically connected to the third scan line sn (d), the source T2S of the Data writing transistor T2 is electrically connected to the Data line Data, and the drain T2D of the Data writing transistor T2 is electrically connected to the second node B;

the storage capacitor Cst includes the first capacitor electrode C11 and the second capacitor electrode C12, the second capacitor electrode C12 is electrically connected to the first power line VDD1, and the first capacitor electrode C11 is electrically connected to the first node a;

a reset transistor T4, a gate T4G of the reset transistor T4 being electrically connected to a first scan line Sn, a source T4S of the reset transistor T4 being electrically connected to the first node a, a drain T4D of the reset transistor T4 being electrically connected to a reset signal source VI, the first scan line Sn including a first main scan line Sn (11) and a first sub scan line Sn (12);

the compensation transistor T3, the gate T3G of the compensation transistor T3 is electrically connected to the second scan line Sn (vt), the source T3S of the compensation transistor T3 is electrically connected to the third node C, the drain T3D of the compensation transistor T3 is electrically connected to the first node a, the second scan line Sn (vt) includes a second main scan line Sn (vt1) and a second sub scan line Sn (vt2), the second main scan line Sn (vt1) and the second sub scan line Sn (vt2) are electrically connected within the pixel 200 or outside the pixel 200, and the second main scan line Sn (vt1) and the second sub scan line Sn (vt2) are electrically connected outside the pixel 200, which may be electrically connected in the non-display region of the array substrate 100;

a reset transistor T7, a gate T7G of the reset transistor T7 is electrically connected to the fourth scan line sn (x), a source T7S of the reset transistor T7 is electrically connected to a reset signal source VI, a drain T7D of the reset transistor T7 is electrically connected to a first electrode of the light emitting element OL, the first electrode of the light emitting element OL may be an anode of the light emitting element, a second electrode of the light emitting element OL may be a cathode, and the reset signal source VI may include one or both of a first reset signal source VI1 and a second reset signal source VI 2;

a first light emission control transistor T5, a gate T5G of the first light emission control transistor T5 being electrically connected to the light emission control signal line EM, a source T5S of the first light emission control transistor T5 being electrically connected to the first power supply line VDD1, a drain T5D of the first light emission control transistor T5 being electrically connected to the second node B;

a second light emission controlling transistor T6, a gate T6G of the second light emission controlling transistor T6 is electrically connected to the light emission controlling signal line EM, a source T6S of the second light emission controlling transistor T6 is electrically connected to the third node C, and a drain T6D of the second light emission controlling transistor T6 is electrically connected to the first electrode of the light emitting element OL.

The second electrode of the light emitting element OL is electrically connected to the third power source VSS.

With reference to fig. 1, fig. 2, and fig. 3, the following further describes the operation process of the pixel 200 according to the above embodiment.

In the reset stage T1, the signal of the first scan line Sn and the signal of the third scan line Sn (d) are at a high potential, the signals of the second scan line Sn (vt), the fourth scan line Sn (x), and the light emission control signal line EM are at a low potential, the driving transistor T1, the data writing transistor T2, the compensating transistor T3, the reset transistor T7, the first light emission control transistor T5, and the second light emission control transistor T6 are turned off, the reset transistor T4, and the reset transistor T7 are turned on, and the reset signal source VI supplies the first node a and the first electrode of the light emitting element OL with a reset signal.

In the Data writing stage T2, the signal of the first scan line Sn, the signal of the third scan line Sn (d), and the signal of the emission control signal line EM are at low potential, the signal of the second scan line Sn (vt) and the signal of the fourth scan line Sn (x) are at high potential, the compensation transistor T3 is turned on, the gate T1G and the drain T1D of the driving transistor T1 are turned on, a voltage difference is generated between the gate T1G and the source T1S of the driving transistor T1 by the threshold voltage of the driving transistor T1, at this time, the driving transistor T1 is turned on, the Data writing transistor T2 is turned on, the Data signal of the Data line Data is input to the second node B, the Data signal of the Data line Data includes the compensated threshold voltage, and is input to the gate T1G of the driving transistor T1, thereby compensating the threshold voltage deviation of the driving transistor T1. The written Data signal of the Data line Data charges the first node a through the driving transistor T1 until the voltage of the first node a becomes Vdata-Vth, and the driving transistor T1 is turned off.

In the light emitting period T3, the signal of the first scan line Sn and the signal of the second scan line Sn (vt) are at a low potential, the signal of the third scan line Sn (d) and the signal of the fourth scan line Sn (x) are at a high potential, the signal of the light emission control signal line EM is at a high potential, the data writing transistor T2, the compensating transistor T3, the reset transistor T4, and the reset transistor T7 are turned off, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, the driving transistor T1 is kept in an on state, the signal of the first power supply VDD flows to the light emitting element OL, and the light emitting element OL emits light.

The structure and connection relationship of the above embodiments are further described below.

Fig. 1, fig. 2, and fig. 4 are combined below. The array substrate 100 includes a first Via1, a second Via2, a third Via3, a fourth Via4, and a fifth Via 5. The second metal layer 17 is connected with the fourth metal layer 23 through a first Via hole Via1, the fourth metal layer 23 is connected with the first semiconductor layer 13 through a second Via hole Via2, the fourth metal layer 23 is connected with the second semiconductor layer 19 through a third Via hole Via3, the fourth metal layer 23 is connected with the first metal layer 15 through a fourth Via hole Via4, and the fifth metal layer 25 is connected with the fourth metal layer 23 through a fifth Via hole Via 5. The first connection electrode 201, the second connection electrode 202, the third connection electrode 203 and the fourth connection electrode 204 are connected to corresponding traces or electrodes of other layers through corresponding via holes.

In the embodiment of the present application, the compensation transistor T3 and the reset transistor T4 electrically connected to the second capacitor Cst12 use an oxide transistor, which has a small leakage current and can improve the instability of the potential difference between the gate and the source of the driving transistor T1, thereby preventing the flicker phenomenon of the display panel, further, the compensation transistor T3 and the reset transistor T4 both use a dual-gate structure, the compensation transistor T3 includes a bottom gate T3G1 and a top gate T3G2, the reset transistor T4 includes a bottom gate T4G1 and a top gate T4G2, the dual-gate structure can better turn off the compensation transistor T3 and the reset transistor T4, the leakage currents of the compensation transistor T3 and the reset transistor T4 are minimized to make the gate and source potential differences of the driving transistor T1 reach the most stable state, thereby preventing the flicker phenomenon of the display panel.

Example II,

The embodiment of the present application further provides a display panel, which includes the array substrate 100 as described in any of the above embodiments, the array substrate 100 further includes a pixel definition layer 28, a light emitting element OL is disposed in an opening of the pixel definition layer 28, and the display panel further includes an encapsulation layer disposed on the light emitting element OL.

The array substrate and the display panel provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein by applying specific examples, and the description of the embodiments is only used to help understand the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.