阅读说明：本技术 晶体管及其制造方法 (Transistor and method of manufacturing the same ) 是由 廖宏魁 刘振强 施咏尧 于 2020-06-04 设计创作，主要内容包括：本发明公开一种晶体管及其制造方法。所述晶体管包括基底、集极、基极、射极以及扩散障碍层。所述集极设置于所述基底上。所述基极设置于所述集极上。所述射极设置于所述基极上。所述扩散障碍层设置于所述基极与所述射极之间。所述基极的上部包括掺杂层,且所述扩散障碍层设置于所述掺杂层上。所述射极、所述掺杂层与所述集极为第一导电型,且所述基极的其余部分为第二导电型。(The invention discloses a transistor and a manufacturing method thereof. The transistor includes a substrate, a collector, a base, an emitter, and a diffusion barrier layer. The collector is disposed on the substrate. The base electrode is arranged on the collector. The emitter is disposed on the base. The diffusion barrier layer is disposed between the base and the emitter. The upper portion of the base electrode includes a doped layer, and the diffusion barrier layer is disposed on the doped layer. The emitter, the doped layer and the collector are of a first conductivity type, and the remainder of the base is of a second conductivity type.)

1. A transistor, comprising:

a substrate;

a collector disposed on the substrate;

a base electrode disposed on the collector;

an emitter disposed on the base; and

a diffusion barrier layer disposed between the base and the emitter;

wherein the upper portion of the base electrode includes a doped layer, the diffusion barrier layer is disposed on the doped layer, and

wherein the emitter, the doped layer and the collector are of a first conductivity type and the remainder of the base is of a second conductivity type.

2. The transistor of claim 1, wherein the diffusion barrier layer comprises a silicon nitride layer.

3. The transistor of claim 1, wherein the diffusion barrier layer has a thickness betweenToIn the meantime.

4. The transistor of claim 1, wherein the base comprises:

a silicon germanium layer disposed on the collector; and

a doped silicon germanium carbide layer disposed on the silicon germanium layer; and

the doped layer is arranged on the doped silicon germanium carbide layer.

5. The transistor of claim 4, wherein the doped layer is a doped polysilicon layer.

6. A method of manufacturing a transistor, comprising:

forming a collector on a substrate;

forming a base electrode on the collector electrode;

forming a diffusion barrier layer on the base; and

forming a doped emitter on the diffusion barrier, wherein dopants in the doped emitter pass through the diffusion barrier into an upper portion of the base to form the upper portion of the base as a doped layer,

wherein the doped emitter, the doped layer and the collector are of a first conductivity type and the base is of a second conductivity type.

7. The method of manufacturing a transistor according to claim 6, wherein the diffusion barrier layer comprises a silicon nitride layer.

8. The method of claim 6, wherein the thickness of the diffusion barrier layer is betweenToIn the meantime.

9. The method of manufacturing a transistor as claimed in claim 6, wherein the method of forming the base comprises:

forming a silicon germanium layer on the collector;

forming a doped silicon germanium carbide layer on the silicon germanium layer; and

forming an undoped layer on the doped silicon germanium carbide layer,

wherein the upper portion of the base is the undoped layer.

10. The method of manufacturing a transistor according to claim 9, wherein the undoped layer comprises an undoped polysilicon layer.

Technical Field

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a transistor and a method of manufacturing the same.

Background

A Heterojunction Bipolar Transistor (HBT) is a bipolar transistor in which an emitter (emitter) and a base (base) each comprise different semiconductor materials to form a heterojunction, i.e., a PN junction. Compared with a general bipolar transistor, the heterojunction bipolar transistor has better high-frequency signal characteristics and base emission efficiency, and thus can be widely applied to work under signals of hundreds of GHz.

Generally, in the fabrication of a heterojunction bipolar transistor, after the base is formed, emitters having different conductivity types are formed on the base. Since the emitter is usually formed by in-situ doping, the dopant in the emitter diffuses into the upper portion of the base. In addition, after the emitter is formed, the subsequent thermal process also causes the dopants in the emitter to diffuse into the upper portion of the base. To avoid further diffusion of these dopants through the base, a base having a greater thickness is typically formed. As a result, the resistance of the base is increased, and the cutoff frequency (cutoff frequency) of the heterojunction bipolar transistor is reduced, so that the device performance is reduced.

Disclosure of Invention

The invention provides a transistor, wherein a diffusion barrier layer is arranged between a base electrode and an emitter electrode.

The invention provides a method for manufacturing a transistor, which forms a diffusion barrier layer between a base and an emitter.

The transistor of the present invention includes a substrate, a collector (collector), a base (base), an emitter (emitter), and a diffusion barrier layer. The collector is disposed on the substrate. The base electrode is arranged on the collector. The emitter is disposed on the base. The diffusion barrier layer is disposed between the base and the emitter. The upper portion of the base electrode includes a doped layer, and the diffusion barrier layer is disposed on the doped layer. The emitter, the doped layer and the collector are of a first conductivity type, and the remainder of the base is of a second conductivity type.

In an embodiment of the transistor of the present invention, the diffusion barrier layer includes a silicon nitride layer.

In an embodiment of the transistor of the present invention, the thickness of the diffusion barrier layer is betweenTo In the meantime.

In an embodiment of the transistor of the present invention, the base comprises a silicon germanium layer, a doped silicon germanium carbide layer and the doped layer. The silicon germanium layer is arranged on the collector. The doped silicon germanium carbide layer is disposed on the silicon germanium layer. The doped layer is disposed on the doped silicon germanium carbide layer.

In an embodiment of the transistor of the present invention, the doped layer is a doped polysilicon layer.

The method for manufacturing a transistor of the present invention includes the following steps. First, a collector is formed on a substrate. Then, a base is formed on the collector. Then, a diffusion barrier layer is formed on the base. Thereafter, a doped emitter is formed on the diffusion barrier layer, wherein dopants in the doped emitter pass through the diffusion barrier layer into an upper portion of the base to form the upper portion of the base as a doped layer. The doped emitter, the doped layer, and the collector are of a first conductivity type, and the base is of a second conductivity type.

In an embodiment of the method for manufacturing a transistor of the present invention, the diffusion barrier layer includes a silicon nitride layer.

In an embodiment of the method for manufacturing a transistor of the present invention, the thickness of the diffusion barrier layer is between that of the first diffusion barrier layer and that of the second diffusion barrier layerToIn the meantime.

In an embodiment of the method for manufacturing a transistor of the present invention, the method for forming the base includes the following steps. First, a silicon germanium layer is formed on the collector. Next, a doped silicon germanium carbide layer is formed on the silicon germanium layer. Thereafter, an undoped layer is formed on the doped silicon germanium carbide layer. The upper portion of the base is the undoped layer.

In an embodiment of the method for manufacturing a transistor of the present invention, the undoped layer includes an undoped polysilicon layer.

Based on the above, in the present invention, the diffusion barrier layer is disposed between the base and the emitter and has the characteristic of reducing the depth of the dopant in the emitter reaching the underlying film, so the thickness of the base can be effectively reduced and the time for forming the base can be effectively shortened.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A to fig. 1C are schematic cross-sectional views illustrating a manufacturing process of a transistor according to a first embodiment of the present invention;

fig. 2A to fig. 2C are schematic cross-sectional views illustrating a manufacturing process of a transistor according to a second embodiment of the invention.

Description of the symbols

10. 20 transistor

100 base

102 collector layer

104 base layer

104a, 206a doped layer

106 diffusion barrier layer

108 emitter layer

202 silicon germanium layer

204 doped silicon germanium carbide layer

206 undoped layer

Detailed Description

The following examples are set forth in detail in conjunction with the accompanying drawings, but are not provided to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, like elements will be described with like reference numerals in the following description.

All terms used herein, including, having, etc., are open-ended terms, i.e., mean "including, but not limited to.

Furthermore, the directional terms used herein, such as "above" and "below", are used with reference to the drawings, and are not intended to limit the present invention.

Fig. 1A to fig. 1C are schematic cross-sectional views illustrating a manufacturing process of a transistor according to a first embodiment of the invention. In the present embodiment, the first conductive type is N-type, and the second conductive type is P-type, but the invention is not limited thereto. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. In addition, in the present embodiment, the transistor formed is a heterojunction bipolar transistor which mainly includes a collector, a base, an emitter, and a diffusion barrier layer, which will be described in detail below.

First, referring to fig. 1A, a substrate 100 is provided. The substrate 100 is, for example, a silicon substrate. In the present embodiment, the substrate 100 may be a silicon substrate of a second conductivity type (P-type). Next, a collector layer 102 is formed on the substrate 100. The collector layer 102 is used to form a collector of the transistor of this embodiment. In this embodiment, the collector is of the first conductivity type (N-type), for example. In the present embodiment, the collector layer 102 is, for example, a silicon layer, and is formed by, for example, performing an epitaxial growth process and simultaneously doping the first conductive type dopant during the formation process. Thereafter, a base layer 104 is formed on the collector layer 102. The base layer 104 is used to form the base of the transistor of this embodiment. In this embodiment, the base is of the second conductivity type (P-type), for example. In the present embodiment, the base layer 104 is, for example, a silicon germanium layer, and the formation method thereof is, for example, a chemical vapor deposition process, and the second conductive type dopant is simultaneously doped during the formation process.

Next, referring to fig. 1B, a diffusion barrier layer 106 is formed on the base layer 104. In the present embodiment, the diffusion barrier layer 106 is, for example, a silicon nitride layer, and the forming method thereof is, for example, a chemical vapor deposition process. The diffusion barrier layer 106 has the property of reducing the depth of dopants (e.g., dopants in a layer subsequently formed on the diffusion barrier layer 106) that pass through the diffusion barrier layer 106 into an underlying layer. On the upper partThe term "reducing the depth of dopant penetration into the underlying layer" refers to a reduction in the depth of dopant penetration into the underlying layer as compared to the case without the diffusion barrier 106. In the present embodiment, the diffusion barrier layer 106 has a thickness, for example, in the range betweenToPreferably betweenToIn the meantime. When the thickness of the diffusion barrier layer 106 exceedsOnly a very small amount of dopant is allowed to pass through, and even no dopant is allowed to pass through. When the thickness of the diffusion barrier layer 106 is less thanThe depth of the dopant reaching the underlying film layer cannot be effectively reduced.

Thereafter, referring to fig. 1C, an emitter layer 108 is formed on the diffusion barrier layer 106 to complete the fabrication of the transistor 10 of the present embodiment. The emitter layer 108 is used to form the emitter of the transistor of this embodiment. In this embodiment, the emitter is of the first conductivity type (N-type), for example. Generally, the emitter layer 108 is a highly doped film, i.e., the doping concentration is usually higher than the doping concentration of the collector layer 102 and the base layer 104. In the present embodiment, the emitter layer 108 is formed by, for example, performing a cvd process, and the first conductive type dopant is doped during the formation process.

During the formation of the emitter layer 108, the dopants in the emitter layer 108 diffuse outward into the underlying base layer 104. In addition, after the transistor 10 is formed, the dopants in the emitter layer 108 are also diffused outward into the underlying base layer 104 in a subsequent thermal process. In the present embodiment, since the diffusion barrier layer 106 is formed on the base layer 104 and the diffusion barrier layer 106 has a characteristic of reducing the depth of the dopant reaching the base layer 104, the dopant in the emitter layer 108 can be diffused only into the upper portion of the base layer 104. At this time, the conductivity type of the upper portion of the base layer 104 is changed from the second conductivity type (P-type) to the first conductivity type (N-type) to form the doped layer 104 a.

In the present embodiment, the diffusion barrier layer 106 can prevent the base layer 104 from being entirely converted into the first conductive type (N-type) due to the dopant in the emitter layer 108. On the other hand, since the diffusion barrier 106 allows the dopants in the emitter layer 108 to enter only the upper portion of the base layer 104, the base layer 104 may not be formed with a larger thickness, i.e., the thickness of the base layer 104 may be reduced compared to the case without the diffusion barrier 106. Thus, the overall thickness of the transistor 10 of the present embodiment can be effectively reduced, and the time for forming the base layer 104 can be effectively shortened.

In the transistor 10 of the present embodiment, the base is a single film layer (base layer 104), but the invention is not limited thereto. In other embodiments, the base electrode may have a composite structure formed by multiple layers.

Fig. 2A to 2C are schematic cross-sectional views illustrating a manufacturing process of a transistor according to a second embodiment of the invention. In the present embodiment, the same elements as those of the first embodiment will be denoted by the same reference numerals, and a description thereof will not be given.

First, referring to fig. 2A, a substrate 100 is provided. In the present embodiment, the substrate 100 is, for example, of a second conductivity type (P-type). Next, the collector layer 102 is formed on the substrate 100. The collector layer 102 is used to form a collector of the transistor of this embodiment. In this embodiment, the collector is of the first conductivity type (N-type), for example. A silicon germanium layer 202 is then formed on the collector layer 102. In the present embodiment, the sige layer 202 is formed by, for example, performing a cvd process. Next, a doped silicon germanium carbide layer 204 is formed on the silicon germanium layer 202. In the present embodiment, the doped silicon germanium carbide layer 204 is, for example, of the second conductivity type (P-type). In the present embodiment, the doped silicon germanium carbide layer 204 is formed by, for example, performing a cvd process and doping the second conductivity type dopant simultaneously during the formation process. Thereafter, an undoped layer 206 is formed on the doped silicon germanium carbide layer 204. Undoped layer 206 is, for example, an undoped polysilicon layer. In the present embodiment, the undoped layer 206 is formed by, for example, a chemical vapor deposition process. In the present embodiment, the sige layer 202, the doped sige carbide layer 204 and the undoped layer 206 are used to form the base of the transistor of the present embodiment.

Next, referring to fig. 2B, the diffusion barrier layer 106 is formed on the undoped layer 206. In the present embodiment, the diffusion barrier layer 106 is, for example, a silicon nitride layer, and the formation method thereof is, for example, a chemical vapor deposition process. The diffusion barrier 106 has the property of reducing the depth of dopants that pass through the diffusion barrier 106 into underlying layers. In the present embodiment, the diffusion barrier layer 106 has a thickness, for example, in the range betweenToPreferably betweenToIn the meantime. When the thickness of the diffusion barrier layer 106 exceeds Only a very small amount of dopant is allowed to pass through, and even no dopant is allowed to pass through. When the thickness of the diffusion barrier layer 106 is less thanThe depth of the dopant reaching the underlying film layer cannot be effectively reduced.

Thereafter, referring to fig. 2C, an emitter layer 108 is formed on the diffusion barrier layer 106 to complete the fabrication of the transistor 20 of the present embodiment. The emitter layer 108 is used to form the emitter of the transistor of this embodiment. In this embodiment, the emitter is of the first conductivity type (N-type), for example. Generally, the emitter layer 108 is a heavily doped layer, i.e., the dopant concentration is generally higher than the dopant concentration of the collector layer 102 and the base (doped silicon germanium carbide layer 204). In the present embodiment, the emitter layer 108 is formed by, for example, a cvd process, and the first conductive type dopant is doped during the formation process.

During the formation of the emitter layer 108, the dopants in the emitter layer 108 diffuse outward into the undoped layer 206 below. In addition, after the transistor 10 is formed, the dopants in the emitter layer 108 may diffuse outward into the undoped layer 206 in the subsequent thermal process. In this embodiment. Since the diffusion barrier layer 106 is formed on the undoped layer 206 and the diffusion barrier layer 106 has a characteristic of reducing the depth of the dopant reaching the underlying film layer, the dopant in the emitter layer 108 can be diffused only into the undoped layer 206. At this time, the undoped layer 206 of the second conductivity type (P type) is converted into the doped layer 206a of the first conductivity type (N type).

In the present embodiment, since the diffusion barrier layer 106 allows the dopant in the emitter layer 108 to enter only the undoped layer 206, the undoped layer 206 can be completely converted into the doped layer 206a by controlling the formation thickness of the undoped layer 206. Furthermore, since the diffusion barrier layer 106 has the property of reducing the depth of the dopant reaching the underlying film layer, the undoped layer 206 with a larger thickness may not be required to be formed to prevent the dopant from penetrating through the undoped layer 206. As a result, the overall thickness of the transistor 20 of the present embodiment can be effectively reduced, and the time for forming the undoped layer 206 can be effectively shortened.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.