阅读说明：本技术 一种高电子迁移率晶体管的栅结构及其制备方法 (Gate structure of high electron mobility transistor and preparation method thereof ) 是由 张昇 魏珂 王鑫华 刘新宇 王万礼 张新玲 张俊芳 于 2021-08-03 设计创作，主要内容包括：一种高电子迁移率晶体管的栅结构,包括：栅极,设于高电子迁移率晶体管的源极和漏极之间,两个栅下凹槽,刻蚀形成于高电子迁移率晶体管的势垒层,栅极的栅脚设于两个栅下凹槽之间,其中,部分栅脚至少设于两个栅下凹槽其中一个中。本公开还提供了该栅结构的制备方法。本公开提供的一种高电子迁移率晶体管的栅结构,可以有效调节高电子迁移率晶体管内部的电场分布,以提高其工作电压,增大其输出功率,还可以通过调节栅极的位置,提高高电子迁移率晶体的栅控能力。(A gate structure of a high electron mobility transistor, comprising: the grid electrode is arranged between the source electrode and the drain electrode of the high electron mobility transistor, the two grid lower grooves are formed in the barrier layer of the high electron mobility transistor in an etching mode, the grid pin of the grid electrode is arranged between the two grid lower grooves, and part of the grid pin is arranged in at least one of the two grid lower grooves. The disclosure also provides a preparation method of the gate structure. The gate structure of the high electron mobility transistor provided by the disclosure can effectively adjust the electric field distribution inside the high electron mobility transistor to improve the working voltage thereof and increase the output power thereof, and can also improve the gate control capability of the high electron mobility transistor by adjusting the position of the gate.)

1. A gate structure of a high electron mobility transistor, comprising:

a gate electrode disposed between the source electrode and the drain electrode of the high electron mobility transistor;

two grooves under the grid, etch and form in the barrier layer of the said high electron mobility transistor;

the grid pin of the grid is arranged between the two grid lower grooves, wherein part of the grid pin is at least arranged in one of the two grid lower grooves.

2. The grid structure of claim 1, wherein the two grid grooves are symmetrically disposed on opposite sides of the grid, and the grid legs of the grid are disposed on opposite sides of the grid adjacent to the two grid grooves.

3. The gate structure of claim 1, wherein the gate leg of the gate electrode is disposed partially in one of the two gate recesses and partially on the barrier layer between the two gate recesses.

4. The grid structure of claim 1, wherein the etched edges of the two grid lower grooves have a curvature.

5. The grid structure of claim 1, wherein the grid is a T-shaped structure.

6. The gate structure of claim 1, wherein the depth of the two under-gate grooves is positively correlated to a positive shift in the preset turn-on voltage of the HEMT and negatively correlated to the output current capability of the HEMT.

7. The gate structure of claim 1, wherein the width of the two under-gate grooves is positively correlated to the size of the HEMT.

8. A method for preparing a gate structure of a high electron mobility transistor is characterized by comprising the following steps:

photoresist is homogenized on a wafer where the high electron mobility transistor is located, after two grid lower groove areas are developed through photoetching, a barrier layer of the high electron mobility transistor is etched, and the two grid lower grooves are formed;

and (5) glue homogenizing again, exposing to form a grid electrode area, and stripping the evaporated grid metal to form a grid electrode.

9. The method of claim 8, further comprising:

and when the two grid lower grooves are formed by photoetching, the edges of the two grid lower grooves are formed into a radian by a reflow technology.

10. The method of claim 8, after forming the two grating grooves, further comprising:

removing photoresist from the wafer where the high electron mobility transistor is located;

and cleaning the surface of the wafer where the high electron mobility transistor is positioned, and then carrying out high-temperature annealing to repair etching damage.

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a gate structure of a high electron mobility transistor and a method for manufacturing the same.

Background

The High Electron Mobility Transistor (HEMT) has the excellent characteristics of High output power density, High frequency and High voltage, High temperature resistance, radiation resistance and the like, is a core device for preparing a High-frequency and High-voltage power amplifier, and has a wide application field. The gate structure of the HEMT is a key structure of the device, and directly determines the performance of the HEMT device.

The conventional grid structure adopts a groove T-shaped grid structure, the source-drain distance and the grid length of an HEMT device are further shortened along with the further expansion of the application field of the HEMT, particularly along with the fact that the HEMT enters a millimeter wave band for application, the grid structure is very important for the off-state leakage current and the grid foot electric field distribution of the HEMT device, the grid structure of the HEMT device needs to be optimized, and the purpose of improving the device performance is achieved, for example, the grid control capability of the device is improved, the grid foot electric field intensity is reduced, and the like.

Disclosure of Invention

In view of the above problems, the present invention provides a gate structure of a high electron mobility transistor and a method for fabricating the same, so as to at least partially solve the above technical problems.

One aspect of the present disclosure provides a gate structure of a high electron mobility transistor, including: a gate electrode disposed between the source electrode and the drain electrode of the high electron mobility transistor; two grooves under the grid, etch and form in the barrier layer of the said high electron mobility transistor; the grid pin of the grid is arranged between the two grid lower grooves, wherein part of the grid pin is at least arranged in one of the two grid lower grooves.

Optionally, the two grid lower grooves are symmetrically arranged on two sides of the grid, and two adjacent sides of the two grid lower grooves are provided with grid legs of part of the grid.

Optionally, a part of the gate leg of the gate is disposed in one of the two gate lower grooves, and another part of the gate leg of the gate is disposed on the barrier layer between the two gate lower grooves.

Optionally, the etched edges of the two grooves under the grid have a radian.

Optionally, the grid is of a T-shaped structure.

Optionally, the depths of the two grooves under the gate are positively correlated with a positive drift of a preset turn-on voltage of the hemt, and negatively correlated with an output current capability of the hemt.

Optionally, the widths of the two grooves under the gate are positively correlated with the size of the hemt.

Another aspect of the present disclosure provides a method for manufacturing a gate structure of a high electron mobility transistor, including: photoresist is homogenized on the wafer where the high electron mobility transistor is located, two grid lower groove areas are formed through photoetching and development, and then the two grid lower grooves are formed through etching; homogenizing glue again, exposing to form a grid electrode area, and stripping evaporated grid metal to form a grid electrode; wherein, part of grid feet of the grid are at least arranged in one of the two grid lower grooves.

Optionally, the method further includes: and when the two grid lower grooves are formed by photoetching, the edges of the two grid lower grooves are formed into a radian by a reflow technology.

Optionally, after the two grid grooves are formed, the method further comprises: removing photoresist from the wafer where the high electron mobility transistor is located; and cleaning the surface of the wafer where the high electron mobility transistor is positioned, and then carrying out high-temperature annealing to repair etching damage.

The at least one technical scheme adopted in the embodiment of the disclosure can achieve the following beneficial effects:

the utility model provides a grid structure of HEMT and a preparation method thereof, which can effectively adjust the electric field distribution inside the device by optimizing the grid structure, thereby further improving the breakdown voltage of the device, namely improving the working voltage of the device and increasing the output power of the device; in addition, a double-gate structure can be obtained by adjusting the position of the gate, and the gate control capability of the device is improved.

Drawings

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

fig. 1 schematically illustrates a schematic diagram of a gate structure of a high electron mobility transistor provided in an embodiment of the present disclosure;

fig. 2 schematically illustrates a schematic diagram of a gate structure of another high electron mobility transistor provided by the embodiment of the present disclosure;

fig. 3 schematically shows a structural diagram of a conventional high electron mobility transistor;

fig. 4 schematically illustrates a structural diagram of a high electron mobility transistor provided by an embodiment of the present disclosure;

fig. 5 is a graph schematically illustrating a channel carrier concentration distribution comparison between a high electron mobility transistor provided by an embodiment of the present disclosure and a conventional high electron mobility transistor in a pinch-off state;

fig. 6 schematically shows a comparison graph of channel electric field distribution at high drain voltage for another hemt provided by the embodiments of the present disclosure and a conventional hemt.

Fig. 7 schematically illustrates a method for manufacturing a gate structure of a high electron mobility transistor according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.

Generally, the HEMT device is in a groove structure, which means that a semiconductor layer under a gate is subjected to shallow etching, a semiconductor region under non-gate metal is not etched, and the gate structure is shown in fig. 3.

The present disclosure provides a gate structure of a high electron mobility transistor, including: a gate electrode disposed between the source electrode and the drain electrode of the high electron mobility transistor; two grooves under the grid, etch and form the barrier layer in the high electron mobility transistor; the grid pin of the grid is arranged between the two grid lower grooves, wherein part of the grid pin is at least arranged in one of the two grid lower grooves. Compared with a traditional gate structure, the gate structure of the high-electron-mobility transistor provided by the disclosure has stronger control capability on channel electrons, increases output current, and can disperse an electric field structure to enhance breakdown voltage.

Fig. 1 and 2 schematically illustrate two gate structures of high electron mobility transistors provided by the embodiments of the present disclosure.

In the embodiment of the present disclosure, the gate has a T-shaped structure.

As shown in fig. 1, in the gate structure of a high electron mobility transistor provided in the embodiment of the present disclosure, two gate lower grooves are symmetrically disposed on two sides of a gate, and two adjacent sides of the two gate lower grooves are both provided with gate legs of a portion of the gate. The structure is similar to a double-gate structure, and is favorable for enhancing the gate control capability of the high-electron-mobility transistor.

As shown in fig. 2, in another gate structure of a hemt according to an embodiment of the present disclosure, a gate pin of a gate electrode is partially disposed in one of two grooves under the gate, and another portion is disposed on a barrier layer between the two grooves under the gate. In the structure, the grid pin part in the groove plays the role of a field plate, the distribution of an electric field in a device can be adjusted, the electric field intensity is inhibited, and the breakdown voltage of the high electron mobility transistor is improved.

Optionally, in the gate structure of the hemt provided in the embodiment of the present disclosure, an etched edge of the groove under the gate may be a vertical right angle, or may have a radian. Preferably, the etched edges of the two grid lower grooves have radians, so that the electric field steep increase caused by sharp right angles can be avoided, the electric field distribution can be favorably dispersed, and the breakdown voltage of the device can be enhanced.

Optionally, in the gate structure of the high electron mobility transistor provided in the embodiment of the present disclosure, the etching depths of the two grooves may be the same or different, and the etching widths may also be the same or different, and may be adjusted according to actual requirements. Specifically, the depths of the two grid lower grooves are positively correlated with the positive drift of the preset starting voltage of the high electron mobility transistor, and are negatively correlated with the output current of the high electron mobility transistor, so that the depths of the two grid lower grooves can be respectively set according to the actual requirements on the starting voltage and the output current. The width of the two grooves under the gate is positively correlated with the size of the hemt, and generally, the wider the width of the grooves under the gate is, the wider the width is, the width can be adjusted according to the requirement of the accuracy of the controllability of the gate to the channel carrier.

Fig. 3 schematically shows a structural diagram of a conventional high electron mobility transistor.

As shown in fig. 3, the structure of the high electron mobility transistor includes, from bottom to top, a substrate 1, a nucleation layer 2, a first semiconductor layer 3, an insertion layer 4, a second semiconductor layer 5, a cap layer 6, and further includes a gate 9, a source 7, and a drain 8, where the gate 9, the source 7, and the drain 8 are located above the cap layer 6, and the gate is located above the gate 9, the source 7, and the drain 89 is located between the source 7 and the drain 8. Wherein, the substrate 1 is SiC, which can also be monocrystalline silicon or gallium nitride or sapphire; the nucleation layer 2 is an A1N layer with the thickness of 2nm and is used for improving the nucleation quality of the first semiconductor layer 3; the first semiconductor layer 3 is a GaN layer with the thickness of 2.5 μm; the insertion layer 4 is an AlN layer with the thickness of 1nm, and is used for improving the threshold limiting capability of a high-density two-dimensional electron gas (2-DEG); the second semiconductor layer 5 (i.e., the barrier layer) is A1GaN with a thickness of 20nm, the band gap width of the material of the second semiconductor layer 5 is larger than that of the first semiconductor layer 3, and it forms a heterojunction with the first semiconductor layer 3; the cap layer 6 is a GaN layer with a thickness of 1-2nm, and is used for protecting the interface of the second semiconductor layer 5; the source electrode 7 and the drain electrode 8 are formed by a titanium layer, an aluminum layer, a nickel layer and a gold layer through high-temperature alloy, and the grid electrode 9 is formed by overlapping the nickel layer and the gold layer. The device structure of multiple periods can pass through N₂And injecting to form isolation between the devices, so that the devices are not influenced with each other.

In a conventional hemt, a gate structure includes a gate and a gate recess, and a gate leg of the gate is disposed in the recess.

Fig. 4 schematically illustrates a structural diagram of a high electron mobility transistor provided in an embodiment of the present disclosure.

Fig. 4 is a schematic diagram of a specific structure of the hemt shown in fig. 1, and as shown in fig. 4, two gate lower grooves are symmetrically disposed on two sides of a gate pin of a gate, and a portion of gate metal is disposed in each of the two gate lower grooves, thereby forming a dual-gate structure. The grooves under the gate are etched in the second semiconductor layer (i.e., in the barrier layer). Compared with the traditional high electron mobility transistor, the added gate lower groove has the advantages that the position of the gate is adjusted, a double-gate structure is formed, the gate control capability of the high electron mobility transistor is enhanced, the output current of a device is increased, and due to the existence of the gate pin groove, the electric field distribution is dispersed, and the breakdown voltage is enhanced.

In the embodiment of the present disclosure, the distance between the source 7 and the drain 8 is 2.4 μm, the distance between the source 7 and the gate 9 is 0.8 μm, and the distance between the gate 9 and the drain 8 is 1.4 μm; the gate 9 has a vertical width of 0.2 μm, a height of 450nm and a horizontal width of 0.6 μm, and is T-shaped.

Fig. 5 is a graph showing a comparison of channel carrier concentration distributions in a pinch-off state between the high electron mobility transistor shown in fig. 1 and a conventional high electron mobility transistor.

As shown in fig. 5, in the high electron mobility transistor shown in fig. 1, when the device is in an off state, the carrier concentration in the channel is reduced, and the device leakage current is reduced, i.e., the gate controllability is stronger, as compared to the conventional high electron mobility transistor.

Fig. 6 schematically shows a comparison of channel electric field distribution at high drain voltage for the hemt shown in fig. 2 and a conventional hemt.

As shown in fig. 6, the peak value of the gate leg electric field of the conventional hemt is 3.5MV/mm, and the peak value of the gate leg electric field of the hemt shown in fig. 2 is 3.28MV/mm, which indicates that the hemt shown in fig. 2 reduces the electric field strength, i.e., increases the operating voltage of the device and increases the output power thereof, compared with the conventional hemt.

Fig. 7 schematically illustrates a method for manufacturing a gate structure of a high electron mobility transistor according to an embodiment of the present disclosure.

As shown in fig. 7, a method for fabricating a gate structure of a high electron mobility transistor according to an embodiment of the present disclosure includes steps S1 to S2.

And S1, photoresist is coated on the wafer where the high electron mobility transistor is located, after the two groove areas under the grid are developed through photoetching, the barrier layer of the high electron mobility transistor is etched, and the two grooves under the grid are formed.

In the disclosed embodiment, when the two grating lower grooves are formed by photoetching, the edges of the two grating lower grooves are formed into a radian by a reflow technology. The etched edges of the two grid lower grooves have radians, so that the electric field steep increase caused by sharp right angles can be avoided, the electric field distribution can be favorably dispersed, and the breakdown voltage of the device can be enhanced.

After forming the two grid lower grooves, S1 further includes steps S101 to S102.

S101, removing photoresist of the wafer where the high electron mobility transistor is located.

S102, cleaning the surface of the wafer where the high electron mobility transistor is located, and then carrying out high-temperature annealing to repair etching damage.

And S2, coating glue again, exposing to form a gate region, and stripping the evaporated gate metal to form a gate.

Wherein, part of grid feet of the grid electrode are at least arranged in one of the two grid lower grooves. Referring to fig. 1, when the gate legs are disposed between two gate lower grooves, so that the two gate lower grooves are symmetrically disposed on two sides of the gate, and two adjacent sides of the two gate lower grooves are both provided with a portion of the gate legs of the gate, a structure similar to a dual gate is obtained, and the gate control capability of the high electron mobility transistor can be improved. Referring to fig. 2, when a portion of the gate pin of the gate electrode is disposed in one of the two gate grooves and another portion of the gate pin is disposed on the barrier layer between the two gate grooves, the gate structure can effectively adjust the distribution of the electric field inside the device, thereby increasing the breakdown voltage of the hemt, i.e., increasing the operating voltage of the hemt and increasing the output power of the hemt.

Those skilled in the art will appreciate that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not expressly recited in the present disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teaching of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.

While the disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments, but should be defined not only by the appended claims, but also by equivalents thereof.