阅读说明：本技术 用于非对称双向以太网物理层的预编码 (Precoding for asymmetric bidirectional Ethernet physical layer ) 是由 戴绍安 吴兴 M·奥伯格 于 2020-08-27 设计创作，主要内容包括：一种以太网物理层(PHY)收发器(20,24)包括发射器(32,40)和接收器(36,44)。发射器被配置为通过将第一数据流的两个或更多个相互延迟的副本相加来对第一数据流进行预编码,并且在全双工有线信道(28)上向对等以太网PHY收发器发射经预编码的第一数据流。接收器被配置为在全双工有线信道上从对等以太网PHY收发器接收第二数据流,并且在发射器并发地发射经预编码的第一数据流的同时对接收到的第二数据流进行解码。(An ethernet physical layer (PHY) transceiver (20, 24) includes a transmitter (32, 40) and a receiver (36, 44). The transmitter is configured to precode the first data stream by adding two or more mutually delayed replicas of the first data stream, and transmit the precoded first data stream to the peer ethernet PHY transceiver over a full duplex wired channel (28). The receiver is configured to receive a second data stream from the peer-to-peer ethernet PHY transceiver over a full-duplex wired channel and decode the received second data stream while the transmitter concurrently transmits the precoded first data stream.)

1. An ethernet physical layer (PHY) transceiver comprising:

a transmitter configured to precode a first data stream by adding two or more mutually delayed replicas of the first data stream and transmit the precoded first data stream to a peer ethernet PHY transceiver over a full duplex wired channel; and

a receiver configured to receive a second data stream from the peer-to-peer Ethernet PHY transceiver over the full-duplex wired channel and decode the received second data stream while the transmitter concurrently transmits the precoded first data stream.

2. The ethernet PHY transceiver of claim 1, wherein the transmitter is configured to precode the first data stream by:

(i) delaying said first data stream to produce a delayed copy, an

(ii) Adding the first data stream and the delayed copy.

3. The ethernet PHY transceiver of claim 1, wherein the transmitter is configured to precode the first data stream by:

(i) delaying said first data stream to produce a delayed copy, an

(ii) Subtracting the delayed copy from the first data stream, or subtracting the first data stream from the delayed copy.

4. An Ethernet PHY transceiver according to any of claims 1 to 3, wherein the transmitter is configured to transmit the first data stream at a first data rate, and wherein the receiver is configured to receive the second data stream at a second data rate higher than the first data rate.

5. An Ethernet PHY transceiver according to any of claims 1 to 3, wherein the receiver is configured to receive the precoded second data stream and to decode the precoded second data stream without concurrently cancelling echoes of the first data stream.

6. An Ethernet PHY transceiver according to any of claims 1 to 3, wherein the transmitter and the receiver are configured to transmit the first data stream and the second data stream between electronic units in a vehicle.

7. An ethernet physical layer (PHY) transceiver comprising:

a receiver configured to:

receiving a first data stream from a peer-to-peer Ethernet (PHY) transceiver over a full duplex wired channel, wherein the first data stream is precoded using a precoding scheme that adds two or more mutually delayed copies of the first data stream; and

decoding the received first data stream, the decoding comprising applying a decoding scheme to the first data stream that reverses the precoding scheme; and

a transmitter configured to transmit a second data stream to the peer-to-peer Ethernet PHY transceiver over the full-duplex wired channel while the receiver concurrently receives and decodes the first data stream.

8. The Ethernet PHY transceiver of claim 7, wherein the receiver is configured to decode the first data stream by:

(i) delaying the first data stream by a delay element to produce a delayed copy,

(ii) feeding back the delayed replica from the output of the delay element to the input of the delay element, an

(iii) Subtracting the delayed copy from the first data stream, or subtracting the first data stream from the delayed copy.

9. The Ethernet PHY transceiver of claim 7, wherein the receiver is configured to decode the first data stream by:

(i) delaying the first data stream by a delay element to produce a delayed copy,

(ii) feeding back the delayed replica from the output of the delay element to the input of the delay element, an

(iii) Adding the delayed copy to the first data stream.

10. An ethernet PHY transceiver according to any one of claims 7 to 9 wherein the receiver is configured to receive the first data stream at a first data rate, and wherein the transmitter is configured to transmit the second data stream at a second data rate higher than the first data rate.

11. An ethernet PHY transceiver according to any one of claims 7 to 9, wherein the receiver is configured to: receiving the precoded first data stream without concurrently cancelling echoes of the second data stream, and decoding the precoded first data stream.

12. An ethernet PHY transceiver according to any one of claims 7 to 9 wherein the transmitter and the receiver are configured to communicate the first and second data streams between electronic units in a vehicle.

13. An ethernet physical layer (PHY) communication method, comprising:

precoding a first data stream by adding two or more mutually delayed copies of the first data stream and transmitting the precoded first data stream over a full-duplex wired channel; and

receiving a second data stream over the full-duplex channel, and decoding the received second data stream while the precoded first data stream is concurrently transmitted.

14. The ethernet PHY communication method of claim 13, wherein pre-encoding the first data stream comprises:

(i) delaying said first data stream to produce a delayed copy, an

(ii) Adding the first data stream and the delayed copy.

15. The ethernet PHY communication method of claim 13, wherein pre-encoding the first data stream comprises:

(i) delaying said first data stream to produce a delayed copy, an

(ii) Subtracting the delayed copy from the first data stream, or subtracting the first data stream from the delayed copy.

16. The ethernet PHY communication method of any of claims 13 to 15, wherein transmitting the first data stream comprises: transmitting the first data stream at a first data rate, and wherein receiving the second data stream comprises: receiving the second data stream at a second data rate that is higher than the first data rate.

17. The ethernet PHY communication method according to any of the claims 13 to 15, wherein receiving the precoded second data stream and decoding the precoded second data stream are performed without concurrently cancelling echoes of the first data stream.

18. An ethernet physical layer (PHY) communication method, comprising:

receiving a first data stream over a full-duplex wired channel, wherein the first data stream is precoded using a precoding scheme that adds two or more mutually delayed replicas of the first data stream;

decoding the received first data stream, the decoding comprising applying a decoding scheme to the first data stream that reverses the precoding scheme; and

transmitting a second data stream over the full-duplex channel while the first data stream is concurrently received and decoded.

19. The ethernet PHY communication method of claim 18, wherein decoding the first data stream comprises:

(i) delaying the first data stream by a delay element to produce a delayed copy,

(ii) feeding back the delayed replica from the output of the delay element to the input of the delay element, an

(iii) Subtracting the delayed copy from the first data stream, or subtracting the first data stream from the delayed copy.

20. The ethernet PHY communication method of claim 18, wherein decoding the first data stream comprises:

(i) delaying the first data stream by a delay element to produce a delayed copy,

(ii) feeding back the delayed replica from the output of the delay element to the input of the delay element, an

(iii) Adding the delayed copy to the first data stream.

21. An ethernet PHY communication method according to any one of claims 18 to 20, wherein receiving the first data stream comprises: receiving the first data stream at a first data rate, and wherein transmitting the second data stream comprises: transmitting the second data stream at a second data stream higher than the first data rate.

22. An ethernet PHY communication method according to any one of claims 18 to 20 wherein receiving the precoded first data stream and decoding the precoded first data stream are performed without concurrently cancelling echoes of the second data stream.

Technical Field

The present disclosure relates generally to network communications, and in particular to techniques for precoding and decoding in a physical layer (PHY) transceiver.

Background

Various applications (e.g., automotive on-board communication systems, certain industrial communication systems, and smart home systems) require communication at high data rates over relatively short distances. Several types of protocols and communication media have been proposed for this application. For example, ethernet communications over twisted pair copper wire media are specified in: IEEE802.3cg-2019 of IEEE802.3 cm in 2020, "IEEE Standard for Ethernet-interpretation 5: Physical Layer specificities and Management Parameters for 10Mb/s Operation and Associated Power Delivery over a Single blanched Pair of drivers"; IEEE802.3 bw-2015 of 2016, "IEEE Standard for Ethernet interpretation 1: Physical Layer specificities and Management Parameters for 100Mb/s Operation over a Single blannced Twisted Pair Cable (100 BASE-T1)"; IEEE802.3 bp-2016 "IEEE Standard for Ethernet interpretation 4: Physical Layer specificities and Management Parameters for 1Gb/s Operation over a Single Twisted-Pair mapper Cable" at 9 months of 2016; and IEEE802.3 ch-2020 of 6.2020, "IEEE Standard for Ethernet-amino 8: Physical Layer specificities and Management Parameters for 2.5Gb/s,5Gb/s, and 10Gb/s automatic electric Ethernet".

The above description is presented as a general overview of the relevant art in this field and should not be construed as an admission that any of the information it contains constitutes prior art to the present patent application.

Disclosure of Invention

Embodiments described herein provide an ethernet physical layer (PHY) transceiver including a transmitter and a receiver. The transmitter is configured to precode the first data stream by adding two or more mutually delayed replicas of the first data stream, and transmit the precoded first data stream to the peer ethernet PHY transceiver over a full duplex wired channel. The receiver is configured to receive a second data stream from the peer-to-peer ethernet PHY transceiver over a full-duplex wired channel and decode the received second data stream while the transmitter concurrently transmits the precoded first data stream.

In one embodiment, the transmitter is configured to precode the first data stream by: (i) delaying the first data stream to produce a delayed copy, and (ii) adding the first data stream and the delayed copy. In another embodiment, the transmitter is configured to precode the first data stream by: (i) delaying the first data stream to produce a delayed copy, and (ii) subtracting the delayed copy from the first data stream, or subtracting the first data stream from the delayed copy.

In a disclosed embodiment, the transmitter is configured to transmit a first data stream at a first data rate, and the receiver is configured to receive a second data stream at a second data rate higher than the first data rate. In an example embodiment, the receiver is configured to: the method further includes receiving a precoded second data stream and decoding the precoded second data stream without concurrently cancelling echoes of the first data stream. In one embodiment, the transmitter and receiver are configured to transmit a first data stream and a second data stream between electronic units in the vehicle.

There is additionally provided, in accordance with an embodiment described herein, an ethernet PHY transceiver including a receiver and a transmitter. The receiver is configured to receive a first data stream from the peer-to-peer ethernet PHY transceiver over a full-duplex wired channel, wherein the first data stream is precoded using a precoding scheme that adds two or more mutually delayed copies of the first data stream; and decoding the received first data stream, the decoding comprising applying a decoding scheme to the first data stream that reverses the precoding scheme. The transmitter is configured to transmit a second data stream to the peer-to-peer ethernet PHY transceiver over the full-duplex wired channel while the receiver concurrently receives and decodes the first data stream.

In one embodiment, the receiver is configured to decode the first data stream by: (i) delaying the first data stream by a delay element to produce a delayed replica, (ii) feeding back the delayed replica from the output of the delay element to the input of the delay element, and (iii) subtracting the delayed replica from the first data stream, or subtracting the first data stream from the delayed replica. In another embodiment, the receiver is configured to decode the first data stream by: (i) delaying the first data stream by a delay element to produce a delayed copy, (ii) feeding back the delayed copy from the output of the delay element to the input of the delay element, and (iii) adding the delayed copy and the first data stream.

In a disclosed embodiment, the receiver is configured to receive a first data stream at a first data rate, and the transmitter is configured to transmit a second data stream at a second data rate higher than the first data rate. In one embodiment, the receiver is configured to: the precoded first data stream is received and decoded without concurrently canceling the echoes of the second data stream. In an example embodiment, the transmitter and receiver are configured to transmit a first data stream and a second data stream between electronic units in the vehicle.

There is also provided, in accordance with an embodiment described herein, an ethernet PHY communication method, including precoding a first data stream by adding two or more mutually delayed copies of the first data stream, and transmitting the precoded first data stream over a full-duplex wired channel. The second data stream is received over a full-duplex channel and the received second data stream is decoded while the precoded first data stream is transmitted.

There is also provided, in accordance with an embodiment described herein, an ethernet PHY communication method, including receiving a first data stream over a full-duplex wired channel, wherein the first data stream is precoded using a precoding scheme that adds two or more mutually delayed replicas of the first data stream. Decoding the received first data stream, the decoding comprising applying a decoding scheme to the first data stream that reverses the precoding scheme. A second data stream is transmitted over the full-duplex channel while the first data stream is received and decoded.

The disclosure will be more fully understood from the following detailed description of embodiments thereof, taken together with the accompanying drawings, in which:

drawings

FIG. 1 is a block diagram that schematically illustrates an automotive communication system, in accordance with embodiments described herein;

fig. 2 is a block diagram that schematically illustrates a pair of asymmetric ethernet physical layer (PHY) transceivers communicating over a full-duplex bidirectional link, in accordance with an embodiment described herein;

fig. 3 is a flow diagram schematically illustrating a method for communication between the asymmetric ethernet PHY transceivers of fig. 2, according to an embodiment described herein; and

fig. 4 is a block diagram that schematically illustrates an asymmetric ethernet PHY transceiver, in accordance with an alternative embodiment described herein.

Detailed Description

Embodiments described herein provide improved ethernet physical layer (PHY) transceivers and related methods for communicating over full-duplex bidirectional links (e.g., twisted pair copper wire links). The embodiments described herein refer primarily to asymmetric links, where the transmission bit rate is different between the two directions of a bi-directional link.

The asymmetric PHY transceivers described herein are useful in, for example, automotive applications, such as systems that collect data from sensors within a vehicle and also control and configure the sensors. However, the disclosed techniques are generally applicable to various other applications involving asymmetric links, such as in industrial and/or smart home networks and video distribution systems. Certain aspects of bidirectional asymmetric ethernet communications in these environments are addressed in: U.S. patent application 16/419,643 entitled "Asymmetric Energy efficiency Ethernet"; and U.S. patent application 16/815,299 entitled "manufacturing Bidirectional Communication in connected Environments," which is assigned to the assignee of the present patent application and the disclosure of which is incorporated herein by reference.

Consider a pair of ethernet PHY transceivers that communicate with each other in full duplex over a single twisted pair link. One PHY transceiver transmits at a bit rate called "low speed" (LS) and receives at a bit rate called "high speed" (HS). Another PHY transceiver transmits at an LS bit rate and receives at an HS bit rate. In a typical example, the HS bit rate is 10 Gbits/sec (10Gbps) and the LS bit rate is 100Mbps or 10 Mbps.

In a full-duplex scenario, the signals transmitted by the two PHY transceivers are present on the twisted-pair link at the same time. Thus, the transmission of each signal may interfere with the reception of another signal. This effect is called "echo". In this context, echo refers to a signal that is transmitted from a transmitter of a PHY transceiver and interferes with a receiver of the same PHY transceiver. In a given PHY transceiver, echoes may propagate from transmitter to receiver on various paths due to various leakage or reflection mechanisms.

Echo cancellation techniques can in principle be used to reduce this interference, but echo cancellation is often complex and increases the cost, size and power consumption of PHY transceivers. Another possibility is to allocate a separate frequency band for each direction of the link with a suitable spectral separation between the frequency bands and with suitable filtering. This solution is both complex and expensive and also reduces the achievable data throughput.

Embodiments described herein eliminate the need for interference cancellation or dense filtering, but instead use transmitter-side precoding and receiver-side decoding to reduce interference. The term "precoding" denotes an arithmetic manipulation of the input data stream at the bit level prior to modulation. Typically, the pre-coding operation involves bit-by-bit addition of two or more mutually delayed copies of the input data stream. For example, in a precoding scheme denoted as "1 + D", the transmitter delays input data by one bit to generate a delayed copy, and adds the input data and the delayed copy. In another precoding scheme, denoted "1-D", the transmitter delays the input data by one bit to produce a delayed replica, and subtracts the delayed replica from the input data (or subtracts the input data from the delayed replica). As will be shown below, a properly selected precoding scheme has a spectral shaping effect similar to low-pass filtering or high-pass filtering, and may therefore be effective in interference suppression.

In some embodiments, the precoding scheme in the disclosed PHY transceiver is selected based on the power spectrum of the LS and HS signals. Thus, a PHY transceiver transmitting LS signals may use a different precoding scheme than a PHY transceiver transmitting HS signals. In an example embodiment, a PHY transceiver transmitting the LS signal (and receiving the HS signal) applies (1+ D) precoding. The (1+ D) precoding scheme has a low pass filtering effect on the spectrum of the transmitted LS signal and thus reduces interference (e.g., local echo) that may interfere with the reception of HS signals in the PHY transceiver. In another example embodiment, a PHY transceiver transmitting HS signals (and receiving LS signals) applies (1-D) precoding. The (1-D) precoding operation has a high pass filtering effect on the spectrum of the transmitted HS signal and thus reduces interference that may interfere with the reception of the LS signal in the PHY transceiver. An example of a simulation of a signal spectrum can be seen in the above-referenced U.S. provisional patent application 62/893,070, which is incorporated by reference herein in its entirety.

In summary, the disclosed techniques reduce interference in a full-duplex bidirectional ethernet link at low cost, small size, and low power consumption with minimal performance degradation. Example PHY device implementations are described. A hybrid configuration is also described, where transmitter side precoding is used only in the LS transmitter, while echo cancellation is applied in the LS receiver. In such a configuration, the echo cancellation operation is performed at the LS rate and therefore incurs only a modest overhead.

Fig. 1 is a block diagram that schematically illustrates a vehicle communication system 10, in accordance with an embodiment described herein. The system 10 is installed in a vehicle 11 and includes a plurality of sensors 12, an ethernet switch 13, a plurality of microcontrollers (μ C)14, a Central Controller (CC)15, a plurality of ethernet physical layer (PHY) transceivers 20 of a first type (denoted as PHY1), and a plurality of ethernet PHY transceivers 24 of a second type (denoted as PHY 1).

In various embodiments, the sensors 28 may include any suitable type of sensor. Several non-limiting examples of sensors include cameras, velocity sensors, accelerometers, audio sensors, infrared sensors, radar sensors, lidar sensors, ultrasonic sensors, rangefinders or other proximity sensors, and the like.

In this example, each sensor 12 is connected to a respective microcontroller 14, which microcontrollers 14 in turn are connected to a respective PHY transceiver 24. The PHY transceiver 24 of each sensor 12 is connected by a link 28 to a peer PHY transceiver 20, the peer PHY transceiver 20 being coupled to a port of the switch 13. On the sensor side of a given link, the microcontroller 14 acts as a Media Access Control (MAC) controller. On the switch side of a given link, the MAC function is performed by switch 13.

The vehicular communication system 10 is an example use case applicable to asymmetric ethernet communication. Typically, the sensors 12 generate large amounts of data that are sent to a Central Computer (CC)15 for analysis. In the opposite direction, the data typically includes configuration data and low rate control from the CC 15 to the sensor 12. In this case, asymmetric communication provides better utilization of the ethernet link 28.

In the embodiment of fig. 1, PHY transceiver 20 (denoted as PHYl) transmits at a bit rate referred to as "low speed" (LS) and receives at a bit rate referred to as "high speed" (HS). PHY transceiver 24 (denoted as PHY2) transmits at a "high speed" (HS) bit rate and receives at a "low speed" (LS) bit rate. The PHY transceiver 20 and 24 pairs communicate with each other over a twisted pair copper link 28, the twisted pair copper line 28 serving as a full duplex line channel. As seen in the figure, in one embodiment, the pair of PHY transceivers 20 and 24 are arranged such that transmissions from sensor 12 to CC 15 are performed at an HS bit rate, and transmissions from CC 15 to sensor 12 are performed at an LS bit rate.

In one embodiment, the HS bit rate is 10 Gbits/sec (10Gbps) according to IEEE802.3 ch, and the LS bit rate is 100Mbps according to IEEE802.3 bw. In another embodiment, the HS bit rate is 10Gbps according to IEEE802.3 ch, and the LS bit rate is 10Mbps according to IEEE802.3cg (10Base-T1 s). In alternate embodiments, the LS bit rate and the HS bit rate may be selected to be any other suitable bit rate. The link between PHY transceivers 20 and 24 may include any other bi-directional medium suitable for full duplex communication.

Fig. 2 is a block diagram that schematically illustrates a pair of asymmetric ethernet physical layer (PHY) transceivers 20 and 24 communicating over a full-duplex bidirectional link 28 in system 10, in accordance with an embodiment described herein. The term "asymmetric" in this context means that the transmission bit rate differs between the two directions of the bidirectional link. As described above, PHY transceiver 20, represented as PHY1, transmits at a "low-speed" (LS) bit rate and receives at a "high-speed" (HS) bit rate. PHY transceiver 24, represented as PHY2, transmits at a "high speed" (HS) bit rate and receives at a "low speed" (LS) bit rate.

In the disclosed embodiment, LS communications (PHY1 to PHY2, left to right in fig. 2) and HS communications (PHY2 to PHY1, right to left in fig. 2) are simultaneously conducted on the same twisted pair link 28. In the frequency domain, the Power Spectral Density (PSD) of the LS signal is concentrated between baseband and 50GHz (for 100Mbps signals) or between baseband and 5GHz (for 10Mbps signals). The PSD of the 10GbpsHS signal is centered between baseband and 5 GHz. Thus, the spectra of the HS and LS signals overlap at the bottom of the spectrum and may interfere with each other. As shown below, this mutual interference is mitigated by using precoding in the transmitter and decoding in the peer receiver, at least in one direction of the link.

In the embodiment of fig. 2, PHY transceiver 20 includes an LS transmitter (LS TX)32 configured to generate and transmit LS signals on link 28, and PHY transceiver 24 includes an LS receiver (LS RX)36 configured to receive LS signals. The PHY transceiver 24 includes an HS transmitter (HS TX)40 configured to generate and transmit HS signals on the link 28, and the PHY transceiver 20 includes an HS receiver (HS RX)44 configured to receive HS signals.

IN one embodiment, LS TX 32 typically receives input LS DATA ("LS DATA IN") from an ethernet Media Access Control (MAC) device (not shown IN the figure for clarity) coupled to PHY transceiver 20. The LS TX 32 includes an LS precoder 48 that precodes input LS DATA ("LS DATA IN"), and a TX driver 52 that transmits the precoded LS DATA over the link 28. In this example, the LS precoder 48 applies a (1+ D) precoding scheme, i.e., uses a delay element (D) to delay the input data by one bit to produce a delayed replica, and uses an adder to add the input data and the delayed replica. Without loss of generality, assume that the input data value is ± 1.

The LS RX 36 includes an input filter 56, and in this example, the input filter 56 includes a combination of a Low Pass Filter (LPF) and a High Pass Filter (HPF) that filters the signal received from the link 28. In alternate embodiments, other suitable types of filters may be used. LS RX 36 also includes an analog-to-digital converter (ADC)60 that digitizes (samples) the filtered signal, an equalizer 64 that equalizes the digitized signal, and a slicer 68 that slices (i.e., makes bit decisions) the signal at the equalizer output. In the absence of errors, the bit stream at the output of the slicer 68 is the same as the precoded data produced by the LS precoder 48. In one embodiment, the output of slicer 68 is fed back to a Digital Timing Loop (DTL)72, and DTL 72 adjusts the sampling clock of ADC 60.

IN the embodiment of fig. 2, LS RX 36 also includes an LS decoder 76 that recovers the original input DATA ("LS DATA IN") from the output of slicer 68 (i.e., from the pre-encoded DATA). The LS decoder 76 applies a decoding scheme that reverses the precoding scheme used by the LS precoder 48. In the present example, the LS decoder 76 applies the (1/(1+ D)) decoding scheme by: (i) delaying the precoded data by one bit using a delay element (D) to produce a delayed replica, (ii) feeding back the delayed replica from the output of the delay element to the input, and (iii) subtracting the delayed replica of the precoded data from the precoded data (or alternatively, subtracting the precoded data from the delayed replica of the precoded data).

IN the absence of errors, the bit stream at the output of the LS decoder 76 ("LS DATA OUT") is the same as the original input DATA ("LS DATA IN"). The "LS DATA OUT" bit stream is provided as a whole as the output of LS RX 36 and the output of PHY transceiver 24. The "LS DATA OUT" bit stream is typically delivered to an ethernet MAC device (not shown in the figure for clarity) that is coupled to PHY transceiver 24.

The (1+ D) precoding operation in the LS TX 32 has a low-pass filtering effect that reduces the PSD of the LS signal at high frequencies. One example of a simulated PSD can be seen in the above-referenced U.S. provisional patent application 62/893,070. Thus, the precoding operation reduces interference (e.g., echo) that may interfere with the reception of the HS signal by the HS RX 44. Meanwhile, the precoding operation of the LS TX 32 can be completely recovered by the inverse decoding operation of the LS RX 36.

IN one embodiment, HS TX 40 is provided with input HS DATA ("HS DATA IN") typically from an ethernet MAC device (not shown) coupled to PHY transceiver 24. The HS TX 40 includes an HS precoder 48 that precodes input HS DATA ("HS DATA IN"), and a TX driver 84 that transmits the precoded HS DATA over the link 28. In this example, the HS precoder 80 applies a (1-D) precoding scheme, i.e., uses a delay element (D) to delay the input data by one bit to produce a delayed replica, and uses an adder to subtract the delayed replica from the input data (or subtract the input data from the delayed replica). Without loss of generality, assume again that the input data value is ± 1.

HS RX44 includes an input filter 88, and in this example, input filter 88 includes a combination of LPF and HPF that filters the signal received from link 28. HS RX44 also includes an ADC 92 that digitizes (samples) the filtered signal, an equalizer 96 that equalizes the digitized signal, and a slicer 100 that slices (i.e., makes bit decisions) the signal at the equalizer output. In the absence of errors, the bit stream at the output of slicer 100 is the same as the precoded data produced by HS precoder 80. In one embodiment, the output of slicer 100 is fed back to DTL 104, and DTL 104 adjusts the sampling clock of ADC 92.

IN the embodiment of fig. 2, HS RX44 also includes HS decoder 108, which HS decoder 108 recovers the original input DATA ("HS DATA IN") from the output of slicer 100 (i.e., from the precoded DATA). The HS decoder 108 applies a decoding scheme that reverses the precoding scheme used by the HS precoder 80 (i.e., inverse). In this example, the HS decoder 108 applies the (1/(1-D)) decoding scheme by: (i) delaying the precoded data by one bit using a delay element (D) to produce a delayed replica, (ii) feeding back the delayed replica from the output of the delay element to the input, and (iii) adding the precoded data to the fed-back delayed replica of the precoded data.

IN the absence of errors, the bit stream at the output of the HS decoder 108 ("HS DATA OUT") is the same as the original input DATA ("HS DATA IN"). The "HS DATA OUT" bit stream is provided as a whole as an output of HS RX44 and an output of PHY transceiver 20. The "HS DATA OUT" bit stream is typically delivered to an ethernet MAC device (not shown) coupled to PHY transceiver 20.

The (1-D) precoding operation in HS TX 40 has a high-pass filtering effect that reduces the PSD of the HS signal at low frequencies, near baseband. A simulated example PSD can be seen in the above-referenced U.S. provisional patent application 62/893,070. Thus, the precoding operation reduces interference (e.g., local echo) that may interfere with the reception of the LS signal by the LS RX 36. At the same time, the precoding operation of HS TX 40 can be fully recovered by the inverse decoding operation of HS RX 44.

In the example of fig. 2, precoding is applied in both LS and HS transmissions. Thus, echo cancellation in both PHY transceivers is not required. In an alternative embodiment, precoding may be applied in only one direction, with one of the PHY transceivers still performing echo cancellation. An embodiment of this type is shown in figure 4 below.

Fig. 3 is a flow diagram that schematically illustrates a method for communication between asymmetric ethernet PHY transceivers 20 and 24 of fig. 2, in accordance with an embodiment described herein. The method is described in the context of one direction, e.g., LS transmission from LS TX 32 to LS RX 36, or HS transmission from HS TX 40 to HS RX 44.

The method starts with: at precoding operation 110, the precoder of TX (precoder 48 or 80, as appropriate) precodes the input data. In the example of fig. 2, the precoding scheme is (1+ D) for LS transmissions and (1-D) for HS transmissions. At transmit operation 114, the TX driver (TX driver 52 or 84, as the case may be) modulates the precoded data and transmits the resulting signal over link 28.

At receive operation 118, the receiver (LS RX 36 or HS RX44, as appropriate) receives a signal from link 28. At a receiver-side processing operation 122, the receiver filters, digitizes, equalizes, and slices the received signal, as described above. At decoding operation 126, the decoder of the receiver (decoder 76 or 108, as the case may be) decodes the precoded data provided by the slicer. In the example of fig. 2, the decoding scheme is (1/(1+ D)) for LS transmissions and (1/(1-D)) for HS transmissions. The decoded data is provided as output.

Fig. 4 is a block diagram that schematically illustrates an asymmetric ethernet PHY transceiver 128, in accordance with an alternative embodiment described herein. In this example, precoding is applied only to LS TX (of peer PHY transceiver) and not to HS TX (of PHY transceiver 128), and thus decoding is applied only to LS RX (of PHY transceiver 128) and not to HS RX (of peer PHY transceiver). Typically, although not necessarily, the precoding scheme is (1+ D) and the decoding scheme is (1/(1+ D)).

Furthermore, PHY devices including LS RX perform echo cancellation for suppressing echoes of transmitted HS signals that may interfere with reception of LS signals. In general, cancellation of the echo of the HS signal in LS RX (interference from the HS TX 130 transmitted signal on the LS signal received by LS RX 134, all local to PHY transceiver 128) only introduces modest computational complexity, since cancellation is performed at the LS bit rate. Echo cancellation in the opposite direction (i.e. echo cancellation of the LS signal in HS RX) is much more complex to implement. Therefore, it is highly desirable to use precoding in LS transmission.

In the example of fig. 4, PHY transceiver 128 includes HS TX 130 and LS RX 134. As in the configuration of fig. 2, the HS bit rate may be 10 gbits/second (10Gbps) and the LS bit rate may be 100Mbps or 10 Mbps.

As can be seen, the HS TX 130 of the PHY transceiver 128 includes the TX driver 84, but no precoder. Thus, TX driver 84 transmits the "HS DATA IN" bit stream directly on link 28 without precoding. The HS RX IN the peer PHY transceiver (not shown IN the figure) does not perform decoding of the received HS DATA IN bit stream.

LS RX 134 of PHY transceiver 128 is similar to LS RX 36 (fig. 2) with the addition of echo cancellation circuitry configured to cancel echoes of the HS signal that interfere with the reception of the LS signal. Similar to LS RX 36 of fig. 2, LS RX 134 receives the precoded LS signal and applies decoding using LS decoder 76.

In one embodiment, the echo cancellation circuitry in LS RX 134 includes LPF/decimation filter 138, echo cancellation filter 142, and summer 146. The LPF/decimation filter 138 receives a copy of the "HS DATA IN" bit stream from the HS TX 130 and performs two functions: (i) low pass filtering the bitstream, and (ii) reducing the rate of the bitstream from the HS bit rate to the LS bit rate. The echo cancellation filter 142 adjusts the gain and phase of the extracted HS signal to match the gain and phase of the echo of the HS signal at the output of the ADC 60. The adder 146 subtracts the output of the filter 142 from the output of the ADC 60, thereby cancelling the echo. Thus, the signal provided to the equalizer 64 has a reduced echo level from the HS signal.

In some embodiments, it is sufficient to implement the echo cancellation filter 142 with a relatively small number of taps (coefficients) (e.g., on the order of sixteen taps) to cancel the echo of the HS signal. The smaller number of taps also simplifies the coefficient calculation process. For example, a 16-tap filter is shown to be sufficient for an LS rate of 100Mbps, two-stage pulse amplitude modulation (PAM2), and a 15 meter long twisted pair link suitable for typical vehicular networks.

The configuration of the PHY transceivers 20, 24, and 128 and their components (e.g., the internal structure of the various LS TX, LS RX, HS TX, and HS RX, as shown in fig. 1, 2, and 3) are example configurations depicted for clarity only. In alternate embodiments, any other suitable configuration may be used. For example, the (1+ D) and (1-D) precoding schemes described above are chosen purely as examples. Alternatively, any other suitable precoding scheme may be used. In general, the pre-coding operation may be implemented by adding two or more mutually delayed copies of the input data stream. The term "mutual delay" does not necessarily mean that all copies are delayed; in each of the (1+ D) and (1-D) schemes, for example, one copy is delayed while the other copy is not delayed.

The various elements of the PHY transceivers 20, 24, and 128 and their components may be implemented using dedicated hardware or firmware, e.g., using hardwired or programmable logic, e.g., in an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA). Additionally or alternatively, some functions of the PHY transceivers 20, 24, and 128 (e.g., functions of the LS precoder 48, LS decoder 76, HS precoder 80, and/or HS decoder 108) may be implemented in software and/or using a combination of hardware and software elements. For the sake of clarity, elements that are not mandatory for understanding the disclosed technology have been omitted from the figures. For example, each PHY transceiver typically includes a Media Dependent Interface (MDI) for coupling the transmitter and receiver to the link 28.

In some embodiments, some of the functions of the PHY transceivers 20, 24, and 128 (e.g., the functions of the LS precoder 48, LS decoder 76, HS precoder 80, and/or HS decoder 108) may be implemented in one or more programmable processors programmed in software to perform the functions described herein. For example, the software may be downloaded to any of the processors in electronic form over a network, or may alternatively or additionally be provided and/or stored on non-transitory tangible media (e.g., magnetic, optical, or electronic memory).

It should be noted that the above-mentioned embodiments are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference into this patent application should be considered an integral part of the application, and definitions in this specification should only be considered unless any term is defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in this specification.