阅读说明：本技术 具有多个输入偏移的跟踪的斩波放大器 (Chopper amplifier with tracking of multiple input offsets ) 是由 楠田義憲 于 2021-06-04 设计创作，主要内容包括：本文公开具有多个输入偏移的跟踪的斩波放大器。在某些实施方案中,斩波放大器包括：斩波放大器电路,包括：输入斩波电路、放大电路和沿着信号路径电连接的输出斩波电路。所述放大电路包括两对或更多对输入晶体管,控制电路从中选择一对选定的输入晶体管以放大输入信号。斩波放大器还包括偏移校正电路,感测信号路径以产生用于放大电路的输入转换补偿信号。而且,所述偏移校正电路分别跟踪所述两对或更多对输入晶体管中的每对的输入偏移。(Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes: a chopper amplifier circuit comprising: an input chopper circuit, an amplifier circuit, and an output chopper circuit electrically connected along a signal path. The amplifying circuit includes two or more pairs of input transistors from which the control circuit selects a selected one of the pairs of input transistors to amplify the input signal. The chopper amplifier also includes an offset correction circuit that senses the signal path to produce an input transition compensation signal for the amplification circuit. Also, the offset correction circuit tracks the input offset of each of the two or more pairs of input transistors, respectively.)

1. A chopper amplifier having a tracking plurality of input offsets, the chopper amplifier comprising:

a chopper amplifier circuit comprising:

an input chopper circuit configured to chop an input signal to produce a chopped input signal;

an amplification circuit configured to amplify the chopped input signal to generate an amplified signal, wherein the amplification circuit comprises two or more pairs of selectable input transistors;

an output chopper circuit configured to chop the amplified signal to produce a chopped output signal; and

a control circuit configured to select a pair of input transistors from the two or more pairs of input transistors, wherein the selected pair of input transistors is configured to amplify the chopped input signal; and

an offset correction circuit configured to generate an input offset compensation signal for the chopper amplifier circuit, wherein the offset correction circuit tracks the input offset of each of the two or more pairs of input transistors, respectively.

2. The chopper amplifier of claim 1, wherein the offset correction circuit comprises a digital circuit configured to generate digital correction data indicative of a value of the input offset compensation signal for each of the two or more pairs of input transistors.

3. The chopper amplifier of claim 2, wherein the digital circuit includes a non-volatile memory configured to store the digital correction data.

4. The chopper amplifier of claim 2, wherein the digital circuit includes a memory configured to store digital correction data, wherein the digital circuit is coupled to a digital interface operable to read or write to the memory.

5. The chopper amplifier of claim 2, wherein the offset correction circuit comprises: an analog sensing circuit configured to generate a sense signal based on sensing a signal path through the chopper amplifier circuit; an analog-to-digital converter configured to convert the sense signal to a digital input signal of the digital circuit; and a digital-to-analog converter configured to control the input offset compensation signal based on the digital correction data.

6. The chopper amplifier of claim 5, wherein the analog-to-digital converter includes a comparator and the digital circuit includes two or more counters, each counter configured to track an input offset of a corresponding one of the two or more pairs of input transistors.

7. The chopper amplifier of claim 5, wherein the analog sensing circuit comprises: a chopper circuit configured to output the sensing signal; and a sense amplifier having an input coupled to the signal path and an output coupled to an input of the chopper circuit.

8. The chopper amplifier of claim 1, wherein the two or more pairs of input transistors include a pair of n-type input transistors and a pair of p-type input transistors.

9. The chopper amplifier of claim 8, further comprising a first pair of isolation switches coupled to the pair of n-type input transistors and a second pair of isolation switches coupled to the pair of P-type input transistors, wherein the control circuit closes the first pair of isolation switches and opens the second pair of isolation switches when the selected pair of input transistors corresponds to the pair of n-type input transistors and closes the second pair of isolation switches and opens the first pair of isolation switches when the selected pair of input transistors corresponds to the pair of P-type input transistors.

10. The chopper amplifier of claim 1, further comprising a pair of input terminals configured to receive an input signal, wherein the control circuit selects the selected pair of input transistors based on sensing an input common mode voltage of the pair of input terminals.

11. The chopper amplifier of claim 1, wherein the offset correction circuit is configured to generate the input offset compensation signal based on sensing a signal path through the chopper amplifier circuit at two or more signal points.

12. The chopper amplifier of claim 11, wherein the two or more signal points include a first signal point before the input chopper circuit and a second signal point after the output chopper circuit.

13. The chopper amplifier of claim 11, wherein the offset correction circuit is configured to provide the input offset compensation signal to an output of the amplification circuit.

14. The chopper amplifier of claim 1, wherein the control circuit generates two or more enable signals, each enable signal operable to select a respective one of the two or more pairs of input transistors, wherein the control circuit provides the two or more enable signals to the offset correction circuit.

15. A method of amplification, the method comprising:

chopping an input signal using an input chopper circuit to produce a chopped input signal;

selecting, using a control circuit, a pair of input transistors from two or more pairs of input transistors of an amplifier circuit;

amplifying the chopped input signal using a selected pair of input transistors to generate an amplified signal;

chopping the amplified signal using an output chopper circuit to produce a chopped output signal; and

compensating the amplification circuit using an input offset compensation signal generated by an offset correction circuit, including tracking input offsets of each of the two or more pairs of input transistors, respectively.

16. The method of claim 15, wherein compensating for the input offset of the amplification circuit comprises generating digital correction data indicative of the value of the input offset compensation signal for each of the two or more pairs of input transistors.

17. The method of claim 16, further comprising storing the digital correction data in a non-volatile memory, performing a power cycle, and using the stored digital correction data to compensate for input offset of the amplification circuit after the power cycle.

18. The method of claim 15, wherein the two or more pairs of input transistors comprise a pair of n-type input transistors and a pair of p-type input transistors, the method further comprising selecting the selected pair of input transistors based on an input common mode voltage.

19. A chopper amplifier comprising:

a pair of input terminals;

a chopper amplifier circuit comprising:

an input chopper circuit including an input coupled to the pair of input terminals;

an amplification circuit comprising an input coupled to an output of the input chopper circuit, wherein the amplification circuit comprises two or more pairs of selectable input transistors;

an output chopper circuit including an input coupled to an output of the amplification circuit; and

a control circuit configured to select a pair of input transistors from the two or more pairs of input transistors to provide amplification; and

an offset correction circuit configured to track input offsets of each of the two or more pairs of input transistors, respectively, and generate an input offset compensation signal for compensating the amplification circuit.

20. The chopper amplifier of claim 19, wherein the offset correction circuit comprises a digital circuit configured to generate digital correction data indicative of a value of the input offset compensation signal for each of the two or more pairs of input transistors.

Technical Field

Embodiments of the present invention relate to electronic systems, and more particularly, to amplifiers.

Background

Amplifiers, such as operational amplifiers or instrumentation amplifiers, may include chopper circuits to help compensate for the input voltage to the amplifier. For example, a chopper amplifier may include an input chopper circuit that may be used to chop the input signal to the amplifier during an input chopping operation, thereby up-regulating the frequency of the amplifier input signal. The chopper amplifier may further include: an amplifying circuit for amplifying the chopped input signal; and an output chopper circuit for shifting down the frequency of the amplified signal during an output chopping operation. By chopping in this manner, the input voltage to the amplifier is separated in frequency from the chopped input signal and thus may be filtered or otherwise attenuated.

Disclosure of Invention

Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes: a chopper amplifier circuit comprising: an input chopper circuit, an amplifier circuit, and an output chopper circuit electrically connected along a signal path. The amplifying circuit includes two or more pairs of input transistors from which the control circuit selects a selected one of the pairs of input transistors to amplify the input signal. The chopper amplifier also includes an offset correction circuit that senses the signal path to produce an input transition compensation signal for the amplification circuit. Also, the offset correction circuit tracks the input offset of each of the two or more pairs of input transistors, respectively. Therefore, in the offset correction circuit for compensating for the input offset and suppressing the chopping ripple, the modification of the selected pair of input transistors can be made with almost no delay. In particular, since the correction calibration circuit tracks the input offset of each pair of input transistors separately, the input correction signal can be quickly updated to the appropriate signal value for compensation in response to changes in the selected pair of input transistors.

In one aspect, a chopper amplifier with tracking multiple input offsets is provided. The chopper amplifier includes: a chopper amplifier circuit comprising: an input chopper circuit configured to chop an input signal to produce a chopped input signal, an amplifier circuit configured to amplify the chopped input signal to produce an amplified signal, wherein the amplifier circuit includes two or more pairs of selectable input transistors, an output chopper circuit configured to chop the amplified signal to produce a chopped output signal, and a control circuit configured to select a pair of input transistors from the two or more pairs of input transistors, wherein the selected pair of input transistors is configured to amplify the chopped input signal. The chopper amplifier also includes an offset correction circuit configured to generate an input offset compensation signal for the chopper amplifier circuit, wherein the offset correction circuit tracks the input offset of each of the two or more pairs of input transistors, respectively.

In another aspect, a method of amplification is provided. The method comprises the following steps: chopping an input signal using an input chopper circuit to produce a chopped input signal, selecting a pair of input transistors from two or more pairs of input transistors of an amplifier circuit using a control circuit, amplifying the chopped input signal using the selected pair of input transistors to generate an amplified signal, chopping the amplified signal using an output chopper circuit to produce a chopped output signal, and compensating the amplifier circuit using an input offset compensation signal produced by an offset correction circuit, including tracking input offsets for each of the two or more pairs of input transistors, respectively.

In another aspect, a chopper amplifier is provided, comprising: a pair of input terminals, and a chopper amplifier circuit comprising an input chopper circuit comprising an input coupled to the pair of input terminals, an amplification circuit comprising an input coupled to an output of the input chopper circuit, wherein the amplification circuit comprises two or more pairs of selectable input transistors, an output chopper circuit comprising an input coupled to an output of the amplification circuit; and a control circuit configured to select a pair of input transistors from the two or more pairs of input transistors to provide amplification. The chopping amplifier further includes an offset correction circuit configured to track an input offset of each of the two or more pairs of input transistors, respectively, and generate an input offset compensation signal for compensating the amplification circuit.

Drawings

Fig. 1 is a schematic diagram of a chopper amplifier according to one embodiment.

Fig. 2A is a schematic diagram of a chopper amplifier according to another embodiment.

Fig. 2B is a schematic diagram of a chopper amplifier according to another embodiment.

Fig. 3 is a schematic diagram of a chopper amplifier according to another embodiment.

Fig. 4 is a schematic diagram of a chopper amplifier according to another embodiment.

Fig. 5 is a schematic diagram of a chopper amplifier according to another embodiment.

Fig. 6 is a schematic diagram of a chopper amplifier according to another embodiment.

FIG. 7 is a schematic diagram of one embodiment of an amplification circuit for a chopper amplifier.

Fig. 8 is a schematic diagram of one example of a chopping switch that may be used in a chopping amplifier.

Detailed Description

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. The invention may, however, be embodied in many different forms. In this description, reference is made to the drawings wherein like reference numbers may indicate identical or functionally similar elements. It will be understood that the elements shown in the figures are not necessarily drawn to scale. Further, it will be understood that certain embodiments may include more elements than are shown in the figures and/or subsets of the elements shown in the figures. Furthermore, some embodiments may incorporate any suitable combination of features from two or more of the figures.

Without compensation, the amplifier may have an input offset voltage and/or low frequency noise, such as flicker or 1/f noise, with an associated noise Power Spectral Density (PSD) that becomes larger at lower frequencies.

To reduce or eliminate the input offset voltage and/or low frequency noise, the amplifier may include a chopper circuit. An amplifier having a chopper circuit is called a chopper amplifier. In one example, a chopper amplifier includes an input chopper circuit that chops or modulates an input signal to the amplifier during an input chopping operation, thereby shifting up the frequency of the input signal to the amplifier. Further, the chopper amplifier includes: an amplifying circuit that amplifies the chopped input signal; and an output chopper circuit that chops or demodulates the amplified signal during an output chopping operation. By chopping in this manner, the input offset voltage and/or low frequency noise of the amplifier is separated in frequency from the desired signal and thus may be filtered or otherwise attenuated.

In some embodiments, the chopper amplifier may further include an auto-zero circuit. The inclusion of both an auto-zero and a chopper circuit in the chopper amplifier may further reduce overall input offset voltage and/or low frequency noise. The teachings herein are applicable not only to chopper amplifiers that provide chopping, but also to chopper amplifiers that combine chopping with auto-zero and/or other compensation schemes.

The chopping operation of the amplifier may cause a ripple in the output voltage of the amplifier. The amplitude of the chopping ripple may vary with the input offset voltage of the amplifier and/or the amplitude of the low frequency noise. Thus, chopping may result in the input offset voltage and/or low frequency noise of the amplifier not being cancelled but being modulated by the chopping frequency, thereby generating chopping ripples that disrupt the spectral integrity of the amplifier output signal.

Although a low pass post filter may be included after the output chopper circuit to filter out chopping ripples associated with modulating the input offset voltage and/or modulating low frequency noise, it may be desirable to reduce the input offset voltage and/or low frequency noise of the amplifier to avoid the need for a post filter or to relax the design constraints of the post filter. In another example, a switched capacitor notch filter may be included after the output chopper circuit to provide attenuation of the chopping ripple wave.

To provide input offset compensation and suppress chopping ripple, feedback and/or feed-forward correction paths may be used. For example, such a correction path may be used to generate an input offset correction signal to compensate for input offsets prior to output chopping, thereby suppressing chopping ripple.

In some applications, a chopper amplifier includes multiple pairs of input transistors, each of which may be selected to amplify an input signal based on operating conditions and/or parameters. For example, some chopper amplifiers operate over a wide range of input common mode voltages, and therefore include pairs of input transistors for amplifying an input signal based on a detected input common mode voltage. In particular, the chopper amplifier may include a pair of n-type input transistors for amplifying the input signal on an upper portion of the input common mode voltage range, and a pair of p-type input transistors for amplifying the input signal on a lower portion of the input common mode voltage range. In contrast, a chopper amplifier with only a pair of input transistors may not have sufficient voltage margin to operate over a wide input common mode voltage range, such as rail-to-rail operation.

When switching from using one pair of input transistors to another, the offset correction circuit of the chopper amplifier may delay the time to properly compensate for the input offset of the newly selected pair of input transistors. For example, each input transistor pair of a chopper amplifier may have a different input offset voltage, and thus, when a selected pair of input transistors changes, the input offset correction signal generated by the offset correction circuit may be delayed in settling to a steady state value suitable for properly compensating the newly selected pair.

Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes: a chopper amplifier circuit comprising: an input chopper circuit, an amplifier circuit, and an output chopper circuit electrically connected along a signal path. The amplifying circuit includes two or more pairs of input transistors from which the control circuit selects a selected one of the pairs of input transistors to amplify the input signal. The chopper amplifier also includes an offset correction circuit that senses the signal path to produce an input transition compensation signal for the amplification circuit. Also, the offset correction circuit tracks the input offset of each of the two or more pairs of input transistors, respectively.

Therefore, in the offset correction circuit for compensating for the input offset and suppressing the chopping ripple, the modification of the selected pair of input transistors can be made with almost no delay. In particular, since the correction calibration circuit tracks the input offset of each pair of input transistors separately, the input correction signal can be quickly updated to the appropriate signal value for compensation in response to changes in the selected pair of input transistors.

In some embodiments, the two or more pairs of input transistors include a pair of p-type input transistors and a pair of n-type input transistors, and the control circuit determines whether to use the pair of p-type input transistors or the pair of n-type input transistors based on sensing an input common mode voltage of the chopper amplifier. For example, the control circuit may use a pair of n-type input transistors in a first range of input common mode voltages and a pair of p-type input transistors in a second range of input common mode voltages. The selection of a pair of n-type input transistors or a pair of p-type input transistors may also change as the input common mode voltage changes. Furthermore, since the input offset of the n-type input transistor and the input offset of the p-type input transistor are tracked separately, the input offset compensation signal can be quickly updated to an appropriate signal level when the selected pair of input transistors is changed. Thus, seamless or near seamless switching between the n-type input transistor and the p-type input transistor is achieved.

The input transistor pair may correspond to a variety of transistor types including, but not limited to, Field Effect Transistors (FETs), such as Metal Oxide Semiconductor (MOS) transistors. MOS transistors may be associated with a variety of manufacturing processes, including not only bulk Complementary MOS (CMOS) processes, but also triple-well CMOS processes, silicon-on-insulator (SOI) processes, double-diffused MOS (dmos) processes, and various other manufacturing processes. In some embodiments, the two or more pairs of input transistors include a pair of n-type mos (nmos) transistors, such as n-type DMOS transistors, and a pair of p-type mos (pmos) transistors, such as p-type DMOS transistors.

The offset correction circuit may be implemented in a variety of ways. In some embodiments, the offset correction circuit includes digital circuitry for tracking input offsets of two or more pairs of input transistors, respectively. The use of digital circuitry may provide a number of advantages.

In a first example, the digital circuit may comprise a non-volatile memory for storing digital data representing the input offset voltage of each pair of input transistors of the amplifying circuit. Thus, the chopper amplifier can accurately amplify the fast recovery using any selected input transistor pair after a power cycle of the chopper amplifier in which the chopper amplifier is powered down and then powered up. Conversely, a chopper amplifier that does not have this function may have a long delay at start-up to settle to a steady-state signal value suitable for input offset compensation.

In a second example, the digital circuit is coupled to a digital interface (e.g., a serial interface or a parallel interface of a semiconductor die or chip) that allows the digital data to be viewed off-chip and/or loaded into a chopper amplifier after power-up to achieve input offset compensation with little delay.

In a third example, the digital circuit may hold the input offset correction data indefinitely without chopping clock signal switching. Thus, the user can stop and resume chopping the clock signal at any time and after any duration. Furthermore, a particular pair of input transistors may be left unused for a long time without affecting the ability of the digital circuit to store input offset correction data for that pair. In contrast, analog circuits may be subject to leakage current and/or noise, and it is therefore necessary for the analog circuits to operate properly with the chopped clock signal to maintain proper input offset compensation.

The offset correction circuit herein may be used not only to compensate for the input offset voltage of two or more pairs of input transistors of the amplification circuit, but also to reduce or eliminate other low frequency input noise sources, such as flicker noise. This in turn results in a reduction in chopping ripple, a reduction in flicker noise current, and/or an increase in spectral output purity at the output of the chopper amplifier.

Fig. 1 is a schematic diagram of a chopper amplifier 20 according to one embodiment. The chopper amplifier 20 includes a chopper amplifier circuit 1 and an offset correction circuit 2, and the offset correction circuit 2 compensates an input offset voltage of the chopper amplifier circuit 1 while suppressing output chopper ripples.

As shown in fig. 1, chopper amplifier 20 receives a positive or non-positive input voltage terminal V_IN+And a negative or inverting input voltage terminal V_IN-Which serves as a pair of differential input terminals V_IN+、V_IN-. Chopper amplifier 20 also has a positive or non-inverting output voltage terminal V_IN+And a negative or inverted output voltage terminal V_IN-Output a differential output signal serving as a pair of differential output terminals V_OUT+、V_OUT-。

Although fig. 1 illustrates a configuration in which chopper amplifier 20 generates a differential output signal, chopper amplifier 20 may be adapted to generate other output signals, including, for example, a single-ended output signal. Additionally, although fig. 1 shows chopper amplifier 20 in an open-loop configuration, chopper amplifier 20 may be used in a closed-loop configuration.

In the illustrated embodiment, the chopper amplifier circuit 1 includes an input chopper circuit 3, an amplification circuit 5, and an output chopper circuit 4 that are electrically connected in cascade along a signal path, with the amplification circuit 5 between the input chopper circuit 3 and the output chopper circuit 4. In the present embodiment, the chopper amplifier circuit 1 further includes a control circuit corresponding to the common mode detection circuit 6.

Although certain components of the chopper amplifier circuit 1 are shown, the chopper amplifier circuit 1 may include additional components or circuits, including, but not limited to, one or more additional amplification stages, output stages, feed-forward paths, and/or feedback paths. Thus, other implementations are possible.

The input chopper circuit 3 operates to chop or modulate the differential input signal to generate a chopped differential input signal, which is amplified by the amplifier circuit 5 to generate an amplified differential signal. The chopping operation of the input chopper circuit 3 raises the frequency of the differential input signal. For example, in some embodiments, the chopping clock signal input to the chopper circuit 3 is a square wave, which can be equivalently represented by a fourier series of sine waves at the chopping frequency and its odd harmonics. By modulating the differential input signal with such a square wave, the frequency components of the differential input signal are shifted up. Thus, the chopped differential input signal includes signal content at the chopping frequency and its odd harmonics. Thus, the chopped differential input signal is separated in frequency from the input offset voltage and/or low frequency noise of the amplification circuit 5.

As shown in fig. 1, in this embodiment, the amplifying circuit 5 includes a plurality of pairs of input transistors corresponding to a pair of n-type input transistors 7 and a pair of p-type input transistors 8. The control circuit of the chopper amplifier circuit may select each pair of input transistors separately, and they may have different input offsets.

In some embodiments, the input chopping circuit 3 includes a separate set of input chopping switches for each pair of input transistors of the amplification circuit 5. In other embodiments, a common set of chopping switches is used for the input transistor pairs.

In the illustrated embodiment, the common mode detection circuit 6 generates a first enable signal N for selecting a pair of N-type input transistors 7 for amplification_ENAnd a second enable signal P for selecting a pair of P-type input transistors 8 to amplify_EN. In this embodiment, the common mode detection circuit 6 selects a selected pair of input transistors based on the sensed input common mode voltage. For example, a pair of n-type input transistors 7 is well suited for use at high input common mode voltages (e.g., near V) due to supply voltage headroom limitations_DD) Amplification is provided below, and a pair of p-type input transistors 8 are well suited at low input common mode voltages (e.g., at V)_SSNearby) to provide amplification.

Thus, in some embodiments, the common mode detection circuit 6 activates a pair of n-type input transistors 7 and deactivates a pair of p-type input transistors 8 when the detected input common mode voltage is high, and activates a pair of p-type input transistors 8 and activates a pair of n-type input transistors 7 when the detected input common mode voltage is low. For the mid-band of the input common mode voltage, the common mode detection circuit 6 may activate either the n-type input transistor 7 or the p-type input transistor 8 depending on the implementation.

The selected pair of input transistors amplifies the chopped differential input signal to generate an amplified differential signal. The amplified differential signal is chopped by the output chopper circuit 4, thereby reducing the content of the signal frequency. The chopped differential output signal may be output with or without further processing (e.g., amplification, filtering, and/or integration) to generate the differential output signal of the chopper amplifier 20.

Chopper amplifier 20 also includes offset correction circuit 2 that senses the signal path through chopper amplifier circuit 1 at one or more points or locations. In addition, the offset correction circuit 2 injects an input offset voltage compensation signal into the signal path of the chopper amplifier circuit 1 to compensate for the input offset voltage and suppress chopper ripple.

In the illustrated embodiment, the offset correction circuit 2 tracks the input offset of each pair of input transistors of the amplification circuit 5, respectively. In particular, the offset correction circuit 2 includes a first tracking circuit 17 for tracking the input offset of the pair of n-type input transistors 7, and a second tracking circuit 18 for tracking the input offset of the pair of p-type input transistors 8. Although depicted as separate components, the first tracking circuit 17 and the second tracking circuit 18 may share certain circuitry, e.g., a portion of the offset correction circuit 2, for sensing, amplification, chopping, and/or other processing.

As shown in fig. 1, the offset correction circuit 2 receives a first enable signal N from the common mode detection circuit 6_ENAnd a second enable signal P_EN. First enable signal N_ENAnd a second enable signal P_ENMay be used to activate the tracking operations of the first tracking circuit 17 and the second tracking circuit 18, respectively. Thus, appropriate input offset correction and chopping ripple suppression are provided for the selected pair of input transistors of the amplification circuit 5.

In some embodiments, the input offset compensation signal is injected into a portion of the signal circuit of the chopper amplifier circuit 1 that is between the amplification circuit 5 and the output chopper circuit 4. By compensating for this low frequency noise prior to output chopping, the generation of chopper voltage ripple in the differential output signal may be reduced or eliminated.

Fig. 2A is a schematic diagram of a chopper amplifier 30 according to another embodiment. The chopper amplifier 30 includes a chopper amplifier circuit 1 and an offset correction circuit 22.

Chopper amplifier 30 of fig. 2A is similar to chopper amplifier 20 of fig. 1, except that chopper amplifier 30 of fig. 2A includes a different implementation of an offset correction circuit. In particular, the offset correction circuit 22 of fig. 2A includes a sense amplifier 13, a resistor 15, a chopper circuit 16, an analog-to-digital converter (ADC)23, a digital circuit 24, and a digital-to-analog converter (DAC) 25. In addition, the digital circuit 24 includes an n-type tracking circuit 27 and a p-type tracking circuit 28.

In the illustrated embodiment, the sense amplifier 13 includes a differential input coupled to a sense point along the signal path of the chopper amplifier circuit 1. In some embodiments, the sensing point follows a signal path after the output chopper circuit 4. The teachings herein are applicable to offset correction circuits that sense input offset in a variety of ways.

As shown in fig. 2A, the output signal from the sense amplifier 13 is supplied to the chopper circuit 16. In some embodiments, the output signal from the sense amplifier 13 is a current that flows through a resistor 15 to produce an input voltage signal for the chopper circuit 16. Chopper circuit 16 produces an output signal that is digitized by ADC 23 and processed by digital circuit 24 to produce digital correction data.

DAC 25 uses the digital correction data to generate a differential input offset compensation signal that is provided to chopper amplifier circuit 1. In some embodiments, a differential input offset compensation signal is provided to the differential output of the amplification circuit 5 to compensate for the input offset voltage of a selected pair of input transistors of the amplification circuit 5.

With continued reference to fig. 2A, the offset correction circuit 22 receives the first enable signal N from the common mode detection circuit 6_ENAnd a second enable signal P_EN. First enable signal N_ENAnd a second enable signal P_ENFor activating the tracking operations of the first tracking circuit 27 and the second tracking circuit 28, respectively.

Thus, when the common mode detection circuit 6 changes the selected input transistor pair from p-type pair 8 to n-type pair 7, and vice versa, the corresponding digital tracking circuit of the offset correction circuit 22 is activated. Accordingly, the digital correction data supplied to DAC 25 is updated so that the differential input offset compensation signal supplied to chopper amplifier circuit 1 is at the appropriate signal level to compensate for the input offset of the selected pair of input transistors. Thus, the selected pair of input transistors can be switched with little delay and without affecting the ability of chopper amplifier 30 to provide accurate amplification with low input offset.

Fig. 2B is a schematic diagram of chopper amplifier 39 according to another embodiment. Chopper amplifier 39 includes chopper amplifier circuit 1 and offset correction circuit 36.

Chopper amplifier 39 of fig. 2B is similar to chopper amplifier 30 of fig. 2A, except that offset correction circuit 36 of fig. 2B omits chopper circuit 16 shown in fig. 2A. In addition, the offset correction circuit 36 includes a digital circuit 37 that provides digital chopping 38. Any offset correction circuit herein may be adapted to operate with digital chopping.

Fig. 3 is a schematic diagram of a chopper amplifier 40 according to another embodiment. Chopper amplifier 40 includes chopper amplifier circuit 1 and offset correction circuit 32.

Chopper amplifier 40 of fig. 3 is similar to chopper amplifier 30 of fig. 2A, except that offset correction circuit 32 of fig. 3 includes digital circuit 34, which digital circuit 34 includes non-volatile memory (NVM) 35. When tracking a pair of n-type input transistors 7 and tracking a pair of p-type input transistors 8, NVM 35 is used to store digital data indicative of the signal values of the differential input offset compensation signals.

By including NVM 35, chopper amplifier 40 can quickly resume amplification after a power cycle. Such power cycles may correspond to a drop and/or rise in the supply voltage of the chopper amplifier, and/or a power down signal (PWR _ DN) may be used to turn on and off the chopper amplifier 40. By including NVM 35, data representing the input offset compensated signal values for each transistor pair is not lost during power cycles. Thus, start-up delays in settling to a steady-state signal value for input offset compensation are avoided. Further, after the power cycling, a pair of n-type input transistors 7 or a pair of p-type input transistors 8 may be used.

Fig. 4 is a schematic diagram of a chopper amplifier 50 according to another embodiment. The chopper amplifier 50 includes a chopper amplifier circuit 1 and an offset correction circuit 42.

Chopper amplifier 50 of fig. 4 is similar to chopper amplifier 30 of fig. 2A, except that offset correction circuit 42 of fig. 4 includes digital circuitry 44 coupled to a digital interface and includes memory 45, which memory 45 may be volatile or non-volatile. The memory 45 is used to store digital data indicative of the signal values used to track the differential input offset compensation signals for the n-type pair 7 and the p-type pair 8. The memory 45 can be read from or written to using a digital interface, which can correspond to a serial interface or a parallel interface of the semiconductor chip on which the chopper amplifier 50 is fabricated.

Implementing the digital circuit 44 to communicate over a digital interface allows digital data to be observed on-chip and/or loaded into the chopper amplifier 50 after power-up or power cycling to achieve input offset compensation with little delay.

Fig. 5 is a schematic diagram of a chopper amplifier 60 according to another embodiment. Chopper amplifier 60 includes chopper amplifier circuit 1 and offset correction circuit 52.

Chopper amplifier 60 of fig. 5 is similar to chopper amplifier 30 of fig. 2A, except that offset correction circuit 52 of fig. 5 also includes second sense amplifier 14. Accordingly, the offset correction circuit 52 senses the signal path of the chopper amplifier circuit 1 at a plurality of points or positions.

In the embodiment shown, the first sense amplifier 13 comprises a differential input coupled to a first sensing point along the signal path of the chopper amplifier circuit 1, while the second sense amplifier 14 comprises a differential input coupled to a second sensing point along the signal path of the chopper amplifier circuit 1. In some embodiments, the first sensing point is before the input chopper circuit 3 and the second sensing point is after the output chopper circuit 4.

The first sense amplifier 13 and the second sense amplifier 14 may each include one or more stages.

In some embodiments, the input stage of the first sense amplifier 13 includes a copy of the n-type pair 7 and a copy of the p-type pair 8 with or without scaling.

As shown in fig. 5, the output signal from the first sense amplifier 13 and the output signal from the second sense amplifier 14 are combined and then chopped using the chopper circuit 16 to produce a combined sense signal that is input to the ADC 23. In some embodiments, the output signal from the first sense amplifier 13 and the output signal from the second sense amplifier 14 correspond to the current flowing through the resistor 15 to produce the input voltage signal for the chopper circuit 16.

The input offset correction circuit herein may be implemented using a variety of sensing configurations, including configurations using one or more feedback paths, one or more feed-forward paths, or a combination thereof.

Fig. 6 is a schematic diagram of a chopper amplifier 70 according to another embodiment. The chopper amplifier 70 includes a chopper amplifier circuit 61 and an offset correction circuit 62. Chopper amplifier 70 also includes a pair of input terminals for receiving a differential input voltage V_SigDifferential input terminal V_IN+、V_IN-And a single-ended output terminal V for outputting a single-ended output voltage_OUT。

In the illustrated embodiment, chopper amplifier circuit 61 includes a common mode detection circuit 51, an input chopper circuit 53 (driven by a chopping clock signal CLK)_CHOPControl), p-type transconductance amplifier G_m1p(including having the voltage supplied by voltage source V_OSPP-type input pair of input offset voltages indicated), n-type transconductance amplifier G_m1n(comprising an n-type input pair with an input offset voltage, the input offset voltage being provided by a voltage source V_OSNShown), an output chopper circuit 54 (with a chopped clock signal CLK)_CHOPControl), a second transconductance amplifier G_m2A first resistor R_CA1A second resistor R_CA2A first capacitor C_CAAnd a second capacitor C_CB。

With continued reference to fig. 6, the common mode detection circuit 51 senses a pair of differential input terminals V_IN+、V_IN-And enabling the p-type transconductance amplifier G according to the detected common-mode input voltage_m1pOr n-type transconductance amplifier G_m1nOne of them. Using a first enable signal N_ENOr the second enabling signal P_ENThe selected transconductance amplifier is enabled. Selected transconductance amplifier output differential signal current I_m1。

Although one embodiment of chopper amplifier circuit 61 is depicted, the teachings herein are applicable to chopper amplifier circuits implemented in a variety of ways. Thus, other implementations are possible.

With continued reference to FIG. 6, the offset correction circuit 62 includes components with or without scalingReplica transconductance amplifier G_m1NRepCorresponding to an n-type transconductance amplifier G_m1nA copy of (1). Offset correction circuit 62 includes a p-type transconductance amplifier G with or without scaling_m1pReplica transconductance amplifier G corresponding to (1)_m1PRep. The offset correction circuit 62 further includes a first resistor R_CARepThe first resistor R_CARepCorresponding to the first resistor R_CA1And a second resistor R_CA2With or without scaling.

The offset correction circuit 62 further includes a first sensing transconductance amplifier G_mS1Second sensing transconductance amplifier G_mS2A second resistor R_SChopper circuit 55, comparator 56, digital circuit 57 (including for G)_m1nFor G, first counter 67 of_m1pA multiplexer 69) and a current dac (idac) 58. Comparator 56 acts as a 1-bit ADC that generates up and down signals that control the state of the active counters of digital circuit 57. The digital circuit 57 outputs digital correction data selected by the multiplexer 69 from the first counter 67 or the second counter 68. The digital correction data is used by current DAC 58 to generate a differential correction current I_Corr。

In the illustrated embodiment, chopper circuit 55 is driven by a chopper clock signal CLK_CHOPIs clocked by the comparator clock signal CLK and the comparator 56 is clocked by the comparator clock signal CLK_COMPProviding a clock, the digital circuit 57 being clocked by the counter clock signal CLK_COUNTA clock is provided. In some embodiments, the comparator clock signal CLK_COMPAnd/or counter clock signal CLK_COUNTBy delaying the chopped clock signal CLK_CHOPOr a divided version thereof. In the example of fig. 6, current DAC 58 is responsive to changes in the digitally corrected data, rather than being driven by a clock signal. Although one example of a clock is shown, the offset correction circuit may be clocked in a number of ways.

With continued reference to FIG. 6, the first enable signal N_ENAnd a second enable signal P_ENIs provided to offset correction circuit 62 to assist inThe input offset of the selected pair of input transistors is tracked. For example, the first enable signal N_ENFor selectively enabling G_m1NRepAnd a first counter 67, and a second enable signal P_ENFor selectively enabling G_m1PRepAnd a second counter 68. In addition, the multiplexer 69 uses the first enable signal N_ENAnd a second enable signal P_ENTo select which counter output is provided as the digital correction data for the current DAC 58.

As shown in fig. 6, the offset correction circuit 62 is at the differential input of the input chopper circuit 53 and at the first resistor R_CA1And a second resistor R_CA2Sense the signal path (corresponding to V) of the chopper amplifier circuit 61 on both of the series combinations of_S2PAnd V_S2NVoltage difference therebetween). In addition, the offset correction circuit 62 corrects the differential correction current I_CorrInjected into the chopper amplifier circuit 61 so that the current I is differentially corrected_CorrAnd differential signal current I_m1And (4) combining.

The use of multiple sensing points has many advantages, including providing a low input offset voltage at chopping and excellent gain and frequency characteristics (including the frequency used at chopping). However, the teachings herein are also applicable to embodiments using a single sensing point.

Thus, although one embodiment of offset correction circuit 62 is shown, the teachings herein are applicable to offset correction circuits implemented in a variety of ways. Thus, other implementations are possible.

Fig. 7 is a schematic diagram of one embodiment of an amplification circuit 130 for a chopper amplifier.

The amplifying circuit 130 includes a pair of NMOS input transistors 101, a pair of PMOS input transistors 102, a pair of PMOS isolation switches 103a, a pair of NMOS isolation switches 103b, a first input chop switch 104a, a second input chop switch 104b, a common mode detection circuit 105, a first set of current sources 107, 108a, and 108b, a second set of current sources 109, 110a, and 110b, a first cascode PMOS transistor 113a, a second cascode PMOS transistor 113b, a first cascode NMOS transistor 114a, a second cascode NMOS transistor 114bA third set of current sources 115a and 115b, a fourth set of current sources 116a and 116b, a first voltage source 117 and a second voltage source 118. The amplifying circuit 130 further includes: a pair of input terminals (IN +, IN-) and a pair of output terminals (OUT +, OUT-), driven by a high supply voltage V_DDAnd a low supply voltage V_SSAnd (5) supplying power.

In the illustrated embodiment, the pair of NMOS input transistors 101 is implemented as a differential transistor pair comprising a first NMOS input transistor 121a and a second NMOS input transistor 121b, each comprising a common bias current I connected to each other and from a current source 107_NA biased source. In addition, the drain of the first NMOS input transistor 121a is biased by the bias current I from the current source 108a_N2 bias and the drain of the second NMOS input transistor 121b is biased by the bias current I from the current source 108b_NAnd/2 biasing.

The pair of PMOS isolation switches 103a includes a first PMOS isolation switch 123a and a second PMOS isolation switch 123 b. The drains of PMOS isolation switches 123a-123b are connected to IN + and IN-, respectively, and the sources of PMOS isolation switches 123a-123b are connected to the gates of NMOS input transistors 121a-121b, respectively, through first input chopper switch 104 a. The gates of the PMOS isolation switches 123a-123b are enabled by the first inverted enable signal N from the common mode detection circuit 105_ENBAnd (5) controlling.

With continued reference to fig. 7, the pair of PMOS input transistors 102 is implemented as a differential transistor pair comprising a first PMOS input transistor 122a and a second PMOS input transistor 122b, each comprising a common bias current I connected to each other and from a current source 109_PA biased source. In addition, the drain of the first PMOS input transistor 122a is biased by the bias current I from the current source 110a_P2 bias and the drain of the second PMOS input transistor 122b is biased by the bias current I from the current source 110b_PAnd/2 biasing.

The pair of NMOS isolation switches 103b includes a first NMOS isolation switch 124a and a second NMOS isolation switch 124 b. The drains of the NMOS isolation switches 124a-124b are connected to IN + and IN-, respectively, and the sources of the NMOS isolation switches 124a-124b are connected to the gates of the PMOS input transistors 122a-122b, respectively, through the second input chopping switch 104 b. NMOS spacerThe gates of the switches 124a-124b are controlled by a second enable signal P from the common mode detection circuit 105_ENAnd (5) controlling.

IN the depicted embodiment, the common mode detection circuit 105 is coupled to a pair of input terminals (IN +, IN-) to sense the input common mode voltage. Based on the sensed input common mode voltage, the common mode detection circuit 105 uses the first enable signal N_ENSelecting a pair of NMOS input transistors 101, or using a second enable signal P_ENA pair of PMOS input transistors 102 is selected. After the first input chopping switch 104a or the second input chopping switch 104b chops, the selected pair of input transistors amplifies the differential input signal received between IN + and IN-.

As shown in FIG. 7, the first and second input chop switches 104a and 104b are each chopped clock signals CLK_CHOPAnd (5) controlling. In the depicted embodiment, a separate set of input chopping switches is used for the n-type input pair 101 and the p-type input pair 102. In other embodiments, a shared set of chopping switches is used. Any of the embodiments herein may use shared or separate input chopping switches. Also, any of the embodiments herein may use shared or separate output chopping switches.

When a pair of NMOS input transistors 101 is used, the common mode detection circuit 105 turns on a pair of PMOS isolation transistors 103a, and turns on the first set of current sources 107, 108a, and 108 b. However, when the pair of NMOS input transistors 101 is not used, the common mode detection circuit 105 turns off the pair of PMOS isolation transistors 103a, and turns off the first group current sources 107, 108a, and 108 b.

With continued reference to fig. 7, when a pair of PMOS input transistors 102 is used, the common mode detection circuit 105 turns on a pair of NMOS isolation transistors 103b and turns on the second set of current sources 109, 110a, and 110 b. However, when the pair of PMOS transistors 102 is not used, the common mode detection circuit 105 turns off the pair of NMOS isolation transistors 103b, and turns off the second group current sources 109, 110a, and 110 b.

The inclusion of PMOS isolation transistor 103a and NMOS isolation transistor 103b helps to reduce the input capacitance. However, the teachings herein are also applicable to embodiments without isolation transistors.

One example of a folded cascode circuit is described as being coupled to a pair of NMOS input transistors 101 and the pair of PMOS input transistors 102. The folded cascode circuit shows one example of a circuit adapted to provide an output signal from a pair of NMOS input transistors 101 and an output signal from a pair of PMOS input transistors 102 to a common pair of output terminals (OUT +, OUT-). However, other implementations of the circuit are possible.

Fig. 8 is a schematic diagram of one example of a chopping switch 210 that may be used in a chopping amplifier. However, chopping switches may be implemented in other ways.

As shown in fig. 8, the chopping switch 210 includes first and second inputs 201a, 201b serving as differential inputs, first and second outputs 202a, 202b serving as differential outputs, first to fourth switches 203a to 203d, and a switch control circuit 204. As shown in FIG. 8, the switch control circuit 204 receives the chopped clock signal CLK_CHOPThe chopped clock signal CLK_CHOPMay be used to control the state of the switches 203a-203d over time. Although shown as including switch control circuit 204, in some configurations, switch control circuit 204 is omitted in order to provide multiple clock signals (e.g., inverted and non-inverted versions of the chopping clock signals, with or without non-overlap) to chopping switches 210.

The first input 201a is electrically connected to a first terminal of a first switch 203a and a first terminal of a second switch 203 b. The second input 201b is electrically connected to a first terminal of a third switch 203c and a first terminal of a fourth switch 203 d. The first output 202a is electrically connected to a second terminal of the second switch 203b and a second terminal of the third switch 203 c. The second output 202b is electrically connected to a second terminal of the first switch 203a and a second terminal of the fourth switch 203 d.

Chopping switch 210 may be used to chop a differential input signal received between first input 201a and second input 201b to generate a differential chopped signal between first output 202a and second output 202 b. For example, in chopping the clock signal CLK_CHOPThe switch control circuit 204 may close the second and fourth switches 203b, 2 during the first clock phase of (a)03d and opens the first and third switches 203a, 203 c. In addition, in chopping the clock signal CLK_CHOPThe switch control circuit 204 may close the first and third switches 203a, 203c and open the second and fourth switches 203b, 203d during the second clock phase.

The clock signals disclosed herein may be implemented in a variety of ways, including, for example, by using any suitable clock generator. In some embodiments, the common clock signal is used to synthesize clock signals for chopping, auto-zeroing, digital processing, and/or other operations of the chopper amplifier.

Applications of

The device adopting the above scheme can be implemented as various electronic devices. Examples of electronic devices include, but are not limited to, consumer electronics, electronic test equipment, communication systems, data converters, and the like.

Conclusion

The foregoing description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematic diagrams shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments have been presented in a given arrangement, alternative embodiments may perform similar functions with different components and/or circuit topologies, and certain elements may be deleted, moved, added, subdivided, combined, and/or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the invention is to be defined only by reference to the following claims.

Although the claims presented herein are filed in a single claim format at the United States Patent and Trademark Office (USPTO), it is to be understood that any claim may be dependent upon any claim of the same type previously unless it is clearly not feasible in the art.