阅读说明：本技术 使用过基板通孔或过模具通孔以及rdl来实现的baw滤波器和3d电感器的共同封装 (Co-packaging of BAW filters and 3D inductors using through-substrate vias or through-mold vias and RDLs ) 是由 刘凯 唐瑞 C·H·芸 M·F·维勒兹 金钟海 于 2020-01-17 设计创作，主要内容包括：本公开的各方面涉及一种带通滤波器,其包括在输入端子和输出端子处具有两个匹配电感器的全晶格布置中的四个BAW谐振器。本公开的另外方面涉及将BAW滤波器芯片与嵌入式3D电感器组合。通过将正面和背面RDL(960、970、980；1667、1675)与过模具通孔、TMV(930)、或过基板通孔(1630)进行组合来将3D电感器嵌入模具(850)或载体基板(1610)中。BAW芯片与TMV电感器位于同一模具中,或位于包含TSV电感器的载体基板上。(Aspects of the present disclosure relate to a band pass filter that includes four BAW resonators in a full lattice arrangement with two matched inductors at the input and output terminals. Further aspects of the disclosure relate to combining BAW filter chips with embedded 3D inductors. The 3D inductor is embedded in the mold (850) or carrier substrate (1610) by combining front and back RDLs (960, 970, 980; 1667, 1675) with over-mold vias, TMV (930), or over-substrate vias (1630). The BAW chip is located in the same mold as the TMV inductor, or on a carrier substrate containing the TSV inductors.)

1. A method for forming one or more individual bandpass filters on an Integrated Circuit (IC), the method comprising:

positioning a first redistribution layer (RDL) in a wafer layer on the Integrated Circuit (IC);

placing one or more vertical conductive pillars over the wafer layer;

forming a plurality of inductors by applying a first passivation layer onto the wafer layer;

plating a second redistribution layer (RDL) on the first passivation layer; and

coating a second passivation layer over the second redistribution layer (RDL).

2. The method of claim 1, wherein the wafer layer is a molded wafer layer.

3. The method of claim 1, wherein the one or more vertical conductive pillars are copper (Cu) pillars or aluminum (Al) pillars.

4. The method of claim 1, wherein the wafer layer is a High Resistivity Silicon (HRS) wafer, a gallium arsenide (GaAs) wafer, or a glass wafer.

5. The method of claim 1, further comprising: assembling a plurality of resonator chips onto the wafer layer.

6. The method of claim 5, wherein one of the plurality of resonator chips is a Bulk Acoustic Wave (BAW) resonator.

7. The method of claim 5, further comprising: the wafer layer is covered with a molding material to form a molded wafer layer.

8. The method of claim 7, wherein the molding material is an epoxy.

9. The method of claim 7, further comprising: a transfer molding process or a compression molding process is used to cover the wafer layer with the molding material.

10. The method of claim 7, further comprising: the molded wafer layer is back ground to expose the one or more vertical conductive pillars.

11. The method of claim 7, further comprising: an interconnect layer is formed over the second passivation layer.

12. The method of claim 11, wherein the interconnect layer comprises one or more of solder balls or conductive pads.

13. The method of claim 11, further comprising: dicing the Integrated Circuit (IC) to obtain the one or more individual bandpass filters.

14. A method for forming one or more individual bandpass filters on an Integrated Circuit (IC), the method comprising:

forming a Through Glass Via (TGV) within a wafer level on the Integrated Circuit (IC);

coating a first passivation layer on top of the wafer layer;

placing a first redistribution layer (RDL) over the first passivation layer, wherein the first RDL is placed over one or more vertical conductive pillars;

flipping the Integrated Circuit (IC);

coating the wafer layer with a second passivation layer; and

a second redistribution layer (RDL) is placed over the second passivation layer to form a plurality of inductors.

15. The method of claim 14, wherein the wafer layer is a High Resistivity Silicon (HRS) wafer, a gallium arsenide (GaAs) wafer, or a glass wafer.

16. The method of claim 14, further comprising: filling the Through Glass Vias (TGVs) with a metallization layer to form the one or more vertical conductive pillars.

17. The method of claim 16, wherein the metal plating is copper plating.

18. The method of claim 14, further comprising: the one or more vertical conductive pillars are formed by a laser drilling process or an etching process.

19. The method of claim 18, further comprising: the one or more vertical conductive pillars are formed by a copper plating process or a conductive paste filling process.

20. The method of claim 14, further comprising: coating a third passivation layer over the first redistribution layer (RDL) and exposing a portion of the third passivation layer for assembling one or more resonator chips.

21. The method of claim 20, further comprising: one or more interconnect pads are placed over the third passivation layer using a plating process.

22. The method of claim 21, wherein the one or more resonator chips are assembled on top of the one or more interconnect pads.

23. The method of claim 22, wherein the one or more resonator chips are a plurality of Bulk Acoustic Wave (BAW) resonators.

24. The method of claim 22, further comprising: covering the third passivation layer and the one or more resonator chips with a molding material.

25. The method of claim 24, wherein the molding material is an epoxy.

26. The method of claim 24, further comprising: using a transfer molding process or a compression molding process to cover the third passivation layer and the one or more resonator chips with the molding material.

27. The method of claim 24, further comprising:

coating a fourth passivation layer over the second RDL; and

an interconnect layer is created over the fourth passivation layer.

28. The method of claim 27, further comprising: one or more conductive pads or solder balls are added for creating the interconnect layer.

29. The method of claim 27, further comprising: dicing the Integrated Circuit (IC) to obtain the one or more individual bandpass filters.

30. A bandpass filter in an Integrated Circuit (IC), comprising:

a plurality of resonators including a first resonator, a second resonator, a third resonator, and a fourth resonator, wherein the second resonator and the third resonator are connected in parallel, an

Wherein the first resonator comprises a first terminal and a second terminal,

wherein the second resonator comprises a second resonator top terminal and a second resonator bottom terminal,

wherein the third resonator comprises a third resonator top terminal and a third resonator bottom terminal,

wherein the fourth resonator comprises a third terminal and a fourth terminal, an

Wherein the first terminal is coupled to the second resonator top terminal,

wherein the second terminal is coupled to the third resonator top terminal,

wherein the third terminal is coupled to the third resonator bottom terminal,

wherein the fourth terminal is coupled to the second resonator bottom terminal; and

a first inductor coupled to the first terminal and the third terminal; and

a second inductor coupled to the second terminal and the fourth terminal.

31. A computer-readable medium storing computer-executable code operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement one or more individual band pass filters on an Integrated Circuit (IC), the computer-executable code comprising:

instructions for causing a computer to position a first redistribution layer (RDL) in a wafer layer on the Integrated Circuit (IC);

instructions for causing the computer to place one or more vertical conductive pillars over the wafer layer;

instructions for causing the computer to assemble a plurality of resonator chips onto the wafer layer;

instructions for causing the computer to cover the wafer layer with a molding material to form a molded wafer layer;

instructions for causing the computer to form a plurality of inductors by coating a first passivation layer onto the molded wafer layer, by plating a second redistribution layer (RDL) over the first passivation layer, and by coating a second passivation layer over the second RDL;

instructions for causing the computer to form an interconnect layer over the second passivation layer; and

instructions for causing the computer to cut the Integrated Circuit (IC) to obtain one or more individual band pass filters.

32. A computer-readable medium storing computer-executable code operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement one or more individual band pass filters on an Integrated Circuit (IC), the computer-executable code comprising:

instructions for causing a computer to form a Through Glass Via (TGV) within a wafer layer on the Integrated Circuit (IC);

instructions for causing the computer to coat a first passivation layer on top of the wafer layer and place a first redistribution layer (RDL) over the first passivation layer, wherein the first RDL is placed on one or more vertical conductive pillars;

instructions for causing the computer to coat a second passivation layer over the first RDL and expose a portion of the second passivation layer to assemble one or more resonator chips;

instructions for causing the computer to place one or more interconnect pads over the second passivation layer using a plating process;

instructions for causing the computer to cover the second passivation layer and the one or more resonator chips with a molding material;

instructions for causing the computer to flip the Integrated Circuit (IC), coat the wafer layer with a third passivation layer, and place a second RDL over the third passivation layer to form a plurality of inductors;

instructions for causing the computer to apply a fourth passivation layer over the second RDL and create an interconnect layer over the fourth passivation layer; and

instructions for causing the computer to cut the Integrated Circuit (IC) to obtain one or more individual band pass filters.

Technical Field

The present disclosure relates generally to the field of wideband filtering, and in particular to wideband filters having resonator(s) and inductor(s).

Background

A band pass filter is a circuit element for selective signal transmission. One band-pass filter used at microwave frequencies is a Bulk Acoustic Wave (BAW) filter. Some implementations of BAW filters have a limited passband width, typically less than 100 MHz. Broadband applications, such as fifth generation (5G) wireless communication systems, require BAW filter implementations with wider passband widths (e.g., up to 400 MHz).

Disclosure of Invention

The following presents a simplified summary of one or more aspects of the disclosure in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated features of the disclosure, and is intended to neither identify key or critical elements of all aspects of the disclosure, nor delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

In one aspect, the present disclosure provides a wideband filter having resonator(s) and inductor(s). Thus, a method of forming one or more individual bandpass filters on an Integrated Circuit (IC), the method comprising: positioning a first redistribution layer (RDL) in a wafer layer on an Integrated Circuit (IC); placing one or more vertical conductive pillars over a wafer layer; forming a plurality of inductors by applying a first passivation layer onto a wafer layer; plating a second redistribution layer (RDL) on the first passivation layer; and coating a second passivation layer over the second redistribution layer (RDL).

In one example, the wafer layer is a molded wafer layer. In one example, the one or more vertical conductive pillars are copper (Cu) pillars or aluminum (Al) pillars. In one example, the wafer layer is a High Resistivity Silicon (HRS) wafer, a gallium arsenide (GaAs) wafer, or a glass wafer.

In one example, the method further comprises: a plurality of resonator chips are assembled onto a wafer level. In one example, one of the plurality of resonator chips is a Bulk Acoustic Wave (BAW) resonator. In one example, the method further comprises: the wafer layer is covered with a molding material to form a molded wafer layer. In one example, the molding material is an epoxy.

In one example, the method further comprises: a transfer molding process or a compression molding process is used to cover the wafer layer with a molding material. In one example, the method further comprises: the molded wafer layer is back ground to expose the one or more vertical conductive pillars. In one example, the method further comprises: an interconnect layer is formed over the second passivation layer. In one example, the interconnect layer includes solder balls or conductive pads. In one example, the method further comprises: the Integrated Circuit (IC) is diced to obtain one or more individual bandpass filters.

Another aspect of the disclosure provides a method for forming one or more individual bandpass filters on an Integrated Circuit (IC), the method comprising: forming a Through Glass Via (TGV) within a wafer level on an Integrated Circuit (IC); coating a first passivation layer on top of the wafer layer; placing a first redistribution layer (RDL) over the first passivation layer, wherein the first RDL is placed over the one or more vertical conductive pillars; a flip Integrated Circuit (IC); coating the wafer layer with a second passivation layer; a second redistribution layer (RDL) is placed over the second passivation layer to form a plurality of inductors.

In one example, the wafer layer is a High Resistivity Silicon (HRS) wafer, a gallium arsenide (GaAs) wafer, or a glass wafer. In one example, the method further comprises: the Through Glass Vias (TGVs) are filled by a metallization layer to form one or more vertical conductive pillars. In one example, the metal plating is copper plating.

In one example, the method further comprises: one or more vertical conductive pillars are formed by a laser drilling process or an etching process. In one example, the method further comprises: one or more vertical conductive pillars are formed by a copper plating process or a conductive paste filling process. In one example, the method further comprises: a third passivation layer is coated over the first redistribution layer (RDL) and a portion of the third passivation layer is exposed for assembly of the one or more resonator chips.

In one example, the method further comprises: one or more interconnect pads are placed over the third passivation layer using a plating process. In one example, one or more resonator chips are assembled on top of one or more interconnect pads. In one example, the one or more resonator chips are a plurality of Bulk Acoustic Wave (BAW) resonators. In one example, the method further comprises: the third passivation layer and the one or more resonator chips are covered with a molding material. In one example, the molding material is an epoxy.

In one example, the method further comprises: a transfer molding process or a compression molding process is used to cover the third passivation layer and the one or more resonator chips with a molding material. In one example, the method further comprises: coating a fourth passivation layer over the second RDL; and creating an interconnect layer over the fourth passivation layer. In one example, the method further comprises: one or more conductive pads or solder balls are added for creating the interconnect layer. In one example, the method further comprises: the Integrated Circuit (IC) is diced to obtain one or more individual bandpass filters.

Another aspect of the present disclosure provides a bandpass filter in an Integrated Circuit (IC), comprising a plurality of resonators, the resonators include a first resonator, a second resonator, a third resonator and a fourth resonator, and wherein the second resonator and the third resonator are connected in parallel, and wherein the first resonator comprises a first terminal and a second terminal, wherein the second resonator comprises a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator comprises a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator comprises a third terminal and a fourth terminal, wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to a third resonator top terminal, wherein the third terminal is coupled to a third resonator bottom terminal, wherein the fourth terminal is coupled to a second resonator bottom terminal; and a first inductor coupled to the first terminal and the third terminal; and a second inductor coupled to the second terminal and the fourth terminal.

Another aspect of the disclosure provides a computer-readable medium storing computer-executable code operable on an apparatus comprising at least one processor configured to implement one or more individual band pass filters on an Integrated Circuit (IC) and at least one memory coupled to the at least one processor, the computer-executable code comprising instructions for causing a computer to position a first redistribution layer (RDL) in a wafer layer on the Integrated Circuit (IC); instructions for causing a computer to place one or more vertical conductive pillars over a wafer layer; instructions for causing a computer to assemble a plurality of resonator chips onto a wafer layer; instructions for causing a computer to cover the wafer layer with a molding material to form a molded wafer layer; instructions for causing a computer to form a plurality of inductors by coating a first passivation layer onto a molded wafer layer, by plating a second redistribution layer (RDL) over the first passivation layer, and by coating a second passivation layer over the second RDL; instructions for causing a computer to form an interconnect layer over the second passivation layer; and instructions for causing a computer to cut an Integrated Circuit (IC) to obtain one or more individual band pass filters.

Another aspect of the disclosure provides a computer-readable medium storing computer-executable code operable on an apparatus comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement one or more individual band pass filters on an Integrated Circuit (IC), the computer-executable code comprising instructions for causing a computer to form a Through Glass Via (TGV) within a wafer level on the Integrated Circuit (IC); instructions for causing a computer to coat a first passivation layer on top of a wafer layer and place a first redistribution layer (RDL) over the first passivation layer, wherein the first RDL is placed on one or more vertical conductive pillars; instructions for causing a computer to coat a second passivation layer over the first RDL and expose a portion of the second passivation layer to assemble one or more resonator chips; instructions for causing a computer to place one or more interconnect pads over the second passivation layer using a plating process; instructions for causing a computer to cover the second passivation layer and the one or more resonator chips with a molding material; instructions for causing a computer to flip an Integrated Circuit (IC), coat a wafer layer with a third passivation layer, and place a second RDL over the third passivation layer to form a plurality of inductors; instructions for causing a computer to coat a fourth passivation layer over the second RDL and create an interconnect layer over the fourth passivation layer; and instructions for causing a computer to cut an Integrated Circuit (IC) to obtain one or more individual band pass filters.

These and other aspects of the disclosure will be more fully understood upon reading the following detailed description. Other aspects, features and implementations of the present disclosure will become apparent to those ordinarily skilled in the art upon review of the following description of specific exemplary implementations of the disclosure in conjunction with the accompanying figures. While features of the invention may be discussed with respect to certain implementations and figures below, all implementations of the invention may include one or more of the advantageous features discussed herein. In other words, while one or more implementations may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various implementations of the invention discussed herein. In a similar manner, while exemplary implementations may be discussed below as device, system, or method implementations, it should be understood that such exemplary implementations may be implemented in a variety of devices, systems, and methods.

Drawings

Fig. 1 illustrates an exemplary diagram of a filter transfer function of a Bulk Acoustic Wave (BAW) filter.

Figure 2 illustrates an example of a band pass filter having a combination of Bulk Acoustic Wave (BAW) resonators and inductors.

Figure 3 illustrates an example of an electrical schematic of a bandpass filter with a combination of resonators and inductors.

Figure 4 illustrates an example filter transfer function for a bandpass filter having a combination of resonators and inductors.

Figure 5 illustrates an example implementation of a bandpass filter with a combination of on-chip resonators and inductors.

Figure 6 illustrates an example first step of a first Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors.

Figure 7 illustrates an example second step of a first Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors.

Figure 8 illustrates an example third step of a first Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors.

Figure 9 illustrates an example fourth step of a first Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors.

Figure 10 illustrates an example top view of a first Integrated Circuit (IC) process for a bandpass filter with a combination of on-chip resonators and inductors.

Figure 11 illustrates an example fifth step of a first Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors.

Figure 12 illustrates an example first step of a second Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors.

Figure 13 illustrates an example second step of a second Integrated Circuit (IC) process for a bandpass filter with a combination of on-chip resonators and inductors.

Figure 14 illustrates an example third step of a second Integrated Circuit (IC) process for a bandpass filter with a combination of on-chip resonators and inductors.

Figure 15 illustrates an example fourth step of a second Integrated Circuit (IC) process for a band pass filter having a combination of on-chip resonators and inductors.

Figure 16 illustrates an example fifth step of a second Integrated Circuit (IC) process for a bandpass filter with a combination of on-chip resonators and inductors.

Figure 17 illustrates an example sixth step of a second Integrated Circuit (IC) process for a band pass filter having a combination of on-chip resonators and inductors.

Figure 18 illustrates an example of a first Integrated Circuit (IC) process flow for fabricating a bandpass filter with a combination of on-chip resonators and inductors within an Integrated Circuit (IC).

Figure 19 illustrates an example of a second Integrated Circuit (IC) process flow for fabricating a bandpass filter with a combination of on-chip resonators and inductors within an Integrated Circuit (IC).

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

While, for purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated that the methodologies are not limited by the order of acts, as some acts may, in accordance with one or more aspects, occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with one or more aspects.

Electrical circuits using passive and active circuit elements are widely used to implement a variety of signal processing functions. In one example, the signal processing function may be described in the time domain (i.e., as a function of time) or in the frequency domain (i.e., as a function of frequency). For example, in the frequency domain, a signal may be described by a frequency spectrum, e.g., an amplitude response and a phase response with frequency. A filter is a circuit element that relies on frequency domain characteristics, such as a filter transfer function for transforming an input spectrum of an input signal to an output spectrum of an output signal. There are many different filter examples such as low pass filters, high pass filters, band stop filters, etc.

In one example, an electrical circuit packageIncluding a Radio Frequency Front End (RFFE) module that may have a power amplifier, a low noise amplifier, switches, filters, and/or transformers, etc. In one example, a band pass filter is a circuit element in an electrical circuit that can be used to selectively transmit or reject a signal depending on the spectrum of the signal. For example, the signal may have a frequency f at a frequency from low_LOWTo high frequencies f_HIGHHas a spectrum with a significant energy distribution in the frequency range of (a). A first key feature of a band-pass filter is its passband, i.e., the first frequency range transmitted through the band-pass filter. For example, the pass band may be specified by a frequency value having a half-power response, e.g., a-3 dB magnitude response point.

The second key feature of a band-pass filter is its stopband. The stop band is the second frequency range rejected by the band pass filter. A third key feature of the band-pass filter is its roll-off (roloff). Roll-off is the attenuation slope (e.g., dB/MHz) of the transition from the passband of the bandpass filter to the stopband of the bandpass filter. A fourth key feature of a bandpass filter is its insertion loss. The insertion loss is the amount of attenuation over the passband of the bandpass filter. In one example, roll-off (attenuation slope) and insertion loss may be trade-off parameters in bandpass filter design. For example, cascading (i.e., series connection) of individual bandpass filter devices may allow for a tradeoff between higher roll-off and lower insertion loss.

In one example, bandpass filter implementations in the microwave frequency region (e.g., about 1GHz to 10GHz) can include Surface Acoustic Wave (SAW) filters and Bulk Acoustic Wave (BAW) filters. For example, a bandpass filter may be implemented using multiple resonators. A resonator is a device that exhibits frequency resonance. In one example, a SAW filter may be implemented using a plurality of SAW resonators. In one example, a BAW filter may be implemented using a plurality of BAW resonators. These SAW/BAW filters can provide sharp roll-off but have relatively narrow band-pass filtering, e.g., providing a pass-band of about 100MHz at a center frequency of about 3GHz to 6 GHz. Those skilled in the art will appreciate that the pass band and center frequency set forth herein are merely examples and that the present disclosure is not limited to the examples disclosed herein.

Alternatively, a narrow band may be defined as a pass band that is less than 5% of the center frequency. However, in some cases (e.g., 5G wireless applications), a band-pass filter with relatively wideband band-pass filtering (e.g., a pass-band up to 400MHz) is desired. Alternatively, the wideband may be defined as a pass band greater than 5% of the center frequency. In some examples, SAW/BAW filters cannot provide such broadband performance. The present disclosure provides bandpass filter implementations for broadband bandpass filtering in a microwave frequency region (e.g., greater than 5% of the center frequency) with broadband performance.

Fig. 1 illustrates an example graph 100 of a filter transfer function of a Bulk Acoustic Wave (BAW) filter. In the example graph 100, the vertical axis shows the magnitude response in decibels (dB) and the horizontal axis shows the frequency range in MHz. In fig. 1, the magnitude response of the BAW filter in the frequency range 1560MHz to 1935MHz is shown to be in the range-70 dB to 0 dB. In the example graph 100, the pass-band width (e.g., between-3 dB amplitude response points) is relatively narrow-band (e.g., less than 100MHz in width).

In one example, the pass band may be specified as a relative bandwidth. The relative bandwidth may be defined as the ratio of the pass band width to the center frequency. In the example graph 100, the fractional bandwidth is less than 5% in this case (i.e., the 75MHz passband width at the 1745MHz center frequency is about 4.3% fractional bandwidth). Fig. 1 shows that the filter transfer function includes a sharp roll-off from pass-band to stop-band without achieving a wide pass-band (e.g., a bandwidth greater than 100 MHz). That is, the filter transfer function of the BAW filter includes a sharp roll-off from the pass band to the stop band, where the pass band bandwidth is less than 100 MHz.

Figure 2 illustrates an example of a band pass filter 200 having a combination of Bulk Acoustic Wave (BAW) resonators and inductors. In one example, the inductor is a three-dimensional (3D) inductor. In the bandpass filter 200, a low-loss substrate (e.g., a glass wafer) may be used to implement the high-Q inductor through a metal plating process. In one example, a high Q (i.e., high quality) inductor is an inductor with a highly resonant behavior. For example, BAW resonator processes cannot be used to implement inductors, such as high Q inductors. In one example, the packaging method of integrating BAW resonators and inductors forms a broadband bandpass filter with sharp roll-off.

Figure 3 illustrates an example of an electrical schematic of a bandpass filter 300 having a combination of resonators and inductors. In one example, the band pass filter 300 includes four resonators: a first resonator 310, a second resonator 320, a third resonator 330 and a fourth resonator 340. Those skilled in the art will appreciate that although four resonators are shown, other numbers of resonators may be used within the scope and spirit of the present disclosure.

In one example, the first resonator 310 is a first BAW resonator, the second resonator 320 is a second BAW resonator, the third resonator is a third BAW resonator, and the fourth resonator is a fourth BAW resonator. Although BAW resonators are disclosed herein, in some examples, other types of resonators may be used, such as, but not limited to, Surface Acoustic Wave (SAW) resonators.

In one example, the third resonator 330 includes a first terminal 331 and a second terminal 332. And, the fourth resonator 340 includes a first terminal 342 and a second terminal 342. In one example, the first resonator 310 is connected to a first terminal 331 of the third resonator 330, and the second resonator 320 is connected to a second terminal 332 of the third resonator 330, as shown in fig. 3. In one example, the first resonator 310 is also connected to the second terminal 342 of the fourth resonator 340, while the second resonator 320 is also connected to the first terminal 341 of the fourth resonator 340, as shown in fig. 3.

In one example, the band pass filter 300 includes two inductors: a first inductor 350 and a second inductor 360. In one example, the first inductor 350 is a first 3D inductor and the second inductor 360 is a second 3D inductor. In one example, the first inductor 350 is connected to the first terminal 331 of the third resonator 330 and the first terminal 341 of the fourth resonator 340. And the second inductor 360 is connected to the second terminal 332 of the third resonator 330 and to the second terminal 342 of the fourth resonator 340. Those skilled in the art will appreciate that although two inductors are shown in fig. 3, other numbers of inductors may be used within the scope and spirit of the present disclosure.

In one example, the band pass filter 300 includes two resistors: a first resistor 370 and a second resistor 380. In one example, the first resistor 370 is in parallel with the first inductor 350 and the second resistor 380 is in parallel with the second inductor 360. In one example, the impedance of the first resistor 370 and the second resistor 380 is 50 ohms. Those skilled in the art will appreciate that other values of the first resistor 370 and the second resistor 380 may be used within the scope and spirit of the present disclosure. Those skilled in the art will appreciate that although two resistors are shown in fig. 3, other numbers of resistors may be used within the scope and spirit of the present disclosure.

Figure 4 illustrates an example filter transfer function 400 for a bandpass filter having a combination of resonators and inductors. With respect to fig. 4, the vertical axis shows the amplitude response, while the horizontal axis shows the frequency range. In the example shown in fig. 4, the amplitude response in decibels (dB) of the bandpass filter is shown to be within a frequency range between 1GHz and 8 GHz. In one example, the magnitude response from the filter input to the filter output is labeled as having two components: s (1,2) as a transfer function from the filter input to the filter output and S (1,1) as a reflection function of the filter input. In this example, the pass band width (e.g., between-3 dB amplitude response points) is relatively wide, e.g., greater than 400MHz in width. For example, at a frequency of 3.460GHz, the amplitude shown is-0.725 dB, while at a frequency of 3.860GHz, the amplitude response shown is-0.666 dB. In one example, the relative bandwidth is greater than 10% in this case. In one example, a sharp roll-off of the band-pass filter is obtained.

Figure 5 illustrates an example implementation of a bandpass filter 500 having a combination of on-chip resonators and inductors. For example, the chip is a monolithic integrated circuit. In one example, the band pass filter 500 includes four resonators: a first resonator 510, a second resonator 520, a third resonator 530, and a fourth resonator 540. In one example, the first resonator 510, the second resonator 520, the third resonator 530, and the fourth resonator 540 are Bulk Acoustic Wave (BAW) resonators embedded in a chip. In another example, one or more of the four resonators are Surface Acoustic Wave (SAW) resonators. In one example, the band pass filter 500 includes two inductors: a first inductor 550 and a second inductor 560. In one example, the first inductor 550 and the second inductor 560 are 3D inductors. In one example, bandpass filter 500 includes module pad 570 (e.g., electrical connector), passivation layer 580, molding layer 590, and glass layer 595.

Figure 6 illustrates an example first step 600 of a first Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors. For example, the first IC process is a Through Mount Via (TMV) process. In one example, wafer layer 610 serves as a substrate for subsequent wafer level processing. In one example, the wafer layer is a glass wafer. In another example, the wafer layer is a silicon (Si) wafer (e.g., a high resistivity silicon wafer) or a gallium arsenide (GaAs) wafer. In one example, bottom redistribution layer (RDL)620 is plated through a wafer plating process and is located in wafer layer 610. The bottom RDL620 may serve as the bottom trace of an inductor (e.g., a 3D inductor). In one example, the vertical conductive pillars 630 are placed over a wafer layer. For example, the vertical conductive pillars may be copper (Cu) pillars, aluminum (Al) pillars, or other metal pillars. For example, the vertical conductive pillars may be made by a photolithography process and a wafer plating process. In one example, the process includes Photoresist (PR), exposure, development, copper plating, photoresist stripping, and the like. For example, the height of the vertical conductive pillars may be 150 micrometers (μm) to 200 micrometers, although other dimensions are within the scope and spirit of the present disclosure.

Figure 7 illustrates an example second step 700 of a first Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors. In one example, a plurality of resonator chips 740 are assembled into a wafer layer 710. In one example, the wafer layer is a glass wafer. For example, the plurality of resonator chips 740 may be a plurality of Bulk Acoustic Wave (BAW) resonators. In another example, the plurality of resonator chips 740 may be a plurality of Surface Acoustic Wave (SAW) resonators. In one example, there is no limitation on the spatial separation between the resonator chip 740 and the vertical conductive pillars 730. In one example, a bottom redistribution layer (RDL)720 is located in the wafer layer 710.

Figure 8 illustrates a third example step 800 of a first Integrated Circuit (IC) process for a band pass filter having a combination of on-chip resonators and inductors. In one example, wafer layer 810 is covered by a molding material 850 (e.g., epoxy) to create a molded cover wafer using a molding process such as transfer molding or compression molding. In one example, the wafer layer is a glass wafer. In one example, the mold cap wafer may be background to expose (i.e., remove the mold material) the vertical conductive pillars 830 for subsequent interconnect processing.

Figure 9 illustrates an example fourth step 900 of a first Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors. In one example, a first passivation layer 960 is coated on top of the mold cover wafer. In one example, the top RDL970 and the via connection 980 may be plated simultaneously over the first passivation layer 960 using a photolithographic process. In one example, a second passivation layer 990 may be coated on top of the top RDL 970. In one example, the inductor is formed from the combination of bottom RDL 920, vertical conductive pillars 930, and top RDL 970. Further, as an example, fig. 9 indicates a region in which the 3D inductor is formed. In one example, the first passivation layer 960 is made of polyimide. In one example, the second passivation layer 990 is made of polyimide.

Figure 10 illustrates an example top view 1000 of a first Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors. Shown in fig. 10 is a 3D inductor formed from bottom RDL 1075, vertical conductive pillars 1030, and top RDL 1070. As an example, fig. 10 is a region in which a 3D inductor is formed.

Figure 11 illustrates an example fifth step 1100 of a first Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors. In one example, an interconnect layer 1195 is formed over the second passivation layer 1190. For example, the interconnect layer 1195 may include solder balls or pads or other interconnect elements using a plating process or a ball drop process.

In one example, the individual bandpass filter devices may be obtained from the IC by a dicing process. Furthermore, for example, a single band pass filter device may be cascaded to obtain an increased roll-off with higher insertion loss. That is, the cascading (i.e., series connection) of the individual bandpass filter devices may allow for a tradeoff between higher roll-off and lower insertion loss.

Figure 12 illustrates an example first step 1200 of a second Integrated Circuit (IC) process for a bandpass filter having a combination of on-chip resonators and inductors. For example, the second IC process is a Through Glass Via (TGV) process. In one example, a Through Glass Via (TGV)1220 is formed within the wafer layer 1210. For example, the wafer layer 1210 may be made of a glass layer or other material (e.g., High Resistivity Silicon (HRS), gallium arsenide (GaAs), etc.). In one example, Through Glass Vias (TGVs) 1220 are filled with a metal plating (e.g., copper plating) to form vertical conductive pillars 1230. For example, the vertical conductive pillars 1230 may be made by a laser drilling or etching process along with a copper plating or conductive paste filling process. In one example, the vertical conductive pillars 1230 are vertical copper pillars.

Figure 13 illustrates an example second step 1300 of a second Integrated Circuit (IC) process for a bandpass filter with a combination of on-chip resonators and inductors. In one example, the wafer layer 1310 is coated with a first passivation layer 1360 (e.g., a first dielectric layer). In one example, the first passivation layer 1360 is made of polyimide. In one example, a first redistribution layer (RDL)1370 is placed over first passivation layer 1360 on vertical conductive pillars 1330. For example, a photolithography process and a plating process may be used to place the first RDL 1370.

Figure 14 illustrates an example third step 1400 of a second Integrated Circuit (IC) process for a bandpass filter with a combination of on-chip resonators and inductors. In one example, a second passivation layer 1465 (e.g., a dielectric material) is coated over the first RDL 1470 and the second passivation layer 1465 is exposed for resonator assembly. In one example, the second passivation layer 1465 is made of polyimide. In one example, interconnect pad 1440 is placed over second passivation layer 1465 using a plating process. In one example, a plurality of resonator chips 1480 are assembled on top of the interconnect pads 1440. For example, the plurality of resonator chips 1480 may be a plurality of Bulk Acoustic Wave (BAW) resonators.

Figure 15 illustrates an example fourth step 1500 of a second Integrated Circuit (IC) process for a band pass filter having a combination of on-chip resonators and inductors. In one example, the second passivation layer 1565 and the plurality of resonator chips 1580 are covered with a molding material 1585 (e.g., epoxy). In one example, the plurality of resonator chips 1580 can be a plurality of Bulk Acoustic Wave (BAW) resonators. In one example, the covering is performed using a molding process (e.g., transfer molding or compression molding).

Figure 16 illustrates an example fifth step 1600 of a second Integrated Circuit (IC) process for a band pass filter having a combination of on-chip resonators and inductors. In one example, the IC is flipped over and the wafer layer 1610 is coated with a third passivation layer 1667. In one example, a second RDL 1675 is placed over the third passivation layer 1667 using photolithography and plating processes. In one example, as part of the wafer packaging process, the inductor is formed from the combination of first RDL (shown in fig. 13 as 1370), vertical conductive pillars 1630, and second RDL 1675.

Figure 17 illustrates an example sixth step 1700 of a second Integrated Circuit (IC) process for a band pass filter having a combination of on-chip resonators and inductors. In one example, a fourth passivation layer 1769 is coated over the second RDL and an interconnect layer 1799 is created over the fourth passivation layer 1769. In one example, the interconnect layer 1799 includes package pads or landing balls using a photolithography process and a plating process.

In one example, the individual bandpass filter devices may be obtained from the IC by a dicing process. Furthermore, for example, a single band pass filter device may be cascaded to obtain an increased roll-off with higher insertion loss. That is, the cascading (i.e., series connection) of the individual bandpass filter devices may allow for a tradeoff between higher roll-off and lower insertion loss.

Figure 18 illustrates an example of a first Integrated Circuit (IC) process flow 1800 for fabricating a bandpass filter with a combination of on-chip resonators and inductors within an Integrated Circuit (IC). In one example, the first IC process flow may include a Through Mold Via (TMV). In one example, the over-mold vias (TMVs) are vertical interconnects, where patterns in both sides of the molding material may be connected. The TMV may be made by a conventional plating process using Photoresist (PR) to define the through-holes. After forming the vias (e.g., copper material), a molding material may be coated on top and cured. A grinding process may be used to remove some of the molding material and expose the vias for subsequent interconnect processes.

In block 1810, a first redistribution layer (RDL) is positioned in a wafer layer on an Integrated Circuit (IC). In one example, the wafer layer is a glass wafer. In another example, the wafer layer is a High Resistivity Silicon (HRS) wafer or a gallium arsenide (GaAs) wafer. For example, the first RDL may be plated using a wafer plating process and may serve as a bottom trace of the inductor.

In block 1820, one or more vertical conductive pillars are placed over the wafer layer. In one example, the vertical conductive pillars may be copper (Cu) pillars, aluminum (Al) pillars, or other metal pillars. For example, the height of the vertical conductive pillars may be 150 micrometers (μm) to 200 micrometers.

In block 1830, a plurality of resonator chips are assembled onto a wafer layer. In one example, the resonator chip is a Bulk Acoustic Wave (BAW) resonator. In one example, the spatial spacing between the resonator chip and the vertical conductive pillars is not limited except for assembly design rules.

In block 1840, the wafer layer is covered with a molding material to form a molded wafer layer. In one example, the molding material is an epoxy. In one example, the cap wafer layer is implemented using a molding process such as transfer molding or compression molding. In one example, the molded wafer layer may be back ground to expose the vertical conductive pillars for subsequent interconnect processing.

In block 1850, a plurality of inductors are formed by applying a first passivation layer onto the molded wafer layer, plating a second redistribution layer (RDL) over the first passivation layer, and applying a second passivation layer over the second RDL. In one example, the first passivation layer and the second passivation layer are made of polyimide. In one example, plating of the second redistribution layer (RDL) also plates the via connection using a photolithography process. In one example, the one or more inductors are formed from the first RDL, the vertical conductive pillars, and/or the second redistribution layer (RDL).

In block 1860, an interconnect layer is formed over the second passivation layer. In one example, the interconnect layer may include one or more of: solder balls, conductive pads, and/or other interconnect elements. In one example, forming the interconnect layer may use a plating process or a ball drop process.

In block 1870, the Integrated Circuit (IC) is diced to obtain one or more individual bandpass filters.

Figure 19 illustrates an example of a second Integrated Circuit (IC) process flow 1900 for fabricating a bandpass filter with a combination of on-chip resonators and inductors within an Integrated Circuit (IC). In one example, the second IC process flow may include a Through Glass Via (TGV). In one example, the through silicon vias are vertical interconnects, where patterns in both sides of the silicon wafer may be connected. The TSV may be made by an etching process or a laser drilling process. In the etching process, some silicon material is etched away and then filled with copper, aluminum, or other metal. In a laser drilling process, holes may be created by a laser drilling process and then possibly filled with copper, aluminum, or other metal.

In block 1910, a Through Glass Via (TGV) is formed within a wafer layer on an Integrated Circuit (IC). In one example, the wafer layer may be made of a glass layer or other material, such as, but not limited to, High Resistivity Silicon (HRS) or gallium arsenide (GaAs), among others. In one example, the Through Glass Vias (TGVs) may be filled with a metal plating (e.g., copper plating) to form vertical conductive pillars. In one example, the vertical conductive pillars may be formed by a laser drilling process or an etching process. In addition, the vertical conductive pillars may also be formed by a copper plating process or a conductive paste filling process. In one example, the vertical conductive pillars are vertical copper pillars.

In block 1920, a first passivation layer is coated on top of the wafer layer and a first redistribution layer (RDL) is placed over the first passivation layer, where the first RDL is placed over the one or more vertical conductive pillars. In one example, the first passivation layer is a first dielectric layer. In one example, the first passivation layer is made of polyimide. In one example, the first RDL may be placed using a photolithography process and a plating process.

In block 1930, a second passivation layer is coated over the first RDL and a portion of the second passivation layer is exposed for assembling one or more resonator chips. In one example, the second passivation layer is a second dielectric layer. In one example, the second passivation layer is made of polyimide.

In block 1940, one or more interconnect pads are placed over the second passivation layer using a plating process. In one example, one or more resonator chips are assembled on top of one or more interconnect pads. In one example, the one or more resonator chips may be a plurality of Bulk Acoustic Wave (BAW) resonators.

In block 1950, a molding material is used to cover the second passivation layer and the one or more resonator chips. In one example, the molding material is an epoxy. In one example, a molding process is used to cover the second passivation layer and the one or more resonator chips with a molding material. In one example, the molding process includes transfer molding or compression molding.

In block 1960, an Integrated Circuit (IC) is flipped, a wafer layer is coated with a third passivation layer and a second RDL is placed over the third passivation layer to form a plurality of inductors. In one example, a photolithography process and/or a plating process is used to place the second RDL over the third passivation layer. In one example, the plurality of inductors are formed from a combination of the first RDL, the vertical conductive pillars, and the second RDL as part of a wafer packaging process.

In block 1970, a fourth passivation layer is applied over the second RDL and an interconnect layer is created over the fourth passivation layer. In one example, the interconnect layer includes package pads or landing balls using a photolithography process and a plating process. In one example, the interconnect layer is created by adding one or more conductive pads and/or solder balls.

In block 1980, the Integrated Circuit (IC) is diced to obtain one or more individual bandpass filters.

In one aspect, the present disclosure relates to the combination of Bulk Acoustic Wave (BAW) resonators and 3-dimensional (3D) inductors to provide a bandpass filter with both a broadband passband and a sharp roll-off. A 3D inductor is implemented using a low loss substrate (e.g., a glass wafer) to fabricate a high Q inductor by a metal plating process. The 3D inductor is integrated with a plurality of BAW resonators to form a band pass filter. In one example, the 3D inductor may be fabricated on a glass wafer by a Through Mold Via (TMV) process or a Through Glass Via (TGV) process.

In one aspect, the present disclosure provides a highly integrated and high performance filter module with improved tolerance with respect to low temperature co-fired ceramic (LTCC) technology and lamination solutions for inductors. Also, in one aspect, the present disclosure discloses methods for providing small form factors and/or at low cost.

In one aspect, one or more of the steps for providing a band pass filter within the integrated circuit in fig. 18 and 19 may be performed by one or more processors, which may include hardware, software, firmware, etc. In one aspect, one or more of the steps in fig. 18 and 19 may be performed by one or more processors, which may include hardware, software, firmware, etc. For example, one or more processors may be used to execute software or firmware required to perform the steps in the flowcharts of fig. 18 and 19. Software should be construed broadly to mean instructions, instruction sets, code segments, program code, programs, subroutines, software modules, applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

The software may reside on a computer readable medium. The computer readable medium may be a non-transitory computer readable medium. By way of example, a non-transitory computer-readable medium includes a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., Compact Disk (CD) or Digital Versatile Disk (DVD)), a smart card, a flash memory device (e.g., card, stick, or key drive), a Random Access Memory (RAM), a Read Only Memory (ROM), a programmable ROM (prom), an erasable prom (eprom), an electrically erasable prom (eeprom), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. By way of example, computer-readable media may also include carrier waves, transmission lines, and any other suitable media for transmitting software and/or instructions that may be accessed and read by a computer. The computer readable medium may reside in a processing system, external to the processing system, or distributed across multiple entities including the processing system. The computer readable medium may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging material. The computer readable medium may include software or firmware for providing a band pass filter within an integrated circuit. Those skilled in the art will recognize how best to implement the described functionality presented in this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

Any circuitry included in one or more processors is provided merely as an example, and other means for performing the described functions including, but not limited to, an instruction readable medium stored in a computer or any other suitable device or means described herein and utilizing, for example, the processes and/or algorithms described herein with respect to example flowcharts may be included within aspects of the present disclosure.

Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object a physically contacts object B, and object B contacts object C, objects a and C may still be considered to be coupled to each other even though they are not in direct physical contact with each other. For example, a first die may be coupled to a second die in a package even though the first die is never in direct physical contact with the second die. The terms "circuit" and "circuitry" are used broadly and are intended to include hardware implementations of electrical devices and conductors that when connected and configured enable the functions described in this disclosure, without limitation as to the type of electronic circuitry and software implementations of information and instructions that when executed by a processor enable the functions described in this disclosure to be performed.

One or more of the components, steps, features and/or functions illustrated in the figures may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps or functions. Additional elements, components, steps, and/or functions may also be added without departing from the novel features disclosed herein. The apparatus, devices, and/or components illustrated in the figures may be configured to perform one or more of the methods, features, or steps described herein. The novel algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.

It is to be understood that the specific order or hierarchy of steps in the methods disclosed is an illustration of exemplary procedures. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the methods may be rearranged. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented unless specifically recited herein.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more. The term "some" means one or more unless specifically stated otherwise. A phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. By way of example, "at least one of a, b, or c" is intended to encompass: a, b, c, a and b, a and c, b and c, and a, b and c. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. Claim elements are not to be construed in accordance with the provisions of paragraph 6 of 35u.s.c. § 112 unless the element is explicitly recited using the phrase "means for … …" or, in the case of a method claim, is recited using the phrase "step for … …".