阅读说明：本技术 显示基板及显示装置 (Display substrate and display device ) 是由 吴超 龙跃 魏锋 刘聪 于 2020-06-23 设计创作，主要内容包括：一种显示基板及显示装置,显示基板包括显示区域。显示区域包括第一、第二显示区域和第一连接线。第一显示区域包括第一发光元件。第二显示区域包括第一像素电路。第一连接线与第一子像素电路和第一子发光元件的阳极电连接。第一连接线位于第一连接层,第一子发光元件的阳极通过贯穿第一绝缘层和第二绝缘层的第一过孔与第一连接线电连接。第一过孔在垂直于显示基板的平面内的截面形状为倒凸台形状,在第一过孔中,第二绝缘层的开口口径大于第一绝缘层的开口口径。第一子发光元件的阳极包括位于第一过孔内的第一凹槽结构,第一凹槽结构的底部与第一连接线接触以实现电连接。该显示基板能降低加工难度,提高电连接的可靠性和透射光线的均一性。(A display substrate and a display device are provided, the display substrate includes a display area. The display area includes first and second display areas and a first connection line. The first display region includes a first light emitting element. The second display region includes the first pixel circuits. The first connection line is electrically connected to the first sub-pixel circuit and the anode of the first sub-light emitting element. The first connecting line is located on the first connecting layer, and the anode of the first sub-light emitting element is electrically connected with the first connecting line through a first via hole penetrating through the first insulating layer and the second insulating layer. The cross section of the first via hole in a plane perpendicular to the display substrate is in an inverted boss shape, and in the first via hole, the opening aperture of the second insulating layer is larger than that of the first insulating layer. The anode of the first sub-light-emitting element comprises a first groove structure positioned in the first through hole, and the bottom of the first groove structure is in contact with the first connecting line to realize electric connection. The display substrate can reduce the processing difficulty and improve the reliability of electric connection and the uniformity of transmitted light.)

1. A display substrate includes a display area;

the display area comprises a first display area and a second display area which are not overlapped with each other, the second display area at least partially surrounds the first display area, and the light transmittance of the first display area is greater than that of the second display area;

the first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit;

the display area further comprises at least one first connecting line, and the first connecting line comprises a first end positioned in the first display area and a second end positioned in the second display area;

the at least one first light emitting element includes a first sub light emitting element, the at least one first pixel circuit includes a first sub pixel circuit, a first end of the first connection line is electrically connected to an anode of the first sub light emitting element, and a second end of the first connection line is electrically connected to the first sub pixel circuit;

the display substrate comprises a first connecting layer, a first insulating layer, a second insulating layer and an anode layer which are sequentially stacked;

the first connecting line is positioned on the first connecting layer, the anode of the first sub-light-emitting element is positioned on the anode layer, and the anode of the first sub-light-emitting element is electrically connected with the first connecting line through a first through hole penetrating through the first insulating layer and the second insulating layer;

the cross section of the first via hole in a plane perpendicular to the display substrate is in an inverted boss shape, and the opening aperture of the second insulating layer in the first via hole is larger than that of the first insulating layer;

the anode of the first sub-light-emitting element comprises a first groove structure, the first groove structure is located in the first through hole, and the bottom of the first groove structure is in contact with the first connecting line to achieve electric connection.

2. The display substrate of claim 1, wherein the display area further comprises at least one second connection line comprising a first end located at the first display area and a second end located at the second display area;

the at least one first light emitting element further comprises a second sub-light emitting element, the at least one first pixel circuit further comprises a second sub-pixel circuit, a first end of the second connecting line is electrically connected with an anode of the second sub-light emitting element, and a second end of the second connecting line is electrically connected with the second sub-pixel circuit;

the display substrate further comprises a second connecting layer, the second connecting layer is located between the first insulating layer and the second insulating layer, and the second connecting line is located on the second connecting layer;

the anode of the second sub-light-emitting element is positioned on the anode layer and is electrically connected with the second connecting line through a second through hole penetrating through the second insulating layer;

the anode of the second sub-light-emitting element comprises a second groove structure, the second groove structure is located in the second through hole, and the bottom of the second groove structure is in contact with the second connecting line to achieve electric connection.

3. The display substrate of claim 2, wherein a surface of the first groove structure away from the first connection layer is curved, and a surface of the second groove structure away from the second connection layer is curved.

4. The display substrate of claim 2, wherein each of the first and second sub-pixel circuits comprises a first switching transistor comprising a gate, a first pole, and a second pole;

the display substrate further comprises a source drain metal layer and a third insulating layer, the third insulating layer is located on the source drain metal layer, the first connecting layer is located on the third insulating layer, and a first pole and a second pole of the first switch transistor are located on the source drain metal layer;

a second end of the first connection line is electrically connected with a first pole or a second pole of a first switching transistor of the first sub-pixel circuit through a third via hole penetrating through the third insulating layer;

a second end of the second connection line is electrically connected to the first pole or the second pole of the first switching transistor of the second sub-pixel circuit through a fourth via hole penetrating the third insulating layer and the first insulating layer.

5. The display substrate according to claim 4, wherein a cross-sectional shape of the fourth via in a plane perpendicular to the display substrate is an inverted-boss shape, and an opening aperture of the first insulating layer is larger than an opening aperture of the third insulating layer in the fourth via.

6. The display substrate of claim 4, wherein in the fourth via, the second connection line is electrically connected to a transition metal layer contact, the transition metal layer is electrically connected to a first pole or a second pole contact of a first switching transistor of the second sub-pixel circuit, and the transition metal layer is formed in the same process as the first connection layer.

7. The display substrate according to claim 4, wherein the second display region further comprises at least one second light-emitting element and at least one second pixel circuit, the second light-emitting element and the second pixel circuit being electrically connected;

the second pixel circuit comprises a second switch transistor, the second switch transistor comprises a grid electrode, a first pole and a second pole, and the first pole and the second pole of the second switch transistor are positioned on the source drain metal layer;

an anode of the second light emitting element is located at the anode layer, and the anode of the second light emitting element is electrically connected with the first pole or the second pole of the second switching transistor through a fifth via hole penetrating through the first insulating layer, the second insulating layer and the third insulating layer;

the cross section of the fifth via hole in a plane perpendicular to the display substrate is in an inverted boss shape, and in the fifth via hole, the opening aperture of the first insulating layer is larger than that of the third insulating layer.

8. The display substrate according to claim 7, wherein in the fifth via hole, an opening aperture of the second insulating layer is equal to or larger than an opening aperture of the first insulating layer.

9. The display substrate according to claim 7, wherein the anode of the second light emitting element comprises a third groove structure, the third groove structure is located in the fifth via hole, and the bottom of the third groove structure is in contact with the first pole or the second pole of the second switching transistor to realize electrical connection.

10. The display substrate of claim 7, wherein the display area further comprises a third display area at least partially surrounding the second display area, the third display area being non-overlapping with the first display area and the second display area;

the third display region includes at least one third light emitting element and at least one third pixel circuit, the third light emitting element and the third pixel circuit being electrically connected;

the third pixel circuit comprises a third switching transistor, the third switching transistor comprises a grid electrode, a first pole and a second pole, and the first pole and the second pole of the third switching transistor are positioned on the source drain metal layer;

an anode of the third light emitting element is located in the anode layer, and the anode of the third light emitting element is electrically connected to the first pole or the second pole of the third switching transistor through a sixth via hole penetrating through the first insulating layer, the second insulating layer, and the third insulating layer;

the cross section of the sixth via hole in a plane perpendicular to the display substrate is in an inverted boss shape, and in the sixth via hole, the opening aperture of the first insulating layer is larger than that of the third insulating layer.

11. The display substrate according to claim 10, wherein in the sixth via hole, an opening aperture of the second insulating layer is equal to or larger than an opening aperture of the first insulating layer.

12. The display substrate according to claim 10, wherein the anode of the third light emitting element comprises a fourth groove structure, the fourth groove structure is located in the sixth via, and a bottom of the fourth groove structure is in contact with the first electrode or the second electrode of the third switching transistor to realize electrical connection.

13. The display substrate of any of claims 2-12, wherein the first connection lines and the second connection lines each comprise a transparent conductive trace.

14. The display substrate according to any one of claims 2 to 12, wherein the at least one first light emitting element comprises a plurality of first light emitting elements arranged in an array, and the first connection line and the second connection line each extend in a row direction of the array of the plurality of first light emitting elements.

15. The display substrate according to any one of claims 10 to 12, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element each include an organic light-emitting diode.

16. The display substrate according to any one of claims 10 to 12, wherein the at least one first light-emitting element comprises a plurality of first light-emitting elements, the at least one second light-emitting element comprises a plurality of second light-emitting elements, and the at least one third light-emitting element comprises a plurality of third light-emitting elements;

the unit area distribution density of the plurality of first light-emitting elements in the first display region is less than or equal to the unit area distribution density of the plurality of second light-emitting elements in the second display region, and the unit area distribution density of the plurality of second light-emitting elements in the second display region is less than the unit area distribution density of the plurality of third light-emitting elements in the third display region.

17. A display device comprising the display substrate of any one of claims 1-16.

18. The display device of claim 17, further comprising a sensor, wherein,

the display substrate having a first side for displaying and a second side opposite the first side, the first display region allowing light from the first side to be at least partially transmitted to the second side,

the sensor is disposed on a second side of the display substrate, the sensor configured to receive light from the first side.

19. The display device of claim 17, wherein an orthographic projection of the sensor on the display substrate at least partially overlaps the first display region.

Technical Field

The embodiment of the disclosure relates to a display substrate and a display device.

Background

An Organic Light-Emitting Diode (OLED) display device has the characteristics of wide viewing angle, high contrast, high response speed, wide color gamut, high screen occupation ratio, self-luminescence, lightness, thinness and the like. Due to the above features and advantages, Organic Light Emitting Diode (OLED) display devices are gradually receiving wide attention from people and may be applied to devices having a display function, such as mobile phones, displays, notebook computers, smart watches, digital cameras, instruments, flexible wearable devices, and the like. With the further development of display technology, display devices with high screen ratio have been unable to meet the needs of people, and display devices with full screen become the development trend of future display technology.

Disclosure of Invention

At least one embodiment of the present disclosure provides a display substrate including a display region; the display area comprises a first display area and a second display area which are not overlapped with each other, the second display area at least partially surrounds the first display area, and the light transmittance of the first display area is greater than that of the second display area; the first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit; the display area further comprises at least one first connecting line, and the first connecting line comprises a first end positioned in the first display area and a second end positioned in the second display area; the at least one first light emitting element includes a first sub light emitting element, the at least one first pixel circuit includes a first sub pixel circuit, a first end of the first connection line is electrically connected to an anode of the first sub light emitting element, and a second end of the first connection line is electrically connected to the first sub pixel circuit; the display substrate comprises a first connecting layer, a first insulating layer, a second insulating layer and an anode layer which are sequentially stacked; the first connecting line is positioned on the first connecting layer, the anode of the first sub-light-emitting element is positioned on the anode layer, and the anode of the first sub-light-emitting element is electrically connected with the first connecting line through a first through hole penetrating through the first insulating layer and the second insulating layer; the cross section of the first via hole in a plane perpendicular to the display substrate is in an inverted boss shape, and the opening aperture of the second insulating layer in the first via hole is larger than that of the first insulating layer; the anode of the first sub-light-emitting element comprises a first groove structure, the first groove structure is located in the first through hole, and the bottom of the first groove structure is in contact with the first connecting line to achieve electric connection.

For example, in a display substrate provided in an embodiment of the present disclosure, the display area further includes at least one second connection line, where the second connection line includes a first end located in the first display area and a second end located in the second display area; the at least one first light emitting element further comprises a second sub-light emitting element, the at least one first pixel circuit further comprises a second sub-pixel circuit, a first end of the second connecting line is electrically connected with an anode of the second sub-light emitting element, and a second end of the second connecting line is electrically connected with the second sub-pixel circuit; the display substrate further comprises a second connecting layer, the second connecting layer is located between the first insulating layer and the second insulating layer, and the second connecting line is located on the second connecting layer; the anode of the second sub-light-emitting element is positioned on the anode layer and is electrically connected with the second connecting line through a second through hole penetrating through the second insulating layer; the anode of the second sub-light-emitting element comprises a second groove structure, the second groove structure is located in the second through hole, and the bottom of the second groove structure is in contact with the second connecting line to achieve electric connection.

For example, in the display substrate provided in an embodiment of the present disclosure, a surface of the first groove structure away from the first connection layer is a curved surface, and a surface of the second groove structure away from the second connection layer is a curved surface.

For example, in a display substrate provided in an embodiment of the present disclosure, each of the first sub-pixel circuit and the second sub-pixel circuit includes a first switching transistor including a gate, a first pole, and a second pole; the display substrate further comprises a source drain metal layer and a third insulating layer, the third insulating layer is located on the source drain metal layer, the first connecting layer is located on the third insulating layer, and a first pole and a second pole of the first switch transistor are located on the source drain metal layer; a second end of the first connection line is electrically connected with a first pole or a second pole of a first switching transistor of the first sub-pixel circuit through a third via hole penetrating through the third insulating layer; a second end of the second connection line is electrically connected to the first pole or the second pole of the first switching transistor of the second sub-pixel circuit through a fourth via hole penetrating the third insulating layer and the first insulating layer.

For example, in the display substrate provided in an embodiment of the present disclosure, a cross-sectional shape of the fourth via in a plane perpendicular to the display substrate is an inverted boss shape, and in the fourth via, an opening aperture of the first insulating layer is larger than an opening aperture of the third insulating layer.

For example, in the display substrate provided in an embodiment of the present disclosure, in the fourth via hole, the second connection line is electrically connected to a transition metal layer contact, the transition metal layer is electrically connected to the first pole or the second pole contact of the first switching transistor of the second sub-pixel circuit, and the transition metal layer and the first connection layer are formed in the same process.

For example, in a display substrate provided in an embodiment of the present disclosure, the second display region further includes at least one second light emitting element and at least one second pixel circuit, and the second light emitting element and the second pixel circuit are electrically connected; the second pixel circuit comprises a second switch transistor, the second switch transistor comprises a grid electrode, a first pole and a second pole, and the first pole and the second pole of the second switch transistor are positioned on the source drain metal layer; an anode of the second light emitting element is located at the anode layer, and the anode of the second light emitting element is electrically connected with the first pole or the second pole of the second switching transistor through a fifth via hole penetrating through the first insulating layer, the second insulating layer and the third insulating layer; the cross section of the fifth via hole in a plane perpendicular to the display substrate is in an inverted boss shape, and in the fifth via hole, the opening aperture of the first insulating layer is larger than that of the third insulating layer.

For example, in the display substrate provided in an embodiment of the present disclosure, in the fifth via hole, an aperture diameter of the second insulating layer is equal to or greater than an aperture diameter of the first insulating layer.

For example, in a display substrate provided in an embodiment of the present disclosure, the anode of the second light emitting element includes a third groove structure, the third groove structure is located in the fifth via, and a bottom of the third groove structure contacts with the first pole or the second pole of the second switching transistor to achieve an electrical connection.

For example, in a display substrate provided in an embodiment of the present disclosure, the display region further includes a third display region, the third display region at least partially surrounds the second display region, and the third display region is not overlapped with the first display region and the second display region; the third display region includes at least one third light emitting element and at least one third pixel circuit, the third light emitting element and the third pixel circuit being electrically connected; the third pixel circuit comprises a third switching transistor, the third switching transistor comprises a grid electrode, a first pole and a second pole, and the first pole and the second pole of the third switching transistor are positioned on the source drain metal layer; an anode of the third light emitting element is located in the anode layer, and the anode of the third light emitting element is electrically connected to the first pole or the second pole of the third switching transistor through a sixth via hole penetrating through the first insulating layer, the second insulating layer, and the third insulating layer; the cross section of the sixth via hole in a plane perpendicular to the display substrate is in an inverted boss shape, and in the sixth via hole, the opening aperture of the first insulating layer is larger than that of the third insulating layer.

For example, in the display substrate provided in an embodiment of the present disclosure, in the sixth via hole, an aperture diameter of the second insulating layer is equal to or greater than an aperture diameter of the first insulating layer.

For example, in a display substrate provided in an embodiment of the present disclosure, the anode of the third light emitting element includes a fourth groove structure, the fourth groove structure is located in the sixth via, and a bottom of the fourth groove structure is in contact with the first pole or the second pole of the third switching transistor to achieve electrical connection.

For example, in a display substrate provided in an embodiment of the present disclosure, the first connection lines and the second connection lines respectively include transparent conductive traces.

For example, in a display substrate provided in an embodiment of the present disclosure, the at least one first light emitting element includes a plurality of first light emitting elements, the plurality of first light emitting elements are arranged in an array, and the first connection line and the second connection line both extend along a row direction of the array formed by the plurality of first light emitting elements.

For example, in a display substrate provided in an embodiment of the present disclosure, the first light emitting element, the second light emitting element, and the third light emitting element each include an organic light emitting diode.

For example, in a display substrate provided in an embodiment of the present disclosure, the at least one first light emitting element includes a plurality of first light emitting elements, the at least one second light emitting element includes a plurality of second light emitting elements, and the at least one third light emitting element includes a plurality of third light emitting elements; the unit area distribution density of the plurality of first light-emitting elements in the first display region is less than or equal to the unit area distribution density of the plurality of second light-emitting elements in the second display region, and the unit area distribution density of the plurality of second light-emitting elements in the second display region is less than the unit area distribution density of the plurality of third light-emitting elements in the third display region.

At least one embodiment of the present disclosure further provides a display device including the display substrate according to any one of the embodiments of the present disclosure.

For example, an embodiment of the present disclosure provides a display device further including a sensor, wherein the display substrate has a first side for displaying and a second side opposite to the first side, the first display area allows light from the first side to be at least partially transmitted to the second side, the sensor is disposed on the second side of the display substrate, and the sensor is configured to receive light from the first side.

For example, in a display device provided by an embodiment of the present disclosure, an orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure;

FIG. 2 is a schematic plan view of a first display region and a second display region of the display substrate shown in FIG. 1;

fig. 3 is an example of a first display region and a second display region of the display substrate shown in fig. 2;

fig. 4 is an enlarged view of a partial region REG1 in fig. 3;

fig. 5A is an enlarged view of a partial region REG2 in fig. 3;

fig. 5B is an enlarged view of an area including only one row of the first pixel circuits, one row of the first light emitting elements, one row of the second pixel circuits, and one row of the second light emitting elements in fig. 5A;

FIG. 6A is a schematic cross-sectional view taken along line A-A' of FIG. 5B;

fig. 6B is an enlarged view of the first via H1 in fig. 6A;

FIG. 6C is a schematic layout of a region corresponding to the first via H1 and the connected anode of FIG. 6A;

FIG. 6D is a schematic layout of a region corresponding to third via H3 and the associated source drain metal layer in FIG. 6A;

FIG. 7A is a schematic cross-sectional view taken along line B-B' of FIG. 5B;

fig. 7B is an enlarged view of the second via H2 in fig. 7A;

FIG. 7C is a schematic layout of a region corresponding to the second via H2 and the connected anode of FIG. 7A;

fig. 7D is another structural diagram of the fourth via H4;

FIG. 7E is a schematic layout of a region corresponding to fourth via H4 and the associated source drain metal layer in FIG. 7A;

FIG. 8A is a schematic cross-sectional view taken along line C-C' of FIG. 5B;

fig. 8B is an enlarged view of the fifth through hole H5 in fig. 8A;

FIG. 8C is a schematic layout of a region corresponding to fifth via H5 and the connected anode and source drain metal layers in FIG. 8A;

fig. 9 is an enlarged view of a partial region REG3 of the third display region of the display substrate shown in fig. 1;

FIG. 10A is a schematic cross-sectional view taken along line D-D' of FIG. 9;

fig. 10B is an enlarged view of the sixth via H6 in fig. 10A;

fig. 11A is a schematic layout corresponding to the partial region REG4 in fig. 4;

fig. 11B is a schematic layout in which only the first connection lines are shown in fig. 11A;

fig. 11C is a schematic layout in which only the second connecting lines are shown in fig. 11A;

FIG. 11D is a schematic cross-sectional view taken along line E-E' of FIG. 11A;

fig. 12A is one of schematic layouts corresponding to second light emitting elements in a second display region of a display substrate according to some embodiments of the present disclosure;

fig. 12B is a second schematic layout corresponding to a second light emitting device in a second display region of a display substrate according to some embodiments of the present disclosure;

fig. 13A is a schematic structural diagram of a 7T1C pixel circuit;

fig. 13B is a driving timing diagram of the 7T1C pixel circuit shown in fig. 13A;

fig. 14 is a schematic block diagram of a display device provided in at least one embodiment of the present disclosure; and

fig. 15 is a schematic view of a stacked structure of a display device according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

For a current display substrate having an under-screen sensor (e.g., a camera), in order to increase light transmittance of a display region of the display substrate corresponding to the under-screen sensor (camera), a distribution density per unit area (PPI) of light emitting elements corresponding to the display region of the under-screen sensor (camera) may be less than that of light emitting elements of other display regions of the display substrate.

However, since the distribution density of the light emitting elements in different regions of the display substrate is different, the arrangement of the light emitting elements and the corresponding pixel circuits in different regions is different, and the wiring pattern and layout design of the display substrate are different from those of a common display substrate having light emitting elements uniformly distributed. This results in the need for more vias on the display substrate to make electrical connections between the layers. When a common via hole arrangement mode is adopted, the stability of electric connection is affected due to more via holes existing in the display substrate, the uniformity of transmitted light is poor, the sensing effect of a sensor (such as a camera) under a screen is affected, and therefore the performance of a display device adopting the display substrate is reduced.

At least one embodiment of the present disclosure provides a display substrate and a display device, where the display substrate can reduce the processing difficulty, improve the reliability of electrical connection, improve the uniformity of transmitted light, and contribute to improving the sensing effect of an off-screen sensor (e.g., a camera).

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements that have been described.

At least one embodiment of the present disclosure provides a display substrate including a display area. The display area comprises a first display area and a second display area which are not overlapped with each other, the second display area at least partially surrounds the first display area, and the light transmittance of the first display area is larger than that of the second display area. The first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit. The display area further includes at least one first connection line including a first end located at the first display area and a second end located at the second display area. The at least one first light emitting element includes a first sub light emitting element, the at least one first pixel circuit includes a first sub pixel circuit, a first end of the first connection line is electrically connected to an anode of the first sub light emitting element, and a second end of the first connection line is electrically connected to the first sub pixel circuit. The display substrate includes a first connection layer, a first insulating layer, a second insulating layer, and an anode layer, which are sequentially stacked. The first connecting line is located on the first connecting layer, the anode of the first sub-light-emitting element is located on the anode layer, and the anode of the first sub-light-emitting element is electrically connected with the first connecting line through a first through hole penetrating through the first insulating layer and the second insulating layer. The cross section of the first via hole in a plane perpendicular to the display substrate is in an inverted boss shape, and in the first via hole, the opening aperture of the second insulating layer is larger than that of the first insulating layer. The anode of the first sub-light-emitting element comprises a first groove structure, the first groove structure is positioned in the first through hole, and the bottom of the first groove structure is in contact with the first connecting wire to realize electric connection.

Fig. 1 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure. As shown in fig. 1, the display substrate 01 includes a display region 10, and the display region 10 includes a first display region 11, a second display region 12, and a third display region 13. For example, the first display area 11, the second display area 12, and the third display area 13 do not overlap with each other. For example, the third display area 13 at least partially surrounds (e.g., partially surrounds) the second display area 12, and the second display area 12 at least partially surrounds (e.g., completely surrounds) the first display area 11. It should be noted that, in some examples, the display substrate 01 may further include a peripheral area, and the peripheral area at least partially surrounds the third display area 13.

For example, the light transmittance of the first display region 11 is greater than that of the second display region 12. For example, in some examples, at least the first display region 11 allows light to pass through. For example, the display substrate 01 has a first side for display and a second side opposite to the first side. For example, in some examples, as shown in fig. 1, the first side is a front side (i.e., the plane shown in fig. 1) of the display substrate 01 and the second side is a back side of the display substrate 01. For example, a sensor, such as an image sensor or an infrared sensor, may be disposed at a position corresponding to the first display region 11 on the second side of the display substrate 01. The sensor is configured to receive light from the first side of the display substrate 01, such that operations such as image capture, distance sensing, light intensity sensing, etc. may be performed, the light being irradiated onto the sensor, for example, after passing through the first display region 11, so as to be sensed by the sensor.

Fig. 2 is a schematic plan view of a first display region and a second display region of the display substrate shown in fig. 1. For example, as shown in fig. 1 and 2, the second display area 12 at least partially surrounds (e.g., completely surrounds) the first display area 11.

For example, the shape of the first display region 11 may be a circle or an ellipse, and the shape of the second display region 12 may be a rectangle, but the embodiment of the present disclosure is not limited thereto. For another example, the first display region 11 and the second display region 12 may both be rectangular in shape or other suitable shapes.

Fig. 3 is an example of a first display region and a second display region of the display substrate shown in fig. 2. Fig. 4 is an enlarged view of a partial region REG1 in fig. 3, fig. 5A is an enlarged view of a partial region REG2 in fig. 3, and fig. 5B is an enlarged view of a region including only one row of the first pixel circuits, one row of the first light emitting elements, one row of the second pixel circuits, and one row of the second light emitting elements in fig. 5A. It should be noted that, in order to clearly show the connection manner between the first pixel circuit and the first light emitting element, fig. 5B shows that the adjacent first pixel circuit and the first light emitting element are connected to each other, but according to fig. 3, fig. 4 and fig. 5A, it can be understood that the left side of the first light emitting element in fig. 5B may be provided with other first light emitting elements not shown, and the right side of the first pixel circuit may be provided with other first pixel circuits not shown.

For example, as shown in fig. 3, 4, 5A, and 5B, the first display region 11 includes at least one (e.g., a plurality of) first light emitting elements 411. It should be noted that, for clarity, the anode structure of the first light emitting element 411 is used in the related drawings to schematically illustrate the first light emitting element 411. For example, the first display region 11 includes a plurality of first light emitting elements 411 arranged in an array, and the first light emitting elements 411 are configured to emit light. For example, there is no pixel circuit in the first display region 11, and a pixel circuit for driving the first light emitting element 411 is disposed in the second display region 12, thereby reducing a metal coverage area of the first display region 11, increasing light transmittance of the first display region 11, and thereby making the light transmittance of the first display region 11 greater than that of the second display region 12.

For example, the plurality of first light emitting elements 411 may be disposed in a plurality of light emitting units arranged in an array. For example, each light emitting unit may include one or more first light emitting elements 411. For example, the plurality of first light emitting elements 411 may emit light of the same color or light of different colors, for example, white light, red light, blue light, green light, etc., which may be determined according to actual needs, and embodiments of the present disclosure are not limited thereto. For example, the arrangement of the plurality of first light emitting elements 411 may refer to a conventional pixel unit arrangement, such as GGRB, RGBG, RGB, and the like, which is not limited by the embodiments of the present disclosure.

For example, the first display region 11 allows light from a first side of the display substrate 01 to be at least partially transmitted to a second side of the display substrate 01. In this way, it is convenient to provide a sensor at a position corresponding to the first display region 11 on the second side of the display substrate 01, and the sensor can receive light from the first side, so that operations such as image capturing, distance sensing, light intensity sensing, and the like can be performed.

For example, as shown in fig. 3, 4, 5A, and 5B, the second display region 12 includes at least one (e.g., a plurality of) first pixel circuits 412. For example, the first light emitting elements 411 are electrically connected to the first pixel circuits 412 in a one-to-one correspondence, and the plurality of first pixel circuits 412 are used to drive the plurality of first light emitting elements 411 in a one-to-one correspondence. For example, rectangular boxes (black frame white filled regions indicated by reference numeral 412) shown in fig. 5B represent first pixel driving units each including the first pixel circuit 412. For example, the first pixel circuits 412 are configured to drive the plurality of first light emitting elements 411 to emit light in a one-to-one correspondence. That is, one first pixel circuit 412 drives one corresponding first light emitting element 411, and different first pixel circuits 412 drive different first light emitting elements 411.

Note that in fig. 3, 4, 5A, and 5B, the first pixel driving unit may include one or more first pixel circuits 412. When the light emitting unit in the first display region 11 includes one first light emitting element 411, the first pixel driving unit also includes one first pixel circuit 412. When the light emitting unit in the first display region 11 includes a plurality of first light emitting elements 411, the first pixel driving unit also includes a plurality of first pixel circuits 412, and the number of the first light emitting elements 411 in each light emitting unit is, for example, equal to the number of the first pixel circuits 412 in each first pixel driving unit, thereby realizing one-to-one driving.

For example, the plurality of first light emitting elements 411 are arranged in an array, and the plurality of first pixel circuits 412 are also arranged in an array. Here, the "array arrangement" may refer to that a plurality of devices are grouped and a plurality of groups of devices are arranged in an array, and may also refer to that a plurality of devices are arranged in an array, and the embodiment of the present disclosure is not limited thereto. For example, in some examples, as shown in fig. 3, 4, 5A and 5B, each 4 first light emitting elements 411 are in one group, the plurality of groups of first light emitting elements 411 are arranged in an array, correspondingly, each 4 first pixel circuits 412 is in one group, and the plurality of groups of first pixel circuits 412 are arranged in an array, in this case, each first pixel driving unit includes 4 first pixel circuits 412.

For example, as shown in fig. 3, 4, 5A and 5B, the display area 10 further includes at least one first connection line 110 and at least one second connection line 120. The first connection line 110 includes a first end located at the first display region 11 and a second end located at the second display region 12, that is, the first connection line 110 extends from the first display region 11 to the second display region 12. Similarly, the second connection line 120 includes a first end located in the first display region 11 and a second end located in the second display region 12, that is, the second connection line 120 extends from the first display region 11 to the second display region 12.

The first light emitting element 411 includes a first sub light emitting element 411a and a second sub light emitting element 411b, and the first pixel circuit 412 includes a first sub pixel circuit 412a and a second sub pixel circuit 412 b. A first end of the first connection line 110 is electrically connected to an anode of the first sub light emitting element 411a, a second end of the first connection line 110 is electrically connected to the first sub pixel circuit 412a, and the first connection line 110 is configured to transmit an electrical signal provided by the first sub pixel circuit 412a to the anode of the first sub light emitting element 411a, thereby driving the first sub light emitting element 411a to emit light. A first end of the second connection line 120 is electrically connected to the anode of the second sub-light emitting element 411b, a second end of the second connection line 120 is electrically connected to the second sub-pixel circuit 412b, and the second connection line 120 is configured to transmit an electrical signal provided by the second sub-pixel circuit 412b to the anode of the second sub-light emitting element 411b, thereby driving the second sub-light emitting element 411b to emit light.

For example, for the plurality of first light emitting elements 411 located in the first display region 11, a part of the first light emitting elements 411 (e.g., the first sub light emitting elements 411a) is electrically connected to the first connection lines 110, and another part of the first light emitting elements 411 (e.g., the second sub light emitting elements 411b) is electrically connected to the second connection lines 120, so that all the first light emitting elements 411 are electrically connected to the corresponding first pixel circuits 412 through the corresponding connection lines, thereby implementing driving of the first light emitting elements 411.

For example, the first connecting line 110 and the second connecting line 120 are located in different film layers of the display substrate 01, that is, the first connecting line 110 and the second connecting line 120 are located in two different film layers. Due to the different film layers, the orthographic projection of the first connecting line 110 on the display substrate 01 and the orthographic projection of the second connecting line 120 on the display substrate 01 can be overlapped, so that the wiring space can be effectively utilized, the wiring is convenient, and all the first light emitting elements 411 in the first display region 11 are electrically connected with the corresponding connecting lines. Even if the number of the first light emitting elements 411 is large and the number of the corresponding connection lines is large, the display substrate 01 can provide a sufficient wiring space.

Note that the different film layers are insulated from each other at the positions where the vias are not provided. For example, when it is required to electrically connect the traces in different film layers, the traces in different film layers may be electrically connected by providing the via holes. For example, the different layers are prepared in different processes, such as a first process to prepare one of the different layers and then a second process to prepare another of the different layers. For example, after the first process is performed and before the second process is performed, an insulating layer may be prepared by a third process, and the insulating layer is located between different film layers to insulate the different film layers from each other at a position where the via hole is not disposed. For example, the first process, the second process, and the third process may be the same or different. For example, when the display substrate 01 includes a base substrate, different film layers have different distances from the base substrate in a direction perpendicular to the base substrate. That is, among the different layers, one layer is closer to the substrate base plate and the other layer is farther from the substrate base plate. In the following description, the meaning of the different film layers can refer to the above description and will not be described again.

It should be noted that, in the embodiment of the present disclosure, the connection lines for electrically connecting the first light emitting element 411 and the first pixel circuit 412 are not limited to being located on two different film layers, but may also be located on 3 different film layers, 4 different film layers, or any number of film layers, that is, the connection lines are not limited to the first connection line 110 and the second connection line 120 described above, and may also include other connection lines located on different film layers from the first connection line 110 and the second connection line 120, which is not limited in this respect.

For example, as shown in fig. 5A, the first connection lines 110 and the second connection lines 120 form a connection line array, and each connection line (which may be the first connection line 110 or the second connection line 120) in the connection line array electrically connects one first light emitting element 411 and one first pixel circuit 412. For example, in order to prevent the difference in the lengths of the plurality of connection lines from being too large and thus improve the balance of the circuit environment, the pitches between the first light emitting element 411 and the first pixel circuit 412 which are correspondingly connected may be substantially similar in the wiring design. For example, in the example shown in fig. 5A, a plurality of pixel circuits (including the first pixel circuit 412 and the second pixel circuit 422) are arranged in an array, and a plurality of first light emitting elements 411 are also arranged in an array. For the pixel circuit and the first light emitting element 411 located at the Q-th row, the first pixel circuit 412 of the (P-1) -th column and the first light emitting element 411 of the W-th column are electrically connected by a connection line (which may be the first connection line 110 or the second connection line 120) having a length of, for example, about S1; the first pixel circuit 412 of the (P +1) th column and the first light-emitting element 411 of the (W +1) th column are electrically connected by a connection line (which may be the first connection line 110 or the second connection line 120) having a length of, for example, about S2. For example, the difference between S1 and S2 is within a certain range and is not too large. For example, the specific value of the difference range between S1 and S2 may depend on actual needs, and the embodiment of the disclosure is not limited thereto. Similarly, the first pixel circuit 412 and the first light emitting element 411 in the (Q-1) th row and the (Q-2) th row may be wired similarly.

Compared to the case where the first pixel circuit 412 of the (P-1) th column is connected to the first light emitting element 411 of the (W +1) th column and the first pixel circuit 412 of the (P +1) th column is connected to the first light emitting element 411 of the W-th column, the example shown in fig. 5A may make the difference in length of the plurality of connection lines not so large, that is, the difference in length of the plurality of first connection lines 110 not so large, the difference in length of the plurality of second connection lines 120 not so large, and the difference in length of the first connection lines 110 and the second connection lines 120 not so large, so that the balance of the circuit environment may be improved. Of course, the embodiment of the disclosure is not limited to the situation shown in fig. 5A, and the distribution positions of the first pixel circuit 412 and the first light emitting element 411 connected by the connection line may also be other positions, which may be determined according to actual requirements, and the embodiment of the disclosure is not limited thereto.

It should be noted that the distribution manner and the position relationship of the plurality of first connecting lines 110 and the plurality of second connecting lines 120 in the plane parallel to the display substrate 01 are not limited, which may be determined according to the actual wiring requirement. For example, in a plane parallel to the display substrate 01, the first connection lines 110 and the second connection lines 120 may be disposed at intervals one by one, may be disposed at intervals in groups, and may be irregularly distributed.

It should be noted that, in the embodiment of the present disclosure, the first sub light emitting element 411a and the second sub light emitting element 411b may not be different in structure and function, and the first sub pixel circuit 412a and the second sub pixel circuit 412b may not be different in structure and function, and are referred to as "first" and "second", only to distinguish the connection lines (i.e., the first connection line 110 and the second connection line 120) connected to these light emitting elements and pixel circuits, which does not limit the embodiment of the present disclosure.

Fig. 6A is a schematic cross-sectional view taken along line a-a' in fig. 5B, fig. 6B is an enlarged view of the first via H1 in fig. 6A, fig. 6C is a schematic layout of a region corresponding to the first via H1 and the connected anode in fig. 6A, and fig. 6D is a schematic layout of a region corresponding to the third via H3 and the connected source-drain metal layer in fig. 6A.

For example, as shown in fig. 6A to 6D, the display substrate 01 includes a third insulating layer 33, a first connection layer 21, a first insulating layer 31, a second insulating layer 32, and an anode layer 40, which are sequentially stacked. The first sub light emitting element 411a includes an anode 4111, a cathode 4113, and a light emitting layer 4112 between the anode 4111 and the cathode 4113. The first connection line 110 is located at the first connection layer 21, and the anode 4111 of the first sub light emitting element 411a is located at the anode layer 40. The anode 4111 of the first sub light emitting element 411a is electrically connected to the first connection line 110 through a first via H1 penetrating the first and second insulating layers 31 and 32.

For example, the cross-sectional shape of the first via H1 in a plane perpendicular to the display substrate 01 is an inverted boss shape. In the illustrated cross-sectional views (e.g., fig. 6A and 6B), the inverted-boss shape may be regarded as a shape in which two rectangles having different sizes are spliced, the rectangle located above is larger, and the rectangle located below is smaller, thereby forming a step on at least one side surface of the inverted-boss shape, e.g., forming a step on both side surfaces; for example, the orthographic projection of the portion corresponding to the lower rectangle on the substrate base plate 74 is completely inside the orthographic projection of the portion corresponding to the upper rectangle on the substrate base plate 74, for example, each edge of the orthographic projection of the portion corresponding to the lower rectangle on the substrate base plate 74 is spaced from each edge of the orthographic projection of the portion corresponding to the upper rectangle on the substrate base plate 74. For example, in the first via H1, the opening caliber L2 of the second insulating layer 32 is larger than the opening caliber L1 of the first insulating layer 31. For example, the aperture diameter L2 of the second insulating layer 32 may be 6 μm × 6 μm, or the aperture diameter L1 of the first insulating layer 31 may be 6 μm × 6 μm. Because the first via hole H1 needs to penetrate through two insulating layers, the depth of the first via hole H1 is large, the first via hole H1 is set to be in an inverted boss shape, the processing difficulty of the first via hole H1 can be reduced, and conductive materials (such as materials of the anode 4111) can be conveniently deposited in the first via hole H1, so that the reliability of electrical connection is improved.

For example, the anode 4111 of the first sub light emitting element 411a includes a first groove structure GR1, the first groove structure GR1 is located within the first via H1, and the bottom of the first groove structure GR1 contacts the first connection line 110 to achieve electrical connection. By arranging the portion of the anode 4111 deposited in the first via hole H1 as a groove structure, the thickness of the portion can be reduced, so that the difference between the thickness of the portion and the thickness of the other portion of the anode 4111 is not large, thereby improving the uniformity of transmitted light on the whole, making no obvious brightness difference in different areas, and making the first display area 11 have better light transmittance, thereby facilitating the improvement of the sensing effect of an off-screen sensor (such as a camera), for example, making imaging clearer. Because the first via hole H1 is in the shape of an inverted boss, the formation of the groove structure is facilitated when the anode 4111 is prepared, and the process difficulty can be reduced.

For example, in some examples, a surface of the first groove structure GR1 distal from the first connection layer 21 is curved. By the mode, the light intensity of the transmitted light can be continuously changed, and the light intensity is prevented from sudden change at a local position, so that the uniformity of the transmitted light is further improved. Of course, the embodiments of the present disclosure are not limited thereto, and in other examples, the surface of the first groove structure GR1 away from the first connection layer 21 may also be a plane, an inclined surface, etc., which may be determined according to actual requirements.

For example, the anode 4111 may include a plurality of anode sublayers, such as an ITO/Ag/ITO three-layer structure (not shown), and the embodiment of the disclosure does not limit the specific form of the anode 4111. For example, cathode 4113 may be a structure formed on the entire surface of display substrate 01, and cathode 4113 may include a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), or silver (Ag). For example, since cathode 4113 can be formed in a very thin layer, cathode 4113 has good light transmittance. For example, when anode 4111 comprises a three-layer structure of ITO/Ag/ITO, its thickness can be 86/1000/86A.

It should be noted that, in the layout shown in fig. 6C, since the second connection line 120 is located at a different layer from the first connection line 110 (the layer where the second connection line 120 is located and the corresponding cross-sectional structure will be described later), and the second connection line 120 and the anode 4111 of the first sub light emitting element 411a are also located at different layers, although the profile of the second connection line 120 overlaps with the anode 4111 of the first sub light emitting element 411a, the second connection line 120 is not electrically connected to the anode 4111 of the first sub light emitting element 411 a.

For example, as shown in fig. 6A, the first sub-pixel circuit 412a includes a first switching transistor (e.g., a switching thin film transistor 412T), a storage capacitor 412C, and the like. The switching thin film transistor 412T includes a gate electrode 4121, an active layer 4122, a first pole 4123, and a second pole 4124. For example, the first pole 4123 can be a source or a drain, and the second pole 4124 can be a drain or a source. For example, the storage capacitor 412C includes a first capacitor plate 4125 and a second capacitor plate 4126.

For example, the active layer 4121 is provided on the substrate base 74, and a first gate insulating layer 741 is provided on a side of the active layer 4121 away from the substrate base 74. The gate electrode 4122 and the first capacitor plate 4125 are disposed on the same layer, and are located on a side of the first gate insulating layer 741 away from the substrate 74, and the second gate insulating layer 742 is disposed on a side of the gate electrode 4122 and the first capacitor plate 4125 away from the substrate 74. The second capacitor plate 4126 is provided on the side of the second gate insulating layer 742 away from the substrate 74, and the interlayer insulating layer 743 is provided on the side of the second capacitor plate 4126 away from the substrate 74. The first and second electrodes 4123 and 4124 (i.e., source and drain electrodes) are disposed on a side of the interlayer insulating layer 743 away from the substrate 74, and are electrically connected to the active layer 4121 through vias located in the first and second gate insulating layers 741 and 742 and the interlayer insulating layer 743. The first and second electrodes 4123 and 4124 are located on the source-drain metal layer SD, the third insulating layer 33 is located on the source-drain metal layer SD, and the first connection layer 21 is located on the third insulating layer 33. The third insulating layer 33 can perform not only an insulating function but also a planarizing function.

For example, the second end of the first connection line 110 is electrically connected to the second electrode 4124 of the first switching transistor (e.g., the switching thin film transistor 412T) included in the first sub-pixel circuit 412a through the third via hole H3 penetrating the third insulating layer 33. Of course, embodiments of the present disclosure are not limited thereto, and in other examples, the second end of the first connection line 110 may also be electrically connected to the first pole 4123 of the switching thin film transistor 412T included in the first sub-pixel circuit 412 a. For example, the cross-sectional dimension of the third via H3 in a plane parallel to the display substrate 01 may be 4 μm × 4 μm.

For example, the first display area 11 further includes a transparent support layer 78 on the substrate base 74, and the first sub light emitting element 411a is located on a side of the transparent support layer 78 away from the substrate base 74. Thus, the first sub light emitting element 411a in the first display region 11 can be at substantially the same height as the light emitting elements in the other display regions (for example, the second light emitting element 421 in the second display region 12 and the third light emitting element 431 in the third display region 13 described later) with respect to the substrate 74, so that the display effect of the display substrate 01 can be improved.

For example, the display substrate 01 may further include a pixel defining layer 746, an encapsulating layer 747, and the like. For example, a pixel defining layer 746 is disposed on the anode 4111 (e.g., a portion of the structure of the anode 4111), and includes a plurality of openings to define different pixels or sub-pixels, and a light emitting layer 4112 is formed in the openings of the pixel defining layer 746. For example, the horizontal distance of the opening of the pixel defining layer 746 from the first via H1 may be 4.6 μm. For example, the encapsulation layer 747 may include a single layer or a multi-layer encapsulation structure, for example, a stack of an inorganic encapsulation layer and an organic encapsulation layer, thereby improving the encapsulation effect for the display substrate 01.

For example, the pixel defining layer 746 in the first, second and third display regions 11, 12 and 13 is disposed on the same layer, and the encapsulating layer 747 in the first, second and third display regions 11, 12 and 13 is disposed on the same layer, and in some embodiments, integrally connected, which is not limited by the embodiments of the present disclosure.

For example, in various embodiments of the present disclosure, the substrate 74 may be a glass substrate, a quartz substrate, a metal substrate, a resin-based substrate, or the like, and may be a rigid substrate or a flexible substrate, which is not limited in this respect.

For example, the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743, the first insulating layer 31, the second insulating layer 32, the third insulating layer 33, the pixel defining layer 746, and the encapsulation layer 747 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or an organic insulating material such as polyimide, polyththalimide, acrylic, benzocyclobutene, or phenol resin. The embodiment of the present disclosure does not specifically limit the materials of the functional layers. For example, the thicknesses of the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 may be 10000 to 15000A, respectively.

For example, the material of the active layer 4121 may include a semiconductor material such as polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). For example, a portion of the active layer 4121 may be made conductive by a conductive process such as doping, thereby having high conductivity.

For example, the material of the gate 4122, the first capacitor plate 4125 and the second capacitor plate 4126 may include a metal material or an alloy material, such as molybdenum, aluminum and titanium.

For example, the material of the first and second poles 4123 and 4124 may include a metal material or an alloy material, such as a metal single layer or a multi-layer structure formed of molybdenum, aluminum, titanium, and the like, for example, the multi-layer structure is a multi-metal layer stack, such as a titanium, aluminum, titanium three-layer metal stack (Ti/Al/Ti), and the like.

For example, the display substrate 01 provided in the embodiments of the present disclosure may be an Organic Light Emitting Diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, and the specific type of the display substrate is not limited in the embodiments of the present disclosure.

For example, in the case that the display substrate 01 is an organic light emitting diode display substrate, the light emitting layer (e.g., the light emitting layer 4112) may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent light emitting material or a phosphorescent light emitting material, and may emit red light, green light, blue light, or white light. In addition, according to actual different needs, in different examples, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

For example, in the case where the display substrate 01 is a quantum dot light emitting diode (QLED) display substrate, the light emitting layer (e.g., the light emitting layer 4112) may include a quantum dot material, such as a silicon quantum dot, a germanium quantum dot, a cadmium sulfide quantum dot, a cadmium selenide quantum dot, a cadmium telluride quantum dot, a zinc selenide quantum dot, a lead sulfide quantum dot, a lead selenide quantum dot, an indium phosphide quantum dot, an indium arsenide quantum dot, and the like, and the particle size of the quantum dot is, for example, 2nm to 20 nm.

Fig. 7A is a schematic cross-sectional view taken along line B-B' in fig. 5B, fig. 7B is an enlarged view of the second via H2 in fig. 7A, fig. 7C is a schematic layout of a region corresponding to the second via H2 and the connected anode in fig. 7A, fig. 7D is another schematic structural view of the fourth via H4, and fig. 7E is a schematic layout of a region corresponding to the fourth via H4 and the connected source-drain metal layer in fig. 7A.

For example, as shown in fig. 7A to 7E, the display substrate 01 further includes a second connection layer 22, the second connection layer 22 is located between the first insulation layer 31 and the second insulation layer 32, and the second connection line 120 is located on the second connection layer 22. The second sub-light emitting element 411b is disposed in a manner similar to that of the first sub-light emitting element 411a, and the second sub-pixel circuit 412b includes a first switching transistor (e.g., a switching thin film transistor 412T) and a storage capacitor 412C, which are disposed in a manner similar to that of the first switching transistor and the storage capacitor 412C of the first sub-pixel circuit 412a, and the related description can refer to the description above with respect to fig. 6A to 6D, and will not be repeated herein.

For example, the anode 4111 of the second sub light emitting element 411b is located at the anode layer 40, and the anode 4111 of the second sub light emitting element 411b is electrically connected to the second connection line 120 through a second via H2 penetrating through the second insulating layer 32.

For example, the anode 4111 of the second sub light emitting element 411b includes a second groove structure GR2, the second groove structure GR2 is located within the second via H2, and the bottom of the second groove structure GR2 contacts the second connection line 120 to achieve electrical connection. By providing the portion of the anode 4111 deposited in the second via hole H2 as a groove structure, the thickness of the portion can be reduced without greatly differing from the thickness of the other portions of the anode 4111, thereby improving the uniformity of transmitted light as a whole.

For example, in some examples, a surface of the second groove structure GR2 distal from the second connection layer 22 is curved. By the mode, the light intensity of the transmitted light can be continuously changed, and the light intensity is prevented from sudden change at a local position, so that the uniformity of the transmitted light is further improved. Of course, the embodiments of the present disclosure are not limited thereto, and in other examples, the surface of the second groove structure GR2 away from the second connection layer 22 may also be a plane, a slope, etc., which may be determined according to actual requirements.

For example, the second end of the second connection line 120 is electrically connected to the second pole 4124 of the first switching transistor (e.g., the switching thin film transistor 412T) of the second sub-pixel circuit 412b through a fourth via H4 passing through the third insulating layer 33 and the first insulating layer 31. Of course, the embodiments of the present disclosure are not limited thereto, and in other examples, the second end of the second connection line 120 may also be electrically connected to the first pole 4123 of the switching thin film transistor 412T included in the second sub-pixel circuit 412 b.

For example, as shown in fig. 7A, the cross-sectional shape of the fourth via H4 in a plane perpendicular to the display substrate 01 is an inverted boss shape. For example, in the fourth via H4, the aperture diameter of the first insulating layer 31 is larger than the aperture diameter of the third insulating layer 33. Because the fourth via hole H4 needs to penetrate through two insulating layers, the depth of the fourth via hole H4 is large, the fourth via hole H4 is set to be in an inverted boss shape, the processing difficulty of the fourth via hole H4 can be reduced, and conductive materials (such as the material of the second connection line 120) can be conveniently deposited in the fourth via hole H4, so that the reliability of electrical connection is improved.

It should be noted that, in the layout shown in fig. 7C, since the first connecting line 110 is located at a different film layer from the second connecting line 120, and the first connecting line 110 and the anode 4111 of the second sub light emitting element 411b are also located at a different film layer, although the outline of the first connecting line 110 overlaps with the anode 4111 of the second sub light emitting element 411b, the first connecting line 110 is not electrically connected to the anode 4111 of the second sub light emitting element 411 b.

It should be noted that the connection manner of the second connection line 120 and the first switching transistor (for example, the switching thin film transistor 412T) is not limited to the manner shown in fig. 7A, and the electrical connection may be realized by disposing a transition metal layer, so as to reduce the process difficulty. For example, in other examples, as shown in fig. 7D, in the fourth via H4, the second connection line 120 is electrically connected to the transition metal layer 23 contact, and the transition metal layer 23 is electrically connected to the first pole 4123 or the second pole 4124 contact of the first switching transistor (e.g., the switching thin film transistor 412T) of the second sub-pixel circuit 412b, thereby achieving the electrical connection of the second connection line 120 and the switching thin film transistor 412T. For example, the transition metal layer 23 and the first connection layer 21 are formed in the same process, that is, the transition metal layer 23 and the first connection layer 21 may be the same film layer in which a portion of the structure forms the first connection line 110 and another portion of the structure is used to electrically connect the second connection line 120 and the switching thin film transistor 412T of the second sub-pixel circuit 412 b. By arranging the transition metal layer 23, the process difficulty can be reduced, and the reliability of electrical connection can be improved.

For example, as shown in fig. 5B, the second display region 12 further includes at least one (e.g., a plurality of) second light emitting elements 421 and at least one (e.g., a plurality of) second pixel circuits 422. The second light emitting elements 421 are electrically connected to the second pixel circuits 422 in a one-to-one correspondence, and the second pixel circuits 422 are used for driving the second light emitting elements 421 to emit light. Note that the rectangular frame indicated by reference numeral 422 in fig. 5B is only used to show the approximate position of the second pixel circuit 422, and does not indicate the specific shape of the second pixel circuit 422 and the specific boundary of the second pixel circuit 422. For example, at least one second light emitting element 421 and its corresponding second pixel circuit 422 constitute one second pixel driving unit 42.

In fig. 5B, the second pixel driving unit 42 may include one second pixel circuit 422 and one second light emitting element 421, or may include a plurality of second pixel circuits 422 and a plurality of second light emitting elements 421. When the second pixel driving unit 42 includes a plurality of second pixel circuits 422 and a plurality of second light emitting elements 421, the number of the second pixel circuits 422 in each of the second pixel driving units 42 is, for example, equal to the number of the second light emitting elements 421, thereby realizing one-to-one driving.

For example, the plurality of second light emitting elements 421 are arranged in an array, and the plurality of second pixel circuits 422 are also arranged in an array. Here, the "array arrangement" may refer to that a plurality of devices are grouped and a plurality of groups of devices are arranged in an array, and may also refer to that a plurality of devices are arranged in an array, and the embodiment of the present disclosure is not limited thereto. For example, in some examples, as shown in fig. 5B, every 4 second light emitting elements 421 are a group, the groups of second light emitting elements 421 are arranged in an array, correspondingly, every 4 second pixel circuits 422 are a group, and the groups of second pixel circuits 422 are arranged in an array, and in this case, each second pixel driving unit 42 includes 4 second pixel circuits 422 and 4 second light emitting elements 421.

Fig. 8A is a schematic cross-sectional view taken along line C-C' in fig. 5B, fig. 8B is an enlarged view of the fifth via H5 in fig. 8A, and fig. 8C is a schematic layout of a region corresponding to the fifth via H5 and the connected anode and source drain metal layers in fig. 8A.

For example, as shown in fig. 8A-8C, the second pixel circuit 422 includes a second switching transistor (e.g., a switching thin film transistor 422T), a storage capacitor 422C, and the like. The switching thin film transistor 422T includes a gate electrode 4221, an active layer 4222, a first pole 4223, and a second pole 4224. For example, the first pole 4223 may be a source or a drain, and the second pole 4224 may be a drain or a source. For example, storage capacitor 422C includes a first capacitor plate 4225 and a second capacitor plate 4226.

For example, the active layer 4221 is provided on the base substrate 74, and a side of the active layer 4221 away from the base substrate 74 is provided with a first gate insulating layer 741. The gate electrode 4222 and the first capacitor plate 4225 are disposed on the same layer, and are located on one side of the first gate insulating layer 741 away from the substrate 74, and the second gate insulating layer 742 is disposed on one side of the gate electrode 4222 and the first capacitor plate 4225 away from the substrate 74. The second capacitor plate 4226 is provided on the side of the second gate insulating layer 742 away from the substrate 74, and the interlayer insulating layer 743 is provided on the side of the second capacitor plate 4226 away from the substrate 74. The first and second electrodes 4223 and 4224 (i.e., source-drain electrodes) are disposed on a side of the interlayer insulating layer 743 remote from the substrate 74, and are electrically connected to the active layer 4221 through vias located in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743. The first and second electrodes 4223 and 4224 are located on the source drain metal layer SD, and the third insulating layer 33 is located on the source drain metal layer SD. The third insulating layer 33 can perform not only an insulating function but also a planarizing function.

For example, the second light-emitting element 421 includes an anode 4211, a cathode 4213, and a light-emitting layer 4212 between the anode 4211 and the cathode 4213, and the anode 4211 is located at the anode layer 40. The anode 4211 of the second light emitting element 421 is electrically connected to the first pole 4223 or the second pole 4224 of the second switching transistor (for example, the switching thin film transistor 422T) through a fifth via H5 penetrating the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33.

For example, the cross-sectional shape of the fifth through hole H5 in a plane perpendicular to the display substrate 01 is an inverted boss shape. In the fifth via H5, the aperture diameter L3 of the first insulating layer 31 is larger than the aperture diameter L4 of the third insulating layer 33. Since the fifth via hole H5 needs to penetrate through 3 insulating layers, the depth of the fifth via hole H5 is large, and the fifth via hole H5 is formed in an inverted boss shape, so that the difficulty in processing the fifth via hole H5 can be reduced, and a conductive material (e.g., the material of the anode 4211) can be deposited in the fifth via hole H5, thereby improving the reliability of electrical connection.

For example, in the fifth via H5, the opening aperture of the second insulating layer 32 is equal to or larger than the opening aperture of the first insulating layer 31. For example, as shown in fig. 8A to 8B, in some examples, the aperture of the second insulating layer 32 is equal to the aperture of the first insulating layer 31, that is, equal to L3, so that the apertures of the first insulating layer 31 and the second insulating layer 32 can be prepared by using the same mask, thereby reducing the number of masks required and reducing the production cost. For example, in other examples, the aperture of the second insulating layer 32 may be larger than the aperture of the first insulating layer 31, so that the fifth via hole H5 may be formed in a three-step shape to further reduce the processing difficulty and facilitate the deposition of a conductive material (e.g., the material of the anode 4211) in the fifth via hole H5, further improving the reliability of the electrical connection.

For example, the anode 4211 of the second light emitting element 421 includes a third groove structure GR3, the third groove structure GR3 is located in the fifth via H5, and a bottom of the third groove structure GR3 contacts the first pole 4223 or the second pole 4224 of the second switching transistor (e.g., the switching thin film transistor 422T) to achieve electrical connection. By providing the portion of the anode 4211 deposited in the fifth through hole H5 as a groove structure, the thickness of the portion can be reduced without much difference from the thickness of the other portions of the anode 4211, thereby improving the uniformity of transmitted light as a whole. Since the fifth through hole H5 is in the shape of an inverted boss, the groove structure is advantageously formed when the anode 4211 is prepared, and the process difficulty can be reduced. For example, the surface of the third groove structure GR3 away from the source drain metal layer SD may be a curved surface, a flat surface, a slope, etc., which is not limited in this embodiment of the present disclosure.

Fig. 9 is an enlarged view of a partial region REG3 of the third display region of the display substrate shown in fig. 1. For example, as shown in fig. 9, the third display region 13 includes at least one (e.g., a plurality of) third light emitting elements 431 and at least one (e.g., a plurality of) third pixel circuits 432. The third light emitting elements 431 are electrically connected to the third pixel circuits 432 in a one-to-one correspondence, and the third pixel circuits 432 are used for driving the third light emitting elements 431 to emit light. Note that the rectangular frame indicated by reference numeral 432 in fig. 9 is only used to show the approximate position of the third pixel circuit 432, and does not indicate the specific shape of the third pixel circuit 432 and the specific boundary of the third pixel circuit 432. For example, at least one third light emitting element 431 and its corresponding third pixel circuit 432 constitute one third pixel driving unit 43.

In fig. 9, the third pixel driving unit 43 may include one third pixel circuit 432 and one third light emitting element 431, or may include a plurality of third pixel circuits 432 and a plurality of third light emitting elements 431. When the third pixel driving unit 43 includes a plurality of third pixel circuits 432 and a plurality of third light emitting elements 431, the number of the third pixel circuits 432 in each of the third pixel driving units 43 is, for example, equal to the number of the third light emitting elements 431, thereby realizing one-to-one corresponding driving.

For example, the plurality of third light emitting elements 431 are arranged in an array, and the plurality of third pixel circuits 432 are also arranged in an array. Here, the "array arrangement" may refer to that a plurality of devices are grouped and a plurality of groups of devices are arranged in an array, and may also refer to that a plurality of devices are arranged in an array, and the embodiment of the present disclosure is not limited thereto. For example, in some examples, as shown in fig. 9, each 4 third light emitting elements 431 is a group, the plurality of groups of third light emitting elements 431 are arranged in an array, and correspondingly, each 4 third pixel circuits 432 is a group, and the plurality of groups of third pixel circuits 432 are arranged in an array, and in this case, each third pixel driving unit 43 includes 4 third pixel circuits 432 and 4 third light emitting elements 431.

Fig. 10A is a schematic cross-sectional view taken along line D-D' in fig. 9, and fig. 10B is an enlarged view of the sixth via H6 in fig. 10A.

For example, as shown in fig. 10A to 10B, the third pixel circuit 432 includes a third switching transistor (e.g., a switching thin film transistor 432T), a storage capacitor 432C, and the like. The switching thin film transistor 432T includes a gate 4321, an active layer 4322, a first pole 4323, and a second pole 4324. For example, the first pole 4323 can be a source or a drain, and the second pole 4324 can be a drain or a source. For example, the storage capacitor 432C includes a first capacitor plate 4325 and a second capacitor plate 4326.

For example, the active layer 4321 is disposed on the base substrate 74, and a first gate insulating layer 741 is disposed on a side of the active layer 4321 away from the base substrate 74. The gate 4322 and the first capacitor plate 4325 are disposed on the same layer, and are located on a side of the first gate insulating layer 741 away from the substrate 74, and the second gate insulating layer 742 is disposed on a side of the gate 4322 and the first capacitor plate 4325 away from the substrate 74. The second capacitor plate 4326 is disposed on a side of the second gate insulating layer 742 away from the substrate 74, and the interlayer insulating layer 743 is disposed on a side of the second capacitor plate 4326 away from the substrate 74. The first and second electrodes 4323 and 4324 (i.e., source-drain electrodes) are provided on a side of the interlayer insulating layer 743 away from the substrate 74, and are electrically connected to the active layer 4321 through vias in the first and second gate insulating layers 741 and 742 and the interlayer insulating layer 743. The first electrode 4323 and the second electrode 4324 are both located on the source-drain metal layer SD, and the third insulating layer 33 is located on the source-drain metal layer SD. The third insulating layer 33 can perform not only an insulating function but also a planarizing function.

For example, the third light emitting element 431 includes an anode 4311, a cathode 4313, and a light emitting layer 4312 between the anode 4311 and the cathode 4313, and the anode 4311 is located at the anode layer 40. The anode 4311 of the third light emitting element 431 is electrically connected to the first pole 4323 or the second pole 4324 of the third switching transistor (for example, the switching thin film transistor 432T) through a sixth via H6 penetrating the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33.

For example, the sectional shape of the sixth via H6 in the plane perpendicular to the display substrate 01 is an inverted boss shape. In the sixth via H6, the opening caliber L5 of the first insulating layer 31 is larger than the opening caliber L6 of the third insulating layer 33. Since the sixth via H6 needs to penetrate through the 3-layer insulating layer, the depth of the sixth via H6 is large, and the sixth via H6 is formed in an inverted-boss shape, so that the processing difficulty of the sixth via H6 can be reduced, and a conductive material (e.g., the material of the anode 4311) can be deposited in the sixth via H6, thereby improving the reliability of electrical connection.

For example, in the sixth via H6, the opening aperture of the second insulating layer 32 is equal to or larger than the opening aperture of the first insulating layer 31. For example, as shown in fig. 10A to 10B, in some examples, the aperture of the second insulating layer 32 is equal to the aperture of the first insulating layer 31, that is, equal to L5, so that the apertures of the first insulating layer 31 and the second insulating layer 32 can be prepared by using the same mask, thereby reducing the number of masks required and reducing the production cost. For example, in other examples, the aperture of the second insulating layer 32 may be larger than the aperture of the first insulating layer 31, so that the sixth via H6 may be formed in a three-step shape to further reduce the processing difficulty and facilitate the deposition of a conductive material (e.g., the material of the anode 4311) in the sixth via H6, further improving the reliability of the electrical connection.

For example, the anode 4311 of the third light emitting element 431 includes a fourth groove structure GR4, the fourth groove structure GR4 is located within the sixth via H6, and the bottom of the fourth groove structure GR4 contacts the first pole 4323 or the second pole 4324 of the third switching transistor (e.g., the switching thin film transistor 432T) to achieve electrical connection. By providing the portion of the anode 4311 deposited in the sixth via hole H6 with a groove structure, the thickness of the portion can be reduced without a large difference from the thickness of the other portion of the anode 4311, thereby improving the uniformity of transmitted light as a whole. Since the sixth via hole H6 is in the shape of an inverted convex, the groove structure is advantageously formed when the anode 4311 is prepared, and the process difficulty can be reduced. For example, the surface of the fourth groove structure GR4 away from the source drain metal layer SD may be a curved surface, a flat surface, a slope, etc., which is not limited in this embodiment of the disclosure.

Fig. 11A is a schematic layout corresponding to the partial region REG4 in fig. 4, fig. 11B is a schematic layout showing only the first connection line in fig. 11A, fig. 11C is a schematic layout showing only the second connection line in fig. 11A, and fig. 11D is a schematic cross-sectional view along line E-E' in fig. 11A. For example, as shown in fig. 11A to 11C, in the first display region 11, in a region where the anode is not disposed, the first connection line 110 and the second connection line 120 extend in respective extending directions, for example, the extending direction of the first connection line 110 and the extending direction of the second connection line 120 may be the same or different. It should be noted that although there is an overlap between the projections of the first connection line 110 and the second connection line 120 in fig. 11A, since the first connection line 110 and the second connection line 120 are located on different film layers, the two lines are still insulated from each other, and the respective signal transmission is not affected. For example, as shown in fig. 11D, the third insulating layer 33, the first connection line 110 (i.e., the first connection layer 21), the first insulating layer 31, the second connection line 120 (i.e., the second connection layer 22), the second insulating layer 32, and the pixel defining layer 746 are sequentially stacked. Since the first insulating layer 31 is provided, the first connection line 110 and the second connection line 120 are insulated from each other and are not short-circuited. Other layers may be referred to above and are not shown in fig. 11D.

Fig. 12A is one of schematic layouts corresponding to the second light emitting element in the second display region of the display substrate according to some embodiments of the present disclosure, and fig. 12B is a second of schematic layouts corresponding to the second light emitting element in the second display region of the display substrate according to some embodiments of the present disclosure. For example, as shown in fig. 12A to 12B, in the second display region 12, in a region where the second light emitting element 421 is provided, the first connection line 110 and the second connection line 120 pass through from below the anode 4211 of the second light emitting element 421 (i.e., a side of the anode 4211 close to the base substrate 74), and are insulated from the anode 4211 of the second light emitting element 421.

For example, in the embodiment of the present disclosure, the first connection line 110 and the second connection line 120 may respectively include transparent conductive traces, which are made of Indium Tin Oxide (ITO), for example. The first connection lines 110 and the second connection lines 120 are transparent conductive traces, which can improve the light transmittance of the display substrate 01.

For example, the plurality of first light emitting elements 411 are arranged in an array, and the first connection line 110 and the second connection line 120 each extend in a row direction of the array formed by the plurality of first light emitting elements 411. Of course, the embodiment of the present disclosure is not limited thereto, and the extending direction of the first connecting line 110 and the second connecting line 120 may also be any other direction, and the embodiment of the present disclosure is not limited thereto. For example, the extending direction of the first connection line 110 and the extending direction of the second connection line 120 may be the same or different.

For example, the first, second, and third light emitting elements 411, 421, and 431 may respectively include Organic Light Emitting Diodes (OLEDs). Of course, the embodiments of the present disclosure are not limited thereto, and the first light emitting element 411, the second light emitting element 421 and the third light emitting element 431 may also be quantum dot light emitting diodes (QLEDs) or other suitable light emitting devices, which is not limited thereto.

For example, the unit area distribution density of the plurality of first light emitting elements 411 in the first display region 11 is smaller than the unit area distribution density of the plurality of second light emitting elements 421 in the second display region 12, and the unit area distribution density of the plurality of second light emitting elements 421 in the second display region 12 is smaller than the unit area distribution density of the plurality of third light emitting elements 431 in the third display region 13. For example, the first display region 11 and the second display region 12 may be referred to as a low resolution region of the display substrate 01, and accordingly, the third display region 13 may be referred to as a high resolution region of the display substrate 01. For example, the sum of the pixel light emitting areas of the second display region 12 and the first display region 11 may be 1/8 to 1/2 of the pixel light emitting area of the third display region 13.

It should be noted that, in some examples, the unit area distribution density of the plurality of first light emitting elements 411 in the first display region 11 may also be equal to the unit area distribution density of the plurality of second light emitting elements 421 in the second display region 12, which may be determined according to practical requirements, and this is not limited by the embodiments of the present disclosure.

The unit area distribution density of the light-emitting elements of the first display area 11, the second display area 12 and the third display area 13 is sequentially increased, so that normal light emission of the three display areas can be guaranteed, meanwhile, light of the first side of the display substrate 01 can conveniently penetrate through the first display area 11 to reach the second side, and then the light can be conveniently sensed by the sensor arranged on the second side of the display substrate 01.

It should be noted that, in the embodiments of the present disclosure, the display substrate 01 may further include other structures or components, and is not limited to the structures and components described above. For example, the display substrate 01 may further include one or more barrier layers, buffer layers, and the like, which are not limited in this respect by the embodiments of the present disclosure.

Fig. 13A is a schematic structural diagram of a 7T1C pixel circuit. For example, the 7T1C pixel circuit can be used for the first pixel circuit 412 (e.g., the first sub-pixel circuit 412a and the second sub-pixel circuit 412b), the second pixel circuit 422, and the third pixel circuit 432.

For example, as shown in fig. 13A, the 7T1C pixel circuit 100 includes a first transistor CT1, a second transistor CT2, a third transistor CT3, a fourth transistor CT4, a fifth transistor CT5, a sixth transistor CT6, a seventh transistor CT7, and a storage capacitor Cst. For example, the first to seventh transistors CT1 to CT7 are all P-type transistors.

As shown in fig. 13A, a first terminal of the storage capacitor Cst is connected to the first power voltage terminal VDD to receive the first power voltage V1, and a second terminal of the storage capacitor Cst is connected to the first node N1. A first terminal of the light emitting element EL is connected to the fourth node N4, and a second terminal of the light emitting element EL is connected to the second power voltage terminal VSS to receive the second power voltage V2. A control terminal of the first transistor CT1 is connected to the first node N1, a first terminal of the first transistor CT1 is connected to the second node N2, and a second terminal of the first transistor CT1 is connected to the third node N3. A first terminal of the second transistor CT2 is connected to the second node N2, and a second terminal of the second transistor CT2 is connected to a data signal terminal DAT to receive a data signal (e.g., a data voltage) Vdata. A first terminal of the third transistor CT3 is coupled to the first node N1, and a second terminal of the third transistor CT3 is coupled to the third node N3.

A first terminal of the fourth transistor CT4 is connected to the first node N1, and a second terminal of the fourth transistor CT4 is connected to the first reset signal terminal Init1 to receive the first reset signal Vinit1 provided by the first reset signal terminal Init 1. A first terminal of the fifth transistor CT5 is connected to the first power voltage terminal VDD, and a first terminal of the fifth transistor CT5 is connected to the second node N2. A first terminal of the sixth transistor CT6 is connected to the fourth node N4, and a second terminal of the sixth transistor CT6 is connected to the second reset signal terminal Init2 to receive the second reset signal Vinit 2. A first terminal of the seventh transistor CT7 is connected to the third node N3, and a second terminal of the seventh transistor CT7 is connected to the fourth node N4.

For example, the control terminal GAT1 of the second transistor CT2 and the control terminal GAT2 of the third transistor CT3 are both connected to the scan signal terminal GAT (not shown), the control terminal EM1 of the fifth transistor CT5 and the control terminal EM2 of the seventh transistor CT7 are both connected to the emission control terminal EM (not shown), the control terminal of the fourth transistor CT4 is configured to be connected to the first reset control terminal RST1, and the control terminal of the sixth transistor CT6 is configured to be connected to the second reset control terminal RST 2. For convenience of description, fig. 13A also shows a first node N1, a second node N2, a third node N3, a fourth node N4, and a light emitting element EL.

Fig. 13B is a driving timing diagram of the 7T1C pixel circuit shown in fig. 13A. As shown in fig. 13B, each driving period of the 7T1C pixel circuit 100 includes a first phase T1, a second phase T2, and a third phase T3.

As shown in fig. 13A and 13B, in the first phase t1, the first reset control terminal RST1 receives an active level, and the scan signal terminal GAT, the second reset control terminal RST2 and the emission control terminal EM all receive an inactive level. In this case, the fourth transistor CT4 is turned on, and the second transistor CT2, the third transistor CT3, the fifth transistor CT5, the sixth transistor CT6, and the seventh transistor CT7 are turned off; the fourth transistor CT4 is configured to receive a first reset signal (e.g., a reset voltage) Vinit1 and write the first reset signal Vinit1 to the storage capacitor Cst to reset the storage capacitor Cst; the voltage at the first node N1 is Vinit1, and Vinit1 is, for example, a negative value. For example, after resetting the storage capacitor Cst, the first transistor CT1 is turned on.

As shown in fig. 13A and 13B, in the second phase t2, the scan signal terminal GAT and the second reset control terminal RST2 receive an active level, and the first reset control terminal RST1 and the emission control terminal EM receive an inactive level; in this case, the first to third transistors CT1 to CT3 and the sixth transistor CT6 are turned on, and the fourth transistor CT4, the fifth transistor CT5 and the seventh transistor CT7 are turned off; the second transistor CT2 receives the data signal Vdata, and the data signal Vdata is written into the control terminal of the first transistor CT1 through the turned-on first transistor CT1 and the turned-on third transistor CT3, the storage capacitor Cst stores the data signal Vdata written into the control terminal of the first transistor CT1 at the control terminal of the first transistor CT1, and the voltage of the first node N1 is Vdata + Vth; the sixth transistor CT6 is configured to receive a second reset signal (e.g., a reset voltage) Vinit2 and write the second reset signal Vinit2 to the first terminal of the light emitting element EL to reset the first terminal of the light emitting element EL, the voltage of the fourth node N4 is Vinit2, and Vinit2 is, for example, a negative value.

As shown in fig. 13A and 13B, in the third stage t3, the emission control terminal EM receives an active level, and the first reset control terminal RST1, the scan signal terminal GAT, and the second reset control terminal RST2 receive an inactive level; in this case, the first transistor CT1, the fifth transistor CT5, and the seventh transistor CT7 are turned on, and the second transistor CT2, the third transistor CT3, the fourth transistor CT4, and the sixth transistor CT6 are turned off; the first transistor CT1 is configured to control a driving current flowing through the first transistor CT1 and from the first power voltage terminal VDD to the light emitting element EL for driving the light emitting element EL, based on the data signal (e.g., data voltage) Vdata stored in the storage capacitor Cst and the received first power voltage V1; the voltage of the first node N1 is Vdata + Vth, and the voltage of the second node N2 is VDD; the drive current Id can be expressed by the following equation:

here, k ═ μ × Cox × W/L; μ is the mobility of carriers in the first transistor CT1, Cox is the capacitance of the gate oxide layer of the first transistor CT1, W/L is the width-to-length ratio of the channel of the first transistor CT1, Vth is the threshold voltage of the first transistor CT1, Vth is the gate-source voltage of the first transistor CT1, Vg is the gate voltage of the first transistor CT1, and Vs is the source voltage of the first transistor CT 1.

As can be seen from the above formula, the driving current Id generated by the first transistor CT1 is independent of the threshold voltage of the first transistor CT1, and therefore, the 7T1C pixel circuit 100 shown in fig. 13A and 13B has a threshold compensation function.

It should be noted that, in the embodiment of the present disclosure, the first pixel circuit 412 (for example, the first sub-pixel circuit 412a and the second sub-pixel circuit 412b), the second pixel circuit 422, and the third pixel circuit 432 are not limited to the above-mentioned 7T1C pixel circuit, and other suitable pixel circuits may also be used, and the embodiment of the present disclosure is not limited thereto. The specific circuit structures of the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 may be the same or different from each other, which may be determined according to actual needs, and the embodiment of the disclosure is not limited thereto.

For example, the first switching transistor in the first pixel circuit 412, the second switching transistor in the second pixel circuit 422, and the third switching transistor in the third pixel circuit 432 may each be the seventh transistor CT7 in fig. 13A, which seventh transistor CT7 supplies an electric signal to the anode of the corresponding light emitting element EL. For example, the first light emitting element 411 (e.g., the first and second sub light emitting elements 411a and 411b), the second light emitting element 421, and the third light emitting element 431 may each be the light emitting element EL in fig. 13A, which may be an Organic Light Emitting Diode (OLED) or a quantum dot light emitting diode (QLED).

At least one embodiment of the present disclosure also provides a display device including the display substrate provided in any one of the embodiments of the present disclosure. The display device can reduce the processing difficulty, improve the reliability of electric connection, improve the uniformity of transmitted light and contribute to improving the sensing effect of a sensor (such as a camera) under a screen.

Fig. 14 is a schematic block diagram of a display device according to at least one embodiment of the present disclosure. For example, as shown in fig. 14, the display device 20 includes a display substrate 210, and the display substrate 210 is a display substrate provided in any embodiment of the disclosure, such as the aforementioned display substrate 01. The display device 20 may be any electronic device with a display function, such as a smart phone, a notebook computer, a tablet computer, a television, and the like. For example, when the display device 20 is a smartphone or tablet computer, the smartphone or tablet computer may have a full-screen design, i.e., no perimeter area surrounding the third display area 13. In addition, the smart phone or the tablet computer is also provided with an off-screen sensor (such as a camera and an infrared sensor), and can perform operations such as image shooting, distance sensing and light intensity sensing.

It should be noted that, for the display substrate 210 and other components of the display device 20 (for example, an image data encoding/decoding device, a clock circuit, etc.), suitable components may be adopted, which are understood by those skilled in the art, and are not described herein again, nor should be used as a limitation to the embodiments of the present disclosure.

Fig. 15 is a schematic view of a stacked structure of a display device according to at least one embodiment of the present disclosure. For example, as shown in fig. 15, the display device 20 includes a display substrate 210, and the display substrate 210 is a display substrate provided in any embodiment of the disclosure, such as the aforementioned display substrate 01. For example, the display device 20 further includes a sensor 220.

For example, the display substrate 01 has a first side F1 for display and a second side F2 opposite to the first side F1. That is, the first side F1 is a display side, and the second side F2 is a non-display side. The display substrate 01 is configured to perform a display operation on the first side F1, that is, the first side F1 of the display substrate 01 is a light exit side of the display substrate 01, and the first side F1 faces a user. The first side F1 and the second side F2 face each other in the normal direction of the display surface of the display substrate 01.

As shown in fig. 15, the sensor 220 is disposed on the second side F2 of the display substrate 01, and the sensor 220 is configured to receive light from the first side F1. For example, the sensor 220 is overlapped with the first display region 11 in a normal direction of the display surface of the display substrate 01 (e.g., a direction perpendicular to the display substrate 01), and the sensor 220 may receive and process an optical signal, which may be visible light, infrared light, or the like, passing through the first display region 11. For example, the first display region 11 allows light from the first side F1 to be at least partially transmitted to the second side F2. For example, the first display region 11 is not provided with a pixel circuit, and in this case, the light transmittance of the first display region 11 can be improved.

For example, the orthographic projection of the sensor 220 on the display substrate 01 at least partially overlaps the first display region 11. For example, in some examples, when the direct-illumination arrangement is employed, an orthographic projection of the sensor 220 on the display substrate 01 is located within the first display region 11. For example, in other examples, when other light guide elements (e.g., a light guide plate, a light guide pipe, etc.) are employed to make light incident on the sensor 220 from the side, the orthographic projection of the sensor 220 on the display substrate 01 partially overlaps the first display region 11. At this time, since the light may laterally propagate to the sensor 220, it is not necessary that the sensor 220 is entirely located at a position corresponding to the first display region 11.

For example, by disposing the first pixel circuit 412 in the second display region 12 and overlapping the sensor 220 and the first display region 11 in the normal direction of the display surface of the display substrate 01, the blocking of the optical signal incident to the first display region 11 and irradiated to the sensor 220 by the elements in the first display region 11 can be reduced, whereby the signal-to-noise ratio of the image output by the sensor 220 can be improved. For example, the first display region 11 may be referred to as a high light transmission region of a low resolution region of the display substrate 01, and the second display region 12 may be referred to as a transition region.

For example, the sensor 220 may be an image sensor, which may be used to capture an image of the external environment to which the light collecting surface of the sensor 220 is facing, such as a CMOS image sensor or a CCD image sensor. The sensor 220 may also be an infrared sensor, a distance sensor, or the like. For example, in the case where the display device 20 is a mobile terminal such as a mobile phone, a notebook, etc., the sensor 220 may be implemented as a camera of the mobile terminal such as a mobile phone, a notebook, etc., and may further include an optical device such as a lens, a mirror, or an optical waveguide, as necessary, to modulate an optical path. For example, the sensor 220 may include an array of photosensitive pixels. For example, each photosensitive pixel may include a photosensitive detector (e.g., photodiode, phototransistor) and a switching transistor (e.g., switching thin film transistor). For example, a photodiode may convert an optical signal irradiated thereto into an electrical signal, and a switching transistor may be electrically connected to the photodiode to control whether or not the photodiode is in a state of collecting the optical signal and a time of collecting the optical signal.

In some examples, the anode of the first light emitting element 411 is of a stacked structure of ITO/Ag/ITO, and only the anode of the first light emitting element 411 is opaque in the first display region 11, that is, the traces (e.g., the first connection line 110 and the second connection line 120) for driving the first light emitting element 411 are set as transparent conductive traces. In this case, not only the light transmittance of the first display region 11 can be further improved, but also diffraction and reflection caused by each element in the first display region 11 can be reduced.

It should be noted that, in the embodiment of the present disclosure, the display device 20 may further include more components and structures, and the embodiment of the present disclosure is not limited thereto. For technical effects and detailed description of the display device 20, reference may be made to the above description of the display substrate 01, which is not repeated herein.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.