阅读说明：本技术 半导体装置以及车载用电子控制装置 (Semiconductor device and on-vehicle electronic control device ) 是由 池谷克己 小林洋一郎 右田稔 于 2020-05-15 设计创作，主要内容包括：提供一种在具备电流镜电路的半导体装置中能够降低电流镜电路的镜像比的偏差以及抑制元件的配对性的经时变化的可靠性高的半导体装置。(Provided is a highly reliable semiconductor device having a current mirror circuit, which can reduce variations in the mirror ratio of the current mirror circuit and suppress changes over time in the matching properties of elements.)

1. A semiconductor device is characterized by comprising:

a 1 st semiconductor element group in which a plurality of semiconductor elements are connected in parallel;

a 2 nd semiconductor element group which is arranged in the same layer as the 1 st semiconductor element group and is formed by connecting a plurality of semiconductor elements in parallel; and

a plurality of wirings which are arranged on an upper layer of the 1 st semiconductor element group and the 2 nd semiconductor element group and have a width wider than a width of each of the semiconductor elements of the 1 st semiconductor element group and the 2 nd semiconductor element group,

the 1 st semiconductor element group and the 2 nd semiconductor element group are paired to constitute a circuit having a predetermined pairing accuracy,

the plurality of wirings are arranged such that a combination of distances in the planar direction from each semiconductor element in the 1 st semiconductor element group to the wiring at the position closest in the planar direction is equal to a combination of distances in the planar direction from each semiconductor element in the 2 nd semiconductor element group to the wiring at the position closest in the planar direction.

2. The semiconductor device according to claim 1,

the plurality of wirings have a plurality of wirings arranged in a 1 st wiring layer and a plurality of wirings arranged in a 2 nd wiring layer different from the 1 st wiring layer,

the plurality of wires of the 1 st wiring layer are arranged so that a combination of distances in the planar direction from each semiconductor element of the 1 st semiconductor element group to the wire arranged in the 1 st wiring layer at a position closest in the planar direction is equal to a combination of distances in the planar direction from each semiconductor element of the 2 nd semiconductor element group to the wire arranged in the 1 st wiring layer at a position closest in the planar direction,

the plurality of wires of the 2 nd wiring layer are arranged so that a combination of distances in the planar direction from each semiconductor element of the 1 st semiconductor element group to the wire arranged in the 2 nd wiring layer at the position closest in the planar direction is equal to a combination of distances in the planar direction from each semiconductor element of the 2 nd semiconductor element group to the wire arranged in the 2 nd wiring layer at the position closest in the planar direction.

3. The semiconductor device according to claim 1,

the plurality of wirings have a plurality of wirings arranged in a 1 st wiring layer and a plurality of wirings arranged in a 2 nd wiring layer different from the 1 st wiring layer,

the plurality of wirings are arranged so that the wiring arranged in the 1 st wiring layer and the wiring arranged in the 2 nd wiring layer overlap each other,

the wiring arranged in the 1 st wiring layer and the wiring arranged in the 2 nd wiring layer are arranged as follows: the combination of the distances in the planar direction from each semiconductor element in the 1 st semiconductor element group to the position where the wiring in the 1 st wiring layer and the wiring in the 2 nd wiring layer overlap each other, which is closest in the planar direction, is equal to the combination of the distances in the planar direction from each semiconductor element in the 2 nd semiconductor element group to the position where the wiring in the 1 st wiring layer and the wiring in the 2 nd wiring layer overlap each other, which is closest in the planar direction.

4. The semiconductor device according to any one of claims 1 to 3,

the circuit is a current mirror circuit,

the 1 st semiconductor element group is a mirror image source of the current mirror circuit,

the 2 nd semiconductor element group is a mirror image target of the current mirror circuit.

5. The semiconductor device according to any one of claims 1 to 3,

the circuit is a current mirror circuit,

the semiconductor device further comprises a 3 rd semiconductor element group formed by connecting a plurality of semiconductor elements in parallel,

the 1 st semiconductor element group and the 2 nd semiconductor element group are mirror targets of the current mirror circuit,

the 3 rd semiconductor element group is a mirror image source of the current mirror circuit.

6. The semiconductor device according to claim 4 or 5,

having a plurality of semiconductor element groups to be targets of mirroring,

each combination of distances in the planar direction from each semiconductor element in the plurality of semiconductor element groups to the wiring at the position where the distance in the planar direction is the closest is equal to the combination of distances in the planar direction of the 1 st semiconductor element group.

7. The semiconductor device according to any one of claims 1 to 3,

the plurality of wirings include a dummy wiring.

8. The semiconductor device according to any one of claims 1 to 3,

a dummy semiconductor element is included in the array of the plurality of semiconductor elements.

9. An in-vehicle electronic control device is characterized in that,

a semiconductor device comprising the semiconductor device according to any one of claims 1 to 8.

Technical Field

The present invention relates to a structure of a semiconductor device configured by using a multilayer wiring technique, and more particularly, to a technique effective for applying to a semiconductor device which requires a small variation in element matching and high reliability.

Background

A current mirror circuit often used in an analog integrated circuit converts an input current into a desired magnification (mirror ratio) and outputs the converted current according to the sizes of MOS transistors on the input side and the output side. In order to operate a semiconductor integrated circuit device using a current mirror circuit with high accuracy, reduction of variation in matching between transistors constituting the current mirror circuit and suppression of temporal variation in matching are required.

In a semiconductor integrated circuit device, metal wirings for connecting elements such as transistors, diodes, resistors, and capacitors are generally formed on these elements with an interlayer insulating film (interlayer oxide film) interposed therebetween. The metal wiring (wiring pattern) is formed by repeating film formation of a metal film and an insulating film and pattern formation by photolithography.

In general, when a plurality of metal wirings are formed, an upper wiring layer far from a transistor is used for a long-distance connection in a chip, a power supply main line, and the like, and in order to reduce impedance, a wiring having a thickness larger than that of a lower wiring layer near the transistor or a wide wiring is often used. In recent years, in a semiconductor device or the like mounted with a power transistor for controlling a large current, a Copper Redistribution (Copper Redistribution) having a wide and thick film may be further used on a passivation film of the semiconductor device.

However, since the metal film and the insulating film formed on the semiconductor substrate have different linear expansion coefficients from the semiconductor substrate, thermal strain is generated in the semiconductor element due to the ambient temperature around the semiconductor element or a temperature change caused by self-heating. Thermal strain of wiring patterns disposed around elements such as transistors and resistors becomes a factor of variation and fluctuation in electrical characteristics of these elements.

As a technique for reducing a change over time in an element due to a wiring pattern, for example, patent document 1 is known. Patent document 1 is a technique of reducing the influence of dummy wirings on MOS transistors by defining the arrangement of dummy wirings formed on the upper layers of the MOS transistors to be paired.

Patent document 1 describes the following: a semiconductor device includes a dummy wiring for leveling in a mechanochemical polishing disposed on an upper layer of a transistor, wherein the dummy wiring is disposed so as not to overlap with any of the pair transistors in a plan view, or so that a portion overlapping with a 1 st transistor and a 2 nd transistor is equal to the 1 st transistor and the 2 nd transistor.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open No. 2003-100899

Disclosure of Invention

Problems to be solved by the invention

As described above, an upper wiring layer distant from the transistor sometimes uses a wide wiring. These wiring widths are sometimes wider than the sizes of the respective transistors constituting the pair and narrower than the entire array of the pair transistors. When such wide wirings are arranged around the paired transistors, the wide wirings need to be routed around the transistor array in order to make the wiring patterns viewed from the transistors the same, which leads to a problem of an increase in chip size.

In particular, in a current mirror circuit used in an analog-digital converter or the like, the number of transistors to be configured is large, and therefore, the influence on the chip size is large.

Therefore, an object of the present invention is to provide a highly reliable semiconductor device including a current mirror circuit, which can reduce variations in the mirror ratio (ミラー ratio) of the current mirror circuit and suppress changes in the matching characteristics of elements with time.

Means for solving the problems

In order to solve the above problems, the present invention includes: a 1 st semiconductor element group in which a plurality of semiconductor elements are connected in parallel; a 2 nd semiconductor element group which is arranged in the same layer as the 1 st semiconductor element group and is formed by connecting a plurality of semiconductor elements in parallel; and a plurality of wirings arranged in an upper layer of the 1 st semiconductor element group and the 2 nd semiconductor element group and having a width larger than a width of each semiconductor element of the 1 st semiconductor element group and the 2 nd semiconductor element group, wherein the 1 st semiconductor element group and the 2 nd semiconductor element group form a pair to constitute a circuit having a predetermined pairing accuracy, and the plurality of wirings are arranged such that a combination of distances in a planar direction from each semiconductor element of the 1 st semiconductor element group to the wiring at a position closest in the planar direction is equal to a combination of distances in a planar direction from each semiconductor element of the 2 nd semiconductor element group to the wiring at a position closest in the planar direction.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, in a semiconductor device including a current mirror circuit, it is possible to realize a highly reliable semiconductor device capable of reducing variations in the mirror ratio of the current mirror circuit and suppressing changes in the matching characteristics of elements with time.

Problems, configurations, and effects other than those described above will be apparent from the following description of the embodiments.

Drawings

Fig. 1 is a plan view of a semiconductor device of embodiment 1 of the present invention.

Fig. 2 is a circuit diagram of a semiconductor device according to embodiment 1 of the present invention.

Fig. 3A is a diagram showing a simulation model of thermal strain of the wiring.

Fig. 3B is a graph showing a simulation result of thermal strain of the model of fig. 3A.

Fig. 4 is a partially enlarged view of the semiconductor device shown in fig. 1.

Fig. 5 is a sectional view a-a' of fig. 4.

Fig. 6 is a plan view of a semiconductor device of a conventional example.

Fig. 7 is a circuit diagram of a conventional semiconductor device.

Fig. 8 is a plan view of a semiconductor device of embodiment 2 of the present invention.

Fig. 9 is a sectional view B-B' of fig. 8.

Fig. 10 is a partially enlarged view of the semiconductor device shown in fig. 8.

Fig. 11 is a cross-sectional view of C-C' of fig. 10.

Fig. 12 is a plan view of a semiconductor device of embodiment 3 of the present invention.

Fig. 13 is a cross-sectional view of D-D' of fig. 12.

Fig. 14 is a partially enlarged view of the semiconductor device shown in fig. 12.

Fig. 15 is a cross-sectional view of E-E' of fig. 14.

Fig. 16 is a plan view of a semiconductor device according to embodiment 4 of the present invention.

Fig. 17 is a circuit diagram of a semiconductor device according to embodiment 4 of the present invention.

Fig. 18 is a partially enlarged view of the semiconductor device shown in fig. 16.

Fig. 19 is a plan view of a semiconductor device according to embodiment 5 of the present invention.

Fig. 20 is a plan view of a semiconductor device of embodiment 6 of the present invention.

Fig. 21 is a circuit diagram of a semiconductor device according to embodiment 6 of the present invention.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and detailed description thereof will be omitted for overlapping portions.

Example 1

A semiconductor device according to embodiment 1 of the present invention will be described with reference to fig. 1 to 7. Fig. 6 and 7 are a plan view and a circuit diagram of a conventional semiconductor device shown as a comparative example to facilitate understanding of the present invention.

Fig. 1 shows an example of the planar positional relationship between the MOS transistors M01 to M74 constituting the current mirror circuit in the semiconductor device of the present embodiment and the wide wiring 20. As shown in fig. 1, the array of the MOS transistors M01 to M74 is arranged in the X direction, and the wide wirings 20 are arranged to extend in the Y direction perpendicular to the MOS transistors M01 to M74, respectively. In addition, the width W2 of the 1 wide wiring 20 is about 4 times the width W1 of the 1 MOS transistor.

Fig. 2 is a circuit diagram of the semiconductor device shown in fig. 1. The mirror source of the mirror circuit of fig. 2 is formed by connecting 4 MOS transistors M01 to M04 in parallel to a mirror terminal 100. The mirror image is configured by connecting 4 MOS transistors M11 to M14, M21 to M24, and the like in parallel to each of the mirror image terminals 101 to 107. However, the order of arrangement of the MOS transistors of fig. 1 may be different from that of fig. 2.

In fig. 1, MOS transistors are distributed in parallel from the left as in M01 to M71, M02 to M72, M03 to M73, and M04 to M74.

Further, M01 to M31 were arranged in the order of M01, M11, M21, and M31 from the left, and M02 to M32 were changed in the order of M12, M22, M32, and M02 from the left. M03 to M43 and M04 to M44 were arranged in the same order. M41 to M71, M42 to M72, M43 to M73, and M44 to M74 were also arranged in the same order.

Here, the influence of the stress of the wiring pattern on the MOS transistor will be described with reference to fig. 3A and 3B. Fig. 3A is a cross-sectional view of a thermal stress simulation model in which a silicon oxide film 401, a polyimide film 500, and a copper wiring 200 are disposed as interlayer oxide films on an SOI substrate including a silicon substrate (semiconductor substrate) 300, a silicon oxide film 400, and a silicon (Si) layer 301. Fig. 3B is a simulation result of the amount of strain at the interface 302 between the silicon layer 301 and the silicon oxide film 401 in fig. 3A.

As shown in fig. 3B, the thermal strain of the silicon interface 302 is affected by the upper layer wiring (copper wiring 200), and varies depending on the plane distance from the wiring end. The mobility of electrons and holes in silicon depends on the amount of strain in silicon. In this way, since the electrical characteristics of the semiconductor element vary depending on the positional relationship with the wiring pattern, it is necessary to consider the arrangement, shape, and the like of the upper wiring pattern of each element in the semiconductor element which requires the compatibility.

Next, a detailed positional relationship between the MOS transistor and the wide wiring 20, which are components in the present embodiment, will be described. Fig. 4 is an enlarged plan view showing regions of 8 MOS transistors M01 to M71 from the left in fig. 1. In addition, fig. 5 is a sectional view a-a' of fig. 4. In fig. 4 and 5, the patterns of the wiring layer 10 on the upper layer close to the MOS transistors are laid out in the same manner as seen from the MOS transistors in the MOS transistors M01 to M71, and the strain applied to the MOS transistors by these wiring layers 10 is the same for the MOS transistors.

Distances in the planar direction from the MOS transistors M01, M11, M21, and M31 to the line end of the wide wiring 20 are D2, D1, E1, and E2, respectively. Distances in the planar direction from M41 to M71 to the wire ends of the wide wires 20 are also the same. Further, M01 to M71 have different effects of thermal strain due to the wide wirings 20, and thus have lower compatibility with MOS transistors, because the presence or absence of the wide wirings 20 in the upper layer and the distance from the end of the wiring in the planar direction are different.

However, in the circuit of fig. 2, when the MOS transistors and the wide wirings 20 are arranged as shown in fig. 1, the combination of the distances in the planar direction from the MOS transistor to the nearest wide wiring 20 in the group of MOS transistors for the mirror terminals 101 to 107 of fig. 2 is as follows, for example.

Mirror image terminal 100 (mirror image source)

Transistors M01 to M04: distances D2, E2, E1, D1 to the wide wiring 20

Mirror image terminal 101 (mirror image target)

Transistors M11 to M14: distances D1, D2, E2, E1 to the wide wiring 20

Mirror image terminal 102 (mirror image target)

Transistors M21 to M24: distances E1, D1, D2, E2 to the wide wiring 20

Mirror image terminal 103 (mirror image target)

Transistors M31 to M34: distances E2, E1, D1, D2 to the wide wiring 20

The same applies to the mirror terminals 104 to 107, and since they are all combinations of (D1, D2, E1, E2), the electrical characteristics of the MOS of each mirror terminal in fig. 2 are the same. Therefore, as the current mirror circuit, the pairing property of the mirror source and each mirror destination can be ensured.

The present embodiment is configured to include: a circuit requiring pairing, comprising at least: a 1 st semiconductor element group (group of mirror terminals 100) in which a plurality of semiconductor elements (MOS transistors M01 to M04) are connected in parallel, and a 2 nd semiconductor element group (group of mirror terminals 101) in which a plurality of semiconductor elements (MOS transistors M11 to M14) are connected in parallel; and a plurality of wirings formed on the upper layer of each semiconductor element group (100, 101) and having a width wider than 1 width of the semiconductor element M01, the plurality of wide wirings 20 are arranged so that the combination of distances (D2, E2, E1, D1) in the planar direction from the respective semiconductor elements (M01 to M04) constituting the 1 st semiconductor element group (100) to the wide wiring 20 at the closest position in the planar direction is the same as the combination of distances (D1, E2, E1, D1) in the planar direction from the respective semiconductor elements (M11 to M14) constituting the 2 nd semiconductor element group (101) to the wide wiring 20 at the closest position in the planar direction, this makes it possible to make the influence of the stress received by the 1 st semiconductor element group (group of mirror terminals 100) from the wide wirings 20 substantially equal to the influence of the stress received by the 2 nd semiconductor element group (group of mirror terminals 101) from the wide wirings 20.

Since the degrees of deterioration due to stress can be equalized, the 1 st semiconductor element group (group of mirror terminals 100) and the 2 nd semiconductor element group (group of mirror terminals 101) can be maintained in a mated state, and the deterioration with age (change with time) can be suppressed.

In the present embodiment, the current mirror circuit is used as the circuit requiring the pairing property, but the present invention is not limited thereto, and can be widely applied to other circuits requiring the pairing property (pairing accuracy).

In addition, a configuration in which the number of MOS transistors (semiconductor elements) constituting each semiconductor element group is 4 is exemplified, but the present invention is not limited thereto. Similarly, the number of semiconductor element groups constituting a circuit requiring the pairing property is not limited to 7.

On the other hand, in the conventional semiconductor device shown in fig. 6 and 7, the MOS transistors constituting the current mirror circuit are not arranged in a dispersed manner, and in this case, the influence of the wide wiring 20 is different among the MOS transistors M0 to M7, so that the matching of the MOS transistors is degraded, and the mirror ratio of the current mirror circuit is also different depending on the mirror destination.

As described above, the semiconductor device of the present embodiment includes: a 1 st semiconductor element group (group of mirror terminals 100) in which a plurality of semiconductor elements (MOS transistors M01 to M04) are connected in parallel; a 2 nd semiconductor element group (group of mirror terminals 101) which is arranged in the same layer as the 1 st semiconductor element group (group of mirror terminals 100) and is formed by connecting a plurality of semiconductor elements (MOS transistors M11 to M14) in parallel; and a plurality of wide wirings 20 which are disposed on the upper layer of the 1 st semiconductor element group (group of mirror terminals 100) and the 2 nd semiconductor element group (group of mirror terminals 101), and have a width W2 wider than a width W1 of each semiconductor element of the 1 st semiconductor element group (group of mirror terminals 101) and the 2 nd semiconductor element group (group of mirror terminals 101). The 1 st semiconductor element group (group of mirror terminals 100) and the 2 nd semiconductor element group (group of mirror terminals 101) constitute a pair, and a circuit having a predetermined pairing accuracy is constituted, and the plurality of wide wirings 20 are arranged so that a combination of distances in the planar direction from the respective semiconductor elements (MOS transistors M01 to M04) of the 1 st semiconductor element group (group of mirror terminals 100) to the wide wiring 20 at the closest position in the planar direction is equal to a combination of distances in the planar direction from the respective semiconductor elements (MOS transistors M11 to M14) of the 2 nd semiconductor element group (group of mirror terminals 101) to the wide wiring 20 at the closest position in the planar direction.

The circuit is a current mirror circuit, the 1 st semiconductor element group (group of mirror terminals 100) is a mirror source of the current mirror circuit, and the 2 nd semiconductor element group (group of mirror terminals 101) is a mirror destination of the current mirror circuit.

Thus, in the semiconductor device including the current mirror circuit, it is possible to realize a highly reliable semiconductor device capable of reducing variations in the mirror ratio of the current mirror circuit and suppressing changes in the matching of elements with time.

Further, by mounting the semiconductor device of the present embodiment on the in-vehicle electronic control device, the reliability of the in-vehicle electronic control device can be improved.

Example 2

A semiconductor device according to embodiment 2 of the present invention will be described with reference to fig. 8 to 11. Fig. 8 shows an example of the positional relationship of the planes of the MOS transistors M01 to M74 constituting the current mirror circuit, the wide wiring 20, and the wide wiring 30 which is a wiring layer different from the wide wiring 20 in the semiconductor device of the present embodiment. In fig. 8, the MOS transistors M01 to M74 and the wide wiring 20 are the same as those in fig. 1. In addition, the current mirror circuit of the present embodiment is the same as that of fig. 2. FIG. 9 shows the section B-B' of FIG. 8.

The detailed arrangement of the MOS transistor, the wide wiring 20, and the wide wiring 30 in the present embodiment will be described below. Fig. 10 is an enlarged plan view showing regions of 8 MOS transistors M01 to M71 from the left in fig. 8, and fig. 11 is a cross-sectional view of C-C' in fig. 10. In fig. 10 and 11, distances D1, D2, E1, and E2 in the planar direction between the MOS transistors M01 to M71 and the wide wirings 20 are the same as those in fig. 4 and 5 of example 1.

As shown in fig. 10 and 11, distances in the planar direction between the wide wiring 30 and the MOS transistors M01, M11, M21, and M31 are G1, F1, F2, and F3, respectively. The same applies to M41, M51, M61 and M71.

By arranging the MOS transistors constituting the current mirror circuit of fig. 9, the wide wiring 20 on the upper layer, and the wide wiring 30 in a wiring layer different from the wide wiring 20 as shown in fig. 8, distances in the planar direction from the MOS transistors to the wide wiring 30 in each group of MOS transistors connected to the terminal mirrors 101 to 107 in the circuit diagram of fig. 2 are, for example, combinations of F1, F2, F3, and G1 as follows.

Mirror image terminal 100 (mirror image source)

Transistors M01 to M04: distances G1, F3, F2, F1 to the wide wiring 30

Mirror terminal 101 (mirror target).

Transistors M11 to M14: distances F1, G1, F3, F2 to the wide wiring 30

Mirror terminal 102 (mirror target).

Transistors M21 to M24: distances F2, F1, G1, F3 to the wide wiring 30

Mirror image terminal 103 (mirror image target)

Transistors M31 to M34: distances F3, F2, F1, G1 to the wide wiring 30

As described above, the combinations of the distances in the planar direction from the MOS transistor to the wide wiring 20 and the wide wiring 30 are the same between the terminals of the mirror source (100) and the mirror targets (101 to 107) of the current mirror circuit, and the influence of the stress of the wide wiring can be equalized between the terminals of the mirror source and the mirror targets, so that the initial variation of the mirror ratio of the current mirror circuit can be reduced and the aged deterioration (change with time) can be suppressed.

As described above, in the semiconductor device of the present embodiment, the plurality of wirings include: a plurality of wide wirings 20 disposed in the 1 st wiring layer; and a plurality of wide wires 30 arranged in a 2 nd wiring layer different from the 1 st wiring layer, wherein the plurality of wide wires 20 of the 1 st wiring layer are arranged so that a combination of distances in the planar direction from the respective semiconductor elements (MOS transistors M01, M11, M21, M31) of the 1 st semiconductor element group (group of mirror terminals 100) to the wide wire 20 arranged in the 1 st wiring layer at the position closest in the planar direction is equal to a combination of distances in the planar direction from the respective semiconductor elements (MOS transistors M41, M51, M61, M71) of the 2 nd semiconductor element group (group of mirror terminals 101) to the wide wire 20 arranged in the 1 st wiring layer at the position closest in the planar direction, and the plurality of wide wires 20 of the 1 st wiring layer are arranged so that a combination of distances in the planar direction from the respective semiconductor elements (MOS transistors M01, M11, M21, M31) of the 1 st semiconductor element group (group of mirror terminals 100) to the wide wire 30 arranged in the 2 nd wiring layer at the position closest in the planar direction The plurality of wide wirings 30 of the 2 nd wiring layer are arranged so as to be equal to combinations of distances in the planar direction from the respective semiconductor elements (MOS transistors M41, M51, M61, M71) of the 2 nd semiconductor element group (group of mirror terminals 101) to the wide wiring 30 arranged in the 2 nd wiring layer at the closest position in the planar direction.

Example 3

A semiconductor device according to embodiment 3 of the present invention will be described with reference to fig. 12 to 15. Fig. 12 shows an example of the planar positional relationship among the MOS transistors M01 to M74 constituting the current mirror circuit in the semiconductor device of the present embodiment, the wide wiring 20, and the wide wiring 31 which is a wiring layer different from the wide wiring 20. In fig. 12, the MOS transistors M01 to M74 and the wide wiring 20 are the same as those in fig. 1. In addition, the current mirror circuit of the present embodiment is the same as that of fig. 2. FIG. 13 shows a cross-sectional view D-D' of FIG. 12.

In the present embodiment, as shown in fig. 13, the wide wiring 31 is disposed on the MOS transistor side (lower layer side) of the wide wiring 20.

The detailed arrangement of the MOS transistor, the wide wiring 20, and the wide wiring 31 in the present embodiment will be described below. Fig. 14 is an enlarged plan view showing regions of 8 MOS transistors M01 to M71 from the left in fig. 12, and fig. 15 is a cross-sectional view of E-E' in fig. 14. In fig. 14 and 15, distances D1, D2, E1, and E2 in the planar direction between the MOS transistors M01 to M71 and the wide wirings 20 are the same as those in fig. 4 and 5 of example 1.

Further, distances in the planar direction between the regions where the wide wirings 20 and the wide wirings 31 overlap each other in the plane and the MOS transistors M01, M11, M21, and M31 are H3, H2, H1, and J1, respectively. When the MOS transistors constituting the current mirror circuit, the upper wide wiring 20, and the wide wiring 31 are arranged as shown in fig. 12 and 13, the distances in the planar direction from the MOS transistors to the overlapping region of the wide wiring 20 and the wide wiring 31 in the group of MOS transistors connected to the mirror terminals 101 to 107 in the circuit diagram of fig. 2 are all combinations of H1, H2, H3, and J1, for example, as described below.

Mirror image terminal 100 (mirror image source)

Transistors M01 to M04: distances H3, J1, H1, H2 to wide-width wiring 31

Mirror image terminal 101 (mirror image target)

Transistors M11 to M14: distances H2, H3, J1, H1 to wide-width wiring 31

Mirror image terminal 102 (mirror image target)

Transistors M21 to M24: distances H1, H2, H3, J1 to wide-width wiring 31

Mirror image terminal 103 (mirror image target)

Transistors M31 to M34: distances J1, H1, H2, H3 to wide-width wiring 31

As described above, by making the combination of the distances in the planar direction from the MOS transistor to the wide wiring 20 and the wide wiring 31 and the combination of the distances in the planar direction from the MOS transistor to the overlap of the wide wiring 20 and the wide wiring 31 the same for each combination of the MOS transistor at the mirror source of the current mirror circuit and the terminal of each mirror target, the influence of the stress of the wide wiring can be made equal between the mirror source and the mirror target, and the initial variation in the mirror ratio of the current mirror circuit can be reduced and the aged deterioration (change with time) can be suppressed.

As described above, in the semiconductor device of the present embodiment, the plurality of wirings include: a plurality of wide wirings 20 disposed in the 1 st wiring layer; and a plurality of wide wirings 31 arranged in a 2 nd wiring layer different from the 1 st wiring layer, the plurality of wide wirings being arranged so that the wide wirings 20 arranged in the 1 st wiring layer and the wide wirings 31 arranged in the 2 nd wiring layer overlap each other, a combination of distances in a planar direction from the respective semiconductor elements (MOS transistors M01, M11, M21, M31) in the 1 st semiconductor element group (group of mirror terminals 100) to a position nearest in the planar direction at which the wide wirings 20 arranged in the 1 st wiring layer and the wide wirings 31 arranged in the 2 nd wiring layer overlap each other is equal to a combination of distances in a planar direction from the respective semiconductor elements (MOS transistors M41, M51, M61, M71) in the 2 nd semiconductor element group (group of mirror terminals 101) to a position nearest in the planar direction at which the wide wirings 20 arranged in the 1 st wiring layer and the wide wirings 31 arranged in the 2 nd wiring layer overlap each other, the wide wiring 20 disposed in the 1 st wiring layer and the wide wiring 31 disposed in the 2 nd wiring layer are disposed.

Example 4

A semiconductor device according to embodiment 4 of the present invention will be described with reference to fig. 16 to 18. Fig. 16 shows an example of the planar positional relationship between the MOS transistors M01 to M84 constituting the current mirror circuit in the semiconductor device of the present embodiment and the wide wiring 21. Fig. 17 is a circuit diagram of the current mirror circuit of fig. 16. In fig. 16, as in fig. 1, the array of the MOS transistors M01 to M84 is arranged in the X direction, and the wide wirings 21 are arranged to extend in the Y direction perpendicular to the MOS transistors M01 to M84, respectively. However, in the present embodiment, the width W3 of the 1 wide wiring 21 is about 5 times the width W1 of the 1 MOS transistor.

In fig. 16, the MOS transistors M01 to M04 connected to the mirror terminal 120 of the mirror source in fig. 17 are all disposed at the center of the wiring 21. On the other hand, the MOS transistors M11 to M84 of the mirror targets are arranged in the same order as in embodiment 1 (fig. 1). In the arrangement of fig. 17, the combination of distances in the planar direction from each mirror destination to the nearest mirror source is the same between the mirror terminals of the mirror destinations. Therefore, the variation depending on the distance from the mirror source can be reduced.

Fig. 18 is an enlarged plan view showing a region of the 9 transistors M11 to M81 from the left in fig. 16. Distances in the planar direction from the MOS transistors M11, M21, M31, and M41 to the wiring end of the wide wiring 21 are D4, D3, E3, and E4, respectively. The same is true for M51 to M81.

In the mirror image terminals 121 to 128 of the mirror image object in fig. 17, by arranging the MOS transistors and the wide wirings 21 as in fig. 16, the combinations of the distances in the plane direction from the MOS transistors to the wide wirings 21 become D3, D4, E3, and E4. Thus, the influence of the wide wiring of each mirror image object becomes the same, and the variation in the mirror image ratio between the mirror image objects is reduced.

However, the influence of wiring stress of the mirror source is different from that of the mirror target. Therefore, in the case of this embodiment, the MOS transistor sizes of the mirror source and the mirror target are adjusted so as to have the necessary mirror ratio, or the mirror ratio is corrected by calibration after the semiconductor integrated circuit device is manufactured.

In addition, for long-term variations in the mirror ratio, correction is required even when there is variation. However, since the influence of the strain due to the wide wiring between the mirror targets is the same, it is not necessary to correct the mirror ratio for each mirror target, and the correction can be simplified.

As described above, in the semiconductor device of the present embodiment, the circuit is a current mirror circuit, and the semiconductor device further includes the 3 rd semiconductor element group (the group of mirror terminals 120) in which a plurality of semiconductor elements (MOS transistors M01 to M04) are connected in parallel, the 1 st semiconductor element group (the group of mirror terminals 121) and the 2 nd semiconductor element group (the group of mirror terminals 122) are targets of mirror images of the current mirror circuit, and the 3 rd semiconductor element group (the group of mirror terminals 120) is a source of mirror images of the current mirror circuit.

Further, the semiconductor device includes a plurality of semiconductor element groups (mirror terminals 121 to 128) to be mirrored, and the combination of distances in the planar direction from each semiconductor element of the plurality of semiconductor element groups (mirror terminals 121 to 128) to the wide wiring 21 at the position where the distance in the planar direction is closest is equal to the combination of distances in the planar direction of the 1 st semiconductor element group (mirror terminal 121).

Example 5

A semiconductor device according to embodiment 5 of the present invention will be described with reference to fig. 19. Fig. 19 shows an example of the positional relationship of the planes of the MOS transistors M01 to M74 and the wide wiring 20 constituting the current mirror circuit in the semiconductor device of the present embodiment, and the dummy wiring 22 which is the same wiring layer as the wide wiring 20. In addition, the current mirror circuit of the present embodiment is the same as that of fig. 2.

In the present embodiment, only 2 wide wirings 20 are arranged for the array of MOS transistors M01 to M74 constituting the current mirror circuit. In a part of the position where the wide wiring 20 is arranged in fig. 1, a dummy wiring 22 having the same width as the wide wiring 20 is arranged in the same wiring layer. For the same reason as in embodiment 1, the dummy interconnection 22 has the same effect as that of embodiment 1 in that the influence of the stress applied to the MOS transistor from the wide interconnection 20 is applied between the terminals of the mirror image target and the mirror image source.

As shown in the stress simulation result of fig. 3B, the stresses applied to the silicon are different at the wire end and the wire center, so the dummy wire 22 of fig. 19 needs to extend in the Y direction from the MOS transistor array.

Example 6

A semiconductor device according to embodiment 6 of the present invention will be described with reference to fig. 20 and 21. Fig. 20 shows an example of the planar positional relationship between the MOS transistors M01 to M64 constituting the current mirror circuit in the semiconductor device of the present embodiment and the wide wiring 20. As in example 1 (fig. 1), the array of MOS transistors M01 to M64 is arranged in the X direction, and the wide wiring 20 is arranged to extend in the Y direction perpendicular to the MOS transistors M01 to M64. In addition, the width W2 of the 1 wide wiring 20 is about 4 times the width W1 of the 1 MOS transistor. Fig. 21 is a circuit diagram of the current mirror circuit of fig. 20.

In fig. 20, dummy transistors DM1 to DM4 as dummy semiconductor elements are arranged in the MOS transistor array in order to adjust the positions of the MOS transistors M01 to M64 and the wide wirings 20. Thus, as in example 1 (fig. 1), in the group of MOS transistors corresponding to the mirror terminals 130 to 136 of fig. 21, since the combinations of distances in the planar direction from the MOS transistors to the nearest wide wiring 20 are the same, the influence of the stress of the wide wiring 20 can be made equal between the mirror source and the mirror destination, and the initial variation of the mirror ratio of the current mirror circuit can be reduced and the time degradation (aging change) can be suppressed.

In addition, although the above-described embodiments 1 to 6 are examples of the arrangement of the MOS transistor group and the upper layer wiring connected in parallel to the mirror terminal of the current mirror circuit, the arrangement of the semiconductor element such as a bipolar transistor or a semiconductor resistor element and the upper layer wiring may be adopted in addition to the MOS transistor.

In addition, the present invention is not limited to the above-described embodiments, and includes various strain examples.

For example, the above-described embodiments are examples explained in detail to explain the present invention easily and understandably, and are not necessarily limited to having all the configurations explained. Further, a part of the configuration of one embodiment may be replaced with the configuration of another embodiment, or the configuration of another embodiment may be added to the configuration of one embodiment. Further, a part of the configuration of each embodiment may be added, deleted, or replaced with another configuration.

Description of the symbols

M0-M7: MOS transistor

M01-M84: MOS transistor

DM 1-DM 4: dummy transistor

10: (Metal) Wiring layer

20. 21: wide-width (metal) wiring

22: dummy wiring (of the same wiring layer as the metal wiring 20)

30. 31: wide (metal) wiring (of a wiring layer different from the metal wiring 20)

W1-W3: transistor size or width of metal wiring

100-107: mirror terminal (of current mirror circuit)

110-117: mirror terminal (of current mirror circuit)

120-128: mirror terminal (of current mirror circuit)

130 to 136: mirror terminal (of current mirror circuit)

D1-D4: distance (in the plane direction from MOS transistor to wide metal wiring)

E1-E5: distance (in the plane direction from MOS transistor to wide metal wiring)

F1-F3: distance (in the plane direction from MOS transistor to wide metal wiring)

G1: distance (in the plane direction from MOS transistor to wide metal wiring)

H1-H3: distance (in the planar direction from MOS transistor to overlap of wide metal wiring)

J1: distance (in the planar direction from MOS transistor to overlap of wide metal wiring)

200: copper wiring

300: silicon substrate (semiconductor substrate)

301: silicon (Si) layer

302: interface (of silicon layer 301 and silicon oxide film 401)

400: silicon oxide film

401: silicon oxide film (interlayer oxide film)

500: a polyimide film.