阅读说明：本技术 像素和具有像素的显示装置 (Pixel and display device having the same ) 是由 李炫旭 康起宁 金珍泽 金泰佑 李咥瑾 蔡景泰 于 2021-06-11 设计创作，主要内容包括：公开了像素和具有像素的显示装置。该像素可以包括：像素电路层,包括设置在基底上的至少一个晶体管和第一电极以及设置在至少一个晶体管和第一电极上的第一绝缘层；以及显示元件层,设置在像素电路层上,显示元件层包括电连接到至少一个晶体管的第二电极以及电连接到第一电极和第二电极中的每者的多个发光元件。第一电极和第二电极可以设置在不同的层上并且可以彼此间隔开。多个发光元件可以在平面图和剖视图中与第一电极和第二电极叠置。(A pixel and a display device having the same are disclosed. The pixel may include: a pixel circuit layer including at least one transistor and a first electrode disposed on the substrate and a first insulating layer disposed on the at least one transistor and the first electrode; and a display element layer disposed on the pixel circuit layer, the display element layer including a second electrode electrically connected to the at least one transistor and a plurality of light emitting elements electrically connected to each of the first electrode and the second electrode. The first and second electrodes may be disposed on different layers and may be spaced apart from each other. The plurality of light emitting elements may overlap the first electrode and the second electrode in a plan view and a sectional view.)

1. A pixel, the pixel comprising:

a pixel circuit layer, the pixel circuit layer comprising: at least one transistor and a first electrode disposed on the substrate; and a first insulating layer disposed on the at least one transistor and the first electrode; and

a display element layer disposed on the pixel circuit layer, the display element layer including: a second electrode electrically connected to the at least one transistor; and a plurality of light emitting elements electrically connected to each of the first electrode and the second electrode, wherein,

the first electrode and the second electrode are disposed on different layers and spaced apart from each other, and

the plurality of light emitting elements overlap the first electrode and the second electrode in a plan view and a sectional view.

2. The pixel of claim 1, wherein the first electrode and the second electrode are spaced apart by a distance in a first direction in the plan view.

3. The pixel according to claim 1, wherein the first electrode and the second electrode overlap with each other in the plan view.

4. The pixel of claim 3,

the second electrode is disposed on the first electrode, and

the first insulating layer is disposed between the second electrode and the first electrode.

5. The pixel according to claim 4, wherein a width of the first electrode in a first direction is larger than a width of the second electrode in the first direction in the plan view and the cross-sectional view.

6. The pixel according to claim 5, wherein the first electrode has a plate shape and is provided between the pixel circuit layer and the display element layer.

7. The pixel according to claim 5,

the first electrode comprises an opaque conductive material, and

the second electrode includes a transparent conductive material.

8. The pixel according to claim 5, wherein a width of an overlapping area of the first electrode and the second electrode in the first direction is smaller than the width of the first electrode in the first direction.

9. The pixel according to claim 1,

the display element layer includes:

a second insulating layer disposed on the second electrode;

a first contact electrode electrically connecting the first electrode and each of the plurality of light emitting elements; and

a second contact electrode electrically connecting the second electrode and each of the plurality of light emitting elements, and

the plurality of light emitting elements are disposed on the second insulating layer.

10. The pixel of claim 1, further comprising:

a third electrode disposed on the pixel circuit layer, wherein,

the second electrode and the third electrode are disposed on the same layer,

each of the second and third electrodes is spaced apart from the first electrode, and

the first insulating layer is disposed between each of the second and third electrodes and the first electrode.

11. The pixel of claim 10, wherein the plurality of light emitting elements comprises:

a first light emitting element overlapping the first electrode and the second electrode in the plan view and the cross-sectional view and electrically connected to each of the first electrode and the second electrode; and

a second light emitting element overlapping the first electrode and the third electrode in the plan view and the cross-sectional view and electrically connected to each of the first electrode and the third electrode.

12. The pixel according to claim 10,

the second electrode, the first electrode, and the third electrode are sequentially arranged in a first direction in the plan view, and

each of the first electrode, the second electrode, and the third electrode is spaced apart from an adjacent electrode in the first direction.

13. The pixel according to claim 10, wherein the first electrode overlaps each of the second electrode and the third electrode in the plan view.

14. The pixel according to claim 13, wherein a width of the first electrode in a first direction is larger than a width of each of the second electrode and the third electrode in the first direction.

15. The pixel according to claim 1,

the second electrode includes 1 st-1 st, 1 st-2 nd, 1 st-3 rd and 1 st-4 th electrodes spaced apart from each other on the pixel circuit layer,

the first electrode includes a 2-1 st electrode, a 2-2 nd electrode and a 2-3 rd electrode spaced apart from each other on the substrate,

the 1 st-1 st electrode, the 2 nd-1 st electrode, the 1 st-2 nd electrode, the 2 nd-2 nd electrode, the 1 st-3 rd electrode, the 2 nd-3 rd electrode, and the 1 st-4 th electrode are sequentially arranged in a first direction in the plan view and the cross-sectional view, and

the first electrode and the second electrode are spaced apart in the first direction in the plan view.

16. The pixel of claim 15, wherein the plurality of light emitting elements comprises:

a first light emitting element disposed between the 1 st-1 st electrode and the 2 nd-1 st electrode in the plan view;

a second light emitting element disposed between the 2 nd-1 st electrode and the 1 st-2 nd electrode in the plan view;

a third light emitting element disposed between the 1 st-2 nd electrode and the 2 nd-2 nd electrode in the plan view;

a fourth light emitting element disposed between the 2 nd-2 nd electrode and the 1 st-3 rd electrode in the plan view;

a fifth light emitting element disposed between the 1 st-3 rd electrode and the 2 nd-3 rd electrode in the plan view; and

a sixth light emitting element disposed between the 2 nd to 3 rd electrodes and the 1 st to 4 th electrodes in the plan view.

17. The pixel according to claim 1,

the second electrode includes 1 st-1 st, 1 st-2 nd, 1 st-3 rd and 1 st-4 th electrodes spaced apart from each other on the pixel circuit layer, and

the first electrode is plate-shaped and overlaps with a portion of the 1 st-1 st electrode, the 1 st-2 nd electrode, the 1 st-3 rd electrode, and the 1 st-4 th electrode.

18. A pixel, the pixel comprising:

a pixel circuit layer, the pixel circuit layer comprising: at least one transistor and a first electrode disposed on the substrate; a first insulating layer disposed on the at least one transistor and the first electrode; and a second electrode disposed on the first insulating layer and electrically connected to the at least one transistor; and

a display element layer disposed on the pixel circuit layer, the display element layer including a plurality of light emitting elements electrically connected to each of the first electrode and the second electrode, wherein,

the first electrode and the second electrode are disposed on different layers and electrically disconnected, an

The plurality of light emitting elements overlap with the first electrode and the second electrode in a plan view.

19. A display device, the display device comprising: a substrate including a plurality of pixel regions and a pixel disposed in each of the pixel regions,

wherein the pixel includes:

a pixel circuit layer, the pixel circuit layer comprising: at least one transistor and a first electrode disposed on the substrate; and a first insulating layer disposed on the at least one transistor and the first electrode; and

a display element layer disposed on the pixel circuit layer, the display element layer including: a second electrode electrically connected to the at least one transistor; and a plurality of light emitting elements electrically connected to each of the first electrode and the second electrode,

the first electrode and the second electrode are disposed on different layers and electrically disconnected, an

The plurality of light emitting elements overlap the first electrode and the second electrode in a plan view and a sectional view.

20. The display device according to claim 19,

the second electrode is disposed on the first electrode, and

the first insulating layer is disposed between the second electrode and the first electrode.

Technical Field

The present disclosure relates to a pixel and a display device including the same.

Background

As interest in information display increases and demand for use of portable information media increases, demand for display devices and commercialization are receiving attention.

Disclosure of Invention

The disclosed object includes providing a pixel capable of improving light output efficiency while improving a short defect between two adjacent electrodes.

It is another object of the disclosure to provide a display device having the above pixel.

A pixel according to a disclosed embodiment may include: a pixel circuit layer including at least one transistor and a first electrode disposed on a substrate and a first insulating layer disposed on the at least one transistor and the first electrode; a display element layer disposed on the pixel circuit layer, the display element layer including a second electrode electrically connected to the at least one transistor and a plurality of light emitting elements electrically connected to each of the first electrode and the second electrode. The first electrode and the second electrode may be disposed on different layers and may be separated from each other. The plurality of light emitting elements may overlap the first electrode and the second electrode in a plan view and a sectional view.

In the disclosed embodiment, the first electrode and the second electrode may be spaced apart by a distance in a first direction in a plan view.

In the disclosed embodiment, the first electrode and the second electrode may be stacked on each other in a plan view.

In disclosed embodiments, the second electrode may be disposed on the first electrode, and the first insulating layer is disposed between the second electrode and the first electrode.

In a disclosed embodiment, a width of the first electrode in the first direction may be greater than a width of the second electrode in the first direction in a plan view and a sectional view.

In the disclosed embodiment, the first electrode may have a plate shape and be disposed between the pixel circuit layer and the display element layer.

In an embodiment of the present disclosure, the first electrode may include an opaque conductive material, and the second electrode may include a transparent conductive material.

In the disclosed embodiment, a width of the overlapping region of the first electrode and the second electrode in the first direction may be smaller than a width of the first electrode in the first direction.

In disclosed embodiments, the display element layer may include: a second insulating layer disposed on the second electrode; a first contact electrode electrically connecting the first electrode and each of the plurality of light emitting elements; and a second contact electrode electrically connecting the second electrode and each of the plurality of light emitting elements, and the plurality of light emitting elements may be disposed on the second insulating layer.

In a disclosed embodiment, the pixel may further include: and a third electrode disposed on the pixel circuit layer. The second and third electrodes may be disposed on the same layer, each of the second and third electrodes and the first electrode may be spaced apart from each other, and a first insulating layer may be disposed between each of the second and third electrodes and the first electrode.

In disclosed embodiments, the plurality of light emitting elements may include: a first light emitting element overlapping the first and second electrodes in a plan view and a sectional view, and electrically connected to each of the first and second electrodes; and a second light emitting element overlapping the first electrode and the third electrode in a plan view and a sectional view, and electrically connected to each of the first electrode and the third electrode.

In the disclosed embodiment, the second electrode, the first electrode, and the third electrode may be sequentially arranged in a first direction in a plan view, and each of the first electrode, the second electrode, and the third electrode may be spaced apart from an adjacent electrode in the first direction.

In the disclosed embodiment, the first electrode may overlap each of the second electrode and the third electrode in a plan view.

In an embodiment of the present disclosure, a width of the first electrode in the first direction may be greater than a width of each of the second and third electrodes in the first direction.

In the disclosed embodiment, the second electrode may include a 1 st-1 st electrode, a 1 st-2 nd electrode, a 1 st-3 rd electrode, and a 1 st-4 th electrode spaced apart from each other on the pixel circuit layer, the first electrode may include a 2 nd-1 st electrode, a 2 nd-2 nd electrode, and a 2 nd-3 rd electrode spaced apart from each other on the substrate, the 1 st-1 st electrode, the 2 nd-1 st electrode, the 1 st-2 nd electrode, the 2 nd-2 nd electrode, the 1 st-3 rd electrode, the 2 nd-3 th electrode, and the 1 st-4 th electrode may be sequentially arranged in a first direction in a plan view and a cross-sectional view, and the first electrode and the second electrode may be spaced apart in the first direction in a plan view.

In disclosed embodiments, the plurality of light emitting elements may include: a first light emitting element disposed between the 1 st-1 st electrode and the 2 nd-1 st electrode in a plan view; a second light emitting element disposed between the 2 nd-1 st electrode and the 1 st-2 nd electrode in a plan view; a third light emitting element disposed between the 1 st-2 nd electrode and the 2 nd-2 nd electrode in a plan view; a fourth light emitting element disposed between the 2 nd-2 nd electrode and the 1 st-3 rd electrode in a plan view; a fifth light emitting element disposed between the 1 st to 3 rd electrodes and the 2 nd to 3 rd electrodes in a plan view; and a sixth light emitting element disposed between the 2 nd to 3 rd electrodes and the 1 st to 4 th electrodes in a plan view.

In the disclosed embodiment, the second electrode may include a 1 st-1 st electrode, a 1 st-2 nd electrode, a 1 st-3 rd electrode, and a 1 st-4 th electrode spaced apart from each other on the pixel circuit layer, and the first electrode may be disposed in a plate shape and overlap a portion of the 1 st-1 st electrode, the 1 st-2 nd electrode, the 1 st-3 rd electrode, and the 1 st-4 th electrode.

A pixel according to another disclosed embodiment may include: a pixel circuit layer including at least one transistor and a first electrode disposed on a substrate, a first insulating layer disposed on the at least one transistor and the first electrode, and a second electrode disposed on the first insulating layer and electrically connected to the at least one transistor; and a display element layer disposed on the pixel circuit layer, the display element layer including a plurality of light emitting elements electrically connected to each of the first electrode and the second electrode. The first electrode and the second electrode may be disposed on different layers and may be electrically disconnected. The plurality of light emitting elements may overlap the first electrode and the second electrode in a plan view.

The display device according to the disclosed embodiment may include: a substrate including a plurality of pixel regions; and a pixel disposed in each of the pixel regions. The pixel may include: a pixel circuit layer including at least one transistor and a first electrode disposed on a substrate and a first insulating layer disposed on the at least one transistor and the first electrode; a display element layer disposed on the pixel circuit layer, the display element layer including a second electrode electrically connected to the at least one transistor and a plurality of light emitting elements electrically connected to each of the first electrode and the second electrode. The first electrode and the second electrode may be disposed on different layers and may be electrically disconnected. The plurality of light emitting elements may overlap the first electrode and the second electrode in a plan view and a sectional view.

In the disclosed embodiments, the second electrode may be disposed on the first electrode, and the first insulating layer may be disposed between the second electrode and the first electrode.

The pixel and the display device including the same according to the disclosed embodiments can improve light output efficiency by effectively aligning light emitting elements between two adjacent electrodes.

The pixel and the display device including the same according to the disclosed embodiments may improve reliability of a light emitting element by using one of a first electrode and a second electrode as a shielding member blocking an electric field induced from a configuration positioned under the one electrode.

The pixel and the display device including the pixel can easily realize high resolution.

Effects according to the disclosed embodiments are not limited to the above, and more various effects are included in the disclosure.

Drawings

The above and other features of the disclosure will become more apparent by describing the disclosed embodiments in more detail with reference to the attached drawings, in which:

FIG. 1 is a perspective view schematically illustrating a light emitting element according to a disclosed embodiment;

FIG. 2 is a schematic cross-sectional view of the light emitting element of FIG. 1;

fig. 3 is a schematic plan view showing a display device (in particular, a display device using the light emitting element shown in fig. 1 and 2 as a light source) according to the disclosed embodiment;

fig. 4 is a schematic circuit diagram showing an electrical connection relationship between components included in the pixel shown in fig. 3 according to the embodiment;

fig. 5 is a plan view schematically showing one of the pixels shown in fig. 3;

fig. 6 is a schematic plan view showing a first electrode and a second electrode and a light emitting element in the pixel of fig. 5;

FIG. 7 is a schematic cross-sectional view taken along line I-I' of FIG. 5;

FIG. 8 is a schematic cross-sectional view taken along line II-II' of FIG. 5;

fig. 9 and 10 are schematic cross-sectional views taken along line I-I' of fig. 5 illustrating an implementation of the first and second electrodes of fig. 7 according to another embodiment;

FIG. 11 is a schematic cross-sectional view taken along line I-I' of FIG. 5 illustrating an implementation of the first and second electrodes of FIG. 7 according to another embodiment;

fig. 12 is a plan view schematically illustrating a pixel according to another embodiment of the disclosure;

FIG. 13 is a schematic cross-sectional view taken along line III-III' of FIG. 12;

fig. 14 is a plan view schematically illustrating a pixel according to still another embodiment of the disclosure;

FIG. 15 is a schematic cross-sectional view taken along line IV-IV' of FIG. 14;

fig. 16 is a plan view schematically illustrating a pixel according to still another embodiment of the disclosure;

FIG. 17 is a schematic cross-sectional view taken along line V-V' of FIG. 16;

fig. 18 is a plan view schematically showing a pixel according to still another embodiment of the disclosure;

FIG. 19 is a schematic cross-sectional view taken along line VI-VI' of FIG. 18;

fig. 20 is a plan view schematically illustrating a pixel according to still another embodiment of the disclosure;

FIG. 21 is a schematic cross-sectional view taken along line VII-VII' of FIG. 20;

FIG. 22 is a schematic plan view of a second electrode implemented in the pixel of FIG. 20 according to another embodiment;

FIG. 23 is a schematic cross-sectional view taken along line VIII-VIII' of FIG. 22;

fig. 24 schematically illustrates a pixel according to still another embodiment of the disclosure, and is a plan view illustrating adjacent electrodes and a light emitting element positioned between the adjacent electrodes;

fig. 25A and 25B are schematic sectional views taken along line IX-IX' of fig. 24; and is

Fig. 26 is a schematic plan view of a second electrode implemented in accordance with another embodiment in the pixel of fig. 24.

Detailed Description

The disclosure may be modified in various ways and have various forms. Therefore, specific embodiments will be shown in the drawings and will be described in detail in the specification. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed, but to the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure.

In describing each of the figures, like reference numerals are used for like components. In the drawings, the size of the structures is exaggerated from actual size for clarity of disclosure. The terms "first," "second," and the like may be used to describe various components, but the components should not be limited by the terms. Terminology is used only for the purpose of distinguishing one component from another. For example, a first component can be termed a second component, and, similarly, a second component can also be termed a first component, without departing from the scope of the disclosure. Unless the context clearly dictates otherwise, singular expressions include plural expressions.

It will be understood that, in the disclosure, the terms "comprises", "comprising", "includes" and the like are used to specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. The case where a part of a layer, a film, a region, a plate, or the like is referred to as being "on" another part includes not only the case where the part is "directly on" the other part but also the case where another part exists between the part and the other part. In the disclosure, when a portion of a layer, a film, a region, a plate, or the like is formed on another portion, the forming direction is not limited to the upper direction but includes forming the portion on a side surface or in the lower direction. In contrast, when a part of a layer, a film, a region, a plate, or the like is formed "under" another part, this includes not only a case where the part is "directly under" the other part but also a case where another part exists between the part and the other part.

In the disclosure, in the case where a component (e.g., a first component) is operatively or communicatively coupled/coupled to another component (e.g., a second component) or connected to another component (e.g., a second component), it should be understood that the component may be directly connected to the other component or may be connected to the other component through yet another component (e.g., a third component). In contrast, in the case where a component (e.g., a first component) is directly bonded/directly bonded to/or directly connected to another component (e.g., a second component), the case may be understood that there is no further component (e.g., a third component) between the component and the other component.

Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, the disclosed embodiments and other embodiments for understanding the disclosure by those skilled in the art will be described in detail with reference to the accompanying drawings.

Fig. 1 is a perspective view schematically showing a light emitting element according to an embodiment, and fig. 2 is a schematic sectional view of the light emitting element of fig. 1.

In embodiments, the type and/or shape of the light emitting elements is not limited to the embodiments shown in fig. 1 and 2.

Referring to fig. 1 and 2, the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may include a light emitting stack body in which a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 are sequentially stacked.

The light emitting element LD may have a shape extending in one direction. In a case where the extending direction of the light emitting element LD is referred to as a longitudinal direction, the light emitting element LD may include one end portion (or a lower end portion) and the other end portion (or an upper end portion) in the extending direction. Either one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at one end (or a lower end) of the light emitting element LD, and the other one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the other end (or an upper end) of the light emitting element LD. For example, the first semiconductor layer 11 may be disposed at one end (or lower end) of the light emitting element LD, and the second semiconductor layer 13 may be disposed at the other end (or upper end) of the light emitting element LD.

The light emitting element LD may be provided in any of various shapes. For example, the light emitting element LD may have, for example, a rod-like or stripe-like shape elongated in the longitudinal direction (for example, the aspect ratio of the light emitting element LD is greater than about 1). In the embodiment, the length L of the light emitting element LD in the longitudinal direction may be larger than the diameter D (or the width of the cross section) of the light emitting element LD. The light emitting element LD may include, for example, a Light Emitting Diode (LED) that is manufactured to be small to have a diameter D and/or a length L on the order of about a micrometer or nanometer scale.

The diameter D of the light emitting element LD may be about 0.5 μm to about 500 μm, and the length L may be about 1 μm to about 1000 μm. However, the diameter D and the length L of the light emitting element LD are not limited thereto. The size of the light emitting element LD may be changed to meet the requirements (or design conditions) of an illumination device or a light emitting display device to which the light emitting element LD is applied.

For example, the first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include any one of semiconductor materials among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or an n-type dopant) such as Si, Ge, or Sn. However, the material forming the first semiconductor layer 11 is not limited thereto, and various materials may form (or configure) the first semiconductor layer 11. In an embodiment, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or an n-type dopant). The first semiconductor layer 11 may include an upper surface contacting the active layer 12 in a direction of the length L of the light emitting element LD and a lower surface exposed to the outside. The lower surface of the first semiconductor layer 11 may be an end portion (or a lower end portion) of the light emitting element LD.

The active layer 12 may be disposed on the first semiconductor layer 11, and may be formed in a single quantum well structure or a multiple quantum well structure. For example, in the case where the active layer 12 is formed in a multiple quantum well structure, the active layer 12 may include a barrier layer (not shown), a strain enhancement layer, and a well layer, which are periodically and repeatedly stacked as a unit. The strain enhancement layer may have a lattice constant smaller than that of the barrier layer to further enhance a strain, such as a compressive strain, applied to the well layer. However, the structure of the active layer 12 is not limited to the above-described embodiment.

The active layer 12 may emit light of a wavelength of about 400nm to about 900nm, and a double heterostructure may be used. In an embodiment, a clad layer (not shown) doped with a conductive dopant may be formed on and/or under the active layer 12 in a direction of the length L of the light emitting element LD. For example, the cladding layer may be formed of or include an AlGaN or InAlGaN layer. According to an embodiment, a material such as AlGaN or InAlGaN may be used to form the active layer 12. Various materials may form the active layer 12. The active layer 12 may include a first surface contacting the first semiconductor layer 11 and a second surface contacting the second semiconductor layer 13.

In the case where an electric field of a predetermined voltage or more is applied to the end portion of the light emitting element LD, the light emitting element LD emits light while electron-hole pairs are recombined in the active layer 12. By controlling the light emission of the light emitting element LD using such a principle, the light emitting element LD can be used as a light source (or a light emission source) of various light emitting devices including a pixel of a display device.

The second semiconductor layer 13 may be disposed on the second surface of the active layer 12, and may include a type of semiconductor layer different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg. However, the material forming the second semiconductor layer 13 is not limited thereto, and various materials may form the second semiconductor layer 13. In an embodiment, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or a p-type dopant). The second semiconductor layer 13 may include a lower surface contacting the second surface of the active layer 12 in the direction of the length L of the light emitting element LD and an upper surface exposed to the outside. Here, the upper surface of the second semiconductor layer 13 may be the other end portion (or the upper end portion) of the light emitting element LD.

In the embodiment, the first semiconductor layer 11 and the second semiconductor layer 13 may have thicknesses different from each other in the direction of the length L of the light emitting element LD. For example, the first semiconductor layer 11 may have a thickness relatively larger than that of the second semiconductor layer 13 in the direction of the length L of the light emitting element LD. Therefore, the active layer 12 of the light emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than the lower surface of the first semiconductor layer 11.

Although the first semiconductor layer 11 and the second semiconductor layer 13 are illustrated as being formed of a layer, the disclosure is not limited thereto. In an embodiment, each of the first and second semiconductor layers 11 and 13 may further include at least one layer, such as a cladding layer and/or a Tensile Strain Barrier Reduction (TSBR) layer, depending on the material of the active layer 12. The TSBR layer may be a strain relief layer disposed between semiconductor layers having different lattice structures and serving as a buffer that reduces differences in lattice constants. The TSBR layer may be formed (or constructed) of a p-type semiconductor layer such as p-GaInP, p-AlInP, and p-AlGaInP, but the disclosure is not limited thereto.

According to an embodiment, the light emitting element LD may further include an additional electrode (not shown, hereinafter referred to as a first additional electrode) disposed on the second semiconductor layer 13, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 described above. According to another embodiment, the light emitting element LD may further include another additional electrode (not shown, hereinafter referred to as a second additional electrode) disposed at an end portion of the first semiconductor layer 11.

Each of the first and second additional electrodes may be an ohmic contact electrode, but the disclosure is not limited thereto. According to an embodiment, the first additional electrode and the second additional electrode may be schottky contact electrodes. The first additional electrode and the second additional electrode may include a conductive material. For example, the first additional electrode and the second additional electrode may include opaque metals using chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), oxides thereof, alloys thereof, etc., alone or in combination, but the disclosure is not limited thereto. According to an embodiment, the first and second additional electrodes may further include a transparent conductive oxide such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), Indium Gallium Zinc Oxide (IGZO), and Indium Tin Zinc Oxide (ITZO).

The materials included in the first additional electrode and the second additional electrode may be the same as or different from each other. The first further electrode and the second further electrode may be substantially transparent or translucent. Therefore, light generated by the light emitting element LD may pass through the first additional electrode and the second additional electrode and may be emitted to the outside of the light emitting element LD. According to the embodiment, in the case where light generated by the light emitting element LD does not pass through the first and second additional electrodes and is emitted to the outside of the light emitting element LD through a region of the light emitting element LD other than the end portion of the light emitting element LD, the first and second additional electrodes may include an opaque metal.

In the embodiment, the light emitting element LD may further include an insulating film 14. However, according to the embodiment, the insulating film 14 may be omitted, and may cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 or overlap a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

The insulating film 14 can prevent an electrical short that may occur in the case where the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film 14 can minimize or reduce surface defects of the light emitting element LD to improve the life and light emitting efficiency of the light emitting element LD. In the case where the light emitting elements LD are closely arranged, the insulating film 14 can prevent an unnecessary short circuit that may occur between the light emitting elements LD. In the case where the active layer 12 prevents short-circuiting with an external conductive material, the insulating film 14 may or may not be present.

The insulating film 14 may surround the entire outer circumferential surface of the light emitting stack including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

In the above-described embodiment, the insulating film 14 may surround the entire outer circumferential surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, but the disclosure is not limited thereto. According to the embodiment, in the case where the light emitting element LD includes the first additional electrode, the insulating film 14 may surround the entire outer circumferential surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first additional electrode. According to another embodiment, the insulating film 14 may not surround the entire outer circumferential surface of the first additional electrode, or may surround only a portion of the outer circumferential surface of the first additional electrode, and may not surround the remaining portion of the outer circumferential surface of the first additional electrode. According to the embodiment, in the case where the first additional electrode is disposed at the other end (or upper end) of the light emitting element LD and the second additional electrode is disposed at one end (or lower end) of the light emitting element LD, the insulating film 14 may expose at least one region of each of the first additional electrode and the second additional electrode.

The insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Silicon oxynitride (SiO)_xN_y) Aluminum oxide (AlO)_x) And titanium dioxide (TiO)₂) At least one insulating material selected from the group consisting of, but the disclosure is not limited thereto, and various materials having insulating properties may be used as the material of the insulating film 14.

According to the embodiment, the light emitting element LD may be implemented with a light emitting pattern having a core-shell structure. In this case, the above-described first semiconductor layer 11 may be positioned in a core (e.g., the middle (or center) of the light emitting element LD), the active layer 12 may be disposed and/or formed around the outer circumferential surface of the first semiconductor layer 11, and the second semiconductor layer 13 may be disposed and/or formed around the outer circumferential surface of the active layer 12. The light emitting element LD may further include an additional electrode (not shown) surrounding at least one side of the second semiconductor layer 13. According to the embodiment, the light emitting element LD may further include the insulating film 14 disposed on the outer circumferential surface of the light emitting pattern having the core-shell structure and including a transparent insulating material. The light emitting element LD realized with the light emitting pattern having the core-shell structure may be manufactured by a growth method.

The light-emitting element LD described above can be used as a light-emitting source of various display devices. The light emitting element LD can be manufactured by a surface treatment process. For example, in the case where the light emitting elements LD are mixed in a fluid solution (or solvent) and supplied to each pixel region (for example, a light emitting region of each pixel or a light emitting region of each sub-pixel), a surface treatment may be performed on each of the light emitting elements LD so that the light emitting elements LD may be uniformly ejected instead of being collected in the solution.

A light-emitting unit (or a light-emitting device) including the above-described light-emitting element LD can be used in various types of electronic devices (such as a display device) that require a light source. For example, in the case where the light emitting element LD is disposed in a pixel region of each pixel of the display panel, the light emitting element LD may be used as a light source of each pixel. However, the application field of the light emitting element LD is not limited to the above example. For example, the light emitting element LD may be used in other types of electronic devices (such as lighting devices) that require a light source.

Fig. 3 is a schematic plan view illustrating a display device (in particular, a display device using the light emitting element illustrated in fig. 1 and 2 as a light source) according to an embodiment.

In fig. 3, the structure of the display device is schematically shown based on the display area DA of the display image for convenience.

Referring to fig. 1 to 3, a display device according to an embodiment may include a substrate SUB, pixels PXL disposed on the substrate SUB and each including at least one light emitting element LD, a driver disposed on the substrate SUB and driving the pixels PXL, and line parts electrically connecting the pixels PXL and the driver to each other.

The disclosure may also be applied to a display device in the case where the display device is an electronic device, such as a smart phone, a television, a tablet PC, a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a PDA, a Portable Multimedia Player (PMP), an MP3 player, a medical device, a camera, or a wearable device, of which at least one surface is a display surface.

The display device can be classified into a passive matrix type display device and an active matrix type display device according to a method of driving the light emitting element LD. For example, in the case where the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor that controls the amount of current supplied to the light emitting element LD, a switching transistor that transmits a data signal to the driving transistor, and the like.

The display device may have various shapes, for example, a rectangular plate shape having two pairs of sides parallel to each other, but the disclosure is not limited thereto. In the case where the display device has a rectangular plate shape, one of the two pairs of sides may be longer than the other of the two pairs of sides. For convenience, the display device may have a rectangular shape having a pair of long sides and a pair of short sides. The extending direction of the long side is denoted as a second direction DR2, the extending direction of the short side is denoted as a first direction DR1, and a direction perpendicular to the extending direction of the long side and the short side is denoted as a third direction DR 3. The display device having a rectangular plate shape may have rounded corner portions where long sides and short sides contact (or meet) each other, but the disclosure is not limited thereto.

The substrate SUB may include a display area DA and a non-display area NDA.

The display area DA may be an area where pixels PXL displaying an image are disposed. The non-display area NDA may be an area provided with a driver for driving the pixels PXL and at least a portion of a line part connecting the pixels PXL and the driver to each other. For convenience, only the pixels PXL are shown in fig. 3, but substantially a plurality of pixels PXL may be disposed in the display area DA of the substrate SUB.

The non-display area NDA may be disposed on at least one side of the display area DA. The non-display area NDA may surround the periphery (or edge) of the display area DA. The non-display area NDA may be provided with line portions electrically connected to the pixels PXL and a driver electrically connected to the line portions and driving the pixels PXL.

The line portion may electrically connect the driver and the pixel PXL to each other. The line portion may provide a signal to each pixel PXL and may be a signal line electrically connected to each pixel PXL, for example, a fanout line electrically connected to a scan line, a data line, a light emission control line, and the like. The line part may be a signal line electrically connected to each pixel PXL (e.g., a fanout line electrically connected to a control line, a sensing line, etc.) to compensate for a change in electrical characteristics of each pixel PXL in real time.

The substrate SUB may include a transparent insulating material and may transmit light. The substrate SUB may be a rigid or flexible substrate.

An area on the substrate SUB may be set as the display area DA and thus the pixels PXL may be set, and the remaining area on the substrate SUB may be set as the non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel area in which each pixel PXL is disposed and a non-display area NDA disposed around the display area DA (or adjacent to the display area DA).

Each of the pixels PXL may be disposed in the display area DA on the substrate SUB. In an embodiment, the pixels PXL may be arranged in the display area DA in a stripe arrangement structure or a pentile (or referred to as "five tiles") arrangement structure, but the disclosure is not limited thereto.

Each of the pixels PXL may include at least one light emitting element LD driven by a corresponding scan signal and a corresponding data signal. The light emitting elements LD may have a size of the order of a micrometer or nanometer and may be electrically connected in parallel with the adjacent light emitting elements LD, but the disclosure is not limited thereto. The light emitting element LD may form a light source of each of the pixels PXL.

Each of the pixels PXL may include at least one light source, for example, the light emitting element LD illustrated in fig. 1, driven by a predetermined signal (e.g., a scan signal, a data signal, etc.) and/or a predetermined power source (e.g., a first driving power source, a second driving power source, etc.). However, the type of the light emitting element LD that can be used as the light source of each of the pixels PXL is not limited thereto.

The driver may supply a predetermined signal and a predetermined power source to each pixel PXL through the line part, thereby controlling the driving of the pixels PXL. The driver may include a scan driver, a light emitting driver, a data driver, and a timing controller.

Fig. 4 is a schematic circuit diagram illustrating an electrical connection relationship between components included in the pixel illustrated in fig. 3 according to an embodiment.

For example, fig. 4 illustrates an electrical connection relationship among components included in the pixel PXL that can be applied to the active display device according to the embodiment. However, the types of components included in the pixel PXL to which the embodiment can be applied are not limited thereto.

In fig. 4, the components included in each of the pixels PXL shown in fig. 3 and the area where the components are disposed are referred to as a pixel PXL.

Referring to fig. 1 to 4, a pixel PXL (hereinafter, referred to as a "pixel") may include a light emitting cell EMU generating light of luminance corresponding to a data signal. The pixel PXL may also optionally include a pixel circuit PXC for driving the light emitting cell EMU.

According to an embodiment, the light emitting unit EMU may include the light emitting elements LD electrically connected in parallel between a first power line PL1 and a second power line PL2, the first power line PL1 being applied with the voltage of the first driving power VDD, and the second power line PL2 being applied with the voltage of the second driving power VSS. For example, the light emitting unit EMU may include a first electrode EL1 (or "first alignment electrode") electrically connected to a first driving power supply VDD via the pixel circuit PXC and a first power supply line PL1, a second electrode EL2 (or "second alignment electrode") electrically connected to a second driving power supply VSS via a second power supply line PL2, and a light emitting element LD electrically connected in parallel in the same direction between the first electrode EL1 and the second electrode EL 2. In an embodiment, the first electrode EL1 may be an anode electrode and the second electrode EL2 may be a cathode electrode.

Each of the light emitting elements LD included in the light emitting unit EMU may include one end electrically connected to the first driving power source VDD through the first electrode EL1 and the other end electrically connected to the second driving power source VSS through the second electrode EL 2. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set to a high potential power supply, and the second driving power supply VSS may be set to a low potential power supply. In this case, during the light emission period of the pixel PXL, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be equal to or greater than the threshold voltage of the light emitting element LD.

As described above, the respective light emitting elements LD electrically connected in parallel in the same direction (for example, the forward direction) between the first electrode EL1 and the second electrode EL2 to which voltages of different potentials are respectively supplied can form (or configure) the respective effective light sources. Such effective light sources may be collected to form the light emitting unit EMU of the pixel PXL.

The light emitting element LD of the light emitting cell EMU may emit light with a luminance corresponding to the driving current supplied through the corresponding pixel circuit PXC. For example, the pixel circuit PXC may supply a driving current corresponding to a gray value of corresponding frame data to the light emitting cell EMU during each frame period. The driving current supplied to the light emitting unit EMU may be shunted and flow to each of the light emitting elements LD. Accordingly, each of the light emitting elements LD may emit light with a luminance corresponding to a current flowing through the light emitting element LD, and thus the light emitting unit EMU may emit light with a luminance corresponding to a driving current.

An embodiment in which the ends of the light emitting elements LD are connected in the same direction between the first driving power source VDD and the second driving power source VSS is illustrated, but the disclosure is not limited thereto. According to the embodiment, the light emitting unit EMU may further include at least one ineffective light source, for example, a reverse light emitting element LDr, in addition to the light emitting element LD forming each effective light source. The reverse light emitting element LDr may be electrically connected in parallel between the first electrode EL1 and the second electrode EL2 together with the light emitting element LD forming an effective light source, and may be electrically connected between the first electrode EL1 and the second electrode EL2 in the opposite direction to the light emitting element LD. The reverse light emitting element LDr may maintain an inactivated state even if a predetermined driving voltage (e.g., a driving voltage of a forward direction) is applied between the first electrode EL1 and the second electrode EL2, and thus a current does not substantially flow through the reverse light emitting element LDr.

The pixel circuit PXC may be electrically connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, in the case where the pixels PXL are disposed in the ith row (i is a natural number) and the jth column (j is a natural number) of the display area DA, the pixel circuits PXC of the pixels PXL may be electrically connected to the ith scanning line Si and the jth data line Dj of the display area DA. The pixel circuit PXC may be electrically connected to the ith control line CLi and the jth sensing line sensj of the display area DA.

The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst.

A first terminal of the second transistor T2 (switching transistor) may be electrically connected to the j-th data line Dj, and a second terminal of the second transistor T2 (switching transistor) may be electrically connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 may be different terminals. For example, in the case where the first terminal is a source electrode, the second terminal may be a drain electrode. The gate electrode of the second transistor T2 may be electrically connected to the ith scan line Si.

The second transistor T2 is turned on in a case where a scan signal of a voltage at which it can be turned on is supplied from the scan line Si to the second transistor T2 to electrically connect the j-th data line Dj and the first node N1 to each other. In this case, the data signal of the corresponding frame may be supplied to the jth data line Dj, and thus the data signal may be transmitted to the first node N1. The data signal transmitted to the first node N1 may be stored in the storage capacitor Cst.

A first terminal of the first transistor T1 (driving transistor) may be electrically connected to the first driving power source VDD, and a second terminal may be electrically connected to the first electrode EL1 of each of the light emitting elements LD. A gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control the amount of driving current supplied to the light emitting element LD corresponding to the voltage of the first node N1.

The third transistor T3 may be electrically connected between the first transistor T1 and the j-th sensing line SENj. For example, a first terminal of the third transistor T3 may be electrically connected to a second terminal (e.g., a source electrode) of the first transistor T1 that is electrically connected to the first electrode EL1, and a second terminal of the third transistor T3 may be electrically connected to the j-th sensing line SENj. A gate electrode of the third transistor T3 may be electrically connected to the ith control line CLi. The third transistor T3 may be turned on by a control signal supplied to a gate-on voltage of the ith control line CLi during a predetermined sensing period to electrically connect the jth sensing line SENj and the first transistor T1 to each other.

The sensing period may be a period for extracting characteristic information (e.g., a threshold voltage of the first transistor T1, etc.) of each of the pixels PXL disposed in the display area DA.

An electrode of the storage capacitor Cst may be electrically connected to the first driving power source VDD, and the other electrode may be electrically connected to the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal supplied to the first node N1, and maintain the charged voltage until the data signal of the next frame is supplied to the storage capacitor Cst.

Fig. 4 illustrates an embodiment in which all of the first to third transistors T1 to T3 are N-type transistors, but the disclosure is not limited thereto. For example, at least one of the first to third transistors T1 to T3 described above may be changed to a P-type transistor. Fig. 4 shows an embodiment in which the light emitting cell EMU is connected between the pixel circuit PXC and the second driving power supply VSS, but the light emitting cell EMU may be connected between the first driving power supply VDD and the pixel circuit PXC.

The structure of the pixel circuit PXC may be variously changed. For example, the pixel circuit PXC may further include at least one transistor element (such as a transistor element for initializing the first node N1 and/or a transistor element for controlling the light emission time of the light emitting element LD) or other circuit elements (such as a boosting capacitor for boosting the voltage of the first node N1).

Fig. 4 illustrates an embodiment in which all of the light emitting elements LD forming each light emitting unit EMU are electrically connected in parallel, but the disclosure is not limited thereto. According to an embodiment, the light emitting unit EMU may include at least one series stage including the light emitting elements LD electrically connected in parallel to each other. For example, the light emitting unit EMU may be configured in a series/parallel hybrid structure.

The structure that can be applied to the disclosed pixel PXL is not limited to the embodiment shown in fig. 4, and the corresponding pixel PXL may have various structures. For example, each pixel PXL may be configured inside a passive light emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and the end portions of the light emitting elements LD included in the light emitting cells EMU may be directly connected to the ith scan line Si, the jth data line Dj, the first power line PL1 to which the first driving power supply VDD is applied, the second power line PL2 to which the second driving power supply VSS is applied, a predetermined control line, and the like.

Fig. 5 is a plan view schematically illustrating one of the pixels illustrated in fig. 3, fig. 6 is a schematic plan view illustrating only first and second electrodes and a light emitting element in the pixel of fig. 5, fig. 7 is a schematic cross-sectional view taken along line I-I 'of fig. 5, fig. 8 is a schematic cross-sectional view taken along line II-II' of fig. 5, fig. 9 and 10 are schematic cross-sectional views taken along line I-I 'of fig. 5 illustrating implementations of the first and second electrodes of fig. 7 according to another embodiment, and fig. 11 is a schematic cross-sectional view illustrating implementations of the first and second electrodes of fig. 7 according to another embodiment and is a cross-sectional view taken along line I-I' of fig. 5.

In fig. 5, a transistor T (see fig. 7) electrically connected to the light emitting element LD and a signal line electrically connected to the transistor T are omitted for convenience.

In fig. 5 to 11, the pixels PXL are simplified and shown, such as showing each electrode as a single-film electrode and each insulating layer as a single-film insulating layer, but the disclosure is not limited thereto.

In an embodiment, "connected" between two components may refer to electrical and/or physical connections.

In the embodiment, for convenience of description, a lateral direction (or a horizontal direction) on a plane is denoted as a first direction DR1, a longitudinal direction (or a vertical direction) on a plane is denoted as a second direction DR2, and a thickness direction of the substrate SUB on a cross section is denoted as a third direction DR 3.

Referring to fig. 1 to 11, a display device according to an embodiment may include pixels PXL disposed on a substrate SUB.

The substrate SUB may include a transparent insulating material and may transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

The flexible substrate may be one of a film substrate and a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

In the manufacturing process of the display device, the material applied to the substrate SUB may have resistance (or heat resistance) to high process temperatures.

The substrate SUB may include a display area DA including a pixel area PXA in which each pixel PXL is disposed and a non-display area NDA disposed around the display area DA (or adjacent to the display area DA).

The pixels PXL may be arranged in a matrix and/or stripe form in a pixel row extending along the first direction DR1 and a pixel column extending over the second direction DR2 different from the first direction DR 1. For example, the second direction DR2 crosses the first direction DR1 in the display area DA on the substrate SUB, but the disclosure is not limited thereto. According to an embodiment, the pixels PXL may be disposed on the substrate SUB in various arrangements in the display area DA.

The pixel area PXA in which each pixel PXL is disposed (or arranged) may include a light-emitting area in which light is emitted and a peripheral area adjacent to (or surrounding the periphery of) the light-emitting area. Here, the peripheral region may include a non-light emitting region in which light is not emitted.

Line portions electrically connected to the pixels PXL may be positioned on the substrate SUB. The line part may include a signal line transmitting a predetermined signal (or a predetermined voltage) to each pixel PXL. The signal lines may include an ith scan line Si transmitting a scan signal to each pixel PXL, a jth data line Dj transmitting a data signal to each pixel PXL, and a first power line PL1 and a driving voltage line DVL transmitting a driving power to each pixel PXL. According to an embodiment, the line part may further include a light emission control line transmitting a light emission control signal to each pixel PXL. According to another embodiment, the line part may further include a sensing line and a control line connected to each pixel PXL.

Each pixel PXL may include a pixel circuit layer PCL disposed on the substrate SUB and including a pixel circuit PXC and a display element layer DPL including a light emitting element LD. The light emitting element LD may be located in the pixel area PXA of each pixel PXL.

For convenience, the pixel circuit layer PCL is described first, and then the display element layer DPL is described.

The pixel circuit layer PCL may include a buffer layer BFL, a pixel circuit PXC, and a passivation layer PSV. The pixel circuit layer PCL may include a second electrode EL 2.

The buffer layer BFL may prevent impurities from diffusing into the transistors T included in the pixel circuit PXC. The buffer layer BFL may be an inorganic insulating film including an inorganic material. The buffer layer BFL may include, for example, silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Silicon oxynitride (SiO)_xN_y) And aluminum oxide (AlO)_x) At least one of metal oxides of (a). The buffer layer BFL may be provided as a single film, but may also be provided as a multi-film of at least two films. In the case where the buffer layer BFL is provided as a multi-film, each layer may be formed of the same material or different materials. The buffer layer BFL may be omitted depending on the material of the substrate SUB, process conditions, etc.

The pixel circuit PXC may include a storage capacitor Cst and at least one transistor T. The transistor T may include a driving transistor Tdr controlling a driving current of the light emitting element LD and a switching transistor Tsw electrically connected to the driving transistor Tdr. However, the disclosure is not limited thereto, and the pixel circuit PXC may include circuit elements performing other functions in addition to the driving transistor Tdr and the switching transistor Tsw. In the following embodiments, the driving transistor Tdr and the switching transistor Tsw are collectively referred to as one transistor T or a plurality of transistors T. The driving transistor Tdr may have the same configuration as the first transistor T1 described with reference to fig. 4, and the switching transistor Tsw may have the same configuration as the second transistor T2 described with reference to fig. 4.

Each of the driving transistor Tdr and the switching transistor Tsw may include a semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be any one of the source electrode and the drain electrode, and the second terminal DE may be the other electrode. For example, in the case where the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

The semiconductor pattern SCL may be disposed and/or formed on the buffer layer BFL. The semiconductor pattern SCL may include a first contact region contacting the first terminal SE and a second contact region contacting the second terminal DE. The region between the first contact region and the second contact region may be a channel region. The channel region may overlap with the gate electrode GE of the corresponding transistor T. The semiconductor pattern SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, or the like. For example, the channel region may be a semiconductor pattern that is not doped with impurities, and may be an intrinsic semiconductor. The first and second contact regions may be semiconductor patterns doped with impurities.

The gate electrode GE may be disposed and/or formed on the gate insulating layer GI to correspond to a channel region of the semiconductor pattern SCL. The gate electrode GE may be disposed on the gate insulating layer GI and overlap a channel region of the semiconductor pattern SCL. The gate electrode GE may be formed as a single film formed of at least one selected individually from copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, or a mixture thereof, or as a double or multi-film structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) as a low resistance material to reduce line resistance.

The gate insulating layer GI may be an inorganic insulating film including an inorganic material. For example, the gate insulating layer GI may include a material such as silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Silicon oxynitride (SiON) and AlO_xAt least one of metal oxides of (a). However, the material of the gate insulating layer GI is not limited to the above embodiment. According to an embodiment, the gate insulating layer GI may be formed of an organic insulating film including an organic material. The gate insulating layer GI may be provided as a single film or a multi-film of at least two films.

The first terminal SE and the second terminal DE may contact the first contact region and the second contact region of the semiconductor pattern SCL through contact holes sequentially passing through the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2, respectively. For example, the first terminal SE may contact a first contact region of the semiconductor pattern SCL, and the second terminal DE may contact a second contact region of the semiconductor pattern SCL. Each of the first and second terminals SE and DE and the gate electrode GE may include the same material. Each of the first and second terminals SE and DE may include one or more materials selected from materials exemplified as a material of construction of the gate electrode GE.

The first interlayer insulating layer ILD1 and the gate insulating layer GI may include the same material. The first interlayer insulating layer ILD1 may include one or more materials selected from materials exemplified as a material of construction of the gate insulating layer GI.

A second interlayer insulating layer ILD2 may be disposed and/or formed on the first interlayer insulating layer ILD 1. The second interlayer insulating layer ILD2 may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. According to an embodiment, the second interlayer insulating layer ILD2 and the first interlayer insulating layer ILD1 may include the same material, but the disclosure is not limited thereto. The second interlayer insulating layer ILD2 may be provided as a single film or a multi-film of at least two films.

In the above-described embodiment, the first terminal SE and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw are described as separate electrodes electrically connected to the semiconductor pattern SCL through contact holes sequentially passing through the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2, but the disclosure is not limited thereto. According to an embodiment, the first terminal SE of each of the driving transistor Tdr and the switching transistor Tsw may be a first contact region adjacent to a channel region of the corresponding semiconductor pattern SCL, and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw may be a second contact region adjacent to a channel region of the corresponding semiconductor pattern SCL. In this case, the second terminal DE of the driving transistor Tdr may be electrically connected to the light emitting element LD of the corresponding pixel PXL by a separate connection means (such as a bridge electrode).

In an embodiment, the transistor T included in the pixel circuit PXC may be formed as a low temperature polysilicon thin film transistor (LTPS TFT), but the disclosure is not limited thereto. According to an embodiment, the transistor T included in the pixel circuit PXC may be composed of or include an oxide semiconductor thin film transistor. The case where the transistor T is a thin film transistor having a top gate structure is described as an example, but the disclosure is not limited thereto. The structure of the transistor T may be variously changed.

The storage capacitor Cst may include a lower electrode LE disposed on the gate insulating layer GI and an upper electrode UE disposed on the first interlayer insulating layer ILD1 and overlapping the lower electrode LE.

The gate electrode GE of each of the lower electrode LE, the driving transistor Tdr, and the switching transistor Tsw may be disposed on the same layer and may include the same material. The lower electrode LE may be integrated with the gate electrode GE of the driving transistor Tdr. In this case, the lower electrode LE may be considered as a region of the gate electrode GE of the driving transistor Tdr. According to the embodiment, the lower electrode LE may be disposed in a separate configuration from the gate electrode GE of the driving transistor Tdr (or may not be integrated with the gate electrode GE of the driving transistor Tdr). In this case, the lower electrode LE and the gate electrode GE of the driving transistor Tdr may be electrically connected by a separate connection means.

The upper electrode UE may overlap or cover the lower electrode LE. The capacitance of the storage capacitor Cst may be increased by increasing an overlapping area of the upper electrode UE and the lower electrode LE. The upper electrode UE may be electrically connected to a first power line PL 1. The storage capacitor Cst may overlap the second interlayer insulating layer ILD2 or be covered by the second interlayer insulating layer ILD 2.

The pixel circuit layer PCL may include a driving voltage line DVL disposed and/or formed on the second interlayer insulating layer ILD 2. The driving voltage line DVL and the second power line PL2 described with reference to fig. 4 may have the same configuration. The driving voltage line DVL may be electrically connected to the second driving power source VSS. Accordingly, the voltage of the second driving power source VSS may be applied to the driving voltage line DVL. The pixel circuit layer PCL may further include a first power line PL1 electrically connected to the first driving power supply VDD. Although not directly shown in the drawings, the first power supply line PL1 and the driving voltage line DVL may be disposed on the same layer or different layers.

Each of the first power line PL1 and the driving voltage line DVL may include a conductive material. For example, each of the first power line PL1 and the driving voltage line DVL may be formed as a single film formed of at least one selected individually from copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, or a mixture thereof, or as a double or multi-film structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) as a low resistance material that reduces line resistance. For example, each of the first power supply line PL1 and the driving voltage line DVL may be formed of or include two films in which a titanium (Ti) layer and a copper (Cu) layer are sequentially stacked.

The third interlayer insulating layer ILD3 may be disposed and/or formed on the transistor T and the driving voltage line DVL.

The third interlayer insulating layer ILD3 and the first and second interlayer insulating layers ILD1 and ILD2 may include the same material, but the disclosure is not limited thereto. For example, the third interlayer insulating layer ILD3 may be an inorganic insulating film including an inorganic material. The third interlayer insulating layer ILD3 may include a first contact hole CH1 exposing the second terminal DE of the driving transistor Tdr and a second contact hole CH2 exposing a region of the driving voltage line DVL to the outside.

The second electrode EL2 may be disposed and/or formed on the third interlayer insulating layer ILD 3.

The second electrode EL2 may be formed of one of the conductive layers included in the pixel circuit layer PCL. For example, in the case where the pixel circuit layer PCL includes a first conductive layer disposed on the gate insulating layer GI, a second conductive layer disposed on the first interlayer insulating layer ILD1, a third conductive layer disposed on the second interlayer insulating layer ILD2, and a fourth conductive layer disposed on the third interlayer insulating layer ILD3, the second electrode EL2 may be the fourth conductive layer. In this case, the gate electrode GE of the transistor T may be a first conductive layer, the upper electrode UE of the storage capacitor Cst may be a second conductive layer, and the driving voltage line DVL may be a third conductive layer.

The second electrode EL2 may be electrically and/or physically connected to the driving voltage line DVL through a second contact hole CH2 passing through the third interlayer insulating layer ILD 3. Accordingly, the second electrode EL2 may be electrically connected to the driving voltage line DVL applied with the voltage of the second driving power source VSS.

The second electrode EL2 may be formed of a conductive material having a predetermined reflectivity. The conductive material may include an opaque metal that facilitates reflection of light emitted from the light emitting element LD in an image display direction (e.g., a front direction) of the display device. For example, the second electrode EL2 and the driving voltage line DVL may include the same material. The second electrode EL2 may include one or more materials selected from materials exemplified as the material of construction of the driving voltage line DVL.

In the embodiment, the second electrode EL2 may be used as an alignment electrode for aligning the light emitting element LD together with some components (such as the first electrode EL1 included in the display element layer DPL). After the alignment of the light emitting element LD, the second electrode EL2 may be used as a driving electrode for driving the light emitting element LD together with the first electrode EL 1.

The passivation layer PSV may be disposed and/or formed on the second electrode EL 2.

The passivation layer PSV may include an organic insulating film, an inorganic insulating film, or an organic insulating film disposed on the inorganic insulating film. For example, the inorganic insulating film may include, for example, silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Silicon oxynitride (SiO)_xN_y) And aluminum oxide (AlO)_x) At least one of metal oxides of (a). For example, the organic insulating film may include at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

The passivation layer PSV may include a first contact hole CH1 corresponding to the first contact hole CH1 passing through the third interlayer insulating layer ILD 3. The passivation layer PSV may include an opening OPN exposing a region of the second electrode EL 2.

The display element layer DPL may be disposed and/or formed on the passivation layer PSV.

The display element layer DPL may include a bank BNK, a first electrode EL1, a light emitting element LD, first and second contact electrodes CNE1 and CNE2, and first to third insulating layers INS1 to INS 3.

The bank BNK may be a structure that defines (or partitions) a pixel area PXA or a light emitting area of each of the corresponding pixel PXL and pixels PXL adjacent to the corresponding pixel PXL, and may be, for example, a pixel defining film. The bank BNK may include at least one light blocking material and/or a reflective material to prevent a light leakage defect in which light (or light rays) leaks between the corresponding pixel PXL and the pixel PXL adjacent thereto.

The first electrode EL1 may extend in a direction such as the second direction DR 2. The first electrode EL1 may be electrically connected to some configurations or components included in the pixel circuit layer PCL of the corresponding pixel PXL, for example, the driving transistor Tdr, through the first contact hole CH1 sequentially passing through the passivation layer PSV and the third interlayer insulating layer ILD 3.

The first electrode EL1 may be formed of a material having a predetermined reflectance so that light emitted from each of the light emitting elements LD travels in an image display direction of the display device. The first electrode EL1 may be formed of a conductive material having a predetermined reflectivity. The conductive material may include an opaque metal that facilitates reflection of light emitted from the light emitting element LD in an image display direction of the display device. For example, the opaque metal may include metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. According to an embodiment, the first electrode EL1 may include a transparent conductive material. The transparent conductive material may include a conductive oxide such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), Indium Gallium Zinc Oxide (IGZO), and Indium Tin Zinc Oxide (ITZO), a conductive polymer such as poly (3, 4-ethylenedioxythiophene) (PEDOT), and the like. In the case where the first electrode EL1 includes a transparent conductive material, a separate conductive layer formed of an opaque metal for reflecting light emitted from the light emitting element LD in the image display direction of the display device may be added. However, the material of the first electrode EL1 is not limited to the above.

The first electrode EL1 and the second electrode EL2 formed of the fourth conductive layer of the pixel circuit layer PCL may include the same material. Each of the first electrode EL1 of the display element layer DPL and the second electrode EL2 of the pixel circuit layer PCL may be provided and/or formed as a single film, but the disclosure is not limited thereto. According to an embodiment, each of the first electrode EL1 and the second electrode EL2 may be disposed and/or formed as a multi-film in which at least two materials of a metal, an alloy, a conductive oxide, and a conductive polymer are stacked. Each of the first electrode EL1 and the second electrode EL2 may be formed of a multi-film of at least two films to minimize or reduce distortion caused by signal delay when a signal (or voltage) is transmitted to an end of each of the light emitting elements LD. For example, each of the first electrode EL1 and the second electrode EL2 may be formed of a multi-film in which an Indium Tin Oxide (ITO) layer, a silver (Ag) layer, and an Indium Tin Oxide (ITO) layer are sequentially stacked.

In a cross-sectional view, the first electrode EL1 and the second electrode EL2 may be spaced apart from each other with the passivation layer PSV between the first electrode EL1 and the second electrode EL 2. The first electrode EL1 and the second electrode EL2 may be spaced apart from each other at a predetermined interval d (or distance) in the first direction DR1 in a plan view. The width w1 of the first electrode EL1 in the first direction DR1 and the width w2 of the second electrode EL2 in the first direction DR1 may be equal to each other in plan view and cross-sectional view, but the disclosure is not limited thereto. According to an embodiment, the width w2 of the second electrode EL2 in the first direction DR1 may be greater than the width w1 of the first electrode EL1 in the first direction DR 1.

As described above, the first electrode EL1 may be connected to some configurations or components of the pixel circuit layer PCL through the first contact hole CH1, and the second electrode EL2 may be connected to some configurations of the pixel circuit layer PCL through the second contact hole CH 2.

Each of the first electrode EL1 and the second electrode EL2 can serve as an alignment electrode (or an alignment line) for alignment of the light emitting element LD by receiving a predetermined alignment signal (or an alignment voltage) from a corresponding partial configuration of the pixel circuit layer PCL. For example, the first electrode EL1 may receive a first alignment signal (or a first alignment voltage) from some configurations of the pixel circuit layer PCL and may serve as a first alignment electrode (or a first alignment line), and the second electrode EL2 may receive a second alignment signal (or a second alignment voltage) from other configurations of the pixel circuit layer PCL and may serve as a second alignment electrode (or a second alignment line). Here, the first alignment signal (or alignment voltage) and the second alignment signal (or alignment voltage) may be signals having a voltage difference and/or a phase difference to the extent that the light emitting element LD may be aligned between the first electrode EL1 and the second electrode EL 2. At least one alignment signal (or alignment voltage) of the first alignment signal (or alignment voltage) and the second alignment signal (or alignment voltage) may be an AC signal (or voltage), but the disclosure is not limited thereto.

After the light emitting element LD is aligned in the pixel area PXA of each pixel PXL, in order to individually (or independently) drive each pixel PXL, a portion of the first electrode EL1 positioned between the adjacent pixels PXL in one direction (for example, in the first direction DR1 or the second direction DR 2) may be removed.

After the light emitting element LD is aligned in the pixel area PXA, the first electrode EL1 and the second electrode EL2 may serve as driving electrodes for driving the light emitting element LD. The first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

Each of the light emitting elements LD may be a micro light emitting diode using an inorganic crystal structure material, for example, to a size of the order of nanometer to micrometer. Each of the light emitting elements LD may be a micro light emitting diode manufactured by an etching method or a growth method.

At least two to several tens of light emitting elements LD may be aligned and/or disposed in the pixel area PXA of each pixel PXL, but the number of light emitting elements LD is not limited thereto. According to the embodiment, the number of light emitting elements LD aligned and/or disposed in the pixel area PXA may be variously changed.

Each of the light emitting elements LD may emit any one of color light and white light. Each of the light emitting elements LD may be aligned on the first insulating layer INS1 between the first electrode EL1 and the second electrode EL2 such that an extending direction or direction of the length L is parallel to the first direction DR1 in a plan view or a sectional view. The light emitting element LD may be ejected in a solution, and may be input to the pixel area PXA of each pixel PXL.

The light emitting element LD may be input to the pixel area PXA of each pixel PXL by an ink jet printing method, a slit coating method, or other various methods. For example, the light emitting element LD may be mixed with a volatile solvent and supplied to the pixel area PXA by an inkjet printing method or a slit coating method. In this case, in the case where an alignment signal corresponding to each of the first electrode EL1 and the second electrode EL2 provided in the pixel area PXA is applied, an electric field may be formed between the first electrode EL1 and the second electrode EL 2. Accordingly, the light emitting element LD may be aligned between the first electrode EL1 and the second electrode EL 2.

After the alignment of the light emitting element LD, the light emitting element LD may be finally aligned and/or disposed in the pixel area PXA of each pixel PXL by volatilizing the solvent or otherwise removing the solvent.

The light emitting element LD may overlap the first electrode EL1 and the second electrode EL2 in a plan view and a sectional view. For example, in a plan view and a sectional view, one end portion of each of the light emitting elements LD may overlap the first electrode EL1, and the other end portion of each of the light emitting elements LD may overlap the second electrode EL 2. The light emitting element LD may overlap each of the first electrode EL1 and the second electrode EL2 in a plan view, and may be arranged on the first insulating layer INS1 to overlap a spaced region between the first electrode EL1 and the second electrode EL 2.

The first insulating layer INS1 may include an inorganic insulating film formed of an inorganic material or an organic insulating film formed of an organic material. The first insulating layer INS1 may be formed of an inorganic insulating film that is advantageous for protecting the light emitting element LD from the pixel circuit layer PCL of each pixel PXL. For example, the first insulating layer INS1 may include a material such as silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Silicon oxynitride (SiO)_xN_y) And aluminum oxide (AlO)_x) At least one of metal oxides of (1)But the disclosure is not limited thereto. According to an embodiment, the first insulating layer INS1 may be formed of an organic insulating film that facilitates planarization of the support surface of the light emitting element LD.

The first insulating layer INS1 may include a first opening OPN1 exposing a region of the first electrode EL1 and a second opening OPN2 exposing a region of the second electrode EL 2. The second opening OPN2 may correspond to the opening OPN of the passivation layer PSV. The first electrode EL1 may directly contact the first contact electrode CNE1 through the first opening OPN1 and may be electrically connected to the first contact electrode CNE1, and the second electrode EL2 may directly contact the second contact electrode CNE2 through the second opening OPN2 of the first insulating layer INS1 and the opening OPN of the passivation layer PSV and may be electrically connected to the second contact electrode CNE 2. The first insulating layer INS1 may overlap the remaining region except for the region of each of the first and second electrodes EL1 and EL2 exposed through the openings (e.g., the first opening OPN1 and the opening OPN), or cover the remaining region except for the region of each of the first and second electrodes EL1 and EL2 exposed through the openings (e.g., the first opening OPN1 and the opening OPN).

The second insulating layer INS2 may be disposed and/or formed on each of the light emitting elements LD. The second insulating layer INS2 may be disposed and/or formed on the light emitting elements LD to partially cover or overlap an outer circumferential surface (or surface) of each of the light emitting elements LD to expose an end portion of each of the light emitting elements LD to the outside. The second insulating layer INS2 may be formed as an independent insulating pattern in the pixel area PXA of each pixel PXL, but the disclosure is not limited thereto.

The second insulating layer INS2 may be formed of a single film or a plurality of films, and may include an inorganic insulating film containing at least one inorganic material or an organic insulating film containing at least one organic material. The second insulating layer INS2 may include an inorganic insulating film that is advantageous for protecting each active layer 12 of the light emitting element LD from external oxygen, moisture, and the like. However, the disclosure is not limited thereto. The second insulating layer INS2 may be formed of an organic insulating film including an organic material according to design conditions of a display device to which the light emitting element LD is applied, or the like. By forming the second insulating layer INS2 on the light emitting element LD after the alignment of the light emitting element LD is completed in each pixel area PXA of the pixel PXL, the light emitting element LD can be prevented from deviating from the alignment position.

Due to the second insulating layer INS2 formed on the light emitting elements LD, the active layer 12 of each of the light emitting elements LD may not contact the external conductive material. The second insulating layer INS2 may overlap only a portion of the outer circumferential surface (or surface) of each of the light emitting elements LD to expose an end portion of each of the light emitting elements LD to the outside.

The first contact electrode CNE1 may be disposed on the first electrode EL1 to be electrically connected to the first electrode EL1 through the first opening OPN1 of the first insulating layer INS 1. According to an embodiment, in the case where a cap layer (not shown) is disposed on the first electrode EL1, the first contact electrode CNE1 may be disposed on the cap layer and may be electrically connected to the first electrode EL1 through the cap layer. The above cap layer may protect the first electrode EL1 from defects and the like generated during the manufacturing process of the display device, and may also enhance adhesion between the first electrode EL1 and the pixel circuit layer PCL positioned below the first electrode EL 1. The capping layer may include a transparent conductive material (or material), such as Indium Zinc Oxide (IZO).

The first contact electrode CNE1 may be disposed and/or formed on one end portion of each of the light emitting elements LD to be electrically connected to one end portion of each of the light emitting elements LD. Accordingly, the first electrode EL1 and one end portion of each of the light emitting elements LD may be electrically connected to each other through the first contact electrode CNE 1.

The second contact electrode CNE2 may be disposed on the second electrode EL2 and may be electrically connected to the second electrode EL2 through the second opening OPN2 of the first insulating layer INS1 and the opening OPN of the passivation layer PSV. According to an embodiment, in the case where a cap layer is disposed on the second electrode EL2, the second contact electrode CNE2 may be disposed on the cap layer and electrically connected to the second electrode EL2 through the cap layer.

The second contact electrode CNE2 may be disposed and/or formed on the other end portion of each of the light emitting elements LD, and may be electrically connected to the other end portion of each of the light emitting elements LD. Therefore, the second electrode EL2 and the other end portion of each of the light-emitting elements LD may be electrically connected to each other through the second contact electrode CNE 2.

The first contact electrode CNE1 and the second contact electrode CNE2 may be formed of various transparent conductive materials so that light emitted from each of the light emitting elements LD and reflected by the first electrode EL1 and the second electrode EL2 travels in the image display direction of the display device without loss. For example, the first and second contact electrodes CNE1 and CNE2 may include at least one of various transparent conductive materials (or materials) including Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), and the like, and may be substantially transparent or semi-transparent to satisfy a predetermined transmittance (or transmissivity). However, the materials of the first and second contact electrodes CNE1 and CNE2 are not limited to the above-described embodiments. According to an embodiment, the first and second contact electrodes CNE1 and CNE2 may be formed of various opaque conductive materials (or materials). The first contact electrode CNE1 and the second contact electrode CNE2 may be formed of a single film or multiple films.

In a plan view, each of the first and second contact electrodes CNE1 and CNE2 may have a stripe shape extending in the second direction DR2, but the disclosure is not limited thereto. According to the embodiment, the shapes of the first and second contact electrodes CNE1 and CNE2 may be variously changed within a range in which the first and second contact electrodes CNE1 and CNE2 are stably electrically connected to each of the light emitting elements LD. The shapes of the first and second contact electrodes CNE1 and CNE2 may be variously changed in consideration of the connection relationship with the electrodes disposed under the first and second contact electrodes CNE1 and CNE 2.

The first and second contact electrodes CNE1 and CNE2 may be spaced apart from each other in the first direction DR 1. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may be spaced apart at predetermined intervals on the light emitting element LD by the second insulating layer INS 2. The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer and formed through the same process. However, the disclosure is not limited thereto, and the first and second contact electrodes CNE1 and CNE2 may be disposed on different layers and formed through different processes according to an embodiment. In this case, as shown in fig. 11, the auxiliary insulating layer AUINS may be disposed and/or formed between the first and second contact electrodes CNE1 and CNE 2. The auxiliary insulating layer AUINS and the first insulating layer INS1 may include the same material. The auxiliary insulating layer AUINS may include one or more materials selected from materials exemplified as the material of construction of the first insulating layer INS 1. For example, the auxiliary insulating layer AUINS may be an inorganic insulating film including an inorganic material.

The third insulating layer INS3 may be disposed and/or formed on the first and second contact electrodes CNE1 and CNE 2. The third insulating layer INS3 may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. For example, the third insulating layer INS3 may have a structure in which at least one inorganic insulating film or at least one organic insulating film is alternately stacked. The third insulating layer INS3 may overlap or cover the entire display element layer DPL to block water, moisture, or the like from entering the display element layer DPL including the light emitting element LD.

According to an embodiment, the display element layer DPL may optionally include an optical layer in addition to the third insulating layer INS 3. Here, the optical layer may include a color conversion layer including color conversion particles that convert light emitted from the light emitting elements LD into light having a specific color.

As described above, the first electrode EL1 and the second electrode EL2 may be disposed on different layers and may be spaced apart from each other, and an insulating layer (e.g., a passivation layer PSV) included in the pixel circuit layer PCL is interposed between the first electrode EL1 and the second electrode EL 2. For example, the first electrode EL1 may be disposed on the second electrode EL2 with the passivation layer PSV interposed between the first electrode EL1 and the second electrode EL 2. In this case, the first electrode EL1 and the second electrode EL2 may not overlap. In the case where the first electrode EL1 and the second electrode EL2 are separated and disposed on different layers, it is possible to minimize or reduce a short defect between the first electrode EL1 and the second electrode EL2, which may occur due to a space limitation in the manufacturing step of each pixel PXL (for example, a Critical Dimension (CD) of an electrode included in each pixel PXL (critical dimension is a line width of each of the electrodes or a width of a gap between the electrodes)) or the like.

The interval d (or distance) between the first electrode EL1 and the second electrode EL2 may be equal to or less than the length L of each of the light emitting elements LD. However, the disclosure is not limited thereto, and the interval d (or distance) between the first electrode EL1 and the second electrode EL2 may be larger than the length L of each of the light emitting elements LD. The interval d (or distance) between the first electrode EL1 and the second electrode EL2 may be less than about 4 μm. For example, the interval d (or distance) between the first electrode EL1 and the second electrode EL2 may be about 2.5 μm, but the disclosure is not limited thereto.

As described above, in the case where the first electrode EL1 is separated from the second electrode EL2 and disposed on different layers, the interval d (or distance) between the first electrode EL1 and the second electrode EL2, which is designed in consideration of process margins such as the limit of the Critical Dimension (CD) (which is the line width of each of the electrodes or the width of the gap between the electrodes), or the like, can be further reduced, as compared with the pixel PXL of another embodiment in which the first electrode EL1 and the second electrode EL2 are formed on the same layer. Accordingly, the limit of the minimum interval d (or distance) between the first electrode EL1 and the second electrode EL2 may be reduced, and thus a display device having high resolution and fine pitch may be easily realized.

In the case where the interval d (or distance) between the first electrode EL1 and the second electrode EL2 is reduced, a larger (or stronger) electric field may be formed between the first electrode EL1 and the second electrode EL 2. Therefore, the number of misaligned light-emitting elements LD can be reduced by more effectively aligning the light-emitting elements LD between the first electrode EL1 and the second electrode EL 2. Therefore, the loss of the light emitting elements LD can be minimized or reduced, and the number of effective light emitting elements LD provided per unit area of each pixel PXL can be increased.

The embodiment in which the first electrode EL1 is provided to (or included in) the display element layer DPL and the second electrode EL2 is provided to (or included in) the pixel circuit layer PCL has been described above, but the disclosure is not limited thereto. According to an embodiment, the first electrode EL1 may be provided to (or included in) the pixel circuit layer PCL, and the second electrode EL2 may be provided to (or included in) the display element layer DPL. As an example, as shown in fig. 9, the first electrode EL1 may be disposed on the third interlayer insulating layer ILD3, and the second electrode EL2 may be disposed on the passivation layer PSV. In this case, the first electrode EL1 may be electrically connected to the driving transistor Tdr through a first contact hole CH1 passing through the third interlayer insulating layer ILD3, and the second electrode EL2 may be electrically connected to the driving voltage line DVL through a second contact hole CH2 sequentially passing through the third interlayer insulating layer ILD3 and the passivation layer PSV.

In the case where the first electrode EL1 is provided to the pixel circuit layer PCL, the first contact electrode CNE1 may be electrically connected to the first electrode EL1 through the first opening OPN1 of the first insulating layer INS1 and the opening OPN of the passivation layer PSV. In the case where the second electrode EL2 is provided to the display element layer DPL, the second contact electrode CNE2 may be electrically connected to the second electrode EL2 through the second opening OPN2 of the first insulating layer INS 1.

The embodiment in which one of the first electrode EL1 and the second electrode EL2 is provided to the display element layer DPL and the other electrode is provided to the pixel circuit layer PCL is described above, but the disclosure is not limited thereto. According to an embodiment, the first electrode EL1 and the second electrode EL2 may be provided to the pixel circuit layer PCL. In this case, the first electrode EL1 and the second electrode EL2 may be formed of two conductive layers disposed on two different layers among the first to fourth conductive layers included in the pixel circuit layer PCL with at least one insulating layer interposed therebetween. For example, as shown in fig. 10, the first electrode EL1 may be formed of a fourth conductive layer disposed on the third interlayer insulating layer ILD3, and the second electrode EL2 may be formed of a third conductive layer disposed on the second interlayer insulating layer ILD 2. In this case, the driving voltage line DVL may be formed of the second conductive layer disposed on the first interlayer insulating layer ILD 1. In this case, the first electrode EL1 may be electrically connected to the driving transistor Tdr through a first contact hole CH1 passing through the third interlayer insulating layer ILD3, and the second electrode EL2 may be electrically connected to the driving voltage line DVL through a second contact hole CH2 passing through the second interlayer insulating layer ILD 2. In the above-described embodiment, the case where the driving voltage line DVL is formed of the second conductive layer is described, but the disclosure is not limited thereto. According to an embodiment, the driving voltage line DVL may be formed of the third conductive layer and may be integrated with the second electrode EL 2.

In the case where the first electrode EL1 is formed of the fourth conductive layer of the pixel circuit layer PCL, the first contact electrode CNE1 may be electrically connected to the first electrode EL1 through the first opening OPN1 of the first insulating layer INS1 and the opening OPN of the passivation layer PSV. In the case where the second electrode EL2 is formed of the third conductive layer of the pixel circuit layer PCL, the second contact electrode CNE2 may be electrically connected to the second electrode EL2 through the second opening OPN2 of the first insulating layer INS1, the third opening OPN3 of the passivation layer PSV, and the fourth opening OPN4 of the third interlayer insulating layer ILD 3. Here, the fourth opening OPN4 of the third interlayer insulating layer ILD3 and the third opening OPN3 of the passivation layer PSV may correspond to the second opening OPN2 of the first insulating layer INS 1. The fourth opening OPN4 of the third interlayer insulating layer ILD3, the third opening OPN3 of the passivation layer PSV, and the second opening OPN2 of the first insulating layer INS1 may be formed through the same process, but the disclosure is not limited thereto, and the fourth opening OPN4 of the third interlayer insulating layer ILD3, the third opening OPN3 of the passivation layer PSV, and the second opening OPN2 of the first insulating layer INS1 may be formed through different processes.

In the case where the pixel circuit layer PCL includes a bottom metal layer (not shown) between the substrate SUB and the buffer layer BFL, the bottom metal layer may be disposed on the same layer as one of the first electrode EL1 and the second electrode EL2, and the other of the first electrode EL1 and the second electrode EL2 may be positioned on the one electrode with the buffer layer BFL interposed therebetween.

The embodiment in which the first electrode EL1 and the second electrode EL2 are disposed on different layers and spaced apart from each other at a predetermined interval d (or distance) when viewed in a plan view has been described above, but the disclosure is not limited thereto. According to an embodiment, the first electrode EL1 and the second electrode EL2 may be disposed on different layers, and at least one region may overlap in a plan view and a cross-sectional view. This is described below with reference to fig. 12 to 15.

Fig. 12 is a plan view schematically showing a pixel according to another embodiment, and fig. 13 is a schematic cross-sectional view taken along the line III-III' of fig. 12.

The pixel PXL shown in fig. 12 and 13 may have substantially the same or similar configuration as that of the pixel PXL of fig. 5 to 8 except that the first electrode EL1 and the second electrode EL2 are partially overlapped with each other.

Therefore, with respect to the pixel PXL of fig. 12 and 13, features different from those of the above-described embodiment are mainly described to avoid repetitive description.

Referring to fig. 1 to 4, 12, and 13, a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL may be disposed in the pixel area PXA of each pixel PXL.

The pixel circuit layer PCL may include at least one insulating layer, at least one transistor T, and a second electrode EL 2. The at least one insulating layer may include a buffer layer BFL, a gate insulating layer GI, first to third interlayer insulating layers ILD1 to ILD3, and a passivation layer PSV. The second electrode EL2 may be disposed on the third interlayer insulating layer ILD 3.

The display element layer DPL may include a bank BNK, a first electrode EL1, a light emitting element LD, first and second contact electrodes CNE1 and CNE2, and first to third insulating layers INS1 to INS 3.

The second electrode EL2 of the pixel circuit layer PCL and the first electrode EL1 of the display element layer DPL may overlap each other in plan view. For example, the first electrode EL1 and the second electrode EL2 may include a region OV where the first electrode EL1 and the second electrode EL2 overlap each other in a plan view (hereinafter referred to as an "overlapping region").

The overlap area OV may correspond to an area in which the light emitting element LD is positioned. For example, the overlap area OV may correspond to an area of the light emitting element LD in a plan view. The width of the overlap area OV in the first direction DR1 may be smaller or larger than the length L of each of the light emitting elements LD.

The width w1 of the first electrode EL1 in the first direction DR1 and the width w2 of the second electrode EL2 in the first direction DR1 may be similar or substantially equal to each other. However, the disclosure is not limited thereto. According to an embodiment, the width w2 of the second electrode EL2 in the first direction DR1 may be greater than the width w1 of the first electrode EL1 in the first direction DR 1.

As described above, in the case where at least a portion of the first electrode EL1 and the second electrode EL2, which are disposed on different layers with the passivation layer PSV interposed therebetween, are designed to overlap, it is possible to minimize or reduce a short defect between the first electrode EL1 and the second electrode EL2, which may occur due to space limitations or the like in the manufacturing step of each pixel PXL. In the case where the first electrode EL1 and the second electrode EL2 are overlapped with each other, a high resolution and fine pitches of the display device can be easily realized by more effectively using the pixel area PXA of each pixel PXL.

Fig. 14 is a plan view schematically showing a pixel according to still another embodiment, and fig. 15 is a schematic cross-sectional view taken along line IV-IV' of fig. 14.

The pixel PXL shown in fig. 14 and 15 may have substantially the same or similar configuration as that of the pixel PXL of fig. 12 and 13 except that the width w2 of the second electrode EL2 in the first direction DR1 is enlarged.

Therefore, with reference to the pixel PXL of fig. 14 and 15, features different from those of the above-described embodiment are mainly described to avoid repetitive description.

Referring to fig. 1 to 4, 14 and 15, the second electrode EL2 may have a width w2 in the first direction DR1 that is greater than a width w1 of the first electrode EL1 in the first direction DR1 and may be disposed under the first electrode EL 1.

The second electrode EL2 may be enlarged in the first direction DR1 to overlap with the remaining portion except for a portion of the first electrode EL1 in a plan view. For example, the second electrode EL2 may have a plate shape corresponding to a light emitting region of the pixel area PXA of each pixel PXL. In the embodiment, the shape of the second electrode EL2 may be changed in various forms within a range that does not directly or indirectly affect the configuration included in the pixel circuit layer PCL.

In the case where the second electrode EL2 is positioned below the first electrode EL1 between the pixel circuit layer PCL and the display element layer DPL and is enlarged into a plate shape, the second electrode EL2 may serve as a shielding member for blocking an electric field induced from the transistor T and a signal line connected to the transistor T. In the case where the second electrode EL2 is used as a shielding member, it is possible to prevent misalignment and/or malfunction of the light emitting element LD by minimizing or reducing interference of an electric field with alignment and/or driving of the light emitting element LD.

The second electrode EL2 may be formed of an opaque conductive material having a predetermined reflectance so that light emitted from the light emitting element LD travels in an image display direction of the display device. As described above, in the case where the second electrode EL2 is enlarged and provided in a plate shape, the overlapping area OV between the second electrode EL2 and the first electrode EL1 can be enlarged, and thus the second electrode EL2 can be used alone as a reflecting member that guides light emitted from the light emitting element LD in the image display direction of the display device. Therefore, by the second electrode EL2 having a relatively large area (or size) compared to the first electrode EL1, the amount of light emitted from the light-emitting element LD and traveling in the image display direction of the display device can be increased, and thus the light emission efficiency of each pixel PXL can be improved. In this case, the light emitting efficiency of each pixel PXL may be further improved by minimizing or reducing the loss of light emitted from the light emitting element LD by constructing or forming the first electrode EL1 with a transparent conductive material.

In the case where the second electrode EL2 is expanded into a plate shape, the overlapping area OV between the first electrode EL1 and the second electrode EL2 can be further ensured in the plan view and the sectional view. Accordingly, it is possible to minimize or reduce a short defect between the first electrode EL1 and the second electrode EL2 that may occur due to a space limitation or the like in a manufacturing step of each pixel PXL.

Fig. 16 is a plan view schematically showing a pixel according to still another embodiment, and fig. 17 is a schematic cross-sectional view taken along a line V-V' of fig. 16.

The pixel PXL shown in fig. 16 and 17 may have substantially the same or similar configuration as that of the pixel PXL of fig. 5 to 8 except that the first bank pattern BNK1 is disposed on the passivation layer PSV.

Therefore, with respect to the pixel PXL of fig. 16 and 17, features different from those of the above-described embodiment are mainly described to avoid repetitive description.

Referring to fig. 1 to 4, 16, and 17, a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL may be disposed in a pixel area PXA of each pixel PXL.

The pixel circuit layer PCL may also include at least one insulating layer, at least one transistor T, and a second electrode EL 2.

The display element layer DPL may include first and second bank patterns BNK1 and BNK2, a first electrode EL1, the light emitting element LD, first and second contact electrodes CNE1 and CNE2, and first to third insulating layers INS1 to INS 3.

The first bank pattern BNK1 may be positioned in an emission area where light is emitted from the pixel area PXA of each pixel PXL. The first bank pattern BNK1 may be a supporting member supporting the first electrode EL1 to change a surface profile (or shape) of the first electrode EL1 so as to guide light emitted from the light emitting element LD in an image display direction of the display device.

The first bank pattern BNK1 may be disposed between the passivation layer PSV and the first electrode EL1 in the light emitting region of the corresponding pixel PXL.

The first bank pattern BNK1 may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. According to an embodiment, the first bank pattern BNK1 may include a single film of an organic insulating film and/or a single film of an inorganic insulating film, but the disclosure is not limited thereto. According to an embodiment, the first bank pattern BNK1 may be formed of a multi-film in which at least one organic insulating film and at least one inorganic insulating film are stacked. However, the material of the first bank pattern BNK1 is not limited to the above-described embodiment, and the first bank pattern BNK1 may include a conductive material according to an embodiment.

The first bank pattern BNK1 may have a cross section having a trapezoidal shape in which a width of the first bank pattern BNK1 becomes narrower from a surface (e.g., an upper surface) of the passivation layer PSV toward an upper portion of the first bank pattern BNK1 in the third direction DR3, but the disclosure is not limited thereto. According to an embodiment, the first bank pattern BNK1 may include a curved surface having a cross section such as a semi-elliptical shape or a semicircular shape (or a hemispherical shape), in which a width of the first bank pattern BNK1 becomes narrower from a surface of the passivation layer PSV toward an upper portion of the first bank pattern BNK1 in the third direction DR 3. In the sectional view, the shape of the first bank pattern BNK1 is not limited to the above-described embodiment, and may be variously changed within a range capable of improving the efficiency of light emitted from each of the light emitting elements LD.

The first bank pattern BNK1 may have a stripe shape extending in the second direction DR2 in a plan view, but the disclosure is not limited thereto. According to an embodiment, the shape of the first bank pattern BNK1 may be variously changed.

The second bank pattern BNK2 may be disposed and/or formed in a peripheral area of the pixel area PXA of each pixel PXL. The second bank pattern BNK2 and the bank BNK described with reference to fig. 5 to 8 may have the same configuration. Therefore, a description of the second bank pattern BNK2 is omitted.

The first electrode EL1 may be disposed and/or formed on the first bank pattern BNK 1. Since the first electrode EL1 has a surface profile corresponding to the shape of the first bank pattern BNK1 disposed under the first electrode EL1, light emitted from each of the light emitting elements LD may be reflected by the first electrode EL1 and may further travel in the image display direction of the display device. The first bank pattern BNK1 and the first electrode EL1 may serve as a reflective member guiding light emitted from the light emitting element LD in a desired direction to improve light efficiency of the display device.

In this case, the first bank pattern BNK1 may not be disposed on the second electrode EL 2. In particular, in order to prevent light emitted from the light emitting element LD and traveling in the image display direction of the display device due to the second electrode EL2 from being dispersed by a structure such as the first bank pattern BNK1, the first bank pattern BNK1 may not be disposed on the second electrode EL 2. However, the disclosure is not limited thereto, and the first bank pattern BNK1 may be disposed on the second electrode EL2 according to an embodiment.

The second electrode EL2 of the pixel circuit layer PCL and the first electrode EL1 of the display element layer DPL may be spaced apart from each other, and the passivation layer PSV is interposed between the second electrode EL2 of the pixel circuit layer PCL and the first electrode EL1 of the display element layer DPL. For example, the first electrode EL1 and the second electrode EL2 may be disposed on different layers and spaced apart from each other with the passivation layer PSV interposed between the first electrode EL1 and the second electrode EL 2. Accordingly, it is possible to minimize or reduce a short defect between the first electrode EL1 and the second electrode EL2 that may occur due to a space limitation or the like in a manufacturing step of each pixel PXL.

Fig. 18 is a plan view schematically showing a pixel according to still another embodiment, and fig. 19 is a schematic cross-sectional view taken along line VI-VI' of fig. 18.

The pixel PXL shown in fig. 18 and 19 may have a configuration substantially the same as or similar to that of the pixel PXL of fig. 5 to 8 except that the third electrode EL3 and the third contact electrode CNE3 are added to the pixel PXL in a plan view and the second electrode EL2 is disposed between the first electrode EL1 and the third electrode EL 3.

Therefore, with respect to the pixel PXL of fig. 18 and 19, features different from those of the above-described embodiment are mainly described to avoid repetitive description.

Referring to fig. 1 to 4, 18, and 19, the substrate SUB, the pixel circuit layer PCL, and the display element layer DPL may be disposed in the pixel area PXA of each of the pixels PXL.

The pixel circuit layer PCL may include at least one insulating layer, at least one transistor T, and a second electrode EL 2. The second electrode EL2 may be disposed on the third interlayer insulating layer ILD 3.

The display element layer DPL may include banks BNK, first and third electrodes EL1 and EL3, a light emitting element LD, first to third contact electrodes CNE1 to CNE3, and first to third insulating layers INS1 to INS 3.

The first electrode EL1 and the third electrode EL3 may be disposed on the passivation layer PSV and may be spaced apart in the first direction DR 1. Each of the first electrode EL1 and the third electrode EL3 may extend in a direction different from the first direction DR1, for example, in a second direction DR2 crossing the first direction DR 1. The width w1 of the first electrode EL1 in the first direction DR1 and the width w3 of the third electrode EL3 in the first direction DR1 may be equal, but the disclosure is not limited thereto.

The first electrode EL1 and the third electrode EL3 may be disposed on the same surface, for example, on a surface (or upper surface) of the passivation layer PSV, and may be spaced apart in the first direction DR 1. In this case, the width w in the first direction DR1 between the first electrode EL1 and the third electrode EL3 may be about 4 μm to about 24 μm, but the disclosure is not limited thereto. The width w between the first electrode EL1 and the third electrode EL3 may be variously adjusted within a range in which the first electrode EL1 and the third electrode EL3 are sufficiently spaced apart in the first direction DR 1.

The first electrode EL1 and the third electrode EL3 may be formed of a conductive material (or materials) having a predetermined reflectivity.

The first electrode EL1 may be electrically connected to the first transistor T1 of the pixel circuit PXC of the corresponding pixel PXL through the first contact hole CH 1. The third electrode EL3 may be electrically connected to the first transistor T1 through a third contact hole CH 3.

In a cross-sectional view, the second electrode EL2 may be spaced apart from the first electrode EL1 and the third electrode EL3, and the passivation layer PSV is interposed between the second electrode EL2 and the first electrode EL1 and the third electrode EL 3. In a plan view, the second electrode EL2 may be spaced apart from the first electrode EL1 at a first interval d1 (or a first distance) in the first direction DR 1. The second electrode EL2 may be spaced apart from the third electrode EL3 at a second interval d2 (or a second distance) in the first direction DR1 in a plan view. In this case, the first and second intervals d1 and d2 may be the same, but the disclosure is not limited thereto. According to an embodiment, the first interval d1 and the second interval d2 may be different.

The first to third electrodes EL1 to EL3 may serve as alignment electrodes (or alignment lines) for alignment of the light emitting element LD in each pixel PXL. After the alignment of the light emitting element LD, the first electrode EL1 to the third electrode EL3 may serve as driving electrodes for driving the light emitting element LD.

In a plan view, the light emitting element LD may be disposed between the first electrode EL1 and the second electrode EL2 and between the second electrode EL2 and the third electrode EL 3. For example, the first light emitting element LD1 may be aligned and/or disposed between the first electrode EL1 and the second electrode EL2, and the second light emitting element LD2 may be aligned and/or disposed between the second electrode EL2 and the third electrode EL 3.

The first light emitting element LD1 may overlap the first electrode EL1 and the second electrode EL2 in a plan view and a sectional view. For example, in a plan view and a sectional view, one end portion of each of the first light emitting elements LD1 may overlap the first electrode EL1, and the other end portion of each of the first light emitting elements LD1 may overlap the second electrode EL 2. The first light emitting element LD1 may be aligned on the first insulating layer INS1 to overlap each of the first electrode EL1 and the second electrode EL2 in a plan view and to overlap a spaced region between the first electrode EL1 and the second electrode EL 2.

The second light emitting element LD2 may overlap the second electrode EL2 and the third electrode EL3 in a plan view and a cross-sectional view. For example, in a plan view and a sectional view, one end portion of each of the second light emitting elements LD2 may overlap the second electrode EL2, and the other end portion of each of the second light emitting elements LD2 may overlap the third electrode EL 3. The second light emitting element LD2 may be aligned on the first insulating layer INS1 to overlap each of the second electrode EL2 and the third electrode EL3 and to overlap a spaced region between the second electrode EL2 and the third electrode EL3 in a plan view.

The first contact electrode CNE1 may be disposed on the first electrode EL1, the second contact electrode CNE2 may be disposed on the second electrode EL2, and the third contact electrode CNE3 may be disposed on the third electrode EL 3. The first to third contact electrodes CNE1 to CNE3 may be disposed on the same layer and include the same material.

The first electrode EL1 may be electrically and/or physically connected to the first contact electrode CNE1 through the first opening OPN1 through the first insulating layer INS 1.

The second electrode EL2 may be electrically and/or physically connected to the second contact electrode CNE2 through the second opening OPN2 of the first insulating layer INS1 and the opening OPN of the passivation layer PSV.

The third electrode EL3 may be electrically and/or physically connected to the third contact electrode CNE3 through the third opening OPN3 passing through the first insulating layer INS 1.

As described above, the second electrode EL2 and the first and third electrodes EL1 and EL3 may be disposed on different layers and may be spaced apart from each other with the passivation layer PSV interposed between the second electrode EL2 and the first and third electrodes EL1 and EL 3. For example, the first and third electrodes EL1 and EL3 may be disposed on the second electrode EL2 with the passivation layer PSV interposed between the first and third electrodes EL1 and EL3 and the second electrode EL 2. In the case where the second electrode EL2 is separated from the first electrode EL1 and the third electrode EL3 in different layers and the first electrode EL1 and the third electrode EL3 provided on the same layer are spaced apart, it is possible to minimize or reduce short defects between the first electrode EL1 and the second electrode EL2 and between the second electrode EL2 and the third electrode EL3, which may occur due to space limitations or the like in the manufacturing step of each pixel PXL.

Fig. 20 is a plan view schematically showing a pixel according to still another embodiment, fig. 21 is a schematic sectional view taken along line VII-VII 'of fig. 20, fig. 22 is a schematic plan view of a second electrode implemented according to another embodiment in the pixel of fig. 20, and fig. 23 is a schematic sectional view taken along line VIII-VIII' of fig. 22.

The pixel PXL shown in fig. 20 to 23 may have a configuration substantially the same as or similar to that of the pixel PXL of fig. 18 and 19 except that the first electrode EL1 and the third electrode EL3 are partially overlapped with the second electrode EL 2.

Therefore, with respect to the pixel PXL of fig. 20 to 23, features different from those of the above-described embodiment are mainly described to avoid repetitive description.

Referring to fig. 1 to 4 and 20 to 23, the second electrode EL2 may have a width w2 in the first direction DR1 that is greater than the width of each of the first electrode EL1 and the third electrode EL3, and may be disposed under the first electrode EL1 and the third electrode EL 3.

The second electrode EL2 may have a plate shape expanded in the first direction DR1 to overlap with the remaining portion except for at least a portion of each of the first electrode EL1 and the third electrode EL3 in a plan view. For example, as shown in fig. 20 and 21, the second electrode EL2 may have a plate shape expanded in the first direction DR1 such that a side surface FS of the second electrode EL2 is more adjacent to the first light emitting element LD1 than a side surface FS of the first electrode EL1, and another side surface SS of the second electrode EL2 is more adjacent to the second light emitting element LD2 than another side surface SS of the third electrode EL 3. However, the disclosure is not limited thereto. According to an embodiment, as shown in fig. 22 and 23, the second electrode EL2 may have a plate shape expanding in the first direction DR1 such that a side surface FS of the second electrode EL2 is more adjacent to the bank BNK than a side surface FS of the first electrode EL1, and another side surface SS of the second electrode EL2 is more adjacent to the bank BNK than another side surface SS of the third electrode EL 3.

Each of the first electrode EL1 and the third electrode EL3 and the second electrode EL2 may overlap each other in a plan view and a sectional view. For example, the first electrode EL1 and the second electrode EL2 may include a region OV1 (hereinafter referred to as "first overlap region") where the first electrode EL1 and the second electrode EL2 overlap each other in a plan view and a cross-sectional view. The third electrode EL3 and the second electrode EL2 may include a region OV2 (hereinafter referred to as "second overlap region") where the third electrode EL3 and the second electrode EL2 overlap each other in a plan view and a sectional view.

As shown in fig. 20 and 21, the width of the first overlap region OV1 in the first direction DR1 may be smaller than the width w1 of the first electrode EL1 in the first direction DR1, but the disclosure is not limited thereto. According to an embodiment, the width of the first overlap region OV1 in the first direction DR1 may be equal to the width w1 of the first electrode EL1 in the first direction DR1, as shown in fig. 22 and 23. As shown in fig. 20 and 21, the width of the second overlap region OV2 in the first direction DR1 may be smaller than the width w3 of the third electrode EL3 in the first direction DR1, but the disclosure is not limited thereto. According to an embodiment, the width of the second overlap region OV2 in the first direction DR1 may be equal to the width w3 of the third electrode EL3 in the first direction DR1, as shown in fig. 22 and 23.

The width of the first overlap region OV1 in the first direction DR1 and the width of the second overlap region OV2 in the first direction DR1 may be equal to each other, but the disclosure is not limited thereto. The width of the first overlap region OV1 in the first direction DR1 and the width of the second overlap region OV2 in the first direction DR1 may be adjusted by arranging the positions of the first electrode EL1 to the third electrode EL 3.

The first overlap region OV1 may correspond to a region in which the first light emitting element LD1 is located. For example, the first overlap region OV1 may at least partially overlap the first light emitting element LD1 in a plan view. The second overlap region OV2 may correspond to the region in which the second light emitting element LD2 is located. For example, the second overlap region OV2 may at least partially overlap the second light emitting element LD2 in a plan view.

As described above, in the case where the second electrode EL2 is positioned below the first electrode EL1 and the third electrode EL3 between the pixel circuit layer PCL and the display element layer DPL and enlarged into a plate shape, the second electrode EL2 can function as a shielding member. In the case where the second electrode EL2 is used as a shielding member, an electric field caused by a configuration or components included in the pixel circuit layer PCL can be blocked, and thus misalignment and/or malfunction of the first and second light emitting elements LD1 and LD2 can be prevented.

In the case where the second electrode EL2 is expanded into a plate shape, the first overlap region OV1 and the second overlap region OV2 can also be ensured in plan view and sectional view. Accordingly, it is possible to minimize short defects between the first electrode EL1 and the second electrode EL2 and between the second electrode EL2 and the third electrode EL3, which may occur due to space limitations or the like in the manufacturing step of each pixel PXL.

In the case where the second electrode EL2 is expanded into a plate shape, the second electrode EL2 may serve alone as a reflecting member that guides light emitted from the first light-emitting element LD1 and the second light-emitting element LD2 in the image display direction of the display device. Accordingly, the amount of light emitted from the first and second light-emitting elements LD1 and LD2 and traveling in the image display direction of the display device can be increased by the second electrode EL2 having a relatively large area (or size) compared to the first and third electrodes EL1 and EL3, and thus the light emission efficiency of each pixel PXL can be improved. In this case, the light emitting efficiency of each pixel PXL may be further improved by reducing the loss of light emitted from the first light emitting element LD1 and the second light emitting element LD2 by forming the first electrode EL1 and the third electrode EL3 with a transparent conductive material.

Fig. 24 schematically shows a pixel according to still another embodiment, and is a schematic plan view showing adjacent electrodes and a light emitting element positioned between the adjacent electrodes, and fig. 25A and 25B are schematic sectional views taken along a line IX-IX'.

With respect to the embodiments of fig. 24 to 25B, features different from those of the above-described embodiments are mainly described to avoid repetitive descriptions. Portions not specifically described in the disclosure may follow the above-described embodiments, like reference numerals denote like components, and like reference numerals denote like components.

Referring to fig. 1 to 4 and fig. 24 to 25B, the substrate SUB, the pixel circuit layer PCL, and the display element layer DPL may be disposed in the pixel area PXA of each pixel PXL.

The pixel circuit layer PCL may include at least one insulating layer, at least one transistor T, and a second electrode EL 2. Here, the at least one insulating layer may include the buffer layer BFL, the gate insulating layer GI, the first to third interlayer insulating layers ILD1 to ILD3, and the passivation layer PSV.

The second electrode EL2 of the pixel circuit layer PCL may be provided on any one of the insulating layers. For example, the second electrode EL2 may be disposed on the third interlayer insulating layer ILD3, as shown in fig. 25A. As another example, the second electrode EL2 may be disposed on the second interlayer insulating layer ILD2, as shown in fig. 25B. In the case where the second electrode EL2 is disposed on the second interlayer insulating layer ILD2, the third interlayer insulating layer ILD3 may not be disposed according to an embodiment.

The second electrode EL2 may include a 2-1 st electrode EL2_1, a 2-2 nd electrode EL2_2, and a 2-3 rd electrode EL2_3 spaced apart in the first direction DR 1. The 2-1 st electrode EL2_1, the 2-2 nd electrode EL2_2, and the 2-3 rd electrode EL2_3 may be disposed on the same layer and include the same material, for example, an opaque conductive material.

A width w4 in the first direction DR1 between the 2-1 st electrode EL2_1 and the 2-2 nd electrode EL2_2 and a width w4 in the first direction DR1 between the 2-2 nd electrode EL2_2 and the 2-3 rd electrode EL2_3 may be equal to each other, but the disclosure is not limited thereto. According to an embodiment, a width w4 in the first direction DR1 between the 2-1 st electrode EL2_1 and the 2-2 nd electrode EL2_2 and a width w4 in the first direction DR1 between the 2-2 nd electrode EL2_2 and the 2-3 rd electrode EL2_3 may be different from each other. For example, the width w4 between the adjacent second electrodes EL2 in the first direction DR1 may be determined by controlling the size, arrangement position, and the like of the 2-1 st electrode EL2_1 to the 2-3 nd electrode EL2_3, so that each of the width w4 in the first direction DR1 between the 2-1 st electrode EL2_1 and the 2-2 nd electrode EL2_2 and the width w4 in the first direction DR1 between the 2-2 nd electrode EL2_2 and the 2-3 th electrode EL2_3 may be in a range of about 4 μm to about 24 μm.

The 2-1 st electrode EL2_1 may be electrically connected to the second power supply line PL2 of the pixel circuit PXC of the corresponding pixel PXL through the second contact hole CH 2. The 2-2 nd electrode EL2_2 may be electrically connected to the second power supply line PL2 through the fourth contact hole CH 4. The 2-3 rd electrode EL2_3 may be electrically connected to the second power line PL2 through a sixth contact hole CH 6.

The display element layer DPL may include a bank BNK (not shown, similar to fig. 18 and 19), a first electrode EL1, a light emitting element LD, and first and second insulating layers INS1 and INS 2. Although not shown in the drawings, the display element layer DPL may further include a first contact electrode disposed on the first electrode EL1, a second contact electrode disposed on the second electrode EL2, and a third insulating layer disposed on the first contact electrode and the second contact electrode.

The first electrode EL1 of the display element layer DPL may be disposed on the passivation layer PSV, and may include a 1 st to 1 st electrode EL1_1, a 1 st to 2 nd electrode EL1_2, a 1 st to 3 rd electrode EL1_3, and a 1 st to 4 th electrode EL1_4 spaced apart in the first direction DR 1. The 1 st-1 st electrode EL1_1, the 1 st-2 nd electrode EL1_2, the 1 st-3 rd electrode EL1_3, and the 1 st-4 th electrode EL1_4 may include the same material, for example, an opaque conductive material or a transparent conductive material.

A width w5 in the first direction DR1 between the 1-1 st electrode EL1_1 and the 1-2 st electrode EL1_2, a width w5 in the first direction DR1 between the 1-2 st electrode EL1_2 and the 1-3 st electrode EL1_3, and a width w5 in the first direction DR1 between the 1-3 st electrode EL1_3 and the 1-4 th electrode EL1_4 may be equal to each other, but the disclosure is not limited thereto. According to an embodiment, a width w5 in the first direction DR1 between the 1-1 st electrode EL1_1 and the 1-2 st electrode EL1_2, a width w5 in the first direction DR1 between the 1-2 st electrode EL1_2 and the 1-3 st electrode EL1_3, and a width w5 in the first direction DR1 between the 1-3 st electrode EL1_3 and the 1-4 th electrode EL1_4 may be different. The width w5 between the adjacent first electrodes EL1 in the first direction DR1 may be adjusted by controlling the size, arrangement position, and the like of the 1-1 st to 1-4 th electrodes EL1_1 to EL1_4, so that each of the width w5 in the first direction DR1 between the 1-1 st electrode EL1_1 and the 1-2 st electrode EL1_2, the width w5 in the first direction DR1 between the 1-2 st electrode EL1_2 and the 1-3 th electrode EL1_3, and the width w5 in the first direction DR1 between the 1-3 st electrode EL1_3 and the 1-4 th electrode EL1_4 may be in the range of about 4 μm to about 24 μm.

The 1-1 st electrode EL1_1 may be electrically connected to the first transistor T1 of the pixel circuit PXC through the first contact hole CH 1. The 1-2 st electrode EL1_2 may be electrically connected to the first transistor T1 through the third contact hole CH 3. The 1-3 st electrode EL1_3 may be electrically connected to the first transistor T1 through the fifth contact hole CH 5. The 1-4 th electrode EL1_4 may be electrically connected to the first transistor T1 through the seventh contact hole CH 7.

The first electrode EL1 and the second electrode EL2 may be arranged in the order of a 1 st-1 st electrode EL1_1, a 2 nd-1 st electrode EL2_1, a 1 st-2 nd electrode EL1_2, a 2 nd-2 nd electrode EL2_2, a 1 st-3 rd electrode EL1_3, a 2 nd-3 rd electrode EL2_3, and a 1 st-4 th electrode EL1_4 in the first direction DR1 in plan view.

The first electrode EL1 and the second electrode EL2 may not overlap each other and may be alternately disposed. For example, the first electrode EL1 and the second electrode EL2 may be spaced apart by a predetermined interval d (or distance) so as not to overlap each other in a plan view. The 2-1 st electrode EL2_1 may be positioned between the 1 st-1 st electrode EL1_1 and the 1 st-2 nd electrode EL1_2, the 2 nd-2 nd electrode EL2_2 may be positioned between the 1 st-2 nd electrode EL1_2 and the 1 st-3 rd electrode EL1_3, and the 2 nd-3 rd electrode EL2_3 may be positioned between the 1 st-3 rd electrode EL1_3 and the 1 st-4 th electrode EL1_ 4.

The interval d between the 1-1 st electrode EL1_1 and the 2-1 st electrode EL2_1, the interval d between the 2-1 st electrode EL2_1 and the 1-2 st electrode EL1_2, the interval d between the 1-2 st electrode EL1_2 and the 2-2 nd electrode EL2_2, the interval d between the 2-2 nd electrode EL2_2 and the 1-3 th electrode EL1_3, the interval d between the 1-3 rd electrode EL1_3 and the 2-3 rd electrode EL2_3, and the interval d between the 2-3 th electrode EL2_3 and the 1-4 th electrode EL1_4 may be the same. For example, the interval d between the first electrode EL1 and the second electrode EL2 disposed on different layers may be about 2.5 μm in a plan view, but the disclosure is not limited thereto.

The embodiment in which the first electrode EL1 and the second electrode EL2 are spaced apart at the predetermined interval d is described, but the disclosure is not limited thereto. According to an embodiment, at least one region of the first electrode EL1 and the second electrode EL2 may overlap each other. For example, the 1-1 st electrode EL1_1 and the 2-1 st electrode EL2_1 may overlap each other, the 2-1 st electrode EL2_1 and the 1-2 st electrode EL1_2 may overlap each other, the 1-2 st electrode EL1_2 and the 2-2 nd electrode EL2_2 may overlap each other, the 2-2 nd electrode EL2_2 and the 1-3 th electrode EL1_3 may overlap each other, the 1-3 rd electrode EL1_3 and the 2-3 rd electrode EL2_3 may overlap each other, and the 2-3 rd electrode EL2_3 and the 1-4 th electrode EL1_4 may overlap each other.

The first electrode EL1 and the second electrode EL2 may serve as alignment electrodes (or alignment lines) for alignment of the light emitting element LD in each pixel PXL. After the alignment of the light emitting element LD, the first electrode EL1 and the second electrode EL2 may serve as driving electrodes for driving the light emitting element LD.

The light emitting element LD may be disposed between the first electrode EL1 and the second electrode EL2, the first electrode EL1 and the second electrode EL2 are disposed on different layers and spaced apart, and the passivation layer PSV is interposed between the first electrode EL1 and the second electrode EL 2. For example, the first light emitting element LD1 may be disposed between the 1 st-1 st electrode EL1_1 and the 2 nd-1 st electrode EL2_1, the second light emitting element LD2 may be disposed between the 2 nd-1 st electrode EL2_1 and the 1 st-2 nd electrode EL1_2, the third light emitting element LD3 may be disposed between the 1 st-2 nd electrode EL1_2 and the 2 nd-2 nd electrode EL2_2, the fourth light emitting element LD4 may be disposed between the 2 nd-2 nd electrode EL2_2 and the 1 st-3 th electrode EL1_3, the fifth light emitting element LD5 may be disposed between the 1 st-3 rd electrode EL1_3 and the 2 nd-3 th electrode EL2_3, and the sixth light emitting element LD6 may be disposed between the 2 nd-3 th electrode EL2_3 and the 1 st-4 th electrode EL1_ 4.

The first light emitting element LD1 may overlap the 1 st-1 st electrode EL1_1 and the 2 nd-1 st electrode EL2_1 in a plan view and a cross-sectional view. For example, in a plan view and a sectional view, one end portion of each of the first light emitting elements LD1 may overlap the 1 st-1 st electrode EL1_1, and the other end portion of each of the first light emitting elements LD1 may overlap the 2 nd-1 st electrode EL2_ 1. The first light emitting element LD1 may overlap each of the 1 st-1 st electrode EL1_1 and the 2 nd-1 st electrode EL2_1 in a plan view, and may be aligned on the first insulating layer INS1 to correspond to a region between the 1 st-1 st electrode EL1_1 and the 2 nd-1 st electrode EL2_ 1. In the case where the 1-1 st electrode EL1_1 and the 2-1 st electrode EL2_1 include a stacking region where the 1-1 st electrode EL1_1 and the 2-1 st electrode EL2_1 are stacked on each other, the first light emitting element LD1 may be aligned on the first insulating layer INS1 to correspond to the stacking region, but the disclosure is not limited thereto.

The second light emitting element LD2 may overlap the 2 nd-1 st electrode EL2_1 and the 1 st-2 nd electrode EL1_2 in a plan view and a cross-sectional view. For example, in a plan view and a sectional view, one end portion of each of the second light emitting elements LD2 may overlap the 2-1 st electrode EL2_1, and the other end portion of each of the second light emitting elements LD2 may overlap the 1-2 nd electrode EL1_ 2. The second light emitting element LD2 may overlap each of the 2-1 st electrode EL2_1 and the 1-2 st electrode EL1_2 in a plan view, and may be aligned on the first insulating layer INS1 to correspond to a spaced region between the 2-1 st electrode EL2_1 and the 1-2 nd electrode EL1_ 2. In the case where the 2-1 st electrode EL2_1 and the 1-2 st electrode EL1_2 include a stacking region where the 2-1 st electrode EL2_1 and the 1-2 st electrode EL1_2 are stacked on each other, the second light emitting element LD2 may be aligned on the first insulating layer INS1 to correspond to the stacking region, but the disclosure is not limited thereto.

The third light emitting element LD3 may overlap the 1 st-2 nd electrode EL1_2 and the 2 nd-2 nd electrode EL2_2 in a plan view and a cross-sectional view. For example, in a plan view and a sectional view, one end portion of each of the third light emitting elements LD3 may overlap the 1 st-2 nd electrode EL1_2, and the other end portion of each of the third light emitting elements LD3 may overlap the 2 nd-2 nd electrode EL2_ 2. The third light emitting element LD3 may overlap each of the 1-2 st and 2-2 nd electrodes EL1_2 and EL2_2 in a plan view, and may be aligned on the first insulating layer INS1 to correspond to a spaced region between the 1-2 st and 2-2 nd electrodes EL1_2 and EL2_ 2. In the case where the 1-2 st electrode EL1_2 and the 2-2 nd electrode EL2_2 include a stacking region where the 1-2 st electrode EL1_2 and the 2-2 nd electrode EL2_2 are stacked on each other, the third light emitting element LD3 may be aligned on the first insulating layer INS1 to correspond to the stacking region, but the disclosure is not limited thereto.

The fourth light emitting element LD4 may overlap the 2 nd-2 nd electrode EL2_2 and the 1 st-3 rd electrode EL1_3 in a plan view and a cross-sectional view. For example, in a plan view and a sectional view, one end portion of each of the fourth light emitting elements LD4 may overlap the 2 nd to 2 nd electrode EL2_2, and the other end portion of each of the fourth light emitting elements LD4 may overlap the 1 st to 3 rd electrode EL1_ 3. The fourth light emitting element LD4 may overlap each of the 2 nd to 2 nd electrode EL2_2 and the 1 st to 3 rd electrode EL1_3 in a plan view, and may be aligned on the first insulating layer INS1 to correspond to a spaced apart region between the 2 nd to 2 nd electrode EL2_2 and the 1 st to 3 rd electrode EL1_ 3. In the case where the 2 nd to 2 nd electrode EL2_2 and the 1 st to 3 rd electrode EL1_3 include a stacking region where the 2 nd to 2 nd electrode EL2_2 and the 1 st to 3 rd electrode EL1_3 are stacked on each other, the fourth light emitting element LD4 may be aligned on the first insulating layer INS1 to correspond to the stacking region, but the disclosure is not limited thereto.

The fifth light emitting element LD5 may overlap the 1 st to 3 rd electrode EL1_3 and the 2 nd to 3 rd electrode EL2_3 in a plan view and a sectional view. For example, in a plan view and a sectional view, one end portion of each of the fifth light emitting elements LD5 may overlap the 1 st to 3 rd electrodes EL1_3, and the other end portion of each of the fifth light emitting elements LD5 may overlap the 2 nd to 3 rd electrodes EL2_ 3. The fifth light emitting element LD5 may overlap each of the 1 st to 3 rd and 2 rd to 3 rd electrodes EL1_3 and EL2_3 in a plan view, and may be aligned on the first insulating layer INS1 to correspond to a spaced region between the 1 st to 3 rd and 2 rd to 3 rd electrodes EL1_3 and EL2_ 3. In the case where the 1-3 st electrode EL1_3 and the 2-3 rd electrode EL2_3 include a stacking region where the 1-3 st electrode EL1_3 and the 2-3 rd electrode EL2_3 are stacked on each other, the fifth light emitting element LD5 may be aligned on the first insulating layer INS1 to correspond to the stacking region, but the disclosure is not limited thereto.

The sixth light emitting element LD6 may overlap the 2 nd to 3 rd electrode EL2_3 and the 1 st to 4 th electrode EL1_4 in a plan view and a sectional view. For example, in a plan view and a sectional view, one end portion of each of the sixth light emitting elements LD6 may overlap the 2 nd to 3 rd electrodes EL2_3, and the other end portion of each of the sixth light emitting elements LD6 may overlap the 1 st to 4 th electrodes EL1_ 4. The sixth light emitting element LD6 may overlap each of the 2-3 nd electrode EL2_3 and the 1-4 th electrode EL1_4 in a plan view, and may be aligned on the first insulating layer INS1 to correspond to spaced apart regions of the 2-3 rd electrode EL2_3 and the 1-4 th electrode EL1_ 4. In the case where the 2-3 rd and 1-4 th electrodes EL2_3 and EL1_4 include a stacking region where the 2-3 rd and 1-4 th electrodes EL2_3 and EL1_4 are stacked on each other, the sixth light emitting element LD6 may be aligned on the first insulating layer INS1 to correspond to the stacking region, but the disclosure is not limited thereto.

The first electrode EL1 and the second electrode EL2 may be disposed on different layers and may be spaced apart, and the passivation layer PSV is interposed between the first electrode EL1 and the second electrode EL 2.

As described above, in the case where the first electrode EL1 and the second electrode EL2 are separated and disposed on different layers, a short defect between the first electrode EL1 and the second electrode EL2, which may occur due to a spatial limitation between the first electrode EL1 and the second electrode EL2, may be minimized or reduced.

Fig. 26 is a schematic plan view of a second electrode implemented in accordance with another embodiment in the pixel of fig. 24.

The pixel PXL shown in fig. 26 may have a configuration substantially the same as or similar to that of the pixel PXL of fig. 24 to 25B except that the second electrode EL2 is enlarged into a plate shape.

Therefore, regarding the pixel PXL of fig. 26, features different from those of the above-described embodiment are mainly described to avoid repetitive description.

Referring to fig. 1 to 4 and 26, the first electrode EL1 and the second electrode EL2 may have different widths. For example, the width w2 of the second electrode EL2 in the first direction DR1 may be greater than the width w1 of each of the 1 st-1 st electrode EL1_1 through the 1 st-4 th electrode EL1_4 in the first direction DR 1.

The second electrode EL2 may be enlarged in the first direction DR1 to overlap with the remaining portion except for a portion of the first electrode EL1 in a plan view. For example, the second electrode EL2 may have a plate shape expanded in the first direction DR1 to overlap the 1 st-2 th electrode EL1_2 and the 1 st-3 rd electrode EL1_ 3. In the embodiment, the shape of the second electrode EL2 may be variously changed within a range that does not directly or indirectly affect the configuration included in the pixel circuit PXC of the corresponding pixel PXL. The second electrode EL2 may include a first opening OP1 and a second opening OP 2. The first opening OP1 may correspond to an area in which a third contact hole CH3 electrically connecting the 1 st-2 nd electrode EL1_2 and the first driving transistor T1 of the pixel circuit PXC is positioned. The second opening OP2 may correspond to a region in which a fifth contact hole CH5 electrically connecting the 1-3 st electrode EL1_3 and the first driving transistor T1 is positioned.

As described above, when the second electrode EL2 is expanded into a plate shape, the second electrode EL2 may function as a shielding member that prevents misalignment and/or malfunction of the light emitting element LD by blocking an electric field induced from a configuration or component included in the pixel circuit PXC.

Although the disclosure has been described with reference to the above embodiments, it will be understood by those skilled in the art or having common general knowledge in the art that various modifications and changes may be made to the disclosure without departing from the spirit and technical field of the disclosure described in the claims.

Therefore, the technical scope of the disclosure should not be limited to what is described in the detailed description of the specification, and the claimed invention should be defined by the claims.