阅读说明：本技术 半导体结构 (Semiconductor structure ) 是由 林鑫成 林志鸿 林柏亨 于 2020-06-30 设计创作，主要内容包括：本发明提供一种半导体结构,包括：基底；通道层,位于基底上；阻障层,位于通道层上；源极结构及漏极结构,位于阻障层的两侧；掺杂化合物半导体层,位于阻障层上,掺杂化合物半导体层具有邻近源极结构的第一侧边、邻近漏极结构的第二侧边、以及至少一开口,此至少一开口露出阻障层的至少一部分；介电层,位于掺杂化合物半导体层及阻障层上；以与门极结构,位于掺杂化合物半导体层上。(The present invention provides a semiconductor structure, comprising: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a source structure and a drain structure located at both sides of the barrier layer; a doped compound semiconductor layer on the barrier layer, the doped compound semiconductor layer having a first side adjacent to the source structure, a second side adjacent to the drain structure, and at least one opening exposing at least a portion of the barrier layer; a dielectric layer on the doped compound semiconductor layer and the barrier layer; and the gate structure is arranged on the doped compound semiconductor layer.)

1. A semiconductor structure, comprising:

a substrate;

a channel layer on the substrate;

a barrier layer on the channel layer;

a source structure and a drain structure located on both sides of the barrier layer;

a doped compound semiconductor layer on the barrier layer, the doped compound semiconductor layer having a first side adjacent to the source structure, a second side adjacent to the drain structure, and at least one opening exposing at least a portion of the barrier layer;

a dielectric layer on the doped compound semiconductor layer and the barrier layer; and

and the grid structure is positioned on the doped compound semiconductor layer.

2. The semiconductor structure of claim 1, wherein a width of the at least one opening is 1/3 to 2/3 of a distance between the first side and the second side of the doped compound semiconductor layer.

3. The semiconductor structure of claim 1, wherein the at least one opening is a plurality of openings, and wherein a width of the opening is 1/3-2/3 of a distance between the first side and the second side of the doped compound semiconductor layer.

4. The semiconductor structure of claim 1, further comprising a buffer layer between the substrate and the channel layer.

5. A semiconductor structure, comprising:

a substrate;

a buffer layer on the substrate;

the channel layer is positioned on the buffer layer;

a barrier layer on the channel layer;

a source structure and a drain structure located on both sides of the barrier layer;

a doped compound semiconductor layer on the barrier layer, wherein at least a portion of the doped compound semiconductor layer is discontinuous in a first direction from the source structure to the drain structure;

a dielectric layer on the doped compound semiconductor layer and the barrier layer; and

and the grid structure is positioned on the doped compound semiconductor layer.

6. The semiconductor structure of claim 5, wherein the doped compound semiconductor layer has at least one opening.

7. The semiconductor structure of claim 6, wherein the at least one opening has a maximum opening width in the first direction, and the maximum opening width is 1/3-2/3 of a maximum width of the doped compound semiconductor layer along the first direction.

8. The semiconductor structure of claim 6, wherein the at least one opening is a plurality of openings, the openings having a maximum width in the first direction and the maximum width sum is 1/3-2/3 of a maximum width of the doped compound semiconductor layer along the first direction.

9. The semiconductor structure of claim 6, wherein the at least one opening is a plurality of openings, a neighboring minimum distance of the openings in a second direction perpendicular to the first direction is 1/2 of a maximum width of the doped compound semiconductor layer along the first direction, a maximum opening width in an opening of the openings in the first direction is 1/3-2/3 of the maximum width of the doped compound semiconductor layer along the first direction.

10. The semiconductor structure of claim 5, wherein the doped compound semiconductor layer has two sides parallel to the first direction, and at least one of the two sides has at least one notch.

11. The semiconductor structure of claim 10, wherein the at least one notch has a maximum notch width in the first direction, and the maximum notch width is 1/3-2/3 of a maximum width of the doped compound semiconductor layer along the first direction.

12. The semiconductor structure of claim 10, wherein the at least one notch is a plurality of notches, the notches having a maximum width in the first direction that is 1/3-2/3 of a maximum width of the doped compound semiconductor layer along the first direction.

13. The semiconductor structure of claim 7, wherein the doped compound semiconductor layer is comprised of a plurality of separate doped compound semiconductor islands.

14. The semiconductor structure of claim 13, wherein the doped compound semiconductor island has a maximum width sum in the first direction that is 1/2 to 2 times the sum of the separation distances in the first direction of adjacent doped compound semiconductor islands.

Technical Field

Embodiments of the present invention relate to semiconductor devices, and more particularly, to a semiconductor device having a doped compound semiconductor.

Background

Gallium nitride-based (GaN-based) semiconductor materials have many excellent material properties, such as: high heat resistance, wide band-gap (band-gap), and high electron saturation rate. Therefore, the gallium nitride based semiconductor material is suitable for high speed and high temperature operation environment. In recent years, gallium nitride-based semiconductor materials have been widely used in Light Emitting Diode (LED) devices, high frequency devices such as High Electron Mobility Transistors (HEMTs) having a hetero-interface structure.

During the fabrication of high electron mobility transistor devices, the semiconductor material may be deactivated by environmental influences (e.g., temperature or environmental elements), which may result in a reduced gate control capability of the device and thus in a reduced current drive capability, and may also degrade the electrical uniformity of different batches of the same or similar processes.

With the development of gallium nitride-based semiconductor materials, these devices using gallium nitride-based semiconductor materials are applied in more severe operating environments, such as higher frequencies, higher temperatures, or higher voltages. Therefore, there is still a need for further improvement of semiconductor devices having gallium nitride based semiconductor materials to overcome the challenges.

Disclosure of Invention

An embodiment of the present invention provides a semiconductor structure, including: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a source structure and a drain structure located at both sides of the barrier layer; a doped compound semiconductor layer on the barrier layer, the doped compound semiconductor layer having a first side adjacent to the source structure, a second side adjacent to the drain structure, and at least one opening exposing at least a portion of the barrier layer; a dielectric layer on the doped compound semiconductor layer and the barrier layer; and the gate structure is arranged on the doped compound semiconductor layer.

An embodiment of the present invention provides a semiconductor structure, including: a substrate; a buffer layer on the substrate; the channel layer is positioned on the buffer layer; a barrier layer on the channel layer; a source structure and a drain structure located at both sides of the barrier layer; a doped compound semiconductor layer on the barrier layer, wherein at least a portion of the doped compound semiconductor layer is discontinuous in a first direction from the source structure to the drain structure; a dielectric layer on the doped compound semiconductor layer and the barrier layer; and the gate structure is arranged on the doped compound semiconductor layer.

Drawings

Embodiments of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.

FIG. 1 is a partial top projection view of a semiconductor structure, according to some embodiments of the present invention.

Fig. 2 is a schematic cross-sectional view illustrating a-a' of the semiconductor structure of fig. 1, according to some embodiments of the present invention.

Fig. 3 is a partial top projection view of a semiconductor structure, according to some embodiments of the present invention.

Fig. 4 is a schematic cross-sectional view illustrating a-a' of the semiconductor structure of fig. 3, according to some embodiments of the present invention.

Fig. 5-11 are partial top-view illustrations of semiconductor structures according to further embodiments of the present invention.

FIG. 12 is a graph depicting electric field intensity near a surface of a semiconductor structure, in accordance with some embodiments of the present invention.

Description of the symbols

200,400: a semiconductor structure;

110: a substrate;

112: a channel layer;

111: a buffer layer;

113: a barrier layer;

114: a source electrode;

115: a drain electrode;

116,316,516: a doped compound semiconductor layer;

117: a dielectric layer;

118: a gate electrode;

119: a gate metal layer;

122: a source metal layer;

123: a drain metal layer;

616,716,816,916,1016,1116: a doped compound semiconductor layer;

1116a,1116b,1116 c: a doped compound semiconductor island;

E₁,E₂,E₃,E₄,E₅,E₆,E₇,E₈: a side edge;

OP₁,OP_3a,OP_3b,OP_5a,OP_5b,OP_5c: an opening;

OP_6a,OP_6b,OP_7a,OP_7b,OP_7c: an opening;

N₈,N_9a,N_9b: a notch;

D₁,D₃,S₁,S₂,S₃,S₄,S₅: spacing;

D₅,D₆,D₇,D₈,D_9,D₁₀: a width;

W₁,W_3a,W_3b,W_5a,W_5b,W_5c,W_6a,W_6b: a width;

W_7a,W_7b,W_7c,W₈,W_9a,W_9b,W₁₀,W_11a,W_11b,W_11c: width.

Detailed Description

The following disclosure provides many embodiments, or examples, for implementing various components of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the embodiments of the invention. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first element being formed over a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below" … …, "below," "lower," "above," "higher," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

Some embodiments of the invention are described below in which additional steps may be provided before, during, and/or after various stages described in the embodiments. Some of the stages may be replaced or eliminated in different embodiments. Additional components may be added to the semiconductor device structure. Some of the described components may be replaced or eliminated in different embodiments. Although some embodiments discussed are performed in a particular order of steps, these steps may be performed in another logical order. Furthermore, the term "about" as used herein means that a given quantity may vary based on the particular technology node associated with the target semiconductor device. In some embodiments, the term "about" may indicate that a given quantity of a value is in the range of, for example, 10% to 30% of the value (e.g., + -10%, + -20%, or + -30% of the value), based on the particular technology node.

The semiconductor structure provided by the embodiment of the invention improves the electrical uniformity by reducing the proportion of the doped compound semiconductor layer in the semiconductor structure, thereby improving the device performance. In some embodiments, device performance may be further enhanced by a liner or protective layer disposed on the sidewalls of the doped compound semiconductor layer and on the barrier layer, and a liner disposed under the source and drain electrodes.

FIG. 1 illustrates a portion of a semiconductor structure, according to some embodiments of the present inventionAnd projecting the upper view. Fig. 2 is a schematic cross-sectional view of fig. 1A-a', according to some embodiments of the invention. The semiconductor structure 200 includes: a substrate 110, a channel layer 112, a barrier layer 113, a source structure composed of a source electrode 114 and a source metal layer 122, a drain structure composed of a drain electrode 115 and a drain metal layer 123, a doped compound semiconductor layer 116, a dielectric layer 117, and a gate structure composed of a gate electrode 118 and a gate metal layer 119. The substrate 110 may be a doped (e.g., doped with p-type or n-type dopants) or undoped semiconductor substrate. For example, the substrate 110 may include: elemental semiconductors including silicon or germanium; compound semiconductors including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); the alloy semiconductor comprises silicon-germanium alloy, phosphorus-arsenic-gallium alloy, arsenic-aluminum-indium alloy, arsenic-aluminum-gallium alloy, arsenic-indium-gallium alloy, phosphorus-indium-gallium alloy and/or phosphorus-arsenic-indium-gallium alloy, or a combination of the materials. In some embodiments, the substrate 110 may also be a semiconductor on insulator (semiconductor on insulator) substrate, such as: silicon on insulator (soi) or Silicon Germanium On Insulator (SGOI). In other embodiments, the substrate 110 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide (Al) substrate₂O₃) A substrate (otherwise known as a Sapphire (Sapphire) substrate), or other similar substrate. In some embodiments, the substrate 110 may comprise a ceramic substrate and a pair of barrier layers respectively disposed on the upper and lower surfaces of the ceramic substrate, wherein the ceramic substrate may comprise a ceramic material, and the ceramic material comprises a metal inorganic material. For example, the ceramic substrate may comprise: silicon carbide, aluminum nitride, sapphire substrates, or other suitable materials. The sapphire substrate may be alumina.

Channel layer 112 is located on substrate 110. In some embodiments, the material of the channel layer comprises a binary (binary) group III-V compound semiconductor material, such as a group III nitride. For example, the material of the channel layer may be gallium nitride. In some embodiments, the channel layer may be doped with n-type dopants or p-type dopants. The channel layer may be formed by an epitaxial growth process, such as: metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), combinations of the foregoing, or the like. In some embodiments, the breakdown voltage (breakdown voltage) of the hemt is mainly determined by the thickness of the gan channel layer. For example, increasing the thickness of the gan channel layer by 1 μm can increase the breakdown voltage (breakdown voltage) of the hemt by about 100V. During the epitaxial growth process for forming the gan layer, a substrate with high thermal conductivity and high mechanical strength is required to deposit gan material thereon, which may otherwise cause the substrate to bend or even crack. Aluminum nitride substrates have higher thermal conductivity and higher mechanical strength than silicon substrates, and thus thicker gallium nitride layers can be formed on the aluminum nitride substrates. For example, the thickness of the gallium nitride layer formed on the surface of the silicon substrate may be about 2 μm to about 4 μm, while the thickness of the gallium nitride channel layer formed on the surface of the aluminum nitride substrate may be up to about 5 μm to about 15 μm.

Due to the fact that the channel layer 112 and the substrate 110 may have lattice difference or different thermal expansion coefficients, strain (strain) may be generated at or near the interface of the channel layer 112 and the substrate 110, and defects such as cracks or warpage may be easily formed in the channel layer 112. In some embodiments, the semiconductor structure 200 may include a buffer layer 111 between the substrate 110 and the channel layer 112, as shown in fig. 2. The buffer layer 111 may relieve strain of the channel layer 112 formed thereon to prevent defects from forming in the channel layer 112. The material of the buffer layer 111 may include: AlN, GaN, Al_xGa_1-xN (wherein 0)<x<1) Combinations of the foregoing, or other similar materials, and may be formed by epitaxial growth processes, such as: metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, combinations of the foregoing, or the like.

Although the buffer layer 111 shown in fig. 2 is a single-layer structure, the buffer layer 111 may be a multi-layer structure (not shown). For example, the buffer layer 111 may include a superlattice buffer layer and/or a graded buffer layer, wherein the superlattice buffer layer is disposed on the substrate 110, and the graded buffer layer is disposed on the superlattice buffer layer, so as to effectively prevent dislocation (dislocation) in the substrate 110 from entering a channelAnd further improve the crystalline quality of other films and/or layers above. In addition, the superlattice buffer layer and the graded buffer layer may have a multi-layer structure, for example, the superlattice buffer layer may include a plurality of alternating layers, each of the alternating layers including at least one aluminum nitride (AlN) layer and at least one aluminum gallium nitride (Al) layer alternately arranged_xGa_(1-x)N) layer and optionally Al in accordance with the aluminum content_xGa_(1-x)N represents, wherein 0 ≦ x<1; the graded buffer layer may comprise a plurality of aluminum gallium nitride (Al)_yGa_(1-y)N) layer, and may be based on different aluminum contents, in terms of Al_yGa_(1-y)N represents, wherein 0 ≦ y<1。

In some embodiments, a seed layer (not shown) may be formed between the substrate 110 and the buffer layer 111. The material of the seed layer may include: AlN and Al₂O₃AlGaN, SiC, Al, combinations of the foregoing, or the like. The seed layer may be a single layer or a multi-layer structure and may be formed by an epitaxial growth process as described above or the like. In some embodiments, the material of the buffer layer 111 is determined by the material of the seed layer and the gas introduced during the epitaxial process.

Barrier layer 113 is disposed on channel layer 112. The material of barrier layer 113 may comprise a ternary (ternary) group III-V compound semiconductor, such as a group III nitride. For example, the barrier layer can be AlGaN, AlInN, or a combination thereof. In other embodiments, barrier layer 113 may also include: GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or combinations of the foregoing. In some embodiments, barrier layer 113 may have dopants, such as n-type dopants or p-type dopants. The barrier layer may be formed by an epitaxial growth process, such as: metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, combinations of the foregoing, or the like. According to some embodiments of the present invention, the channel layer 112 and the barrier layer 113 are made of different materials, and the interface is a heterojunction (heterojunction) structure, wherein the piezoelectric polarization effect is caused by stress generated due to lattice mismatch between the channel layer 112 and the barrier layer 113, and the spontaneous polarization is caused by strong ionic bonding of group III metal (such as Al, Ga, or In) and nitrogen. Due to the energy gap (energy gap) between the channel layer 112 and the barrier layer 113 and the aforementioned piezoelectric polarization and spontaneous polarization effects, a two-dimensional electron gas (2DEG) (not shown) is formed at the hetero-interface between the channel layer 112 and the barrier layer 113. Some of the semiconductor devices in embodiments of the present invention are High Electron Mobility Transistors (HEMTs) that utilize a two-dimensional electron gas (2DEG) as a conducting carrier.

Referring to fig. 2, a doped compound semiconductor layer 116 is disposed on the barrier layer 113. The doped compound semiconductor layer 116 has a side E adjacent to the source structure₁Side E adjacent to the drain structure₂And an opening OP₁. Side edge E₁And side edge E₂Has a spacing of D₁Opening OP₁Has a width of W₁And a portion of the barrier layer 113 is exposed. The doped compound semiconductor layer 116 may suppress the generation of a two-dimensional electron gas (2DEG) below the gate electrode 118 to be formed thereon later, to achieve a normally-off (normal-off) state of the semiconductor device. During the process, the doped compound semiconductor layer 116 may be deactivated by environmental influences (e.g., temperature or elements in the environment), and the embodiment of the present invention is provided with an opening OP₁The doped compound semiconductor layer 116 is used to reduce the area of the doped compound semiconductor layer 116 in the semiconductor structure 200, so as to reduce the proportion of the doped compound semiconductor layer 116 in the device design, thereby improving the performance degradation of the device caused by the influence of the environmental factors on the doped compound semiconductor layer 116 in the process. In some embodiments, the opening OP₁Width W of₁Is a side edge E₁And side edge E₂The distance D between the two₁1/3-2/3, the performance degradation of the device caused by the environmental factors of the doped compound semiconductor layer 116 during the manufacturing process can be improved without substantially affecting the original functions and characteristics of the doped compound semiconductor layer 116. In addition, since the area of the doped compound semiconductor layer 116 is reduced, the control capability of the gate electrode 118 is prevented from being deteriorated due to the influence of environmental factors on the doped compound semiconductor layer in the process, thereby improving the current driving capability.

According to some embodiments of the present invention, the material of the doped compound semiconductor layer 116 may be p-type doped or n-type doped GaN. The thickness of the doped compound semiconductor layer 116 may be about 50nm to about 150 nm. The step of forming the doped compound semiconductor layer 116 may include: a doped compound semiconductor is deposited on the barrier layer 113 and a patterned shield layer is formed on the doped compound semiconductor through an epitaxial growth process, and then an etching process is performed on the doped compound semiconductor to remove a portion of the doped compound semiconductor not covered by the patterned shield layer, thereby forming a doped compound semiconductor layer 116 corresponding to a position where the gate electrode 118 is intended to be formed. Then, the patterned mask is removed. The patterned mask layer may be a hard mask or a photoresist. In some embodiments, the doped compound semiconductor layer may be deposited in-situ (in-situ) in the same deposition chamber as the seed layer, buffer layer 111, channel layer 112, and barrier layer 113. The doped compound semiconductor layer 116 may have a rectangular cross section as shown in fig. 2, or may have another shape, for example, a trapezoidal cross section. Further, the upper surface of the doped compound semiconductor layer 116 may not be flat.

In other embodiments, the doped compound semiconductor layer 116 may comprise other p-type doped group III-V semiconductors, such as: AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs. In addition, the doped compound semiconductor layer 108 may also include p-type doped II-VI semiconductors, such as: CdS, CdTe, or ZnS. In some embodiments, the doped compound semiconductor layer 116 can Be doped with elements such as Li, Be, C, Na, Mg, Zn, Ca, Sr, Ba, Ra, Ag, Au, etc., while the doped compound semiconductor layer 116 is p-type doped.

With continued reference to fig. 2, a dielectric layer 117 is disposed on the barrier layer 113 and the doped compound semiconductor layer 116, a gate electrode 118 is disposed on the doped compound semiconductor layer 116 and embedded in the dielectric layer 117, and a gate metal layer 119 is disposed on the dielectric layer 117 and can serve as a gate field plate. As described above, the gate electrode 118 is disposed on the doped compound semiconductor layer 116, and the doped compound semiconductor layer 116 can suppress the generation of the two-dimensional electron gas (2DEG) under the gate electrode 118 to achieve the normally-off state of the semiconductor device. Dielectric layer 117 may comprise one or more single or multiple layers of dielectric materials, such as: silicon oxide, silicon nitride, silicon oxynitride, Tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. The low-k dielectric material may include (but is not limited to): fluorinated Silica Glass (FSG), Hydrogen Silsesquioxane (HSQ), carbon doped silicon oxide, amorphous carbon fluoride (fluorinated carbon), parylene, benzocyclobutene (BCB), or polyimide (polyimide). For example, the dielectric layer 117 may be formed by spin coating (spin coating), chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, other suitable methods, or a combination thereof.

The material of the gate electrode 118 may be a conductive material, such as: metals, metal nitrides or semiconductor materials, for example, the metals may be: au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, similar materials, combinations of the foregoing, or multilayer structures of the foregoing; the metal nitride may be: MoN, WN, TiN, TaN, or similar material; the semiconductor material may be: polycrystalline silicon or polycrystalline germanium. The aforementioned conductive materials may be formed by a deposition process, such as: chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD), such as sputtering or evaporation, and then patterning the conductive material to form the gate electrode 118. In some embodiments, the gate metal layer 119 may be formed by a similar method. Gate metal layer 119 may comprise the same or similar material as gate electrode 118 and may be formed by the same process or a different process. The material of the gate metal layer 119 may include: NiSi, CoSi, TaC, TaSiN, TaCN, TiAl, TiAlN, metal oxides, metal alloys, other suitable conductive materials, or combinations of the foregoing.

As shown in fig. 2, the source structure and the drain structure are disposed on two sides of the barrier layer 113. The source structure may include a source electrode 114 and a source metal layer 122 disposed on the source electrode 114, and the drain structure may include a drain electrode 115 and a drain metal layer 123 disposed on the drain electrode 115. In some embodiments, the method of forming the source electrode 114 and the drain electrode 115 includes: a patterning process is performed on the barrier layer to form a pair (or a plurality) of openings in the barrier layer, and then a planarization process (e.g., chemical mechanical polishing) or an etchback (etchback) process is performed to fill the openings with a conductive material to remove excess material outside the openings, thereby forming the source electrode 114 and the drain electrode 115. In other embodiments, a similar process may be performed to form the source electrode 114 and the drain electrode 115 after the dielectric layer 117 is formed. The conductive material and the method of forming the same are similar to the conductive material of the gate electrode 118. In some embodiments, the source metal layer 122 or the drain metal layer 123 may be formed in a subsequent process by a similar method. According to some embodiments of the present invention, the gate electrode 118 may be formed in a similar manner as the source electrode 114 and the drain electrode 115.

In some embodiments, the source metal layer 122 may be directly on and in direct contact with the source electrode 114, or electrically connected to the source electrode 114 through a contact. Similarly, the drain metal layer 123 may be directly on and in direct contact with the drain electrode 115, or may be electrically connected to the drain electrode 115 through a contact. For example, the source electrode 114 of the source structure is embedded in the dielectric layer 117, and the source metal layer 122 of the source structure may be disposed on the dielectric layer 117, wherein the source electrode 114 and the source metal layer 122 are electrically connected by a source contact embedded in the dielectric layer 117. The potential of the source metal layer 122 electrically connected to the source electrode 114 is different from the potential of the gate metal layer 119 electrically connected to the gate electrode 118. in such embodiments, the source metal layer 122 extends in a direction from the source structure to the drain structure and acts as a source field plate (source field plate), thereby reducing the electric field strength. In other embodiments, the source electrode 114 and the drain electrode 115 may contact the channel layer 112 through the barrier layer 113. The source metal layer 122 and the drain metal layer 123 may include the same or similar material as the source electrode 114 and the drain electrode 115, and may be formed by the same process or by different processes. In some embodiments, the materials of the source metal layer 122 and the drain metal layer 123 may include: NiSi, CoSi, TaC, TaSiN, TaCN, TiAl, TiAlN, metal oxides, metal alloys, other suitable conductive materials, or combinations of the foregoing.

In addition, as described above, the doped compound semiconductor layer 116, which is affected by the environment (e.g., temperature or elements in the environment) during the process, may generate a deactivation phenomenon. Deactivation may cause poor control of the gate electrode 118, thereby affecting current drive capability. Therefore, in order to reduce the proportion of the doped compound semiconductor layer 116 in the device design, the embodiment of the invention has the opening OP₁The doped compound semiconductor layer 116 reduces the area of the doped compound semiconductor layer 116 in the semiconductor structure 200, thereby improving the controllability of the gate electrode 118 due to the environmental factors affecting the doped compound semiconductor layer 116 in the process, and further improving the current driving capability and electrical uniformity. For example, under the same conditions (e.g., the same voltage), there is an opening OP₁The doped compound semiconductor layer 116 can increase the driving current of the device by more than about 25%. According to some embodiments, the opening OP₁Width W of₁Is a side edge E₁And side edge E₂Distance D of₁1/3-2/3, the control capability of the gate electrode 118 is improved due to the environmental effect of the doped compound semiconductor layer 116 in the process, and the current driving capability is improved without substantially affecting the original functions and characteristics of the compound semiconductor layer 116.

In some embodiments, the semiconductor structure 200 may further include a passivation layer and a liner layer (not shown). A protective layer may be disposed on sidewalls and a portion of an upper surface of the doped compound semiconductor layer 116, and a portion of an upper surface of the barrier layer 113. In some embodiments, the protective layer can repair lattice defects on the sidewalls of the doped compound semiconductor layer 116 caused by the aforementioned etching process, thereby reducing gate leakage current of the formed device. In addition, the passivation layer formed on a portion of the upper surface of the barrier layer 113 can be used to prevent the barrierThe surface of layer 113 is oxidized to enhance the performance of the resulting device. The thickness of the protective layer may be from about 0.5nm to about 500nm, depending on the process requirements or device design. The material of the protective layer may comprise an insulating material or a dielectric material, for example: SiO 2₂、SiN、SiON、Al₂O₃、AlN、MgO、Mg₃N₂、ZnO、TiO₂Combinations of the foregoing, or the like.

In some embodiments, the material of the protective layer is a nitride, such as silicon nitride or aluminum nitride, which can preferably repair lattice defects of the sidewalls of the doped compound semiconductor layer 116. In some embodiments, the aforementioned material layer may be formed over the substrate 110 by chemical vapor deposition, such as plasma-assisted chemical vapor deposition, atomic layer deposition, physical vapor deposition (e.g., sputtering), or the like, and patterned to form a protective layer. In other embodiments, the patterning process may completely remove the passivation layer on the top surface of the doped compound semiconductor layer 116, such that the passivation layer is on the sidewalls of the doped compound semiconductor layer 116 and the top surface of the barrier layer 113.

In some embodiments, a liner layer may be disposed on the bottom and portions of the sidewalls of the source electrode 114 and the drain electrode 115, and on a portion of the upper surface of the barrier layer 113. In some embodiments, the liner helps to generate more two-dimensional electron gas (2DEG) at the heterointerface between the source electrode 114 and the drain electrode 115 to reduce the contact resistance (R) between the source electrode 114 and the drain electrode 115 and the channel layer 112_contact) Thereby reducing the on-resistance of the semiconductor structure. In addition, the liner layer formed on a portion of the upper surface of the barrier layer 113 can be used to prevent oxidation of the surface of the barrier layer 113, thereby improving the performance of the device formed.

In some embodiments, the material of the underlayer may comprise a binary compound semiconductor of the hexagonal system (hexagonal crystal), such as: AlN, ZnO, InN, combinations of the foregoing, or similar materials, and may be deposited by atomic layer deposition or epitaxial growth processes (e.g., metal organic chemical vapor deposition). In one embodiment, the liner layer is formed by mocvd (metal organic chemical vapor deposition), and since mocvd is a Selective Area Growth (SAG) process, the liner layer is formed on the area of the upper surface of the barrier layer 113 not covered by the passivation layer to contact the passivation layer, but not formed on the passivation layer. In another embodiment, the liner layer formed by atomic layer deposition is not only formed on the area of the upper surface of the barrier layer 113 not covered by the protection layer, but also extends to the protection layer. In addition, in other embodiments, the material of the underlayer may further include graphene (graphene) having a hexagonal system, and the underlayer may be formed by chemical vapor deposition or atomic layer deposition. In some embodiments, the material of the liner layer may be the same as the material of the protective layer, e.g., both are AlN. In other embodiments, the material of the liner layer is different from that of the protective layer, for example, the liner layer is AlN and the protective layer is aluminum silicide SiN.

Fig. 3 is a partial top projection view of a semiconductor structure, according to some embodiments of the present invention. Fig. 4 is a schematic cross-sectional view of fig. 3A-a', according to some embodiments of the invention. The semiconductor structure 400 is similar to the semiconductor structure 200 except that the doped compound semiconductor layer 316 of the semiconductor structure 400 has two openings, and for simplicity, the same components as those of fig. 2 are given the same reference numerals in fig. 4 and their descriptions are omitted. As shown in FIG. 4, the doped compound semiconductor layer 316 has a side E adjacent to the source structure₃Side E adjacent to the drain structure₄And an opening OP_3aAnd OP_3b. Side edge E₃And side edge E₄Has a spacing of D₃Opening OP_3aHas a width of W_3aAnd an opening OP_3bHas a width of W_3bThe two openings expose part of barrier layer 113. The semiconductor structure 400 includes a substrate having an opening OP_3aAnd OP_3bAs described above, since the area of the doped compound semiconductor layer 316 in the semiconductor structure 400 is reduced, the control capability of the gate electrode 118 may be deteriorated due to the influence of the environmental factors on the doped compound semiconductor layer 316 during the process, thereby improving the current driving capability.

According to some embodiments, the opening OP_3aWidth W of_3aAnd opening OP_3bWidth W of_3bSum of side E₃And side edge E₄Distance D of₃1/3-2/3, the control capability of the gate electrode 118 is improved due to the influence of environmental factors on the doped compound semiconductor layer 316 in the process, and the current driving capability is improved without substantially affecting the original functions and characteristics of the compound semiconductor layer 316. It should be noted that the number of openings shown in fig. 4 is only an example, and the number of openings of the compound semiconductor layer in the embodiment of the invention may be more than two. In some embodiments where the compound semiconductor layer has more than two openings, the width of the openings and the distance between the side of the doped compound semiconductor layer adjacent to the source structure and the side of the doped compound semiconductor layer adjacent to the drain structure are 1/3-2/3, which, as described above, can improve the controllability of the gate electrode without substantially affecting the original functions and characteristics of the compound semiconductor layer, thereby improving the current driving capability. In some embodiments, the semiconductor structure 400 may also include a protective layer and/or a liner layer, for example, to reduce gate leakage and/or reduce on-resistance of the formed device, and to prevent oxidation of the surface of the barrier layer 113 to enhance the performance of the formed device. Further, as shown in the above view fig. 3, the doped compound semiconductor layer 316 has a rectangular opening OP_3aAnd an elliptical opening OP_3bIn detail, the doped compound semiconductor layer 316 has two openings OP in the a-a' direction from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure)_3aAnd OP_3bAnd an opening OP_3aAnd OP_3bHaving a maximum width sum (W) in the A-A' direction_3a+W_3b). In some embodiments, the opening OP is formed to maintain the original functions and characteristics of the doped compound semiconductor layer 316_3aAnd OP_3bMaximum width in the A-A' direction and (W)_3a+W_3b) Is the maximum width D of the doped compound semiconductor layer 316 in the A-A' direction₃1/3 to 2/3, and an opening OP_3aAnd OP_3bAdjacent minimum spacing in the A-A' direction being an opening OP_3aAnd OP_3bWidth in the A-A' directionAverage value of (i), i.e., (W)_3a+W_3b)/2. The doped compound semiconductor layer 316 having the opening can improve the control capability of the gate electrode and improve the current driving capability, as described above.

Fig. 5-11 are partial top-view illustrations of semiconductor structures, according to some variations of the present invention. Referring to FIG. 5, which includes the source electrode 114, the drain electrode 115, and the doped compound semiconductor layer 516, as shown in the above view, the doped compound semiconductor layer 516 has a rectangular opening OP_5aOval opening OP_5bAnd a triangular opening OP_5cThe doped compound semiconductor layer 516 has three openings in the a-a' direction from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure), and the opening OP_5a、OP_5bAnd OP_5cHaving a maximum width sum (W) in the A-A' direction_5a+W_5b+W_5c). In some embodiments, the opening OP is used to maintain the original function and characteristics of the doped compound semiconductor layer 516_5a、OP_5bAnd OP_5cMaximum width in the A-A' direction and (W)_5a+W_5b+W_5c) Is the maximum width D of the doped compound semiconductor layer 516 in the A-A' direction₅1/3 to 2/3, and an opening OP_5a、OP_5bAnd OP_5cAdjacent minimum spacing in the A-A' direction being an opening OP_5a、OP_5bAnd OP_5cAverage of the width in the A-A' direction, i.e., (W)_5a+W_5b+W_5c)/3. The doped compound semiconductor layer 516 with an opening can improve the control capability of the gate electrode and enhance the current driving capability.

Referring to fig. 6, which includes the source electrode 114, the drain electrode 115, and the doped compound semiconductor layer 616, as shown in the above view, the doped compound semiconductor layer 616 has a rectangular opening OP_6aAnd OP_6bAt least a portion of the doped compound semiconductor layer 616 is discontinuous in the a-a' direction from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure), and has an opening OP_6aIn a direction parallel to the A-A' directionHas a width W_6aAn opening OP_6bHaving a width W in the A-A' direction_6bWherein W is_6bGreater than W_6a. In some embodiments, the opening OP is formed to maintain the original functions and characteristics of the doped compound semiconductor layer 616_6bHas a larger width W6b that is the maximum width D of the doped compound semiconductor layer 616 in the A-A' direction₆1/3 to 2/3, and an opening OP_6aAnd opening OP_6bA spacing S in a direction B-B' perpendicular to the direction A-A₁Is the maximum width D of the doped compound semiconductor layer 616 in the A-A' direction₆1/2 of (1). The doped compound semiconductor layer 616 with the opening can improve the control capability of the gate electrode and improve the current driving capability, as described above.

Referring to fig. 7, which includes the source electrode 114, the drain electrode 115, and the doped compound semiconductor layer 716, as shown in the above view, the doped compound semiconductor layer 716 has a rectangular opening OP_7aAnd a trapezoidal opening OP_7bAnd a circular opening OP_7cAt least a portion of the doped compound semiconductor layer 716 is discontinuous in the a-a' direction from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure), and has a rectangular opening OP_7aHaving a width W in a direction parallel to the A-A' direction_7aAnd a trapezoidal opening OP_7bThe larger base in the A-A' direction has a width W_7bCircular opening OP_7cHaving a width W in the other direction parallel to the A-A' direction_7cWherein W is_7bGreater than W_7aAnd W_7c. In some embodiments, the opening OP is formed to maintain the original functions and characteristics of the doped compound semiconductor layer 716_7bWidth W of the larger base_7bIs the maximum width D of the doped compound semiconductor layer 716 in the A-A' direction₇1/3 to 2/3, and an opening OP_7aAnd opening OP_7bA spacing S in a direction B-B' perpendicular to the direction A-A₂And opening OP_7bAnd opening OP_7cA spacing S in a direction B-B' perpendicular to the direction A-A₃Is the smallest value of the doped compound semiconductor layer 716 in the A-A' directionMaximum width D₇1/2 of (1). The doped compound semiconductor layer 716 with the opening can improve the control capability of the gate electrode and improve the current driving capability, as described above.

The shape of the opening of the doped compound semiconductor layer is only used as an example and is not meant to limit the embodiments of the present invention, and the shape of the opening may include: rectangular, diamond, trapezoidal, circular, oval, triangular, or combinations of the foregoing. In addition, the embodiment of the invention is also suitable for the openings with irregular shapes.

Besides the opening, the doped compound semiconductor layer may be formed on both sides E thereof in a direction parallel to A-A₅、E₆Has a gap, as shown in fig. 8, which includes a source electrode 114, a drain electrode 115, and a doped compound semiconductor layer 816, the doped compound semiconductor layer 816 has a rectangular gap N₈At least a portion of the doped compound semiconductor layer 816 is discontinuous in the a-a' direction from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure), and the gap N is₈Is oriented perpendicular to the A-A' direction and has a gap N₈The maximum width in the A-A' direction is W₈. In some embodiments, the gap N is designed to maintain the original function and characteristics of the doped compound semiconductor layer 816₈Maximum width W in A-A' direction₈Is the maximum width D of the doped compound semiconductor layer 816 in the A-A' direction₈1/3 to 2/3. The doped compound semiconductor layer 816 having the opening reduces the area of the doped compound semiconductor layer in the semiconductor structure, so that the control capability of the gate electrode can be improved due to the influence of the doped compound semiconductor layer from environmental factors in the process, and the current driving capability can be further improved.

The doped compound semiconductor layer may be formed on both sides E of the doped compound semiconductor layer in a direction parallel to A-A₇、E₈Has more than one notch to form an M-shape or comb shape (comb shape), as shown in fig. 9, which includes a source electrode 114, a drain electrode 115, and a doped compound semiconductor layer 916, wherein the doped compound semiconductor layer 916 has a partial oval notchMouth N_9aAnd a triangular notch N_9bAt least a portion of the doped compound semiconductor layer 916 is discontinuous in the direction a-a 'from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure), and the two notches are oriented perpendicular to the direction a-a' and are partially elliptical notches N_9aAnd a triangular notch N_9bHaving a maximum width sum (W) in the A-A' direction_9a+W_9b). In some embodiments, the local oval notch N is designed to maintain the original function and characteristics of the doped compound semiconductor layer 916_9aAnd a triangular notch N_9bMaximum width in the A-A' direction and (W)_9a+W_9b) Is the maximum width D of the doped compound semiconductor layer 916 in the A-A' direction₉1/3 to 2/3, and an oval notch N_9aAnd a triangular notch N_9bThe adjacent minimum spacing in the A-A' direction is an elliptical notch N_9aAnd a triangular notch N_9bAverage of the width in the A-A' direction, i.e., (W)_9a+W_9b)/2. The doped compound semiconductor layer 916 with the gap can improve the control capability of the gate electrode and enhance the current driving capability, as described above.

Referring to fig. 10 including the source electrode 114, the drain electrode 115, and the dopant compound semiconductor layer 1016, as shown in the top view, the dopant compound semiconductor layer 1016 has a U-shape, at least a portion of the dopant compound semiconductor layer 1016 is discontinuous in a-a ' direction from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure), and a gap of the dopant compound semiconductor layer 1016 is oriented perpendicular to the a-a ' direction and has a maximum width W in the a-a ' direction₁₀. In some embodiments, the gap has a maximum width W in the A-A' direction to maintain the original function and characteristics of the doped compound semiconductor layer 1016₁₀Is the maximum width D of the doped compound semiconductor layer 1016 in the A-A' direction₁₀1/3 to 2/3. The doped compound semiconductor layer 1016 having the gap can improve the control capability of the gate electrode and improve the current driving capability, as described above.

The shape of the notch of the doped compound semiconductor layer is only an example, and is not intended to limit the embodiments of the present invention, and the shape of the notch may include: rectangular, trapezoidal, partially circular, partially elliptical, triangular, or combinations thereof. The embodiment of the present invention also does not limit the shape of the doped compound semiconductor layer having the notch, and may include: m-shaped, U-shaped, comb-shaped, or a combination of the foregoing.

Referring to fig. 11 including the source electrode 114, the drain electrode 115, and the doped compound semiconductor layer 1116 composed of a plurality of separated doped compound semiconductor islands, as shown in the top view, the doped compound semiconductor islands include a rectangular doped compound semiconductor island 1116a, an elliptical doped compound semiconductor island 1116b, and an elliptical doped compound semiconductor island 1116c, the doped compound semiconductor layer 1116 is discontinuous in the a-a 'direction from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure), and the doped compound semiconductor islands 1116a,1116b, and 1116c have the maximum width sum (W) in the a-a' direction_11a+W_11b+W_11c). In some embodiments, the maximum width sum (W) of the doped compound semiconductor islands 1116a,1116b and 1116c in the A-A' direction is maintained in order to maintain the original functions and characteristics of the doped compound semiconductor layer 1116_11a+W_11b+W_11c) The spacing distance between adjacent doped compound semiconductor islands in the A-A' direction is equal to₄+S₅) 1/2 to 2 times higher. The doped compound semiconductor layer 1116 formed by the plurality of separated doped compound semiconductor islands can also reduce the area of the doped compound semiconductor layer in the semiconductor structure, thereby improving the current driving capability. The shapes of the doped compound semiconductor islands described above are merely exemplary, and are not intended to limit the embodiments of the present invention, and the shapes of the doped compound semiconductor islands may include: rectangular, trapezoidal, circular, oval, triangular, or combinations of the foregoing.

Fig. 12 is a comparison of experimental data of the comparative example and the embodiment of fig. 6, wherein the Y-axis represents the electric field strength between the channel layer and the barrier layer near the surface of the semiconductor structure, the X-axis represents the position of the electric field strength in the horizontal direction of the semiconductor structure, and the origin of the X-axis represents the position of the semiconductor structure near the source, and the origin of the X-axis is away from the source and approaches the drain as the coordinate of the X-axis increases. In the embodiment of fig. 6, the doped compound semiconductor layer has no opening or gap, and the area of the doped compound semiconductor layer is reduced, so that the electric field near the surface is effectively reduced.

The doped compound semiconductor layer with the opening or the gap or the doped compound semiconductor layer with the discontinuous structure provided by the embodiment of the invention reduces the area of the doped compound semiconductor layer in the semiconductor structure, so that the control capability of a grid electrode is reduced due to the influence of environmental factors on the doped compound semiconductor layer in the process, the current driving capability and the electrical uniformity are improved, and the performance of a component is further improved. In addition, the area of the doped compound semiconductor layer in the semiconductor structure is REduced, and the electric Field near the SURface can be further REduced, so that the effect of reducing the SURface electric Field (RESURF) is achieved.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art to which the invention pertains will also appreciate that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.