阅读说明：本技术 一种具有碳化硅超级结的半导体功率器件 (Semiconductor power device with silicon carbide super junction ) 是由 原小明 于 2021-09-01 设计创作，主要内容包括：本发明公开了一种具有碳化硅超级结的半导体功率器件,是一种具有第一和第二类型栅沟槽,用于形成栅极和超级结区的SiC超级结沟槽式MOSFET。其中,栅极位于底部具有厚氧化层的第一类型栅沟槽内,超级结区围绕在完全被厚氧化层填充的第二类型栅沟槽的周围。此器件还进一步包括一个毗邻体区下表面、并临近栅沟槽的栅氧化层电场降低区。(The invention discloses a semiconductor power device with a silicon carbide super junction, which is a SiC super junction groove type MOSFET with a first type gate groove and a second type gate groove and used for forming a gate and a super junction area. Wherein the grid is positioned in the first type grid groove with the thick oxidation layer at the bottom, and the super junction area surrounds the second type grid groove which is completely filled by the thick oxidation layer. The device further includes a gate oxide field-reduction region adjacent the lower surface of the body region and adjacent the gate trench.)

1. A SiC power device comprising a super junction trench MOSFET formed within an epitaxial layer having a first conductivity type, the epitaxial layer being located over a substrate having the first conductivity type, further comprising:

a plurality of trenches surrounded by source regions of said first conductivity type in body regions of a second conductivity type and proximate to an upper surface of said epitaxial layer within the active region;

each groove comprises a first type gate groove and a second type gate groove; the first type gate groove is positioned above the second type gate groove, and the width of the first type gate groove is larger than that of the second type gate groove;

a gate electrode in said first type gate trench surrounded by a first insulating layer at the bottom of said trench and a second insulating layer on the sidewalls of said trench; the thickness of the first insulating layer is greater than that of the second insulating layer;

a super junction region surrounding a lower portion of said gate trench and comprising a first doped column region of a second conductivity type adjacent to a sidewall of said second type gate trench and a second doped column region of said first conductivity type formed side-by-side, said second doped column region being surrounded by said first doped column region, wherein said second type gate trench is completely filled with said first insulating layer;

the body region and the source region are connected to a source metal through a plurality of source contact regions.

2. The SiC power device of claim 1 wherein the epitaxial layer is a single epitaxial layer having a uniform doping concentration.

3. The SiC power device of claim 1 wherein the epitaxial layers include a lower epitaxial layer having a resistivity of R1 and an upper epitaxial layer having a resistivity of R2 located between the substrate and the super junction region, wherein R1 and R2 have a relationship of R1< R2.

4. The SiC power device of claim 1 wherein the source contact regions are trenched contact regions.

5. The SiC power device of claim 1 further including a gate oxide electric field reduction region of said second conductivity type adjacent a lower surface of said body region and adjacent said gate trench.

6. The SiC power device of claim 4 wherein the source contact region is a Ti/TiN/Al alloy.

7. The SiC power device of claim 4 wherein the source contact region is Ti/TiN/W.

8. A method for fabricating a SiC power device, comprising the steps of:

growing an epitaxial layer with a first conductivity type on a substrate with the first conductivity type, wherein the doping concentration of the epitaxial layer is lower than that of the substrate; forming a first type and a second type gate trench by performing the steps of:

(a) forming a groove mask on the upper surface of the epitaxial layer for defining a plurality of first type gate grooves;

(b) forming the first type gate trench in the epitaxial layer by etching an open region in a trench mask;

(c) forming a dielectric layer on the side wall and the bottom of the first type gate groove;

(d) removing the bottom of the first type gate trench by anisotropic etching;

(e) and carrying out anisotropic silicon etching to form a plurality of second-type gate trenches.

9. The method of manufacturing the SiC power device of claim 8, further comprising performing an angled ion implantation to implant the second conductivity type dopants into the sidewalls and bottom of the second type gate trench to form a second conductivity type doped region surrounding the second type gate trench.

10. The method of manufacturing the SiC power device of claim 9, further comprising performing a zero degree ion implantation of the second conductivity type dopant.

11. The method of manufacturing the SiC power device of claim 8, further comprising depositing a BSG layer into the trench after step (e) to form a second conductivity type doped region surrounding a lower portion of the trench.

12. The method of manufacturing the SiC power device of claim 8, further comprising the steps of:

(f) forming a first insulating layer along inner surfaces of the first-type and second-type gate trenches, wherein the second-type gate trenches are completely filled with the first insulating layer;

(g) back etching the first insulating layer along the upper part of the first type gate groove;

(h) forming a second insulating layer along the side wall of the groove to serve as a gate oxide layer;

(i) depositing a doped polysilicon layer into the first type gate trench;

(j) and etching back the first doped polysilicon layer to be used as a gate electrode.

Technical Field

The present invention relates generally to semiconductor power devices and, more particularly, to a silicon carbide (SiC) SUPER JUNCTION (SUPER JUNCTION) trench MOSFET (metal oxide semiconductor field effect transistor) having a thick oxide layer at the bottom of the trench and a p-type doped region surrounding the lower portion of the trench for forming a SUPER JUNCTION structure above the substrate to achieve lower gate oxide electric field strength, lower on-resistance, smaller gate-to-drain charge (Qgd) and lower switching loss.

Background

Due to the physical properties of SiC, SiC-MOSFETs have higher breakdown voltages, lower on-resistances and faster switching speeds than Si-MOSFETs. However, SiC-MOSFETs require higher Vgs to fully open the channel of the device due to the poor interface state between SiC and the gate oxide layer, and thus have higher gate oxide field strength than Si-MOSFETs. For example, for Si devices, Vgs 10V can fully open the device channel, but for SiC devices Vgs 18V can fully open the device channel. The higher the Vgs, the higher the gate oxide field strength, leading to reliability issues.

Another problem is that the gate oxide layer grown at the bottom of the trench of the SiC device has a much thinner thickness (about 3-5 times thinner) than the sidewall of the trench, which not only results in a larger Qgd, but also greatly increases the electric field strength of the gate oxide layer at the bottom of the trench, as shown in fig. 1. The device structure shown in fig. 1 is similar to a conventional Si trench MOSFET except that N + SiC substrate 101 and SiC epitaxial layer 102 have N + source regions 111 and P body regions 110. A gate trench 103 filling the gate electrode 105 is formed in the epitaxial layer 102, and the trench sidewalls and trench bottom of the gate trench 103 are thermally oxidized to grow gate oxide layers 109 and 106, respectively. The oxidation rate at the bottom of the trench of the Si face is the lowest in the SiC crystal face, so that the thickness of the gate oxide layer 106 is thinner than 109.

Therefore, in the field of designing and manufacturing semiconductor devices, especially in the field of designing and manufacturing SiC trench MOSFETs, there is still a need to provide a novel cell structure, device structure and manufacturing method that can solve the above-mentioned difficulties and limitations, so that SiC trench MOSFETs have lower gate oxide electric field strength, achieve lower on-resistance, smaller Qgd and lower switching loss.

Disclosure of Invention

The invention discloses a novel SiC super junction groove type MOSFET, which is provided with a first type gate groove and a second type gate groove and is used for forming a grid electrode and a super junction area, wherein the grid electrode is positioned in the first type gate groove, the bottom of the first type gate groove is provided with a thick oxidation layer, and a p-type doping area surrounds the second type gate groove so as to form the super junction area positioned on a substrate. The device is characterized in that the electric field intensity of the gate oxide layer is reduced, and meanwhile, the on-resistance generated by the formation of the super junction is reduced. The device further includes a gate oxide electric field reduction p-region adjacent a lower surface of the body region and adjacent the gate trench. Furthermore, as a unipolar device, the switching losses of SiC MOSFETs should be lower than those of IGBTs. Compared with the traditional SiC MOSFET, the SiC MOSFET has smaller Qgd and can further reduce the switching loss due to the existence of the thick bottom oxide layer of the device.

In one aspect of the invention, a SiC power device is disclosed that includes a super junction trench MOSFET formed within an epitaxial layer having a first conductivity type, the epitaxial layer being located over a substrate having the first conductivity type, further comprising: a plurality of trenches surrounded by source regions of a first conductivity type, the source regions being located in body regions of a second conductivity type and being proximate to an upper surface of the epitaxial layer within the active regions; each groove comprises a first type gate groove and a second type gate groove; the first type gate groove is positioned above the second type gate groove, and the width of the first type gate groove is larger than that of the second type gate groove; a gate electrode in the first type gate trench surrounded by the first insulating layer at the bottom of the trench and the second insulating layer at the sidewall of the trench; the thickness of the first insulating layer is larger than that of the second insulating layer; a super junction region surrounding the lower portion of the trench and including a first doped column region of the second conductivity type adjacent the sidewalls of the second-type gate trench and a second doped column region of the first conductivity type formed in parallel and surrounded by the first doped column region, wherein the second-type gate trench is completely filled with the first insulating layer; a body region and a source region connected to the source metal through a plurality of source contact regions.

According to another aspect of the invention, in some preferred embodiments, the epitaxial layer is a single epitaxial layer having a uniform doping concentration. In further preferred embodiments, the epitaxial layer comprises a lower epitaxial layer having a resistivity of R1 and an upper epitaxial layer having a resistivity of R2 located between the substrate and the superjunction region, wherein R1 and R2 have the relationship R1< R2.

According to another aspect of the invention, in some preferred embodiments, the source contact regions are trench contact regions.

In accordance with another aspect of the present invention, a trench semiconductor power device is also disclosed that further includes a gate oxide electric field reduction region having a second conductivity type adjacent a lower surface of the body region and adjacent the gate trench.

According to another aspect of the invention, in some preferred embodiments, the source contact region is a Ti/TiN/Al alloy. In other preferred embodiments, the source contact region is Ti/TiN/W.

The invention also discloses a method for manufacturing the SiC power device, which comprises the following steps: growing an epitaxial layer with a first conductivity type on a substrate with the first conductivity type, wherein the doping concentration of the epitaxial layer is lower than that of the substrate; forming a first type and a second type gate trench by performing the steps of:

(a) forming a trench mask on the upper surface of the epitaxial layer for defining a plurality of first type gate trenches;

(b) forming a first type gate trench in the epitaxial layer by etching the open region in the trench mask;

(c) forming a dielectric layer on the side wall and the bottom of the first type gate groove;

(d) removing the bottom of the first type gate trench by anisotropic etching;

(e) and carrying out anisotropic silicon etching to form a plurality of second-type gate trenches.

According to another aspect of the invention, in some preferred embodiments, a method for manufacturing a trench semiconductor power device further comprises the steps of: and performing angle ion implantation to implant second conductivity type dopants into the side walls and the bottom of the second-type gate trenches to form second conductivity type doped regions around the second-type gate trenches.

According to another aspect of the invention, in some preferred embodiments, a method for manufacturing a trench semiconductor power device further comprises the steps of: a zero degree ion implantation of a second conductivity type dopant is performed.

According to another aspect of the invention, in some preferred embodiments, a method for manufacturing a trench semiconductor power device further comprises the steps of: depositing a BSG layer into the trench after step (e) to form a second conductivity-type doped region surrounding a lower portion of the trench.

According to another aspect of the invention, in some preferred embodiments, a method for manufacturing a trench semiconductor power device further comprises the steps of:

(f) forming a first insulating layer along inner surfaces of the first-type and second-type gate trenches, wherein the second-type gate trenches are completely filled with the first insulating layer;

(g) etching back the first insulating layer along the upper part of the first type gate groove;

(h) forming a second insulating layer along the side wall of the groove to serve as a gate oxide layer;

(i) depositing a doped polysilicon layer into the first type gate trench;

(j) the first doped polysilicon layer is etched back to serve as a gate electrode.

The above and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments, which is illustrated in the various drawing figures.

Drawings

Fig. 1 is a cross-sectional view of a conventional SiC semiconductor device having a trench-gate vertical double-diffused MOSFET as disclosed in the prior art.

Fig. 2A is a cross-sectional view of a preferred embodiment according to the present invention.

Fig. 2B is a cross-sectional view of another preferred embodiment according to the present invention.

Fig. 3 is a cross-sectional view of another preferred embodiment according to the present invention.

Fig. 4 is a cross-sectional view of another preferred embodiment according to the present invention.

Fig. 5A to 5L are a series of cross-sectional views showing steps of manufacturing the SiC super junction trench MOSFET of fig. 4.

Detailed Description

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The present invention may, but need not, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. For example, the description herein makes more reference to an N-channel semiconductor integrated circuit, but it is apparent that other devices are possible. The following is a detailed description of preferred embodiments for practicing the invention, with reference to the various figures. Some directional terminology, such as "top," "bottom," "front," "back," "above," "below," etc., is described with reference to the orientation of the various figures. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used in the description above for purposes of illustration and is in no way limiting. It should be understood that various structural or logical substitutions and modifications in the embodiments are intended to be included within the true spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that the inventive features of the various preferred embodiments described herein may be combined with each other, unless specifically noted otherwise.

Figure 2A shows a preferred embodiment of the present invention. The SiC power device comprises a super junction trench MOSFET formed on an N-type SiC epitaxial layer 202, wherein the epitaxial layer 202 is positioned on an N + SiC substrate 201, and a metal layer 220 is used as a drain metal after the back surface of the N + SiC substrate 201 is coated with Ti/Ni/Ag. In N-epitaxial layer 202, a plurality of trenches are formed including a first type gate trench 203 and a second type gate trench 204 extending from an upper surface of epitaxial layer 202 down into epitaxial layer 202 without contacting interface 216 of N-epitaxial layer 202 and N + substrate 201, wherein first type gate trench 203 has a greater width than second type gate trench 204. The gate electrode 205 is located at the upper portion of the first-type gate trench 203, and is surrounded by a thick bottom oxide layer located at the bottom of the gate trench 203 and serving as a first insulating layer 206, and a second insulating layer 209 located at the sidewall of the gate trench 203, wherein the thickness of the second insulating layer 209 is smaller than that of the first insulating layer 206, and the second-type gate trench 204 is completely filled with the first insulating layer 206. Between each two adjacent first-type gate trenches 203, a p-body region 210 having an N + source region 211 is formed, extending from near the upper surface of the N-epitaxial layer 202 and surrounding the gate electrode 205 lined with a second gate insulating layer 209. A dielectric spacer layer 221 is formed over the epitaxial layer 202 and a source metal 212 is formed over the dielectric spacer layer 221. The p-body region 210 and the n + source region 211 are further connected to the source metal 212 by a plurality of trench contact regions 223, wherein the trench contact regions 223 are filled with contact plugs 213, the contact plugs 213 and the source metal 212 are both Ti/TiN/Al alloy, and the bottom of the trench contact regions 223 are surrounded by the p + body contact regions 214 located below the n + source region 211. According to the present invention, a super junction region is formed in p-body regions 215 adjacent to second-type gate trenches 204 into N-epitaxial layer 202, the super junction region including a plurality of alternating p-body regions 215 and N-regions 202 over N + substrate 201. According to the present invention, the super junction region surrounds at least a lower portion of the second-type gate trench 204, and p-region 215 is located above a bottom surface 216 of N-epitaxial layer 202. P regions 215 are formed along the sidewalls and bottom of the second-type gate trenches 204 by performing an angled boron ion implantation, or a combination of an angled and zero boron ion implantation, or a BSG layer deposition step on the sidewalls and bottom of the second-type gate trenches 204.

Fig. 2B shows a trench power device having a similar structure to the structure of fig. 2A, except that the trench source contact area 323 in the structure of the present invention is filled with a contact plug 313 of Ti/TiN/W and the source metal 312 is a Ti/TiN/Al alloy, according to another preferred embodiment of the present invention.

Fig. 3 shows a trench semiconductor power device as shown in fig. 3 formed in an epitaxial layer according to another preferred embodiment of the present invention, compared to the embodiment of the invention shown in fig. 2B, wherein the epitaxial layer further comprises a lower epitaxial layer 402-1 of N1 with resistivity R1 and an upper epitaxial layer 402-2 of N2 with resistivity R2, located between the N + substrate 401 and the super junction region, wherein the relationship between R1 and R2 is R1< R2. In addition, the super junction region includes a plurality of p regions 415 and N2 regions 402-2 alternately disposed on the lower epitaxial layer 402-1 of N1, wherein the p regions 415 are in contact with the bottom surface 416 of the upper epitaxial layer 402-2 of N2. The contact plug 413 filled in the trench source contact 423 in the structure of the present invention is Ti/TiN/W, and the source metal 412 is Al alloy.

Fig. 4 shows a trench semiconductor power device having a similar structure to the invention of fig. 3, except that in the structure of the invention, a p-type gate oxide electric field reduction region 517(Pr, as shown) is included adjacent to the lower surface of the p-body region 510 and adjacent to the gate trench, according to another preferred embodiment of the invention. The contact plug 513 filled in the trench type source contact region 523 in the structure of the invention is Ti/TiN/W, and the source metal 512 is Al alloy.

Fig. 5A-5K are a series of exemplary fabrication steps for forming the preferred embodiment of the invention of fig. 4. As shown in fig. 5A, an epitaxial layer is first formed on an N + SiC substrate 601, the epitaxial layer including an N1 lower epitaxial layer 602-1 having a resistivity of R1 and an N2 upper epitaxial layer 602-2 having a resistivity of R2, wherein the relationship of R1 and R2 is R1< R2, and the doping concentration of the epitaxial layer is lower than that of the N + substrate 601. P-body regions 610 and N + source regions 611 are then formed within the active region N2 epitaxial layer 602-2. A hard mask 613 (not shown) such as an oxide layer is formed on the top surface of the N2 epi layer 602-2 to define a plurality of first-type gate trenches 603. Subsequently, a plurality of first-type gate trenches 603 are formed by dry oxide etching and dry silicon etching, and extend into the epitaxial layer 602-2 on the N2 through the open regions in the hard mask, and the bottom of the first-type gate trenches does not contact the bottom surface 616 of the epitaxial layer 602-2 on the N2. A sacrificial oxide layer (not shown) is grown and removed to eliminate plasma damage introduced during the formation of the gate trench 603.

As shown in fig. 5B, a dielectric layer 617 is formed on the sidewalls and bottom of the first-type gate trench 603 by an oxide deposition method or a thermal oxidation growth method.

As shown in fig. 5C, the dielectric layer 617 at the bottom of the first-type gate trench 603 is removed by dry oxide etching.

As shown in fig. 5D, a plurality of second-type gate trenches 604 are formed using an anisotropic silicon etching method.

As shown in fig. 5E, an angled boron ion implantation and diffusion step are sequentially performed on the sidewalls and bottom of the second-type gate trench 604 to form p regions 615 surrounding the second-type gate trench 604. Furthermore, if the bottom of the gate trench 604 is too narrow, a combination of zero and angled implants may be used to achieve the boron ion implant.

As shown in fig. 5F, depositing a BSG layer in the two types of trenches provides another method for forming p regions 615 around the second type of trench 604.

As shown in fig. 5G, the dielectric layer 617 is removed.

As shown in fig. 5H, a thick oxide layer is grown as a first insulating layer 606 along the inner walls of the two types of gate trenches 603 and 604 and the upper surface of the epitaxial layer 602-2 on N2 by a thermal oxide growth method or a thick oxide deposition method, wherein the second type of gate trench 604 is completely filled with the first insulating layer 606.

As shown in fig. 5I, the first insulating layer 606 is etched back from the upper surface of the epitaxial layer 602-2 on N2 and the upper portion of the first-type gate trench 603.

As shown in fig. 5J, a second insulating layer 609 is formed as a gate oxide layer along the sidewalls of the first-type gate trench 603 and the upper surface of the epitaxial layer 602-2 on N2 by using a thermal growth method or a deposition method, and the thickness of the second insulating layer 609 is thinner than that of the first insulating layer 606. Subsequently, a first doped polysilicon layer is deposited on the first gate insulating layer 606, filling the upper portion of the first type gate trench 603, and then etched back by using a CMP method (chemical mechanical polishing method) or a plasma etching method to serve as the single gate electrode 605.

As shown in fig. 5K, a second dielectric layer, which is an undoped oxide layer and a BPSG layer, is formed on the top surface of the entire structure by conventional techniques. A mask (not shown) is applied to the top surface of the second dielectric layer and etched back to form the dielectric spacer 621. A contact mask (not shown) is applied over the spacer 621 to form a plurality of trench contact 623 by a sequential dry oxide etch and dry silicon etch. The trench contact 623 extends through the dielectric spacer 621 and the n + source 611 into the p body 610, forming a trench source-body contact. A p-type gate oxide field-reducing region 617(Pr, as shown) is then formed adjacent the lower surface of p-body region 610 and adjacent trench 603 by performing a boron ion implantation. Subsequently, BF2 ion implantation is performed to form a p + body contact doped region 614 within the p body region 610, surrounding at least the bottom of the trenched source-body contact region. A Ti/TiN barrier metal layer is deposited on the sidewalls and bottom of the trench contact 623 followed by an RTA operation for silicide formation. A W metal layer is deposited over the barrier metal layer and the W metal layer and barrier metal layer are etched back to form a Ti/TiN/W contact metal plug 613 in the trench source-body contact region.

As shown in FIG. 5L, an Al alloy metal layer is deposited on the top surface of the dielectric spacer 621, and the Al alloy metal layer is lined with a Ti or Ti/TiN resist-reducing layer. Subsequently, a metal mask (not shown) is covered, and the metal layer is etched to form a source metal 612.

While the invention has been described in terms of preferred embodiments, it is to be understood that the above disclosure is not to be considered as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above disclosure. Therefore, the appended claims should be construed to cover all such alternatives and modifications as fall within the true spirit and scope of the invention.