阅读说明：本技术 一种晶体管及其制作方法 (Transistor and manufacturing method thereof ) 是由 张璐 于 2021-09-18 设计创作，主要内容包括：本申请公开了一种晶体管及其制作方法,该晶体管包括衬底；设于衬底上的六方氮化硼绝缘层；设于六方氮化硼绝缘层上的沟道层、源电极和漏电极,沟道层包括多层不同种类的二维半导体层,源电极和漏电极分别与沟道层的端部接触,六方氮化硼绝缘层和二维半导体层在制备时分别经过退火处理得到。晶体管中绝缘层为六方氮化硼绝缘层,厚度非常薄,可以降低晶体管的阈值电压和功耗,沟道层包括多层不同种类的二维半导体层,不同的二维半导体层之间通过范德瓦尔斯力结合,不同种类的二维半导体层可提高晶体管的开关比；六方氮化硼绝缘层和二维半导体层在制备时分别经过退火处理得到,可使相邻的两种层结构形成良好的范德瓦尔斯界面,提升晶体管的性能。(The application discloses a transistor and a manufacturing method thereof, wherein the transistor comprises a substrate; a hexagonal boron nitride insulating layer disposed on the substrate; the channel layer comprises a plurality of layers of different two-dimensional semiconductor layers, the source electrode and the drain electrode are respectively contacted with the end part of the channel layer, and the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer are respectively obtained by annealing treatment during preparation. The insulating layer in the transistor is a hexagonal boron nitride insulating layer, the thickness is very thin, the threshold voltage and the power consumption of the transistor can be reduced, the channel layer comprises a plurality of layers of different two-dimensional semiconductor layers, the different two-dimensional semiconductor layers are combined through Van der Waals force, and the on-off ratio of the transistor can be improved through the different two-dimensional semiconductor layers; the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer are obtained by annealing treatment during preparation, so that good van der Waals interfaces can be formed between two adjacent layer structures, and the performance of the transistor is improved.)

1. A transistor, comprising:

a substrate;

a hexagonal boron nitride insulating layer disposed on the substrate;

the hexagonal boron nitride semiconductor structure comprises a channel layer, a source electrode and a drain electrode which are arranged on the hexagonal boron nitride insulating layer, wherein the channel layer comprises a plurality of layers of two-dimensional semiconductor layers of different types, the source electrode and the drain electrode are respectively contacted with the end part of the channel layer, and the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layers are respectively obtained through annealing treatment during preparation.

2. The transistor according to claim 1, wherein the number of the two-dimensional semiconductor layers in the channel layer is two layers.

3. The transistor according to claim 1 or 2, wherein a material of the two-dimensional semiconductor layer is a transition metal disulfide.

4. A method for manufacturing a transistor, comprising:

preparing a hexagonal boron nitride insulating layer;

transferring the hexagonal boron nitride insulating layer to the upper surface of a substrate, and annealing the substrate with the hexagonal boron nitride insulating layer;

preparing different kinds of two-dimensional semiconductor layers;

transferring the two-dimensional semiconductor layers of different types to enable the two-dimensional semiconductor layers to be sequentially laminated on the upper surface of the hexagonal boron nitride insulating layer, and carrying out annealing treatment after each two-dimensional semiconductor layer is transferred to form a channel layer;

and depositing a source electrode and a drain electrode on the upper surface of the hexagonal boron nitride insulating layer, wherein the source electrode and the drain electrode are respectively contacted with the end parts of the channel layer.

5. The method for fabricating a transistor according to claim 4, wherein said fabricating a hexagonal boron nitride insulating layer comprises:

and thinning the cubic boron nitride crystal block by adopting a mechanical stripping method to obtain the hexagonal boron nitride insulating layer.

6. The method of fabricating a transistor according to claim 5, wherein said transferring said hexagonal boron nitride insulating layer to an upper surface of a substrate comprises:

preparing a PDMS matrix, wherein the weight ratio of the basic components to the curing agent is 10: 1;

transferring the hexagonal boron nitride insulating layer to the PDMS substrate;

fixing the substrate on a rotating base of transfer equipment, and fixing the PDMS base with the hexagonal boron nitride insulating layer on a glass slide, wherein the hexagonal boron nitride insulating layer is opposite to the substrate;

adjusting the position of the substrate to the focal length of a microscope under the maximum magnification, and adjusting the position of the hexagonal boron nitride insulating layer to enable the hexagonal boron nitride insulating layer to be in contact with the substrate for preset time;

and removing the PDMS matrix, and transferring the hexagonal boron nitride insulating layer to the upper surface of the substrate.

7. The method of fabricating a transistor according to claim 4, wherein said preparing different kinds of two-dimensional semiconductor layers comprises:

and thinning the two-dimensional semiconductor bulk materials of different types by adopting a mechanical stripping method to obtain two-dimensional semiconductor layers of different types correspondingly.

8. The method for manufacturing a transistor according to claim 7, wherein when the two-dimensional semiconductor layer to be manufactured includes two-dimensional semiconductor layers having a number of layers exceeding a preset threshold, after the manufacturing of the two-dimensional semiconductor layers of different types, the method further includes:

and screening out the two-dimensional semiconductor layers with the layer number smaller than the preset threshold value by adopting an optical contrast method.

9. The method for manufacturing a transistor according to claim 8, wherein the transferring the two-dimensional semiconductor layers of different types such that the two-dimensional semiconductor layers are sequentially stacked on the upper surface of the hexagonal boron nitride insulating layer, and performing an annealing process after the transferring of each of the two-dimensional semiconductor layers to form a channel layer comprises:

step S1: fixing the substrate with the hexagonal boron nitride insulating layer on a rotating base of transfer equipment, and fixing the PDMS base with the two-dimensional semiconductor layer on a glass slide, wherein the two-dimensional semiconductor layer is opposite to the upper surface of the substrate;

step S2: adjusting the position of the two-dimensional semiconductor layer to the focal length of a microscope under the maximum magnification, marking a first outline of the two-dimensional semiconductor layer, and removing the two-dimensional semiconductor layer;

step S3: adjusting the focal distance from the film layer on the upper surface of the substrate to the microscope at the maximum magnification, and marking a second contour of the film layer on the upper surface of the substrate;

step S4: enabling the two-dimensional semiconductor layer to be in contact with a film layer on the upper surface of the substrate for a preset time according to the first contour and the second contour;

step S5: and removing the PDMS matrix, transferring the two-dimensional semiconductor layer to the substrate, annealing the substrate with the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer to obtain a new substrate, transferring different types of new two-dimensional semiconductor layers to the PDMS matrix, and returning to the step S1 until all the two-dimensional semiconductor layers are transferred.

10. The method of fabricating a transistor according to claim 9, wherein before bringing the two-dimensional semiconductor layer into contact with the hexagonal boron nitride insulating layer according to the first profile and the second profile for a predetermined time, further comprising:

rotating the rotating base to bring the second profile into perfect alignment with the first profile;

before the step of contacting the new two-dimensional semiconductor layer with the two-dimensional semiconductor layer according to the third profile and the fourth profile for a preset time, the method further includes:

rotating the rotating base brings the fourth profile into perfect alignment with the third profile.

Technical Field

The present disclosure relates to a transistor technology field, and more particularly, to a transistor and a method for fabricating the same.

Background

With the development of technology, the requirement for heat dissipation of integrated circuits is higher and higher, and how to enhance heat dissipation is always the focus of industrial research. The transistor is a basic unit of the integrated circuit, reduces the power consumption of a single transistor, and can effectively inhibit the heat of a unit area in the integrated circuit, thereby improving the integration level and the performance. At present, transistors are generally based on crystalline silicon, most of channel layers can be formed by amorphous silicon layers, and the channel length of the transistors is shortened to tens of nanometers. In light of this trend, silicon-based integrated circuit technology has reached size limits in recent years and has not been able to continue to evolve.

Therefore, how to solve the above technical problems should be a great concern to those skilled in the art.

Disclosure of Invention

The invention aims to provide a transistor and a manufacturing method thereof, so that the power consumption of the transistor is reduced, and the switching ratio and the performance of the transistor are improved.

In order to solve the above technical problem, the present application provides a transistor, including:

a substrate;

a hexagonal boron nitride insulating layer disposed on the substrate;

the hexagonal boron nitride semiconductor structure comprises a channel layer, a source electrode and a drain electrode which are arranged on the hexagonal boron nitride insulating layer, wherein the channel layer comprises a plurality of layers of two-dimensional semiconductor layers of different types, the source electrode and the drain electrode are respectively contacted with the end part of the channel layer, and the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layers are respectively obtained through annealing treatment during preparation.

Optionally, the number of the two-dimensional semiconductor layers in the channel layer is two.

Optionally, the material of the two-dimensional semiconductor layer is a transition metal disulfide.

The application also provides a transistor manufacturing method, which comprises the following steps:

preparing a hexagonal boron nitride insulating layer;

transferring the hexagonal boron nitride insulating layer to the upper surface of a substrate, and annealing the substrate with the hexagonal boron nitride insulating layer;

preparing different kinds of two-dimensional semiconductor layers;

transferring the two-dimensional semiconductor layers of different types to enable the two-dimensional semiconductor layers to be sequentially laminated on the upper surface of the hexagonal boron nitride insulating layer, and carrying out annealing treatment after each two-dimensional semiconductor layer is transferred to form a channel layer;

and depositing a source electrode and a drain electrode on the upper surface of the hexagonal boron nitride insulating layer, wherein the source electrode and the drain electrode are respectively contacted with the end parts of the channel layer.

Optionally, the preparing the hexagonal boron nitride insulating layer includes:

and thinning the cubic boron nitride crystal block by adopting a mechanical stripping method to obtain the hexagonal boron nitride insulating layer.

Optionally, the transferring the hexagonal boron nitride insulating layer to the upper surface of the substrate includes:

preparing a PDMS matrix, wherein the weight ratio of the basic components to the curing agent is 10: 1;

transferring the hexagonal boron nitride insulating layer to the PDMS substrate;

fixing the substrate on a rotating base of transfer equipment, and fixing the PDMS base with the hexagonal boron nitride insulating layer on a glass slide, wherein the hexagonal boron nitride insulating layer is opposite to the substrate;

adjusting the position of the substrate to the focal length of a microscope under the maximum magnification, and adjusting the position of the hexagonal boron nitride insulating layer to enable the hexagonal boron nitride insulating layer to be in contact with the substrate for preset time;

and removing the PDMS matrix, and transferring the hexagonal boron nitride insulating layer to the upper surface of the substrate.

Optionally, the preparing the different kinds of two-dimensional semiconductor layers includes:

and thinning the two-dimensional semiconductor bulk materials of different types by adopting a mechanical stripping method to obtain two-dimensional semiconductor layers of different types correspondingly.

Optionally, when the prepared two-dimensional semiconductor layer includes a two-dimensional semiconductor layer whose number of layers exceeds a preset threshold, after preparing different types of two-dimensional semiconductor layers, the method further includes:

and screening out the two-dimensional semiconductor layers with the layer number smaller than the preset threshold value by adopting an optical contrast method.

Optionally, the transferring the different types of the two-dimensional semiconductor layers may be performed such that the two-dimensional semiconductor layers are sequentially stacked on the upper surface of the hexagonal boron nitride insulating layer, and the annealing process is performed after each layer of the two-dimensional semiconductor layers is transferred, so as to form a channel layer, where the annealing process includes:

step S1: fixing the substrate with the hexagonal boron nitride insulating layer on a rotating base of transfer equipment, and fixing the PDMS base with the two-dimensional semiconductor layer on a glass slide, wherein the two-dimensional semiconductor layer is opposite to the upper surface of the substrate;

step S2: adjusting the position of the two-dimensional semiconductor layer to the focal length of a microscope under the maximum magnification, marking a first outline of the two-dimensional semiconductor layer, and removing the two-dimensional semiconductor layer;

step S3: adjusting the focal distance from the film layer on the upper surface of the substrate to the microscope at the maximum magnification, and marking a second contour of the film layer on the upper surface of the substrate;

step S4: enabling the two-dimensional semiconductor layer to be in contact with a film layer on the upper surface of the substrate for a preset time according to the first contour and the second contour;

step S5: and removing the PDMS matrix, transferring the two-dimensional semiconductor layer to the substrate, annealing the substrate with the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer to obtain a new substrate, transferring different types of new two-dimensional semiconductor layers to the PDMS matrix, and returning to the step S1 until all the two-dimensional semiconductor layers are transferred. Optionally, before contacting the two-dimensional semiconductor layer with the hexagonal boron nitride insulating layer according to the first profile and the second profile for a preset time, the method further includes:

rotating the rotating base to bring the second profile into perfect alignment with the first profile;

before the step of contacting the new two-dimensional semiconductor layer with the two-dimensional semiconductor layer according to the third profile and the fourth profile for a preset time, the method further includes:

rotating the rotating base brings the fourth profile into perfect alignment with the third profile.

The application provides a transistor, which comprises a substrate; a hexagonal boron nitride insulating layer disposed on the substrate; the hexagonal boron nitride semiconductor structure comprises a channel layer, a source electrode and a drain electrode which are arranged on the hexagonal boron nitride insulating layer, wherein the channel layer comprises a plurality of layers of two-dimensional semiconductor layers of different types, the source electrode and the drain electrode are respectively contacted with the end part of the channel layer, and the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layers are respectively obtained through annealing treatment during preparation.

Therefore, in the application, the transistor insulating layer is a hexagonal boron nitride insulating layer, the hexagonal boron nitride is a two-dimensional crystal material, the thickness is very thin, the threshold voltage and the power consumption of the transistor can be reduced, the channel layer comprises a plurality of layers of different two-dimensional semiconductor layers, and the different two-dimensional semiconductor layers are combined through Van der Waals force, so that the crystal structures and lattice constants of the different two-dimensional semiconductor layers and the hexagonal boron nitride insulating layer do not need to be matched, a heterostructure can be directly formed, and the on-off ratio of the transistor can be improved through the different two-dimensional semiconductor layers; and the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer are obtained by annealing treatment during preparation respectively, so that a good van der Waals interface can be formed between two adjacent layer structures, the electron mobility and the uniformity of carriers can be improved, and the performance of the transistor can be improved.

In addition, the application also provides a transistor manufacturing method with the advantages.

Drawings

For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure;

fig. 2 is a flowchart illustrating a method for fabricating a transistor according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a transfer apparatus in the present application.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

As described in the background section, the transistors are currently generally crystalline silicon-based transistors, and the channel layer can be formed mostly of an amorphous silicon layer, and the channel length of the transistors has been shortened to tens of nanometers. In light of this trend, silicon-based integrated circuit technology has reached size limits in recent years and has not been able to continue to evolve.

In view of the above, the present application provides a transistor, please refer to fig. 1, where fig. 1 is a schematic structural diagram of a transistor according to an embodiment of the present application, including:

a substrate 1;

a hexagonal boron nitride insulating layer 2 provided on the substrate 1;

the structure of the hexagonal boron nitride semiconductor device comprises a channel layer, a source electrode 4 and a drain electrode 5 which are arranged on the hexagonal boron nitride insulating layer 2, wherein the channel layer comprises a plurality of layers of two-dimensional semiconductor layers 3 of different types, the source electrode 4 and the drain electrode 5 are respectively contacted with the end part of the channel layer, and the hexagonal boron nitride insulating layer 2 and the two-dimensional semiconductor layers 3 are respectively obtained through annealing treatment during preparation.

The substrate 1 is a silicon-based substrate 1 having a layer of silicon dioxide on its upper surface.

The number of the two-dimensional semiconductor layers 3 included in the channel layer is not limited in the present application as appropriate. For example, the number of layers of the two-dimensional semiconductor layer 3 is two, three, four, five, and so on, and two layers are exemplified in fig. 1. The properties of the two-dimensional semiconductor layers 3 with different numbers of layers are greatly different, so that the electrical performance of the transistor can be adjusted and controlled simply by controlling the number of the layers of the two-dimensional semiconductor layers 3.

The material of the two-dimensional semiconductor layer 3 may be a transition metal disulfide, such as tungsten disulfide, molybdenum disulfide, or the like, or the material of the two-dimensional semiconductor layer 3 may be a transition metal diselenide, such as tungsten diselenide, molybdenum diselenide, or the like.

The hexagonal boron nitride insulating layer 2 and the two-dimensional semiconductor layer 3 are obtained by annealing treatment during preparation, namely, after the hexagonal boron nitride insulating layer 2 is prepared on the substrate 1, the annealing treatment is performed once, and after the two-dimensional semiconductor layer 3 of each layer is prepared, the annealing treatment is performed once.

The source electrode 4 and the drain electrode 5 may be generally metal electrodes such as a chromium electrode, a gold electrode, or the like.

In the application, the transistor insulating layer is a hexagonal boron nitride insulating layer 2, the hexagonal boron nitride is a two-dimensional crystal material, the thickness is very thin, the threshold voltage and the power consumption of the transistor can be reduced, the channel layer comprises a plurality of layers of different two-dimensional semiconductor layers 3, and the different two-dimensional semiconductor layers 3 are combined through Van der Waals force, so that the crystal structures and lattice constants of the different two-dimensional semiconductor layers 3 and the hexagonal boron nitride insulating layer 2 do not need to be matched, a heterostructure can be directly formed, and the different two-dimensional semiconductor layers 3 can improve the on-off ratio of the transistor; moreover, the hexagonal boron nitride insulating layer 2 and the two-dimensional semiconductor layer 3 are obtained by annealing treatment during preparation, so that a good van der Waals interface can be formed between two adjacent layer structures, the electron mobility and the uniformity of carriers can be improved, and the performance of the transistor can be improved.

Referring to fig. 2, fig. 2 is a flowchart illustrating a method for fabricating a transistor according to an embodiment of the present disclosure, the method including:

step S101: and preparing the hexagonal boron nitride insulating layer.

As an implementation, a chemical vapor deposition method may be used to prepare the hexagonal boron nitride insulating layer. As another possible embodiment, the preparing the hexagonal boron nitride insulating layer includes: and thinning the cubic boron nitride crystal block by adopting a mechanical stripping method to obtain the hexagonal boron nitride insulating layer.

The mechanical stripping method comprises the following specific processes: preparing a strip-shaped adhesive tape (such as Scotch adhesive tape of 3M company), placing a cubic boron nitride (hBN) crystal block at the center of the adhesive surface of the adhesive tape, folding the adhesive tape along the central symmetrical part of the adhesive surface, and then separating the adhesive tape, repeating the steps for several times to achieve the purpose of thinning the crystal block, thereby obtaining the hexagonal boron nitride insulating layer. The method is simple and rapid to operate, has low cost, does not need a doping process, and retains the inherent properties of the material.

Step S102: and transferring the hexagonal boron nitride insulating layer to the upper surface of a substrate, and annealing the substrate with the hexagonal boron nitride insulating layer.

The transfer process is described in detail below. The annealing process is to put the substrate with the hexagonal boron nitride insulating layer into a vacuum tube furnace, and anneal for 2 hours at 200 ℃ under the protection of argon with the pressure of 5 Torr.

Step S103: two-dimensional semiconductor layers of different kinds are prepared.

As an embodiment, the preparing the different kinds of two-dimensional semiconductor layers includes: and thinning the two-dimensional semiconductor bulk materials of different types by adopting a mechanical stripping method to obtain two-dimensional semiconductor layers of different types correspondingly. As another possible embodiment, a chemical vapor deposition method may be used to prepare the two-dimensional semiconductor layer.

The mechanical stripping method comprises the following specific processes: preparing a strip-shaped adhesive tape (such as Scotch adhesive tape of 3M company), placing a two-dimensional semiconductor bulk material at the center of the adhesive surface of the strip-shaped adhesive tape, folding the adhesive tape along the central symmetrical position of the adhesive surface, and then separating the adhesive tape, repeating the steps for several times to thin the two-dimensional semiconductor bulk material, thereby obtaining the two-dimensional semiconductor layer. The method is simple and rapid to operate, has low cost, does not need a doping process, and retains the inherent properties of the material.

When the prepared two-dimensional semiconductor layer comprises two-dimensional semiconductor layers with the number of layers exceeding a preset threshold value, after the preparation of different types of two-dimensional semiconductor layers, the method further comprises the following steps:

and screening out the two-dimensional semiconductor layers with the layer number smaller than the preset threshold value by adopting an optical contrast method.

The preset threshold value is not limited in the application and can be set by self. For example, there may be one layer, two layers, three layers, and so on. The screening mode of the optical contrast is very quick and accurate.

Step S104: and transferring the two-dimensional semiconductor layers of different types to enable the two-dimensional semiconductor layers to be sequentially laminated on the upper surface of the hexagonal boron nitride insulating layer, and carrying out annealing treatment after each two-dimensional semiconductor layer is transferred to form a channel layer.

And (3) carrying out annealing treatment once when transferring a two-dimensional semiconductor layer, wherein the annealing treatment process comprises the steps of putting the substrate with the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer into a vacuum tube furnace, and annealing for 2 hours at 200 ℃ under the condition that argon with the pressure of 5Torr is used as protective gas.

The transfer process of the two-dimensional semiconductor layer is explained below.

Step S105: and depositing a source electrode and a drain electrode on the upper surface of the hexagonal boron nitride insulating layer, wherein the source electrode and the drain electrode are respectively contacted with the end parts of the channel layer.

Optionally, the depositing a source electrode and a drain electrode on the upper surface of the hexagonal boron nitride insulating layer includes: and depositing a source electrode and a drain electrode on the upper surface of the hexagonal boron nitride insulating layer by adopting an electron beam evaporation method. Or depositing a source electrode and a drain electrode on the upper surface of the hexagonal boron nitride insulating layer by adopting a thermal evaporation method.

The transferring the hexagonal boron nitride insulating layer to the upper surface of the substrate comprises:

step S201: a PDMS (Polydimethylsiloxane) matrix was prepared in which the weight ratio of the base component to the curing agent was 10: 1.

The weight ratio of the basic components to the curing agent is controlled to be 10:1, so that the PDMS matrix has proper flexibility and viscosity, when the weight ratio is less than 10:1, the PDMS matrix is hard and has small viscosity, the hexagonal boron nitride insulating layer on the adhesive tape is not easy to transfer to the PDMS matrix, when the weight ratio is more than 10:1, the PDMS matrix is soft and has large viscosity, and the hexagonal boron nitride insulating layer on the adhesive tape is easy to transfer to the PDMS matrix, but is not easy to transfer to other materials in the following transfer step, so that the phenomena of cracking of the materials and the like are caused, and the transfer fails.

Step S202: and transferring the hexagonal boron nitride insulating layer to the PDMS substrate.

And (3) contacting the adhesive surface of the adhesive tape with the PDMS substrate, and slowly uncovering the adhesive tape, so that a part of the ultrathin hexagonal boron nitride insulating layer is transferred to the PDMS substrate.

Step S203: and fixing the substrate on a rotating base of transfer equipment, and fixing the PDMS matrix with the hexagonal boron nitride insulating layer on a glass slide, wherein the hexagonal boron nitride insulating layer is opposite to the substrate.

The structure of the transfer device is schematically shown in fig. 3, and includes a base table 7, a support 6, a first displacement table 9 and a second displacement table 8 on the base table 7, a microscope 12 fixed on the support 6, a rotary base 10 on the first displacement table 9, and a slide 11 connected to the second displacement table 8, wherein the first displacement table 9 and the second displacement table 8 can move up and down, left and right, and the rotary base 10 can rotate 360 degrees in a plane.

Step S204: and adjusting the position of the substrate to the focal length of a microscope under the maximum magnification, and adjusting the position of the hexagonal boron nitride insulating layer to enable the hexagonal boron nitride insulating layer to be in contact with the substrate for preset time.

Because the area of the hexagonal boron nitride insulating layer is smaller, the hexagonal boron nitride insulating layer is placed at the focal distance of a microscope under the maximum magnification so as to be convenient for determining the position of the hexagonal boron nitride insulating layer, and then the hexagonal boron nitride insulating layer is moved away. And adjusting the position of the substrate to the focal length of a microscope under the maximum magnification so as to observe the contact position of the hexagonal boron nitride insulating layer and the substrate.

The area of the substrate is large, the area of the hexagonal boron nitride insulating layer is small and thin, the substrate can be divided into a plurality of small areas, and each area is marked with metal, so that the operation in the process of contacting the two-dimensional semiconductor layer with the hexagonal boron nitride insulating layer is facilitated.

The preset time is not limited in this application, and may be, for example, 2 minutes, 3 minutes, 5 minutes, or the like.

Step S205: and removing the PDMS matrix, and transferring the hexagonal boron nitride insulating layer to the upper surface of the substrate.

The second displacement stage is moved upwards, i.e. the PDMS substrate is removed.

Transferring the two-dimensional semiconductor layers of different types to enable the two-dimensional semiconductor layers to be sequentially laminated on the upper surface of the hexagonal boron nitride insulating layer, and performing annealing treatment after each layer of the two-dimensional semiconductor layers is transferred to form a channel layer, wherein the forming of the channel layer comprises:

step S1: and fixing the substrate with the hexagonal boron nitride insulating layer on a rotating base of transfer equipment, and fixing the PDMS base with the two-dimensional semiconductor layer on a glass slide, wherein the two-dimensional semiconductor layer is opposite to the upper surface of the substrate.

Step S2: and adjusting the position of the two-dimensional semiconductor layer to the focal length of the microscope under the maximum magnification, marking the first outline of the two-dimensional semiconductor layer, and removing the two-dimensional semiconductor layer.

Step S3: and adjusting the focal distance from the film layer on the upper surface of the substrate to the microscope at the maximum magnification, and marking a second contour of the film layer on the upper surface of the substrate.

It is understood that when the first two-dimensional semiconductor layer is transferred, the film layer on the upper surface of the substrate in this step is a hexagonal boron nitride insulating layer; when the second two-dimensional semiconductor layer is transferred to the last two-dimensional semiconductor layer, the film layer on the upper surface of the substrate in the step is the transferred upper two-dimensional semiconductor layer.

Step S4: and contacting the two-dimensional semiconductor layer with a film layer on the upper surface of the substrate according to the first profile and the second profile for a preset time.

The preset time is not limited in this application, and may be, for example, 2 minutes, 3 minutes, 5 minutes, or the like.

It is understood that when the first two-dimensional semiconductor layer is transferred, the film layer on the upper surface of the substrate in this step is a hexagonal boron nitride insulating layer; when the second two-dimensional semiconductor layer is transferred to the last two-dimensional semiconductor layer, the film layer on the upper surface of the substrate in the step is the transferred upper two-dimensional semiconductor layer.

Step S5: and removing the PDMS matrix, transferring the two-dimensional semiconductor layer to the substrate, annealing the substrate with the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer to obtain a new substrate, transferring different types of new two-dimensional semiconductor layers to the PDMS matrix, and returning to the step S1 until all the two-dimensional semiconductor layers are transferred.

Taking the number of layers of the two-dimensional semiconductor layer as two layers as an example, the process of transferring the two-dimensional semiconductor layer is explained as follows:

step S301: and transferring the two-dimensional semiconductor layer to a PDMS substrate.

The adhesive surface of the adhesive tape with the two-dimensional semiconductor layer is contacted with the PDMS substrate, and then the adhesive tape is slowly uncovered, so that a part of the single-layer or few-layer two-dimensional semiconductor layer is transferred to the PDMS substrate.

Step S302: and fixing the substrate with the hexagonal boron nitride insulating layer on a rotating base of transfer equipment, and fixing the PDMS matrix with the two-dimensional semiconductor layer on a glass slide, wherein the hexagonal boron nitride insulating layer is opposite to the two-dimensional semiconductor layer.

Step S303: and adjusting the position of the two-dimensional semiconductor layer to the focal length of the microscope under the maximum magnification, marking the first outline of the two-dimensional semiconductor layer, and removing the two-dimensional semiconductor layer.

The two-dimensional semiconductor layer is positioned at the focal distance at maximum magnification due to its small area so as to facilitate the determination of the position of the two-dimensional semiconductor layer, the first contour being marked in order to facilitate the contact of the two-dimensional semiconductor layer with the hexagonal boron nitride insulating layer.

Step S304: adjusting the position of the hexagonal boron nitride insulating layer to the focal length of the microscope at the maximum magnification and marking a second contour of the hexagonal boron nitride insulating layer.

The area of the hexagonal boron nitride insulating layer is small and the second contour of the hexagonal boron nitride insulating layer is marked to facilitate the contact of the two-dimensional semiconductor layer with the hexagonal boron nitride insulating layer.

Step S305: and contacting the two-dimensional semiconductor layer with the hexagonal boron nitride insulating layer according to the first profile and the second profile for a preset time.

And judging the contact condition of the two-dimensional semiconductor layer and the hexagonal boron nitride insulating layer by observing the overlapping condition of the first outline and the second outline.

Step S306: and removing the PDMS matrix, transferring the two-dimensional semiconductor layer onto the hexagonal boron nitride insulating layer, and annealing the substrate with the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer.

The substrate with the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer was placed in a vacuum tube furnace and annealed at 200 ℃ for 2 hours under a protective gas of argon at a pressure of 5 Torr. At this point, the transfer of the first two-dimensional semiconductor layer is completed.

Step S307: a new two-dimensional semiconductor layer of a different kind was transferred onto the PDMS matrix.

For details, please refer to step S301, which is not described herein in detail.

Step S308: and fixing the substrate with the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer on a rotating base of transfer equipment, and fixing the PDMS matrix with the new two-dimensional semiconductor layer on a glass slide, wherein the new two-dimensional semiconductor layer is opposite to the two-dimensional semiconductor layer.

Step S309: adjusting the position of the new two-dimensional semiconductor layer to the focal length of the microscope at the maximum magnification, marking a third profile of the new two-dimensional semiconductor layer, and removing the new two-dimensional semiconductor layer.

The purpose of marking the third profile is to facilitate the contact of the new two-dimensional semiconductor layer with the two-dimensional semiconductor layer.

Step S310: adjusting the focus of the two-dimensional semiconductor layer to the microscope at the maximum magnification, and marking a fourth profile of the two-dimensional semiconductor layer.

And judging the contact condition of the two-dimensional semiconductor layer and the new two-dimensional semiconductor layer by observing the overlapping condition of the third contour and the fourth contour.

Step S311: and enabling the new two-dimensional semiconductor layer to be in contact with the two-dimensional semiconductor layer for a preset time according to the third profile and the fourth profile.

Step S312: and removing the PDMS matrix, transferring the new two-dimensional semiconductor layer onto the two-dimensional semiconductor layer, and annealing the substrate with the hexagonal boron nitride insulating layer, the two-dimensional semiconductor layer and the new two-dimensional semiconductor layer.

The substrate with the hexagonal boron nitride insulating layer, the two-dimensional semiconductor layer and the new two-dimensional semiconductor layer was placed in a vacuum tube furnace and annealed at 200 ℃ for 2 hours under a protective gas of argon at a pressure of 5 Torr. At this point, the transfer of the second two-dimensional semiconductor layer is completed.

When the number of the two-dimensional semiconductor layers exceeds two, the above-described processes of S309 to S312 may be repeated.

In an embodiment of the present application, before bringing the two-dimensional semiconductor layer into contact with the hexagonal boron nitride insulating layer according to the first profile and the second profile for a preset time, the method further includes:

rotating the rotating base to bring the second profile into perfect alignment with the first profile;

before the step of contacting the new two-dimensional semiconductor layer with the two-dimensional semiconductor layer according to the third profile and the fourth profile for a preset time, the method further includes:

rotating the rotating base brings the fourth profile into perfect alignment with the third profile.

The second contour is completely aligned with the first contour, so that the hexagonal boron nitride insulating layer is completely overlapped with the two-dimensional semiconductor layer, the overlapping area is the largest, the third contour is completely aligned with the fourth contour, the new two-dimensional semiconductor layer is completely overlapped with the two-dimensional semiconductor layer, and the overlapping area is the largest, so that the performance of the transistor is improved.

In the transistor manufactured by the manufacturing method, the insulating layer is a hexagonal boron nitride insulating layer, the hexagonal boron nitride is a two-dimensional crystal material, the thickness is very thin, the threshold voltage and the power consumption of the transistor can be reduced, the channel layer comprises a plurality of layers of two-dimensional semiconductor layers of different types, and the different two-dimensional semiconductor layers are combined through Van der Waals force, so that the crystal structures and lattice constants of the different two-dimensional semiconductor layers and the hexagonal boron nitride insulating layer do not need to be matched, a heterostructure can be directly formed, and the on-off ratio of the transistor can be improved through the two-dimensional semiconductor layers of different types; and the hexagonal boron nitride insulating layer and the two-dimensional semiconductor layer are obtained by annealing treatment during preparation respectively, so that a good van der Waals interface can be formed between two adjacent layer structures, the electron mobility and the uniformity of carriers can be improved, and the performance of the transistor can be improved.

The following describes a method for manufacturing a transistor in this application with a specific process.

Step 1, preparing a PDMS matrix: it needs to use SYLGARD 184SILICONE ELASTOMER kit, and PDMS is mainly composed of the basic components and curing agent in the kit, and the preparation method is as follows: (1) preparing a beaker which is cleaned by deionized water and dried by a blower, adding 17.5g of basic components and 1.75g of curing agent into the beaker, (2) uniformly stirring the mixed liquid of the basic components and the curing agent by a glass rod for about 10 minutes in a clockwise manner, (3) pouring the liquid in the beaker into a glass culture dish to ensure that the liquid in the culture dish is a thin layer with the height of about 1mm, (4) covering the culture dish with a cover to prevent pollutants from polluting PMDS liquid, putting the culture dish into an oven, heating the culture dish for 1 hour at 60 ℃, finally taking out the culture dish, standing for 5 days, and waiting for the PDMS liquid to solidify and form solids like jelly to obtain the PDMS matrix.

And 2, cutting off a long strip-shaped adhesive tape from the Scotch adhesive tape produced by the 3M company for standby, placing the blocky hBN crystal at the center of the adhesive surface of the long strip-shaped adhesive tape, folding the adhesive tape along the central symmetrical part of the adhesive surface, and then separating the adhesive tape, wherein the process is repeated for several times to achieve the purpose of thinning the crystal. Then the adhesive surface of the tape was brought into contact with the PDMS substrate and the tape was slowly peeled off, so that a portion of the ultra-thin hexagonal hBN insulation layer was transferred to the PDMS substrate.

And 3, taking the PDMS substrate with the hBN in the step 2, placing the PDMS substrate under a microscope for observation, adjusting the light intensity of the microscope to ensure that the exposure of the optical image of the sample displayed in the computer software does not exceed the range of the software, observing and finding out the sample through optical contrast, wherein the lighter the color of the sample is, the closer the sample is to the transparency, the thinner the sample is, the lower the requirement on the thickness of the hexagonal hBN insulating layer is, and only the hexagonal hBN insulating layer with the lighter color, the closer the color to the transparency, is selected.

And 4, fixing the substrate on a rotary base, fixing the PMDS matrix with the hexagonal hBN insulating layer below the glass slide, connecting a microscope with a computer, observing an image observed by the microscope through software on the computer, and displaying different magnification factors by moving up and down and matching with different focal lengths. The specific transfer process is as follows: (1) fixing a substrate on a rotating base, finding the position of the center of the substrate by adjusting the height of a first displacement table and the focal length of a microscope by using a metal mark plated on the substrate, and then adjusting a knob of the first displacement table to enable the first displacement table to descend, (2) fixing a PDMS matrix with a hexagonal hBN insulating layer below a glass slide, and finding the hexagonal hBN insulating layer serving as an upper layer material by adjusting the up, down, left and right sides of a second displacement table and the focal length of the microscope. Then under the maximum magnification, adjusting the height of a second displacement table to ensure that the upper layer material is just positioned at the focal distance of the microscope, the image in the computer software is displayed most clearly, then adjusting a knob of the second displacement table to enable the second displacement table to rise, (3) under the same maximum magnification, utilizing the transparent characteristics of a glass slide and a PDMS matrix, adjusting the height of a first displacement table to ensure that a substrate as the lower layer material is just positioned at the focal distance of the microscope at the moment, the image in the computer software is displayed most clearly, (4) adjusting the height of the second displacement table to enable the second displacement table to fall, enabling the upper layer material to slowly contact with the substrate, after the hexagonal hBN insulating layer in the image of the computer software is clear, not doing any operation to enable the hexagonal hBN insulating layer to contact with the silicon substrate for 3 minutes, then moving the second displacement table upwards, enabling the upper layer material to be separated from the PDMS matrix and left on the silicon substrate, and placing the silicon substrate with the hexagonal hBN insulating layer into a vacuum tube furnace, annealing was carried out at 200 ℃ for 2 hours under a protective atmosphere of argon at a pressure of 5 Torr.

Step 5, preparing a first two-dimensional semiconductor layer: a piece of long strip is cut off from Scotch adhesive tape produced by 3M company and is assembled for standby, a blocky two-dimensional crystal material is placed at the center of the adhesive surface of the long strip of adhesive tape, then the adhesive tape is folded in half along the central symmetry position of the adhesive surface and is separated, the process is repeated for several times to achieve the purpose of thinning the crystal, then the adhesive surface of the adhesive tape is contacted with a PDMS matrix, then the adhesive tape is slowly uncovered, and a part of single-layer or few-layer two-dimensional crystal material is transferred onto the PDMS matrix.

And 6, screening the first two-dimensional semiconductor layer: observing the PDMS substrate with the first two-dimensional semiconductor layer under a microscope, adjusting the light intensity of the microscope to ensure that the exposure of the optical image of the sample displayed in the computer software does not exceed the range of the software, then storing the image of the sample under the condition of no over-exposure, and then analyzing the optical contrast by using image software. For example, using Image J Image software, using the Image-Color-Split Channel function therein, splitting the optical Image into red, blue and green channels, selecting the green Channel therein for analysis, using the Analyze-Label function, taking a straight line to mark the optical Image value at the sample position, the straight line should include the PDMS matrix position and the thin layer sample position, then using the Analyze-Plot Profile function to map the optical Image value on the straight line, and then saving the data. And finally, calculating the optical contrast of the sample (sample image value-substrate image value)/substrate image value by using data processing software, wherein the optical contrast of a single-layer material is about 8 percent generally, and thus, the contrast of an optical microscope is used for screening out the desired single-layer or few-layer first two-dimensional semiconductor layer.

And 7, (1) fixing the PDMS substrate with the first two-dimensional semiconductor layer below the glass slide, and finding the first two-dimensional semiconductor layer as an upper layer material by adjusting the upper, lower, left and right sides of the second displacement table and the focal length of the microscope. Then under the maximum magnification, adjusting the height of a second displacement table to ensure that the upper layer material is just positioned at the focal distance of the microscope, the image display in computer software is clearest, drawing the outline of a first two-dimensional semiconductor layer to be transferred by using a red line on the software, then adjusting a knob of the second displacement table to enable the second displacement table to ascend, (2) fixing a silicon substrate with a hexagonal hBN insulating layer on a rotating base, finding an ultrathin hexagonal hBN insulating layer as a lower layer material by using a metal mark plated on silicon through adjusting the upper, lower, left and right sides of a first displacement table and the focal distance of the microscope, under the same maximum magnification, adjusting the height of the first displacement table by using the transparent characteristics of a glass slide and PDMS to ensure that the lower layer material is just positioned at the focal distance of the microscope, the image display in computer software is clearest, drawing the outline of the hexagonal hBN insulating layer by using a blue line on the software, (3) according to the marked line profile, whether the part of the upper layer material to be transferred is matched with the blue line profile direction or not is observed, if not, the direction of the rotating base and the left and right of the first displacement table are adjusted to enable the lower layer material and the upper layer material to be in a relative position in a proper direction, 4, the height of the second displacement table is adjusted to enable the second displacement table to descend, the upper layer material is enabled to slowly contact with the lower layer material, at the moment, the image displayed by a microscope in computer software changes, like liquid moves from a certain corner of an edge to a corner of the opposite angle, after the liquid moves to the corner of the opposite angle, the two layers of materials are contacted for 3 minutes without any operation, then the second displacement table is moved upwards, due to van der Waals force between the two layers of materials, the upper layer material can be separated from PDMS and remained above the lower layer material, then the silicon substrate with the ultrathin hexagonal hBN and the first two-dimensional semiconductor layer is placed into a vacuum tube furnace, annealing was carried out at 200 ℃ for 2 hours under a protective atmosphere of argon at a pressure of 5 Torr.

And 8, preparing the second two-dimensional semiconductor layer in the same way as the step 5.

Step 9, the screening step of the second two-dimensional semiconductor layer is the same as step 6, and the second two-dimensional semiconductor layer with a desired single layer or a few layers is screened out by using the contrast of the optical microscope.

Step 10, transferring the second two-dimensional semiconductor layer as the upper layer material to the first two-dimensional semiconductor layer as the lower layer material to form a heterojunction, wherein the assembly process of the heterojunction is as follows: (1) fixing a PDMS substrate with a second two-dimensional semiconductor layer below a glass slide, finding the second two-dimensional semiconductor layer as an upper layer material by adjusting the upper, lower, left and right sides of a second displacement table and the focal length of a microscope, then adjusting the height of the second displacement table under the maximum magnification to ensure that the upper layer material is just positioned at the focal length of the microscope, wherein the image display in computer software is clearest, drawing the outline of a part to be transferred by using red lines on software, then adjusting a knob of the second displacement table to enable the second displacement table to ascend, (2) fixing a silicon substrate with the first two-dimensional semiconductor layer on a rotating base, utilizing a metal mark plated on silicon, finding a lower layer material by adjusting the upper, lower, left and right sides of the first displacement table and the focal length of the microscope under the same maximum magnification by utilizing the transparent characteristics of the glass slide and the PDMS, adjusting the height of the first displacement table to ensure that the lower layer material is just positioned at the focal length of the microscope, the image display in the computer software is clearest, the contour of the hexagonal hBN insulating layer is drawn by blue lines on the software, (3) according to the marked line contour, whether the red line of the part of the upper layer material to be transferred is matched with the blue line contour at the moment is observed, if the red line and the blue line contour are not matched, the relative position of the lower layer material and the upper layer material in a proper direction is made by adjusting the direction of a rotating base and the left and the right of a first displacement platform, (4) the height of a second displacement platform is adjusted to be lowered, so that the upper layer material is slowly contacted with the lower layer material, the image displayed in the computer software by a microscope is changed, if liquid moves from a certain corner of an edge to a corner of an opposite angle, after the liquid moves to the corner of the opposite angle, the two layers of materials are contacted for 3 minutes without any operation, then the second displacement platform is moved upwards, due to the van der Waals force action between the two layers of materials, the upper layer material will leave the PDMS above the lower layer material, thus completing the assembly of the heterojunction.

Step 11, heterojunction formation: and putting the silicon substrate with the hexagonal hBN insulating layer, the first two-dimensional semiconductor layer and the second two-dimensional semiconductor layer into a vacuum tube furnace, and annealing for 2 hours at 200 ℃ under the condition that argon with the pressure of 5Torr is used as protective gas. Impurities and air between interfaces of different crystal materials are removed through three times of annealing treatment, so that Van der Waals interfaces with excellent cleaning performance are formed among several crystals to ensure the performance of the device, and finally, heterojunction is formed among several different crystal materials.

When more layers of heterojunction are required to be prepared, only the steps 8, 9 and 10 need to be repeated, more layers of two-dimensional semiconductor layers and the like can be prepared, and more layers of heterojunction can be prepared.

Step 12, preparation of a transistor: and (3) taking the annealed silicon substrate with the two-dimensional heterojunction crystal, soaking the annealed silicon substrate in an acetone solution, then quickly spin-coating a layer of PMMA photoresist, and baking the coated silicon substrate on a hot plate. After baking, the silicon substrate is placed on a mask plate, an electron beam exposure machine is used for exposing an electrode, developing is carried out by using a developing solution, IPA is used for fixing, and then dry nitrogen is used for drying. And finally, depositing a metal film electrode layer on the substrate and the heterojunction by electron beam evaporation.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The transistor and the method for fabricating the same provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.