阅读说明：本技术 一种多浮栅叠层型突触晶体管及其制备方法 (Multi-floating-gate laminated type synaptic transistor and preparation method thereof ) 是由 黎明 李海霞 李小康 黄如 于 2021-09-27 设计创作，主要内容包括：本发明公开了一种多浮栅叠层型突触晶体管,具有叠层的多晶硅俘获层-氧化物阻挡层,该多浮栅叠层结构采用多电平技术时能够保证每个电平之间的窗口大小,大容量的存储能够降低对电路的精确性的要求；多层俘获层的设计能够在器件尺寸减小、隧穿层减薄的情况下保证电荷的保持特性,且避免了单层俘获层电荷一处泄露则全部泄露的情况,减小漏电概率；通过调整叠层的厚度配比和层数可以实现存储窗口最大化。这些优良的器件特性使得其有潜力应用到未来大规模神经形态计算系统。(The invention discloses a multi-floating gate laminated synaptic transistor, which is provided with a laminated polysilicon trapping layer-oxide blocking layer, wherein the multi-floating gate laminated structure can ensure the size of a window between each level by adopting a multi-level technology, and the requirement on the accuracy of a circuit can be reduced by large-capacity storage; the design of the multi-layer trapping layer can ensure the charge retention characteristic under the conditions of reduced device size and thinned tunneling layer, and avoid the condition that all charges of the single-layer trapping layer leak at one position, thereby reducing the leakage probability; the maximization of the storage window can be realized by adjusting the thickness ratio and the number of the laminated layers. These superior device characteristics make it potentially applicable to future large-scale neuromorphic computing systems.)

1. A multi-floating-gate laminated synapse transistor comprises a semiconductor substrate, a nanowire channel region, a source region, a drain region, an interlayer dielectric, a grid electrode, an isolation layer and a metal leading-out layer, wherein the semiconductor substrate is an SOI substrate, the source region, the drain region and the nanowire channel region connecting the source region and the drain region are formed on the SOI substrate, the interlayer dielectric and the grid electrode are arranged above the nanowire channel region, and the isolation layer covers the surface of the synapse transistor device; the metal lead-out layer forms metal lead-out wires connected to the source region, the drain region and the grid electrode through the through holes respectively; the interlayer dielectric is characterized by comprising a tunneling oxide layer, a laminated polysilicon trapping layer-barrier layer combination and a top barrier layer which are sequentially laminated on a nanowire channel region.

2. The multi-floating gate stacked synapse transistor of claim 1, wherein the tunneling oxide layer is silicon oxide and has a thickness of 1-2 nm.

3. The multi-floating gate stacked synapse transistor of claim 1, wherein the stacked polysilicon trapping layer-barrier layer combination comprises a plurality of polysilicon trapping layers, a single polysilicon trapping layer having a thickness of no more than 4 nm; an oxide barrier layer with the thickness of 1-5 nm is arranged between every two polysilicon trapping layers.

4. The multi-floating gate stacked synapse transistor of claim 3, wherein the oxide blocking layer between the two polysilicon trapping layers is aluminum oxide or silicon oxide.

5. The multi-floating gate stacked synapse transistor of claim 1, wherein the top barrier layer is made of alumina or silica with a thickness of 8-10 nm.

6. The multi-floating gate stacked synapse transistor of claim 1, wherein the gate is made of titanium nitride or tantalum nitride and has a thickness of 50-100 nm.

7. The method of fabricating a multi-floating gate stacked synapse transistor as claimed in any of claims 1-6, comprising the steps of:

1) patterning and etching the silicon nanowire channel region and a source region and a drain region which are respectively connected with the two ends of the silicon nanowire channel region on the SOI substrate by utilizing a photoetching technology to obtain a dumbbell-shaped silicon structure, and doping and annealing the source region and the drain region;

2) forming a tunneling oxide layer on the surface of the dumbbell-shaped silicon structure in an oxidation mode;

3) depositing a laminated polysilicon trapping layer, namely a barrier layer and a top barrier layer on the tunneling oxide layer in sequence;

4) depositing a metal gate material on the top barrier layer, and forming a gate through photoetching definition and etching;

5) and depositing an isolation layer, flattening the surface, and then manufacturing metal lead-out of the source drain gate.

8. The method of claim 7, wherein step 1) comprises:

1a) spin-coating an inorganic negative photoresist on an SOI substrate, and then patterning the inorganic negative photoresist as a nanowire hard mask by using an electron beam lithography technology;

1b) spin-coating an organic positive photoresist, and patterning the organic positive photoresist as a source-drain mask by a photoetching technology;

1c) the nanowire hard mask and the source drain mask are used as mixed masks, and the silicon is anisotropically etched to form a dumbbell-shaped structure;

1d) and removing the source and drain masks, reserving the nanowire hard mask, heavily doping the source and drain by an ion implantation technology, then removing the nanowire hard mask by wet etching, and annealing and activating source and drain impurities.

9. The method according to claim 7, wherein the oxidation mode in the step 2) is dry oxygen oxidation or oxyhydrogen synthesis oxidation; depositing a polysilicon trapping layer by adopting a low-pressure chemical vapor deposition method in the step 3), and depositing a barrier layer by adopting an atomic layer deposition method; and 4) depositing the metal gate material by adopting a magnetron sputtering or evaporation method.

10. The preparation method of claim 7, wherein in the step 5), when the metal for manufacturing the source and drain gates is led out, the photolithographic technique is used for defining and etching to form through holes of the source, the drain and the gate, then metal is deposited for filling, the photolithographic technique is used for defining the metal lead-out wire after surface planarization is carried out, and the metal layer is etched to the isolation layer to form the metal lead-out wire.

Technical Field

The invention belongs to the field of synapse devices oriented to neural network hardware application, and particularly relates to a multi-floating-gate laminated synapse transistor with a large-capacity storage function and a preparation method thereof.

Background

The neuromorphic computing is a novel computing architecture which realizes the integration of storage and computation and shows more excellent performance compared with the traditional Von Neumann architecture. The neuromorphic computing needs to be developed from multiple aspects such as devices, circuits and system architectures, wherein the underlying synapses, nerve components and synapse networks are the basis for building a complex neuromorphic computing system.

The current artificial synapse devices include two-terminal synapse devices represented by Resistive Random Access Memory (RRAM) and Phase Change Memory (PCRAM), and three-terminal synapse devices represented by ion-Gated-Field-effect transistors (IGFET) and Charge-Trapped-Field-effect transistors (CTFET). The former has a simple structure and can be integrated, but has the problems of large fluctuation, poor reliability and the like, the ion-gate control synaptic transistor in the latter has the problems of difficult integration with a CMOS circuit and the like, and the charge trapping synaptic transistor has the problems of incomplete function, high operating voltage and the like. In addition, a Flash memory (Flash) device based on a traditional Very Large Scale Integration (VLSI) technology can also be used for simulating biological synapses, but most of them can only realize binary storage, or when a Multi-Level Cell (MLC) technology is adopted, it inevitably faces the accuracy trouble caused by the undersize of threshold windows between different levels to read the circuit along with the size reduction, and at the same time, it generates more rigorous requirements on the control of charge injection amount and the control of charge leakage number, which is not favorable for the realization of high-accuracy neural network.

Therefore, a large-capacity, integratable synapse device is urgently needed to be developed and researched.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a multi-floating gate synapse device with high reliability and multi-valued storage and a method for fabricating the same.

The conventional floating gate device controls the amount of charge injected into the floating gate by controlling the time and voltage of a programming pulse, thereby realizing multi-value storage. However, originally, a two-level memory window is divided into several parts, and the threshold voltage window between different levels is too small, so that higher requirements on the accuracy of the circuit are put forward. In addition, conventional floating gate devices face reliability issues. On one hand, as the size is reduced and the thickness of the tunneling oxide layer is reduced, the probability of direct tunneling loss of the charges stored in the floating gate is increased, and the device retention characteristic is reduced. On the other hand, after multiple programming and erasing, the tunnel oxide layer generates defects, and the leakage current is increased.

The invention provides a laminated polysilicon-oxide multi-floating gate type synapse device. The multiple floating gate stacks ensure window size between each level, and large-capacity storage can reduce the requirement on circuit accuracy. The design of the multi-layer trapping layer can ensure the charge retention characteristic under the condition that the size of the device is reduced and the tunnel layer is thinned, avoid the condition that all charges of the single-layer trapping layer are leaked, and reduce electric leakage. The maximization of a storage window and the maximization of the reliability can be realized by adjusting the thickness proportion and the number of the laminated layers.

The invention provides a multi-floating-gate laminated synapse transistor for high-performance multi-value storage, which comprises a semiconductor substrate, a nanowire channel region, a source region, a drain region, an interlayer medium, a grid electrode, an isolation layer and a metal leading-out layer, wherein the semiconductor substrate is an SOI substrate, the source region, the drain region and the nanowire channel region for connecting the source region and the drain region are formed on the SOI substrate, the interlayer medium and the grid electrode are arranged above the nanowire channel region, and the isolation layer covers the surface of a synapse transistor device; the metal lead-out layer forms metal lead-out wires connected to the source region, the drain region and the grid electrode through the through holes respectively; the interlayer dielectric is characterized by comprising a tunneling oxide layer, a laminated polysilicon trapping layer-barrier layer combination and a top barrier layer which are sequentially laminated on a nanowire channel region.

In the multi-floating gate stacked synapse transistor for high-performance multi-value storage, the material of the tunneling oxide layer is preferably silicon oxide (SiO)₂) And the thickness is preferably 1 to 2 nm.

In the multi-floating-gate stacked synapse transistor for high-performance multi-valued storage, the charge trapping layers are a plurality of polysilicon trapping layers, and the maximum thickness of a single layer is 3-4 nm; the thickness between every two polysilicon trapping layers is 1-5A nm oxide barrier layer, the material of the barrier layer is preferably aluminum oxide (Al)₂O₃) Silicon oxide (SiO)₂) And the like.

In the multi-floating gate stacked synapse transistor for high-performance multivalue storage, the material of the top barrier layer is preferably alumina (Al)₂O₃) Silicon oxide (SiO)₂) And the thickness is preferably 8 to 10 nm.

In the multi-floating-gate stacked synapse transistor for high-performance multi-value storage, the gate is preferably made of titanium nitride (TiN), tantalum nitride (TaN) and the like, and the thickness is preferably 50-100 nm.

The invention also provides a preparation method of the multi-floating-gate type synaptic transistor with the laminated trapping layer, which comprises the following steps:

1) patterning and etching the silicon nanowire channel region and a source region and a drain region which are respectively connected with the two ends of the silicon nanowire channel region on the SOI substrate by utilizing a photoetching technology to obtain a dumbbell-shaped silicon structure, and doping and annealing the source region and the drain region;

2) forming a tunneling oxide layer on the surface of the dumbbell-shaped silicon structure in an oxidation mode;

3) depositing a laminated polysilicon trapping layer, namely a barrier layer and a top barrier layer on the tunneling oxide layer in sequence;

4) depositing a metal gate material on the top barrier layer, and forming a gate through photoetching definition and etching;

5) and depositing an isolation layer, flattening the surface, and then manufacturing metal lead-out of the source drain gate.

The step 1) specifically comprises:

1a) spin-coating inorganic negative photoresist such as HSQ (hydrogen silsesquioxane) electron beam photoresist containing hydrogen silicate on an SOI substrate, and patterning the inorganic negative photoresist as a nanowire hard mask by using an electron beam lithography technique;

1b) spin-coating an organic positive photoresist, and patterning the organic positive photoresist as a source-drain mask by a photoetching technology;

1c) the nanowire hard mask (inorganic glue) and the source drain mask (organic glue) are used as mixed masks, and silicon is anisotropically etched to form a dumbbell-shaped structure;

1d) and removing the source and drain masks, reserving the nanowire hard mask, heavily doping the source and drain by an ion implantation technology, then removing the nanowire hard mask by wet etching, and annealing and activating source and drain impurities.

The Annealing method may be one of Rapid Thermal Annealing (RTA), Laser Annealing (Laser Annealing), Flash Annealing (Flash Annealing), and Spike Annealing (Spike Annealing).

The oxidation mode in the step 2) can be dry oxygen oxidation or hydrogen-oxygen synthetic oxidation.

The Deposition method of the polysilicon trapping layer in the step 3) can be Low Pressure Chemical Vapor Deposition (LPCVD), etc.; the Deposition manner of the barrier Layer can be selected from Atomic Layer Deposition (ALD), etc.

The Deposition manner of the Metal gate material in the step 4) may adopt Physical Vapor Deposition (PVD) manners such as Magnetron Sputtering (Magnetron Sputtering) and Metal Evaporation (Metal Evaporation).

The step 5) is preferably to deposit silicon oxide as the isolation layer, and the Deposition method can adopt methods such as Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD) and the like. The planarization is preferably Chemical Mechanical Polishing (CMP).

And 6) when the metal for manufacturing the source and drain gates is led out, defining and etching the through holes for forming the source, drain and gate by utilizing the photoetching technology, depositing metal for filling, defining the metal lead-out wire by utilizing the photoetching technology after surface planarization, and etching the metal layer to the isolation layer to form the metal lead-out.

Further, the lithography technology adopted in the above preparation method is a lithography technology capable of defining nanometer scale, such as 193nm ultraviolet lithography technology; the adopted Etching technology can be Reactive Ion Etching (RIE), Inductively Coupled Plasma Etching (ICPE) and other methods.

The invention has the following advantages and positive effects:

1) the multi-floating-gate laminated synaptic transistor provided by the invention comprises a plurality of floating gate laminations, the window size between each level can be ensured by adopting a multi-level technology, and the requirement on the accuracy of a circuit can be reduced by large-capacity storage;

2) the design of the multi-layer trapping layer can ensure the charge retention characteristic under the condition that the size of the device is reduced and the tunneling layer is thinned;

3) the design of the multi-layer trapping layer avoids the situation that the charges of the single-layer trapping layer leak at one position and then leak completely, and the leakage probability is reduced;

4) the maximization of the storage window can be realized by adjusting the thickness ratio and the number of the laminated layers.

Drawings

FIGS. 1-8 are schematic diagrams of key process steps of a multi-floating gate stacked synapse transistor for high performance multi-value storage in accordance with the present invention. In the drawings, (a) is a top view of the device, (B) is a cross-sectional view of the device taken along the A-A 'direction, and (c) is a cross-sectional view of the device taken along the B-B' direction. Wherein:

FIG. 1 is an SOI substrate after spin-coating HSQ paste;

FIG. 2 is a diagram illustrating the definition of a nanowire mask by electron beam exposure techniques;

FIG. 3 is a diagram illustrating a dumbbell-structured source-drain and nanowire channel structure formed by defining a source-drain mask and etching the source-drain mask and a nanowire mask as a hybrid mask by using an optical lithography technique;

FIG. 4 is a schematic representation of a thermal oxidation generated tunneling oxide layer, a sequentially deposited stack of a polysilicon trapping layer and an alumina barrier layer, a top alumina barrier layer, and a titanium nitride gate electrode layer;

FIG. 5 is a top aluminum oxide barrier layer etched to form a gate electrode defined by photolithography;

FIG. 6 is a deposition of a silicon oxide isolation layer;

FIG. 7 is a through hole etched to a source drain silicon interface and a gate electrode surface;

FIG. 8 is a metal layer deposited, planarized, and patterned to form metal leads.

Fig. 9 is an illustration of the materials used in fig. 1-8.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples.

As shown in fig. 1 to 8, a multi-floating gate type synapse transistor with stacked polysilicon trapping layers is prepared according to the following steps:

1) thinning a silicon film of an SOI substrate, specifically oxidizing the silicon film on the surface into a silicon oxide film by dry oxygen oxidation or hydrogen-oxygen synthesis, rinsing the silicon oxide film on the surface by using a hydrofluoric acid solution, and then spin-coating HSQ glue, as shown in FIG. 1;

2) defining a nanowire mask by using an electron beam lithography technology, wherein the width of the nanowire mask is the line width of a subsequently formed silicon nanowire channel, as shown in fig. 2;

3) defining a source-drain mask by utilizing a photoetching technology, forming a mixed exposure mask with a dumbbell-shaped structure together with a hard mask above the nanowire, and then performing dry etching to form the dumbbell-shaped structure, wherein the mixed exposure mask is as shown in FIG. 3; removing the organic mask above the source and drain, reserving the inorganic hard mask above the silicon nanowire, heavily doping the source and drain by an ion implantation technology, then removing the inorganic hard mask by wet etching, and activating source and drain impurities by rapid thermal annealing;

4) generating a tunneling Layer silicon oxide film with the thickness of 2nm on the surface of the silicon nanowire channel through thermal oxidation, and then repeatedly depositing polycrystalline silicon with the thickness of 3nm by using a Low Pressure Chemical Vapor Deposition (LPCVD) technology and depositing an alumina barrier Layer with the thickness of 3nm by using an Atomic Layer Deposition (ALD) technology to form an interlayer medium of a multi-Layer polycrystalline silicon capture Layer-alumina barrier Layer; then, depositing a top aluminum oxide barrier Layer with a thickness of 8nm by using an Atomic Layer Deposition (ALD) technique, and finally depositing a titanium nitride metal Layer with a thickness of 100nm by using a Magnetron Sputtering (magnetic Sputtering) technique, as shown in fig. 4;

5) defining a gate electrode by using a photolithography technique, Etching a titanium nitride film to a top aluminum oxide layer by using an Inductively Coupled Plasma Etching (ICPE) with a photoresist as a mask, and performing appropriate over-Etching on the aluminum oxide layer to prevent a metal short circuit, as shown in fig. 5;

6) a 200nm thick silicon oxide isolation layer was deposited by low pressure Chemical vapor deposition and surface planarized by Chemical Mechanical Polishing (CMP), as shown in fig. 6;

7) defining a through hole above a source drain gate by using a photoetching technology, and etching off a silicon oxide isolation layer and an interlayer medium in the source drain through hole and a silicon oxide isolation layer in a gate through hole by using a photoresist as a mask and a dry etching technology, as shown in FIG. 7;

8) depositing metal titanium (adhesion layer) and metal aluminum in sequence by magnetron sputtering to fill the through hole and form a metal film, performing surface planarization by Chemical Mechanical Polishing (CMP), defining a metal lead-out wire by using a photolithography technique, and etching the metal layer to the silicon oxide isolation layer by using ICP, as shown in fig. 8.

The embodiments of the present invention are not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present invention, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.