阅读说明：本技术 一种星载数传发射装置、系统以及智能终端 (Satellite-borne data transmission transmitting device, system and intelligent terminal ) 是由 高恩宇 郇一恒 刁占林 齐培军 于 2021-10-12 设计创作，主要内容包括：本申请提供了一种星载数传发射装置、系统以及智能终端,包括：电源模块、基带模块、射频模块和接口模块,通过优化各模块之间的电路连接,减少电路占用的输入输出引脚数量,减少了星载数传发射系统的布线空间要求,改变各模块内芯片,减小模块占用空间,满足了卫星对数传发射机提出的体积小、容量大、下行码速率高的需求。相比现有技术中传统的数传分系统占用空间小,可以满足星载占用空间的要求。(The application provides a satellite-borne data transmission transmitting device, system and intelligent terminal, include: the satellite digital transmission transmitter comprises a power supply module, a baseband module, a radio frequency module and an interface module, wherein the number of input and output pins occupied by a circuit is reduced by optimizing the circuit connection among the modules, the wiring space requirement of the satellite digital transmission transmitting system is reduced, chips in the modules are changed, the occupied space of the modules is reduced, and the requirements of small size, large capacity and high downlink code rate provided by a satellite digital transmission transmitter are met. Compared with the traditional data transmission subsystem in the prior art, the system has small occupied space and can meet the requirement of space-borne occupied space.)

1. A satellite-borne data transmission transmitting device is characterized by comprising:

the radio frequency module is used for providing working current for the baseband module, the radio frequency module and the interface module;

the interface module includes: the system comprises a communication interface, a low-speed interface and a high-speed interface, wherein the high-speed interface adopts a CXP interface;

the baseband module includes: the high-level reduced instruction set machine is connected with the communication interface through a CAN bus interface, the high-level reduced instruction set machine is connected with the programmable logic array through an SPI interface, the programmable logic array receives external data through the low-speed interface and the high-speed interface, and the storage array is arranged in a parallel structure by adopting an embedded memory chip; the output end of the programmable logic array is connected with the input end of the digital-to-analog conversion circuit, and the output end of the digital-to-analog conversion circuit is connected with the radio frequency module.

2. The satellite-borne data transmission transmitting device according to claim 1, wherein the power supply module comprises a current limiting protection circuit, a relay, a surge suppression circuit, an EMI circuit, a voltage and current acquisition circuit and a voltage conversion circuit;

the current-limiting protection circuit, the relay, the surge suppression circuit, the EMI circuit, the voltage and current acquisition circuit and the voltage conversion circuit are sequentially connected in series, and the voltage conversion circuit is electrically connected with the baseband module, the radio frequency module and the interface module.

3. The satellite-borne data transmission transmitting device according to claim 1, further comprising:

the clock module is electrically connected with the power supply module, and the clock module is mutually connected with the baseband module, the radio frequency module and the interface module in parallel;

the output end of the clock module is connected with the baseband module and the radio frequency module.

4. The satellite-borne data transmission device according to claim 3, wherein the radio frequency module comprises:

the device comprises an intermediate frequency filtering unit, a temperature compensation attenuation circuit, an intermediate frequency amplifying unit, a frequency mixing unit, a local oscillation isolating unit, a first filtering unit, a driving amplifying unit, a second filtering unit, a power amplifying circuit, a coupling circuit, a detection circuit and an output isolating unit;

the input of intermediate frequency filter unit is connected in the baseband module conversion circuit's output, intermediate frequency filter unit's output is connected temperature compensation attenuator circuit's input, temperature compensation attenuator circuit's output is connected intermediate frequency amplifier unit's input, intermediate frequency amplifier unit's output is connected the input of mixing unit, mixing unit's output is connected first filter unit's input, first filter unit's output is connected drive amplifier unit's output is connected second filter unit's input, second filter unit's output is connected power amplifier circuit's input, power amplifier circuit's output is connected coupling circuit's input, coupling circuit's output is connected respectively output isolation unit's input with detection circuit's input And the output end of the detection circuit is connected with the advanced reduced instruction set machine through the input end connected with the communication interface.

5. The satellite-borne data transmission device according to claim 4, wherein the radio frequency module further comprises: the device comprises a local oscillator unit, a local oscillator filtering unit and a local oscillator amplifying unit;

the input of local oscillator unit is connected the output of clock module, the output of local oscillator unit is connected the input of local oscillator filter unit, the output of local oscillator filter unit is connected the input of local oscillator amplifying unit, the output of local oscillator amplifying unit is connected the input of local oscillator isolating unit, the output of local oscillator isolating unit with the output parallel connection of intermediate frequency amplifying unit is in the input of mixing unit.

6. The satellite-borne data transmission device according to claim 1, wherein the baseband module further comprises:

and the memory unit MRAM is connected with the advanced reduced instruction set machine through a data transmission channel and is used for receiving the secret key and the initial value sent by the advanced reduced instruction set machine.

7. The satellite-borne data transmission device according to claim 1, wherein the baseband module further comprises:

and the cache circuit is connected with the programmable logic array through a data transmission channel and is used for processing external data received through the high-speed interface.

8. A satellite-borne data transmission transmitting system, comprising: the box body, the satellite-borne output antenna and the satellite-borne data transmission transmitting device of any one of claims 1 to 7;

a partition wall is arranged in the box body, the box body is divided into a first space and a second space by the partition wall, a power module of the satellite borne data transmission transmitting device and a radio frequency module of the satellite borne data transmission transmitting device are placed in the first space of the box body, and a baseband module of the satellite borne data transmission transmitting device, an interface module of the satellite borne data transmission transmitting system and a clock module of the satellite borne data transmission transmitting system are fixed on the same PCB board card and are placed in the second space;

the radio frequency module is characterized in that an internal connector and an external connector are respectively arranged inside and outside the box body, the power module is connected with the baseband module through the internal connector, and the radio frequency module is connected with the clock module through the external connector.

9. The spaceborne data transmission system according to claim 8, wherein the wall thickness of the partition wall is larger than 2mm, and shielding cavities are arranged on two sides of the partition wall.

10. An intelligent terminal, characterized in that the intelligent terminal comprises the satellite-borne data transmission transmitting device according to any one of claims 1 to 7 and an intelligent device connected with the satellite-borne data transmission transmitting device.

Technical Field

The application relates to the technical field of spaceflight, in particular to a satellite-borne data transmission transmitting device, a satellite-borne data transmission transmitting system and an intelligent terminal.

Background

In low-orbit satellites launched in recent years, the remote sensing satellite accounts for over 30 percent. Satellite remote sensing technology is supported by many remote sensing instruments such as multispectral scanners, infrared radiometers, infrared detectors, and the like. With the increase of the number of remote sensing loads and the improvement of the resolution of a remote sensing camera, a satellite can generate a large amount of load data, and therefore the interface rate, the storage capacity and the downlink code rate of a satellite platform data transmission subsystem need to be improved.

The traditional data transmission subsystem has large equipment volume, the weight of the traditional data transmission subsystem often exceeds 5 kilograms, the total power consumption is over 50W, the load input of the traditional data transmission subsystem usually adopts a TLK2711 or a camera link interface, and a plurality of programmable logic array input and output pins are occupied, so that the volume is further increased, and the use of a rapidly developed remote sensing satellite cannot be met.

Disclosure of Invention

In view of this, an object of the present application is to provide a satellite borne data transmission transmitting device, a satellite borne data transmission transmitting system, and an intelligent terminal, which can reduce the requirement of the satellite borne data transmission transmitting system on the wiring space, and further reduce the volume of the satellite borne data transmission transmitting device, the satellite borne data transmission transmitting system, and the intelligent terminal.

In a first aspect, an embodiment of the present application provides a satellite-borne data transmission transmitting apparatus, including:

the radio frequency module is used for providing working current for the baseband module, the radio frequency module and the interface module;

the interface module includes: the system comprises a communication interface, a low-speed interface and a high-speed interface, wherein the high-speed interface adopts a high-speed interface CXP;

the baseband module includes: the high-level reduced instruction set machine is connected with the communication interface through a CAN bus so as to enable the baseband module to receive remote control information sent by a satellite-borne computer; the high-level compact instruction set machine is connected with the programmable logic array through the SPI, the programmable logic array receives the remote control information, the programmable logic array receives external data through the low-speed interface and the high-speed interface, so that the programmable logic array performs data interaction with the storage array according to the remote control information and the external data, and the storage array is arranged in a parallel structure by adopting an embedded memory chip; the output end of the programmable logic array is connected with the input end of the digital-to-analog conversion circuit, so that the digital-to-analog conversion circuit receives the digital signals sent by the programmable logic array, and the output end of the digital-to-analog conversion circuit is connected with the radio frequency module.

Optionally, the power supply module includes a current-limiting protection circuit, a relay, a surge suppression circuit, an EMI circuit, a voltage and current acquisition circuit, and a voltage conversion circuit;

the current-limiting protection circuit, the relay, the surge suppression circuit, the EMI circuit, the voltage and current acquisition circuit and the voltage conversion circuit are sequentially connected in series, and the voltage conversion circuit is electrically connected with the baseband module, the radio frequency module and the interface module.

Optionally, the system further includes:

the clock module is electrically connected with the power supply module, and the clock module is mutually connected with the baseband module, the radio frequency module and the interface module in parallel;

the output end of the clock module is connected with the baseband module and the radio frequency module.

Optionally, the radio frequency module includes:

the device comprises an intermediate frequency filtering unit, a temperature compensation attenuation circuit, an intermediate frequency amplifying unit, a frequency mixing unit, a local oscillation isolating unit, a first filtering unit, a driving amplifying unit, a second filtering unit, a power amplifying circuit, a coupling circuit, a detection circuit and an output isolating unit;

the input of intermediate frequency filter unit is connected in the baseband module conversion circuit's output, intermediate frequency filter unit's output is connected temperature compensation attenuator circuit's input, temperature compensation attenuator circuit's output is connected intermediate frequency amplifier unit's input, intermediate frequency amplifier unit's output is connected the input of mixing unit, mixing unit's output is connected first filter unit's input, first filter unit's output is connected drive amplifier unit's output is connected second filter unit's input, second filter unit's output is connected power amplifier circuit's input, power amplifier circuit's output is connected coupling circuit's input, coupling circuit's output is connected respectively output isolation unit's input with detection circuit's input And the output end of the detection circuit is connected with the advanced reduced instruction set machine through the input end connected with the communication interface.

Optionally, the radio frequency module further includes: the device comprises a local oscillator unit, a local oscillator filtering unit and a local oscillator amplifying unit;

the input of local oscillator unit is connected the output of clock module, the output of local oscillator unit is connected the input of local oscillator filter unit, the output of local oscillator filter unit is connected the input of local oscillator amplifying unit, the output of local oscillator amplifying unit is connected the input of local oscillator isolating unit, the output of local oscillator isolating unit with the output parallel connection of intermediate frequency amplifying unit is in the input of mixing unit.

Optionally, the baseband module further includes:

and the storage unit is connected with the advanced reduced instruction set machine through a data transmission channel and is used for receiving the secret key and the initial value sent by the advanced reduced instruction set machine.

Optionally, the baseband module further includes:

and the cache circuit is connected with the programmable logic array through a data transmission channel and is used for processing external data received through the high-speed interface.

In a second aspect, an embodiment of the present application provides a satellite-borne data transmission system, including: the satellite-borne data transmission system comprises a box body, a satellite-borne output antenna and a satellite-borne data transmission transmitting device;

a partition wall is arranged in the box body, the box body is divided into a first space and a second space by the partition wall, a power module of the satellite borne data transmission transmitting system and a radio frequency module of the satellite borne data transmission transmitting system are placed in the first space of the box body, and a baseband module of the satellite borne data transmission transmitting system, an interface module of the satellite borne data transmission transmitting system and a clock module of the satellite borne data transmission transmitting system are fixed on the same PCB board card and are placed in the second space;

the radio frequency module is characterized in that an internal connector and an external connector are respectively arranged inside and outside the box body, the power module is connected with the baseband module through the internal connector, and the radio frequency module is connected with the clock module through the external connector.

Optionally, the wall thickness of the partition wall is greater than 2mm, and shielding cavities are arranged on two sides of the partition wall.

In a third aspect, an embodiment of the present application provides an intelligent terminal, where the intelligent terminal includes the above satellite borne data transmission transmitting device and an intelligent device connected to the satellite borne data transmission transmitting device.

According to the satellite-borne data transmission transmitting system, the satellite-borne data transmission transmitting device and the intelligent terminal, the power module is arranged in the satellite-borne data transmission transmitting system in the intelligent terminal and is electrically connected with the baseband module, the radio frequency module and the interface module respectively, the power module is used for providing working current for the baseband module, the radio frequency module and the interface module, and the baseband module, the radio frequency module and the interface module are connected in parallel; the interface module includes: the system comprises a communication interface, a low-speed interface and a high-speed interface, wherein the high-speed interface adopts a high-speed interface CXP; the CXP drive chip has the characteristics of small size and few pins, and each output is connected to a pair of GTX high-speed interfaces of FPGA, two outputs occupy two pairs of GTX high-speed interfaces of FPGA, so as to reduce the occupation of input and output pins in the system, and simultaneously, the single-path rate of the GTX high-speed interfaces reaches 6.25Gbps, and the two input interface rates can reach 12.5Gbps, thereby greatly improving the data transmission rate, the baseband module comprises: the system comprises an advanced reduced instruction set machine, a programmable logic array, a storage array and a conversion circuit, wherein the input end of the advanced reduced instruction set machine is connected with the output end of the communication interface so that the baseband module receives remote control information sent by an on-board computer; the output end of the advanced reduced instruction set machine is connected with the input end of the programmable logic array, the programmable logic array receives the remote control information, the programmable logic array receives external data through the low-speed interface and the high-speed interface, so that the programmable logic array performs data interaction with the storage array according to the remote control information and the external data, and the storage array is arranged in a parallel structure by adopting an embedded memory chip; the embedded memory chip has the advantages of small volume and large capacity, the occupied space can be reduced on a large scale on the premise of ensuring the capacity, the output end of the programmable logic array is connected with the input end of the conversion circuit, so that the conversion circuit receives digital signals sent by the programmable logic array, and the output end of the conversion circuit is connected with the radio frequency module. The requirements of small volume, large capacity and high downlink code rate provided by the satellite for the number-transmission transmitter are met.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic diagram illustrating a circuit composition of a digital transmission transmitting apparatus according to an embodiment of the present application;

fig. 2 is a schematic diagram illustrating a CXP high-speed load input interface of a data transmission transmitting device according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating a memory array of a data transmission apparatus according to an embodiment of the present application;

fig. 4 is a signal flow diagram illustrating signal processing performed by an FPGA according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram illustrating a data transmission system provided in an embodiment of the present application;

fig. 6 shows a schematic structural diagram of an intelligent terminal provided in an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. Every other embodiment that can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present application falls within the protection scope of the present application.

In the description of the embodiments of the present application, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the present invention are usually placed in when used, and are only used for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements indicated must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

Furthermore, the terms "horizontal", "vertical" and the like do not imply that the components are required to be absolutely horizontal or pendant, but rather may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.

In the description of the embodiments of the present application, it should also be noted that, unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

First, an application scenario to which the present application is applicable will be described. This application can be applied to intelligent terminal technical field, along with the development of scientific and technological, more and more the appearance of intelligent terminal is in people's life, and people's daily life also more and more relies on intelligent terminal, how to guarantee that intelligent terminal is in normal power supply constantly, keeps normal operating condition and work efficiency, and then does not influence user's normal life, work, amusement etc. are the problem that needs to solve urgently.

Research shows that in the present stage, a traditional data transmission subsystem is often composed of three or more devices, the weight of the traditional data transmission subsystem is often more than 5 kilograms, the total power consumption is more than 50W, the load input of the traditional data transmission subsystem is often TLK2711 or camera link interfaces, the input and output pins of a plurality of FPGAs are occupied, the interface rate is less than 6Gbps, the storage capacity of the traditional data transmission subsystem is generally not more than 500GB, the downlink rate is below 300Mbps, and the traditional data transmission subsystem can not be used for a rapidly-developed remote sensing satellite.

Based on this, as shown in fig. 1, an embodiment of the present application provides a satellite borne data transmission transmitting system, including:

the radio frequency module is used for providing working current for the baseband module, the radio frequency module and the interface module;

the interface module includes: the system comprises a communication interface, a low-speed interface and a high-speed interface, wherein the high-speed interface adopts a high-speed interface CXP;

the baseband module includes: the system comprises an advanced reduced instruction set machine ARM, a programmable logic array FPGA, a storage array and a conversion DAC circuit, wherein the advanced reduced instruction set machine is connected with a communication interface through a CAN bus so that a baseband module receives remote control information sent by an on-board computer; the high-level compact instruction set machine is connected with the programmable logic array through the SPI, the programmable logic array receives the remote control information, the programmable logic array receives external data through the low-speed interface and the high-speed interface, so that the programmable logic array performs data interaction with the storage array according to the remote control information and the external data, and the storage array is arranged in a parallel structure by adopting an embedded memory chip; the output end of the programmable logic array is connected with the input end of the digital-to-analog conversion circuit, so that the digital-to-analog conversion circuit receives the digital signals sent by the programmable logic array, and the output end of the conversion circuit is connected with the radio frequency module.

In one possible embodiment, the power supply module comprises a current-limiting protection circuit, a relay, a surge suppression circuit, an EMI circuit, a voltage and current acquisition circuit and a voltage conversion circuit;

the current-limiting protection circuit, the relay, the surge suppression circuit, the EMI circuit, the voltage and current acquisition circuit and the voltage conversion circuit are sequentially connected in series, and the voltage conversion circuit is electrically connected with the baseband module, the radio frequency module and the interface module.

In one possible embodiment, the system further comprises:

the clock module is electrically connected with the power supply module, and the clock module is mutually connected with the baseband module, the radio frequency module and the interface module in parallel;

the output end of the clock module is connected with the baseband module and the radio frequency module.

In one possible embodiment, the radio frequency module includes:

the device comprises an intermediate frequency filtering unit, a temperature compensation attenuation circuit, an intermediate frequency amplifying unit, a frequency mixing unit, a local oscillation isolating unit, a first filtering unit, a driving amplifying unit, a second filtering unit, a power amplifying circuit, a coupling circuit, a detection circuit and an output isolating unit;

the input of intermediate frequency filter unit is connected in the baseband module conversion circuit's output, intermediate frequency filter unit's output is connected temperature compensation attenuator circuit's input, temperature compensation attenuator circuit's output is connected intermediate frequency amplifier unit's input, intermediate frequency amplifier unit's output is connected the input of mixing unit, mixing unit's output is connected first filter unit's input, first filter unit's output is connected drive amplifier unit's output is connected second filter unit's input, second filter unit's output is connected power amplifier circuit's input, power amplifier circuit's output is connected coupling circuit's input, coupling circuit's output is connected respectively output isolation unit's input with detection circuit's input And the output end of the detection circuit is connected with the advanced reduced instruction set machine through the input end connected with the communication interface.

In one possible implementation, the radio frequency module further includes: the device comprises a local oscillator unit, a local oscillator filtering unit and a local oscillator amplifying unit;

the input of local oscillator unit is connected the output of clock module, the output of local oscillator unit is connected the input of local oscillator filter unit, the output of local oscillator filter unit is connected the input of local oscillator amplifying unit, the output of local oscillator amplifying unit is connected the input of local oscillator isolating unit, the output of local oscillator isolating unit with the output parallel connection of intermediate frequency amplifying unit is in the input of mixing unit.

In one possible implementation, the baseband module further includes:

and the memory unit MRAM is connected with the advanced reduced instruction set machine through a data transmission channel and is used for receiving the secret key and the initial value sent by the advanced reduced instruction set machine.

Illustratively, as shown in fig. 1, the power supply module includes a current limiting protection circuit, a relay, a surge suppression circuit, an EMI circuit, a voltage and current acquisition circuit, and a voltage conversion circuit. The power supply module converts a primary power supply provided by a satellite platform into a secondary power supply required by the baseband module, the radio frequency module, the interface module and the clock module. When the digital transmitter needs to work, the satellite platform sends a starting instruction to control the relay in the power supply module to be started, a primary power supply 28V input signal provided by the satellite platform passes through a current-limiting protection circuit, the relay, a surge suppression circuit, an EMI circuit, a voltage current acquisition circuit and a voltage conversion circuit, and then 12V voltage required by the radio frequency module and 5V voltage required by the baseband module, the interface module and the clock module are output.

The baseband module comprises an ARM, an FPGA, a storage array, a cache circuit, a storage unit MRAM and a DAC circuit. And the baseband module receives data from the interface module according to the remote control information sent by the satellite-borne computer and stores the data. And the baseband module reads load data in the storage array according to remote control information sent by the spaceborne computer, processes the data, realizes digital-to-analog conversion, converts a digital signal into 720MHz intermediate frequency analog and sends the intermediate frequency analog to the radio frequency unit.

Specifically, the ARM receives a remote control instruction of the satellite borne computer through the communication interface CAN and performs information interaction with the FPGA according to instruction information, so that the FPGA performs functions of data storage or data reading, data processing and the like. The ARM sends the returned telemetering information to the satellite-borne computer through the communication interface CAN, and the telemetering information is mainly used for displaying information such as the working state of the satellite-borne data transmission transmitter. The ARM realizes the management function of the secret key and the initial value through the read-write operation of the MRAM. And the MRAM is used for receiving and storing important data such as a secret key and an initial value sent by the ARM. The storage unit MRAM storage data is not lost when power is down. The low-speed interface LVDS transmits the satellite low-speed load interface to the FPGA at the rate of 1Mbps-60Mbps, and the FPGA transmits data to the storage array according to a certain format. As shown in fig. 2, the high-speed interface CXP is an asymmetric point-to-point serial communication standard that can provide transmission speeds of at least 1.25Gbps (CXP-1) and at most 12.5Gbps (CXP-12). In the invention, two CXP-6 connections are selected, the single-path speed of the CXP-6 connection can reach 6.25Gbps, and the two input interface speeds can reach 12.5 Gbps. The CXP driving chip has the characteristics of small size and few pins, each output is connected to one pair of GTX high-speed interfaces of the FPGA, and the two outputs occupy two pairs of GTX high-speed interfaces of the FPGA. The FPGA firstly places high-speed load interface data into the cache DDR3 circuit, caches and arranges the data and then sends the DDR3 data to the storage array. As shown in fig. 3, the storage array receives and stores data sent by the FPGA; the storage array sends the stored data to the FPGA for signal processing; the memory array adopts a mode of parallel design of 12 eMMC (embedded memory) chips, and the eMMC has the advantages of small size and large capacity. The monolithic read-write speed is 130MBps, the monolithic capacity is 256GB at most, the total storage capacity of the 12 eMMC is 3072GB, and the requirement that the capacity is not less than 2TB can be met at the end of the service life of the memory. The memory array circuit design is shown in FIG. 4. The cache circuit is used for assisting the FPGA to write in and read load data; the cache circuit is composed of a plurality of DDR3 chips. The DAC circuit receives the digital signals sent by the FPGA and converts the digital signals into intermediate frequency signals required by the radio frequency unit; the frequency of the intermediate frequency signal of the DAC circuit data transmission is 720 MHz. The FPGA carries out data flow with the memory through the core logic block, the multimedia card interface and the memory interface.

The FPGA also needs to implement the function of signal processing, as shown in fig. 4. The FPGA signal processing flow mainly comprises encryption, data caching, framing, channel coding, scrambling, serial-parallel conversion, constellation mapping, forming filtering, interpolation, modulation and the like.

Specifically, the encryption adopts an AES256 counter mode, and information such as a key and an initial value thereof is stored in the memory cell MRAM. The encryption module is a gating function module, and when downloading in a bright state, the encryption module does not change the downloaded data; when the data is downloaded in a secret state, the module encrypts the downloaded data and outputs the encrypted data to a subsequent processing module. The encryption module only encrypts data in a data domain without influencing the code rate of the downloaded data, and the downlink highest code rate of the invention is 800 Mbps. When encryption is executed, the FPGA reads information such as a secret key and an initial value in the MRAM through the ARM to encrypt load data. The data cache is used for input data cache and read-write clock isolation. And a synchronous filling frame processing module is added to the load data after the data caching, so that the synchronous filling frame processing of the data and the addition of a synchronous frame header are completed, and the framing function is realized. The channel coding implements high-gain channel coding on the input load data, and the example adopts LDPC coding conforming to CCSDS standard. The scrambling is to avoid the occurrence of all "0", all "1" long codes, and uses a pseudo-random sequence to scramble the encoded data. The serial-parallel conversion is used for converting the scrambled serial data stream into 3 paths of parallel data required by 8PSK modulation. The mapping is to map every 3bit signal into the level of the corresponding quadrature and in-phase branch circuit, generate I, Q two-path data for parallel output, map every 3bit into the level of the corresponding quadrature and in-phase branch circuit, the forming filtering is to effectively utilize the channel, the root raised cosine forming filtering, carry on the frequency spectrum compression to the transmitting signal, in order to eliminate the intersymbol interference and reach the prerequisite of the best detection, raise the utilization factor of the frequency spectrum, the forming filtering adopts the root raised cosine forming filter of the roll-off coefficient 0.25, when the downlink code rate is 800Mbp, its occupied channel bandwidth is about 333MHz, less than 350 MHz. The interpolation is used for making the transmission rate of the system configurable, completing the matching of different modulation rates and realizing the continuous and adjustable transmission rate. The modulation completes digital intermediate frequency modulation, and the output signal is an 8PSK signal. And D/A conversion is carried out on the output 8PSK signal through a DAC circuit in the baseband module, and the 8PSK signal is changed into an intermediate frequency 720M signal required by the radio frequency module.

The radio frequency module comprises an intermediate frequency filter, a temperature compensation attenuation circuit, an intermediate frequency amplifier, a frequency mixing unit, a local oscillator filter, a local oscillator amplifier, a local oscillator isolator, a first filter, a drive amplifier, a second filter, a power amplifier circuit, a coupling circuit, a detection circuit, an output isolator and the like. The radio frequency module receives an intermediate frequency 720MHz signal sent by the baseband module, and the received intermediate frequency signal is converted into a radio frequency X frequency band signal after filtering, attenuation and amplification; and the radio frequency module filters and amplifies the radio frequency signal after frequency conversion to the power of 2W, and then sends the radio frequency signal to the satellite-borne data transmission antenna. The radio frequency unit has a transmission power detection function, the detection result is a direct current level signal, and the direct current level signal is sent to the baseband unit. The radio frequency module is placed in the shielding structure cavity, and partitions are arranged among all functions and used for isolating and shielding signals.

Specifically, the intermediate frequency filter receives and filters an intermediate frequency signal sent by the baseband module, and sends the filtered signal to the temperature compensation attenuation circuit, where the center frequency of the intermediate frequency filter circuit is 720MHz, and the bandwidth is not less than 350 MHz. The temperature compensation attenuation circuit receives the intermediate frequency filtering signal and sends the signal after temperature compensation attenuation to the intermediate frequency amplifier; the temperature compensation attenuation circuit is used for compensating the gain change of the radio frequency module caused by the temperature change. And the intermediate frequency amplifier receives and amplifies the signal of the temperature compensation attenuation circuit, and sends the amplified signal to the mixing circuit, and the flatness in the intermediate frequency amplifier band is less than 0.5 dB. The mixing circuit receives the signals after the intermediate frequency amplification and the local oscillator isolation, converts the received intermediate frequency signals and the local oscillator signals into radio frequency X frequency band signals, and sends the converted radio frequency signals to the first filter. The frequency range of the radio frequency signal output by the frequency mixing circuit is 8025MHz-8375 MHz. The local oscillation unit receives a 100MHz clock signal sent by the clock module, generates a local oscillation signal after frequency change, and sends the local oscillation signal to the local oscillation filter; the local oscillation signal generated by the local oscillation unit is a low local oscillation signal 7480 MHz. The local oscillator filtering receiving and local oscillator signal sent by the local oscillator unit is filtered, and the filtered signal is sent to the local oscillator for amplification; the local oscillator filtering function is to prevent the generation of redundant mixing signals in the mixing after filtering out the harmonic waves and the out-of-band spurious signals of the local oscillator signals. And the local oscillator amplifying receives the local oscillator filtered signal for amplifying, and sends the amplified signal to the local oscillator isolation. The local oscillator amplification function is to provide sufficient driving power for the mixing, avoiding further mixing signal loss. And the local oscillator isolation receives the signals amplified by the local oscillator, isolates the received signals and sends the signals to the frequency mixing circuit. The local oscillator isolation function is to prevent the reverse transmission of local oscillator signals and simultaneously play a role in impedance matching. The first filtering receives the radio-frequency signals after the frequency mixing, and sends the filtered signals to the driving amplifier; the first filtering function is to filter out the mixed stray and out-of-band signals, and the bandwidth of the first filtering is not less than 350 MHz. The driving amplifier receives the first filtered signal, amplifies the first filtered signal and sends the amplified signal to the second filter; the function of the driving amplification is to provide enough driving power for the power amplifier circuit. The second filter receives the signal after the drive amplification and sends the filtered signal to the power amplifier circuit; the second filtering function is to filter out the mixed stray and out-of-band signals, and the bandwidth of the second filtering is not less than 350 MHz. And the power amplifier circuit receives the second filtered signal to amplify the power and sends the amplified signal to the coupling circuit. The output power of the power amplifier circuit is at least 2W. The coupling circuit receives the signal of the power amplifier circuit, sends the coupling signal to the detection circuit and sends the through signal to the output isolation; the function of the coupling circuit is to couple a part of signals sent by the power amplification circuit to the detection circuit. The detection circuit receives the coupling signal of the coupling circuit to detect power and sends the detected signal to the baseband module. The output signal of the detection circuit is a direct current level signal. And the output isolation signal receives the through signal of the coupling circuit for isolation, and sends the isolated signal to the satellite-borne antenna unit. The output isolation has the function of preventing the return of the transmitted signal and has the function of impedance matching.

The clock module at least comprises: a temperature compensation crystal oscillator and a clock distribution circuit; the frequency generated by the temperature compensation crystal oscillator is 100MHz, and the temperature stability is 2ppm at minus 40-80 ℃. The clock distribution chip is used for responding to the received clock signals and distributing the clock signals into 2 paths of reference clock signals according to preset clock distribution conditions; and respectively sending the distributed 2 paths of reference clock signals to the baseband module and the radio frequency module.

In one possible implementation, the baseband module further includes:

and the cache circuit is connected with the programmable logic array through a data transmission channel and is used for processing external data received through the high-speed interface.

In one possible implementation, as shown in fig. 5, an embodiment of the present application provides a satellite borne data transmission transmitting system, including: the satellite-borne data transmission system comprises a box body 100, a satellite-borne output antenna and the satellite-borne data transmission system;

a partition wall 110 is arranged in the box body, the partition wall divides the box body into a first space and a second space, a power module 210 of the satellite borne data transmission transmitting system and a radio frequency module 220 of the satellite borne data transmission transmitting system are arranged in the first space of the box body, and a baseband module 230 of the satellite borne data transmission transmitting system, an interface module 240 of the satellite borne data transmission transmitting system and a clock module 250 of the satellite borne data transmission transmitting system are fixed on the same PCB board card and are arranged in the second space;

an internal connector 120 and an external connector 130 are respectively arranged inside and outside the box body, the power module is connected with the baseband module through the internal connector, and the radio frequency module is connected with the clock module through the external connector.

In a possible embodiment, the wall thickness of the partition wall is greater than 2mm, and the partition wall is provided with shielding cavities 140 on both sides.

In a possible implementation manner, as shown in fig. 6, the present embodiment provides an intelligent terminal, which includes the above-mentioned satellite borne data transmission transmitting device 300 and an intelligent device 310 connected to the above-mentioned satellite borne data transmission transmitting device.

Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used for illustrating the technical solutions of the present application, but not limiting the same, and the scope of the present application is not limited thereto, and although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the exemplary embodiments of the present application, and are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.