阅读说明：本技术 阱电阻模型及利用该模型描述阱电阻的方法 (Trap resistance model and method for describing trap resistance by using same ) 是由 张晓东 张昊 于 2021-02-20 设计创作，主要内容包括：本发明公开了一种阱电阻模型及利用该模型描述阱电阻的方法,其中,测量在不同温度下不同长度和宽度的阱电阻器件阵列的iv曲线；提取长度相同但宽度不同的器件的电压系数；获取电压系数随宽度变化的趋势；得到电压系数与宽度的幂律关系；利用该模型描述阱电阻特性,在芯片设计仿真使用。本发明的阱电阻模型将宽度方向的电压系数考虑在内,同时包含了电压系数在宽度方向和长度方向的依赖关系,这样利用该模型能够更加准确地描述阱电阻,不但适用于宽度较大的器件,而且也适用于宽度较小的器件。(The invention discloses a trap resistance model and a method for describing trap resistance by using the same, wherein the iv curve of a trap resistance device array with different lengths and widths at different temperatures is measured; extracting voltage coefficients of devices with the same length but different widths; acquiring the trend of the voltage coefficient changing along with the width; obtaining a power law relation between a voltage coefficient and a width; the well resistance characteristics are described by using the model, and the model is used in chip design simulation. The well resistance model takes the voltage coefficient in the width direction into consideration, and simultaneously contains the dependency relationship of the voltage coefficient in the width direction and the length direction, so that the well resistance can be more accurately described by using the model, and the well resistance model is not only suitable for devices with larger widths, but also suitable for devices with smaller widths.)

1. A well resistance model, characterized in that the model is described using the following formula:

R＝rsh*(leff/weff)*tfac*[1.0+ec1*(weff^wec1)*v/(leff^elfact)+ec2*(weff^wec2)*v*v/(leff^(2*elfact))]；

leff＝l-dl-lwleff

weff＝w-dw-wwleff

tfac＝1+tc1*pt+tc2*pt*pt

pt＝temper-25

lwleff＝ll/(l^lln)+lw/(w^lwn)+lwl/[(l^lln)*(w^lwn)]

wwleff＝wl/(l^wln)+ww/(w^wwn)+wwl/[(l^wln)*(w^wwn)]

wherein lwleff is an effective length offset parameter calculated by a length/width/area of the resistor in a length direction, wleff is an effective width offset parameter calculated by a length/width/area of the resistor in a width direction, l is a length of the resistor, w is a width of the resistor, ll is a length direction offset length dependent parameter, lw is a length direction offset width dependent parameter, wl is a width direction offset length dependent parameter, ww is a width direction offset width dependent parameter, dl is a resistance etching length error, dw is a resistance etching width error, lln is a length direction offset length dependent parameter coefficient, lwn is a length direction offset width dependent parameter coefficient, lwl is a length direction offset length width cross coefficient, wln is a width direction offset length dependent parameter coefficient, wwn is a width dependent parameter coefficient, wwl is a width direction offset length width cross coefficient, leff is an effective length of a resistor, weff is an effective width of a resistor, temper is an actual temperature, pt is a difference value between the actual temperature and 25, tfac is a temperature coefficient term, tc1 is a first-order temperature coefficient, tc2 is a second-order temperature coefficient, R is a resistor, rsh is a square resistor, v is a voltage, elfact is an exponential term coefficient in a length direction, ec1 is a first-order voltage coefficient parameter, ec2 is a second-order voltage coefficient parameter, wec1 is a first-order voltage coefficient width direction dependent power index, and wec2 is a second-order voltage coefficient width direction dependent power index.

2. A method for describing well resistance using the well resistance model of claim 1, comprising the steps of:

step S1, measuring iv curves of the trap resistor device arrays with different lengths and widths at different temperatures;

step S2, extracting voltage coefficients of devices with the same length but different widths;

step S3, acquiring the trend of the voltage coefficient changing along with the width;

step S4, obtaining a power law relation between a voltage coefficient and a width;

step S5, describing the characteristics of the well resistance by the model of claim 1, for the design simulation of the chip.

Technical Field

The invention relates to the field of semiconductor integrated circuit design, in particular to a trap resistance model and a method for describing trap resistance by using the same.

Background

In analog circuit design, a resistor is a common important component, which requires high precision of the resistor and accurate resistor parameters to correctly describe the performance of the resistor. The conventional well resistance calculation formula at present is as follows:

lwleff＝ll/(l^lln)+lw/(w^lwn)+lwl/[(l^lln)*(w^lwn)]

wwleff＝wl/(l^wln)+ww/(w^wwn)+wwl/[(l^wln)*(w^wwn)]

leff＝l-dl-lwleff

weff＝w-dw-wwleff

pt＝temper-25

tfac＝1+tc1*pt+tc2*pt*pt

R＝rsh*(leff/weff)*tfac*[1.0+ec1*v/(leff^elfact)+ec2*v*v/(leff^(2*elfact))]

wherein lwleff is an effective length offset parameter calculated by a length/width/area of the resistor in a length direction, wleff is an effective width offset parameter calculated by a length/width/area of the resistor in a width direction, l is a length of the resistor, w is a width of the resistor, ll is a length direction offset length dependent parameter, lw is a length direction offset width dependent parameter, wl is a width direction offset length dependent parameter, ww is a width direction offset width dependent parameter, dl is a resistance etching length error, dw is a resistance etching width error, lln is a length direction offset length dependent parameter coefficient, lwn is a length direction offset width dependent parameter coefficient, lwl is a length direction offset length width cross coefficient, wln is a width direction offset length dependent parameter coefficient, wwn is a width dependent parameter coefficient, wwl is the length-width cross coefficient of the offset in the width direction, leff is the effective length of the resistor, weff is the effective width of the resistor, temper is the actual temperature, pt is the difference between the actual temperature and 25, tfac is the temperature coefficient term, tc1 is the first-order temperature coefficient, tc2 is the second-order temperature coefficient, R is the resistor, rsh is the square resistor, v is the voltage, elfact is the exponential term coefficient in the length direction, ec1 is the first-order voltage coefficient parameter, and ec2 is the second-order voltage coefficient parameter.

Fig. 1 to 4 are schematic diagrams illustrating the effect of fitting the resistance of devices with different widths by using a conventional well resistance model, in which a solid line represents the model fitting result and a dotted line represents the test result. The conventional well resistance model only considers the voltage coefficient in the length direction, and it is difficult to obtain the best fit of the well resistance, especially for the resistor with small width (narrow device), which has poor accuracy, as shown in fig. 1 and fig. 2.

Disclosure of Invention

The invention aims to provide a trap resistance model, which can solve the problem that the existing trap resistance model can not obtain accurate resistance only by considering the voltage coefficient in the length direction. Meanwhile, the invention also provides a method for describing the well resistance by using the model.

In order to solve the technical problem, the trap resistance model provided by the invention is described by adopting the following formula:

R＝rsh*(leff/weff)*tfac*[1.0+ec1*(weff^wec1)*v/(leff^elfact)+ec2*(weff^wec2)*v*v/(leff^(2*elfact))]；

leff＝l-dl-lwleff

weff＝w-dw-wwleff

tfac＝1+tc1*pt+tc2*pt*pt

pt＝temper-25

lwleff＝ll/(l^lln)+lw/(w^lwn)+lwl/[(l^lln)*(w^lwn)]

wwleff＝wl/(l^wln)+ww/(w^wwn)+wwl/[(l^wln)*(w^wwn)]

wherein lwleff is an effective length offset parameter calculated by a length/width/area of the resistor in a length direction, wleff is an effective width offset parameter calculated by a length/width/area of the resistor in a width direction, l is a length of the resistor, w is a width of the resistor, ll is a length direction offset length dependent parameter, lw is a length direction offset width dependent parameter, wl is a width direction offset length dependent parameter, ww is a width direction offset width dependent parameter, dl is a resistance etching length error, dw is a resistance etching width error, lln is a length direction offset length dependent parameter coefficient, lwn is a length direction offset width dependent parameter coefficient, lwl is a length direction offset length width cross coefficient, wln is a width direction offset length dependent parameter coefficient, wwn is a width dependent parameter coefficient, wwl is a width direction offset length width cross coefficient, leff is an effective length of a resistor, weff is an effective width of a resistor, temper is an actual temperature, pt is a difference value between the actual temperature and 25, tfac is a temperature coefficient term, tc1 is a first-order temperature coefficient, tc2 is a second-order temperature coefficient, R is a resistor, rsh is a square resistor, v is a voltage, elfact is an exponential term coefficient in a length direction, ec1 is a first-order voltage coefficient parameter, ec2 is a second-order voltage coefficient parameter, wec1 is a first-order voltage coefficient width direction dependent power index, and wec2 is a first-order voltage coefficient width direction dependent power index.

Meanwhile, in order to solve the above technical problem, the present invention further provides a method for obtaining a well resistance, comprising the following steps:

step S1, measuring iv curves of the trap resistor device arrays with different lengths and widths at different temperatures;

step S2, extracting voltage coefficients of devices with the same length but different widths;

step S3, acquiring the trend of the voltage coefficient changing along with the width;

step S4, obtaining a power law relation between a voltage coefficient and a width;

step S5, the characteristics of the well resistance are described by using the above model for the design simulation of the chip.

Compared with the existing trap resistance model, the trap resistance model takes the voltage coefficient in the width direction into consideration, and simultaneously contains the dependency relationship of the voltage coefficient in the width direction and the length direction, so that the trap resistance can be more accurately described by using the model, and the trap resistance model is not only suitable for devices with larger widths, but also suitable for devices with smaller widths.

Drawings

Fig. 1 to 4 are schematic diagrams illustrating the effect of resistance fitting on devices with different widths by using a conventional well resistance model;

FIG. 5 is a flow chart of a method of obtaining well resistance in the present invention;

FIGS. 6-9 are schematic diagrams illustrating the effect of using the well resistance model of the present invention to perform resistance fitting on devices of different widths;

fig. 10 and 11 are fitting curves obtained by using the well resistance model of the present invention to describe the relationship between the fitting voltage coefficient and the effective resistance width in the process of well resistance description.

Detailed Description

Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein it is shown in the accompanying drawings, wherein the specific embodiments are by way of illustration. In the following description, specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced or applied in different embodiments, and the details may be based on different viewpoints and applications, and may be widely spread and replaced by those skilled in the art without departing from the spirit of the present invention.

In view of the fact that only the dependence of the voltage coefficient and the resistance length is considered in the conventional well resistance model, it is difficult to obtain an accurate fitting result for some narrow devices with small widths.

On the basis, the well resistance model of the application fully considers the dependency relationship between the voltage coefficient and the resistance width, and is described by the following formula:

R＝rsh*(leff/weff)*tfac*[1.0+ec1*(weff^wec1)*v/(leff^elfact)+ec2*(weff^wec2)*v*v/(leff^(2*elfact))]；

leff＝l-dl-lwleff

weff＝w-dw-wwleff

tfac＝1+tc1*pt+tc2*pt*pt

pt＝temper-25

lwleff＝ll/(l^lln)+lw/(w^lwn)+lwl/[(l^lln)*(w^lwn)]

wwleff＝wl/(l^wln)+ww/(w^wwn)+wwl/[(l^wln)*(w^wwn)]

wherein lwleff is an effective length offset parameter calculated by a length/width/area of the resistor in a length direction, wleff is an effective width offset parameter calculated by a length/width/area of the resistor in a width direction, l is a length of the resistor, w is a width of the resistor, ll is a length direction offset length dependent parameter, lw is a length direction offset width dependent parameter, wl is a width direction offset length dependent parameter, ww is a width direction offset width dependent parameter, dl is a resistance etching length error, dw is a resistance etching width error, lln is a length direction offset length dependent parameter coefficient, lwn is a length direction offset width dependent parameter coefficient, lwl is a length direction offset length width cross coefficient, wln is a width direction offset length dependent parameter coefficient, wwn is a width dependent parameter coefficient, wwl is a width direction offset length width cross coefficient, leff is an effective length of a resistor, weff is an effective width of a resistor, temper is an actual temperature, pt is a difference value between the actual temperature and 25, tfac is a temperature coefficient term, tc1 is a first-order temperature coefficient, tc2 is a second-order temperature coefficient, R is a resistor, rsh is a square resistor, v is a voltage, elfact is an exponential term coefficient in a length direction, ec1 is a first-order voltage coefficient parameter, ec2 is a second-order voltage coefficient parameter, wec1 is a first-order voltage coefficient width direction dependent power index, wec2 is a second-order voltage coefficient width direction dependent power index, and wec1 and wec2 are fitting values.

The method for describing the well resistance based on the well resistance model, as shown in fig. 5, includes the following steps:

step S1, measuring iv (current-voltage) curves of the trap resistor device arrays with different lengths and widths at different temperatures;

step S2, extracting voltage coefficients of devices with the same length but different widths;

step S3, acquiring the trend of the voltage coefficient changing along with the width;

step S4, obtaining a power law relation between a voltage coefficient and a width;

step S5, characterizing the well resistance by using the model of claim 1 for design simulation of the chip.

The above description is of a method for describing well resistance using the well resistance model of the present invention, and is described with reference to an embodiment.

Firstly, measuring iv curves of trap resistor device arrays with different lengths and widths at different temperatures;

then, devices with the same length but different widths are selected, voltage coefficients, for example, trap resistances with a set of sizes of W/L0.9/100, W/L1.2/100, W/L10/100 and W/L20/100 are extracted, and the voltage coefficients are extracted;

then, acquiring the trend of the voltage coefficient changing along with the width;

then, determining the power law relation between the voltage coefficient and the width;

specifically, the voltage coefficient formula R ═ a (1+ VCR1 ═ v + VCR2 ×. v), where VCR1 is the first order voltage coefficient and VCR2 is the second order voltage coefficient. FIGS. 10 and 11 are graphs of the fit of VCR1 and VCR2 to the effective width of the resistor, respectively, where the indicator R of the degree of fit of the trend line²The closer to 1, the higher the degree of fit; during the actual fitting process, wec1 and wec2 are adjusted to fit the voltage coefficient to the effective width of the resistor;

finally, the well resistance is described based on the above model.

Fig. 6 to 9 are schematic diagrams illustrating the effect of fitting the resistance of devices with different widths by using the well resistance model of the present invention, wherein the solid line represents the model fitting result, and the dotted line represents the test result. The well resistance model of the invention takes the voltage coefficient in the width direction into consideration and also includes the dependency relationship of the voltage coefficient in the width direction and the length direction, so that the well resistance can be more accurately obtained by using the model, and the well resistance model is not only suitable for devices with larger width (as shown in fig. 8 and 9) but also suitable for devices with smaller width (as shown in fig. 6 and 7).

The present invention has been described in detail with reference to the specific embodiments, which are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. Equivalent alterations and modifications made by those skilled in the art without departing from the principle of the invention should be considered to be within the technical scope of the invention.