阅读说明：本技术 五倍频器及其方法 (Five-time frequency converter and method thereof ) 是由 林嘉亮 于 2020-05-15 设计创作，主要内容包括：本公开提供一种五倍频器及方法。五倍频器包括第一、第二、第三、第四、第五三态电荷泵以及负载。第一三态电荷泵接收五相位时钟的第一及第三相位信号,并输出第一电流至输出节点。第二三态电荷泵接收五相位时钟的第二及第四相位信号,并输出第二电流至输出节点。第三三态电荷泵接收五相位时钟的第三及第五相位信号,并输出第三电流至输出节点。第四三态电荷泵接收五相位时钟的第四及第一相位信号,并输出第四电流至输出节点。第五三态电荷泵接收五相位时钟的第五及第二相位信号,并输出第五电流至输出节点。负载耦接于输出节点。(The present disclosure provides a five-fold frequency converter and a method. The five-time frequency multiplier comprises a first tri-state charge pump, a second tri-state charge pump, a third tri-state charge pump, a fourth tri-state charge pump, a fifth tri-state charge pump and a load. The first tri-state charge pump receives the first and third phase signals of the five-phase clock and outputs a first current to the output node. The second tri-state charge pump receives the second and fourth phase signals of the five-phase clock and outputs a second current to the output node. The third tri-state charge pump receives the third and fifth phase signals of the five-phase clock and outputs a third current to the output node. The fourth tri-state charge pump receives the fourth and first phase signals of the five-phase clock and outputs a fourth current to the output node. The fifth tri-state charge pump receives the fifth and second phase signals of the five-phase clock and outputs a fifth current to the output node. The load is coupled to the output node.)

1. A five-fold frequency converter, comprising:

a first tri-state charge pump for receiving a first phase signal of a five-phase clock and a third phase signal of the five-phase clock and outputting a first current to an output node;

a second tri-state charge pump for receiving a second phase signal of the five-phase clock and a fourth phase signal of the five-phase clock and outputting a second current to the output node;

a third tri-state charge pump for receiving the third phase signal of the five-phase clock and a fifth phase signal of the five-phase clock and outputting a third current to the output node;

a fourth tri-state charge pump for receiving the fourth phase signal of the five-phase clock and the first phase signal of the five-phase clock and outputting a fourth current to the output node;

a fifth tri-state charge pump for receiving the fifth phase signal of the five-phase clock and the second phase signal of the five-phase clock and outputting a fifth current to the output node; and

a load coupled to the output node.

2. The five-fold frequency converter as claimed in claim 1, wherein the first tri-state charge pump, the second tri-state charge pump, the third tri-state charge pump, the fourth tri-state charge pump and the fifth tri-state charge pump are all a charge pump circuit, the charge pump circuit is in a negative output current state, a positive output current state or a zero output current state according to two control signals, wherein the two control signals are logic signals, and the logic signals are in a first logic state or a second logic state.

3. The penta-frequency divider of claim 2, wherein:

when the two control signals are both in the first logic state, the charge pump circuit is in the negative output current state;

when the two control signals are both in the second logic state, the charge pump circuit is in the positive output current state; and

when one of the two control signals is in the first logic state and the other of the two control signals is in the second logic state, the charge pump circuit is in the zero output current state.

4. The five-fold frequency divider of claim 3, wherein:

the first phase signal of the five-phase clock and the third phase signal of the five-phase clock are the two control signals of the first tri-state charge pump;

the second phase signal of the five-phase clock and the fourth phase signal of the five-phase clock are the two control signals of the second tri-state charge pump;

the third phase signal of the five-phase clock and the fifth phase signal of the five-phase clock are the two control signals of the third tri-state charge pump;

the fourth phase signal of the five-phase clock and the first phase signal of the five-phase clock are the two control signals of the fourth tri-state charge pump; and

the fifth phase signal of the five-phase clock and the second phase signal of the five-phase clock are the two control signals of the fifth tri-state charge pump.

5. The five-fold frequency divider of claim 1 wherein the load comprises a parasitic capacitor.

6. The five-fold frequency converter of claim 1, wherein the load comprises a resonant tank, the resonant tank comprising:

an inductor; and

a capacitor;

wherein the inductor and the capacitor are connected in parallel.

7. The five-fold frequency divider of claim 6, wherein the resonant frequency of the resonant tank is higher than a fundamental frequency of the five-phase clock and five times the fundamental frequency of the five-phase clock.

8. A method of frequency quintupling, comprising:

receiving a five-phase clock, wherein the five-phase clock comprises a first phase signal, a second phase signal, a third phase signal, a fourth phase signal and a fifth phase signal;

outputting a first current to an output node by using a first tri-state charge pump according to the first phase signal of the five-phase clock and the third phase signal of the five-phase clock;

outputting a second current to the output node by using a second tri-state charge pump according to the second phase signal of the five-phase clock and the fourth phase signal of the five-phase clock;

outputting a third current to the output node by using a third tri-state charge pump according to the third phase signal of the five-phase clock and the fifth phase signal of the five-phase clock;

outputting a fourth current to the output node by using a fourth tri-state charge pump according to the fourth phase signal of the five-phase clock and the first phase signal of the five-phase clock;

outputting a fifth current to the output node using a fifth tri-state charge pump according to the fifth phase signal of the five-phase clock and the second phase signal of the five-phase clock; and

a load is coupled to the output node.

9. The method of claim 8, wherein the first tri-state charge pump, the second tri-state charge pump, the third tri-state charge pump, the fourth tri-state charge pump, and the fifth tri-state charge pump are all a charge pump circuit, the charge pump circuit being in a negative output current state, a positive output current state, or a zero output current state according to two control signals, wherein the two control signals are logic signals, the logic signals being in a first logic state or a second logic state.

10. The frequency quintupling method of claim 9, wherein:

when the two control signals are both in the first logic state, the charge pump circuit is in the negative output current state;

when the two control signals are both in the second logic state, the charge pump circuit is in the positive output current state; and

when one of the two control signals is in the first logic state and the other of the two control signals is in the second logic state, the charge pump circuit is in the zero output current state.

Technical Field

The present disclosure relates to frequency quintuple, and more particularly, to a frequency quintuple and a method thereof capable of reducing a pull-up frequency of a voltage controlled oscillator and frequency modulation of noise.

Background

A five-multiplier (frequency quintupler) receives an input clock at a fundamental frequency and outputs an output clock at a frequency five times higher than the fundamental frequency (i.e., the output frequency is five times the fundamental frequency). For example, if the fundamental frequency is 2 gigahertz (GHz), the quintupling frequency is 10 GHz. The quintupling of the frequency is typically accomplished using a phase lock loop (phase lock loop). The phase-locked loop includes a frequency/phase detector (frequency/phase detector), a loop filter (loop filter), a voltage-controlled oscillator (VCO), and a frequency-by-5 circuit (frequency-by-5 circuit). The frequency/phase detector is used for receiving an input clock and a down-clock (digital-down clock) and outputting a phase error signal. The loop filter is used for receiving the phase error signal and outputting a control voltage. The voltage control oscillator is used for receiving the control voltage and outputting an output clock. The quintuple frequency dividing circuit is used for receiving the output clock and outputting the frequency-reducing clock, so that the frequency of the frequency-reducing clock is one fifth of the frequency of the output clock.

Phase locked loops are well known to those skilled in the art and therefore will not be described in detail herein. In a phase locked loop, a VCO is subject to a problem called "VCO pulling", in which the oscillation frequency of the VCO is pulled by an interference signal (a frequency that is similar to the natural oscillation frequency of the VCO) rather than being controlled by a control voltage. Furthermore, voltage controlled oscillators are subject to unwanted frequency modulation, which is generated by the power supply noise of the voltage controlled oscillator.

Therefore, what is desired is a penta-multiplier and method thereof that reduces the pull-up of the vco and the frequency modulation of the noise.

Disclosure of Invention

In one embodiment, the five-multiplier comprises a first tri-state charge pump, a second tri-state charge pump, a third tri-state charge pump, a fourth tri-state charge pump, a fifth tri-state charge pump and a load. The first tri-state charge pump is used for receiving a first phase signal of the five-phase clock and a third phase signal of the five-phase clock and outputting a first current to an output node. The second tri-state charge pump is used for receiving the second phase signal of the five-phase clock and the fourth phase signal of the five-phase clock and outputting a second current to the output node. The third tri-state charge pump is used for receiving a third phase signal of the five-phase clock and a fifth phase signal of the five-phase clock and outputting a third current to the output node. The fourth tri-state charge pump is used for receiving a fourth phase signal of the five-phase clock and the first phase signal of the five-phase clock and outputting a fourth current to the output node. The fifth tri-state charge pump is configured to receive a fifth phase signal of the five-phase clock and the second phase signal of the five-phase clock, and output a fifth current to the output node. The load is coupled to the output node.

In one embodiment, the frequency quintupling method comprises the steps of: receiving a five-phase clock, wherein the five-phase clock comprises a first phase signal, a second phase signal, a third phase signal, a fourth phase signal and a fifth phase signal; outputting a first current to an output node by using a first tri-state charge pump according to a first phase signal of a five-phase clock and a third phase signal of the five-phase clock; outputting a second current to an output node by using a second tri-state charge pump according to a second phase signal of the five-phase clock and a fourth phase signal of the five-phase clock; outputting a third current to an output node by using a third tri-state charge pump according to a third phase signal of the five-phase clock and a fifth phase signal of the five-phase clock; outputting a fourth current to the output node by using a fourth tri-state charge pump according to a fourth phase signal of the five-phase clock and the first phase signal of the five-phase clock; outputting a fifth current to the output node by using a fifth three-state charge pump according to a fifth phase signal of the five-phase clock and a second phase signal of the five-phase clock; and coupling the output node using a load.

Drawings

Fig. 1 is a functional block diagram of a five-fold frequency divider according to some embodiments of the present disclosure.

Fig. 2 is a schematic diagram of a tri-state charge pump, shown in accordance with some embodiments of the present disclosure.

Fig. 3 is a functional block diagram of a five-multiplier according to some embodiments of the present disclosure, the five-multiplier of fig. 3 in combination with the five-multiplier of fig. 1 can implement a differential five-multiplier.

Fig. 4 is a flow chart of a method of frequency quintupling as shown in accordance with some embodiments of the present disclosure.

Description of the symbols

100: five-time frequency converter

101: output node

110: first three-state charge pump

120: second three-state charge pump

130: third tri-state charge pump

140: fourth tri-state charge pump

150: fifth three-state charge pump

160: load(s)

211: n-type transistor

212: n-type transistor

221: p-type transistor

222: p-type transistor

300: five-time frequency converter

301: output node

310: first three-state charge pump

320: second three-state charge pump

330: third tri-state charge pump

340: fourth tri-state charge pump

350: fifth three-state charge pump

360: load(s)

S₀: first phase signal

S₁: second phase signal

S₂: third phase signal

S₃: fourth phase signal

S₄: fifth phase signal

S_OUT: output clock

I₀: first current

I₁: the second current

I₂: third current

I₃: the fourth current

I₄: the fifth current

I_S: total current of

S’₀: first phaseSignal

S’₁: second phase signal

S’₂: third phase signal

S’₃: fourth phase signal

S’₄: fifth phase signal

S’_OUT: output clock

I’₀: first current

I’₁: the second current

I’₂: third current

I’₃: the fourth current

I’₄: the fifth current

I’_S: total current of

V_CM: direct current node

V_DD: power supply node

V_SS: DC grounding node

410-470 parts by weight: step (ii) of

Detailed Description

The present disclosure relates to quintupling frequencies. While several preferred modes of carrying out the disclosure are described in the specification, it is to be understood that the disclosure may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth below or to specific ways to practice the features described below. In other instances, well-known details will not be set forth or discussed in order to avoid obscuring the focus of the present disclosure.

Those skilled in the art will understand the terms and concepts used in the present disclosure with respect to microelectronics, such as "voltage", "current", "node", "power node", "ground", "signal", "logic inversion (local inversion)", "clock", "frequency", "period", "phase", "Complementary Metal Oxide Semiconductor (CMOS)", "N-type transistor (NMOS)", "P-type transistor (PMOS)", "single-ended", "differential", "charge pump", "cascode", and "dc". Terms like the above are often used in the field of microelectronics and the related concepts will be obvious to a person skilled in the art and will therefore not be explained in detail here. One skilled in the art can also recognize the circuit symbols for the P-type transistor and the N-type transistor and can distinguish which is the "source", "gate" and "drain". One skilled in the art can also read the schematic diagram of a circuit comprising N-type transistors and/or P-type transistors without having to describe in detail how a transistor is connected to another transistor in the schematic diagram. Units such as micrometers and nanometers are also understood by those skilled in the art.

The present disclosure is expressed from an engineering aspect (i.e., from the aspect of one skilled in the art). For example, "X equals Y" means "the difference between X and Y is less than a certain engineering tolerance". "X is significantly less than Y" means that "the ratio between X and Y is less than a certain engineering tolerance". "X is zero" means "X is less than a specified engineering tolerance".

In the present disclosure, the signal representing the information (information) is either a voltage or a current.

In the present disclosure, a logic signal is a voltage signal having two possible states, i.e., a high state and a low state. When the level of the logic signal is higher than a trip point (trip point) associated with the logic signal, the logic signal is said to be in a high state. Conversely, a logic signal is said to be in a low state when the level of the logic signal is below a trip point associated with the logic signal. In the context of a logic signal, it is stated that "(logic signal) X is high", which means that "(logic signal) X is in a high state". Similarly, in the context of a logic signal, it is stated that "(logic signal) X is low", which means that "(logic signal) X is in a low state". The high state is also referred to as "1" state, and the low state is also referred to as "0" state. In the context of a logic signal, it is stated that "(logic signal) X is 1", which means that "(logic signal) X is in a high potential state". Likewise, in the context of a logic signal, it is stated that the "(logic signal) X signal is 0" which means that the "(logic signal) X is in a low state".

In the present disclosure, it is assumed that the first logic signal and the second logic signal are always in opposite states, i.e., when one of them is 1 and the other is 0, the first logic signal is a logical inversion of the second logic signal.

In the present disclosure, when the first logic signal is the logical inverse of the second logic signal, the first logic signal and the second logic signal are complementary.

In the present disclosure, when a first current is considered to be the opposite of a second current, the first and second currents have approximately the same magnitude but opposite signs.

In the present disclosure, a "clock signal" (or simply "clock") is a logic signal that is periodically switched between a low state and a high state.

In the present disclosure, the power supply node is at "V_DD"means. For convenience of explanation, "V" is_DD"may also refer to the supply voltage provided at the supply node. That is, "V_DDIs 0.9 volts (V) "means" the supply voltage V of the supply node_DDAt 0.9 volts. By way of example and not limitation, in the present disclosure, the circuit is fabricated using a 28 nanometer CMOS process, and the supply voltage V of the supply node_DDAt 0.9 volts.

In this disclosure, "V_SS"denotes a Direct Current (DC) ground node. DC ground node V_SS"is nominally 0 volts.

The present disclosure discloses a five-fold frequency divider (frequency doubling apparatus), which can be implemented by a single-ended circuit or a differential circuit. First, an embodiment of a single-ended circuit will be described, and later, an embodiment of a complete differential circuit will be described.

Fig. 1 is a functional block diagram of a five-fold frequency divider 100 according to some embodiments of the present disclosure. Referring to FIG. 1, in some embodimentsFor the sake of brevity, the present specification will simply refer to the single-ended five-multiplier 100 as the five-multiplier 100, and will describe the five-multiplier 100. The five-fold frequency converter 100 receives a five-phase clock including a first phase signal S₀A second phase signal S₁A third phase signal S₂A fourth phase signal S₃And a fifth phase signal S₄And the frequency pentamultiplier 100 outputs an output clock S_OUT. The five-multiplier 100 includes a first tri-state charge pump (TSCP) 110, a second tri-state charge pump 120, a third tri-state charge pump 130, a fourth tri-state charge pump 140, a fifth tri-state charge pump 150, and a load 160. The first tri-state charge pump 110 is used for receiving a first phase signal S of a five-phase clock₀And a third phase signal S of a five-phase clock₂And outputs a first current I₀To the output node 101. The second tri-state charge pump 120 is used for receiving the second phase signal S of the five-phase clock₁And a fourth phase signal S of the five-phase clock₃And outputs a second current I₁To the output node 101. The third tri-state charge pump 130 is used for receiving the third phase signal S of the five-phase clock₂And a fifth phase signal S of the five-phase clock₄And outputs a third current I₂To the output node 101. The fourth tri-state charge pump 140 is used for receiving the fourth phase signal S of the five-phase clock₃And a first phase signal S of a five-phase clock₀And outputs a fourth current I₃To the output node 101. The fifth tri-state charge pump 150 is used for receiving the fifth phase signal S4 of the five-phase clock and the second phase signal S of the five-phase clock₁And outputs a fifth current I₄To the output node 101. The load 160 is used to terminate the output node 101 and establish the output clock S_OUT. Here, "V" is_CM"denotes a dc node.

In some embodiments, assume that the period of the five-phase clock is T. Mathematically, a five-phase clock can be represented by the following equation:

herein, "T" is a time variable, "mod (·, ·) represents a modulus function (modular function), and" mod (T, T) "is the remainder of T divided by T, in some embodiments.

In some embodiments, mathematically, the first tri-state charge pump 110 can be implemented by the following equation:

herein, in some embodiments, "I_E"represents a current value. When the first phase signal S₀And a third phase signal S₂When both are 0, the first tri-state charge pump 110 outputs a positive current. When the first phase signal S₀And a third phase signal S₂With 1, the first tri-state charge pump 110 outputs a negative current. Otherwise (e.g. when the first phase signal S₀And a third phase signal S₂Is 0, and the first phase signal S₀And a third phase signal S₂Is 1), the first tri-state charge pump 110 outputs zero current. Similarly, the first tri-state charge pump 110, the second tri-state charge pump 120, the third tri-state charge pump 130, the fourth tri-state charge pump 140, and the fifth tri-state charge pump 150 can be divided intoThe following equations are used:

in some embodiments, the first phase signal S₀A second phase signal S₁A third phase signal S₂A fourth phase signal S₃And a fifth phase signal S₄Added at the output node 101, thus obtaining the total current I_S. The total current I between one cycle of the five-phase clock according to equations (1), (2), (3), (4), (5), (6), (7), (8), (9) and (10)_SAre shown in table 1 below:

table 1:

in some embodiments, as shown in Table 1, the total current I_SIs periodic and the total current I_SCorresponding to each cycle of the input five-phase clock. The five-fold frequency converter 100 can realize the function of five times frequency. The load 160 acts as an impedance at the output node 101 and provides the total current I_SEfficient conversion to output clock S_OUT：

S_OUT＝I_SZ_L。 (11)

Herein, in some embodiments, Z_LIs the impedance value of the load 160. Thus, the clock S is output_OUTHaving five times the frequency.

Fig. 2 is a schematic diagram of a tri-state charge pump (e.g., the first tri-state charge pump 110) according to some embodiments of the present disclosure. Referring to fig. 2, in some embodiments, the first tri-state charge pump 110 includes an N-type transistor 211, an N-type transistor 212, a P-type transistor 221, and a P-type transistor 222. The N-type transistor 211 is driven by the first phase signal S₀Controlling the N-type transistor 212 to be controlled by the third phase signal S₂And the N-type transistor 211 and the N-type transistor 212 are configured in a cascode topology. The P-type transistor 221 is driven by the first phase signal S₀Controlling the P-type transistor 222 to be driven by the third phase signal S₂The P-type transistor 221 and the P-type transistor 222 are controlled and configured in a stacked topology. When the first phase signal S₀And a third phase signal S₂Is 0 (i.e., low state), the N-type transistor 211 and the N-type transistor 212 are turned off, the P-type transistor 221 and the P-type transistor 222 are turned on, and the current flowing through the P-type transistor 221 and the P-type transistor 222 is from the power supply node V_DDFlows to the output node 101, thus obtaining a positive first current I₀. When the first phase signal S₀And a third phase signal S₂When both are 1 (i.e., high state), the P-type transistor 221 and the P-type transistor 222 are turned off, the N-type transistor 211 and the N-type transistor 212 are turned on, and the current flowing through the N-type transistor 211 and the N-type transistor 212 flows from the output node 101 to the DC ground node V_SSThus obtaining a negative first current I₀. Otherwise (e.g. when the first phase signal S₀And a third phase signal S₂Is 0, and the first phase signal S₀And a third phase signal S₂When the other is 1), at power supply node V_DDNo current conduction path to the output node 101, and a DC ground node V_SSNo current conduction path to the output node 101So as to obtain a first current I of zero value₀. For a detailed description of the interconnection between devices and/or nodes, for example, "the source of the N-type transistor 212 is connected to the drain of the N-type transistor 211, and the gate of the N-type transistor 212 is connected to the third phase signal S₂And the drain of the N-type transistor 212 is connected to the drain of the P-type transistor 222, and the drain of the N-type transistor 212 and the drain of the P-type transistor 222 are connected to the output node 101 "are not necessary as they will be apparent to those skilled in the art.

In some embodiments, the first phase signal S is replaced₀For the second phase signal S₁And replacing the third phase signal S₂Is a fourth phase signal S₃The first tri-state charge pump 110 of fig. 2 can be used to implement the second tri-state charge pump 120. Replacing the first phase signal S₀Is a third phase signal S₂And replacing the third phase signal S₂Is a fifth phase signal S₄The first tri-state charge pump 110 of fig. 2 can be used to implement the third tri-state charge pump 130. Replacing the first phase signal S₀Is a fourth phase signal S₃And replacing the third phase signal S₂Is a first phase signal S₀The first tri-state charge pump 110 of fig. 2 can be used to implement the fourth tri-state charge pump 140. Replacing the first phase signal S₀Is a fifth phase signal S₄And replacing the third phase signal S₂For the second phase signal S₁The first tri-state charge pump 110 of fig. 2 can be used to implement the fifth tri-state charge pump 150.

In some embodiments, the first tri-state charge pump 110, the second tri-state charge pump 120, the third tri-state charge pump 130, the fourth tri-state charge pump 140, and the fifth tri-state charge pump 150 are charge pump circuits. The charge pump circuit is in a negative output current state, a positive output current state, or a zero output current state according to the two control signals. Specifically, when the charge pump circuit outputs a negative current, the charge pump circuit is in a negative output current state. When the charge pump circuit outputs a positive current, the charge pump circuit is in a positive output current state. When the charge pump circuit outputs zero current, the charge pump circuit is in a zero output current state.

In some embodiments, the charge pump circuit is in a negative output current state when both control signals are in a first logic state (i.e., both are 1). When both control signals are in the second logic state (i.e., both are 0), the charge pump circuit is in the positive output current state. When one of the two control signals is in a first logic state (i.e., is 1) and the other of the two control signals is in a second logic state (i.e., is 0), the charge pump circuit is in a zero output current state.

In some embodiments, the first phase signal S of the five-phase clock₀And a third phase signal S of a five-phase clock₂Two control signals for the first tri-state charge pump 110. Second phase signal S of five-phase clock₁And a fourth phase signal S of the five-phase clock₃Two control signals for the second tri-state charge pump 120. Third phase signal S of five-phase clock₂And a fifth phase signal S of the five-phase clock₄Two control signals for the third tri-state charge pump 130. Fourth phase signal S of five-phase clock₃And a first phase signal S of a five-phase clock₀Two control signals for the fourth tri-state charge pump 140. Fifth phase signal S of five-phase clock₄And a second phase signal S of a five-phase clock₁Two control signals for the fifth tri-state charge pump 150.

In some embodiments, load 160 is not a distinct circuit element, but rather a parasitic capacitance at output node 101. In this case, the DC node V_CMNot an explicit circuit node.

In some embodiments, the load 160 is a resonant tank (resonant tank) including an inductor and a capacitor, the inductor and the capacitor are connected in parallel, and the inductor and the capacitor are configured to have resonance, thereby providing high impedance at five times the frequency. In this case, the DC node V_CMDefining the output clock S_OUTOf the common mode voltage. In some embodiments, the resonant frequency of the resonant tank is higher than the fundamental frequency of the five-phase clock and five times the fundamental frequency of the five-phase clock.

FIG. 3 is a graph according toThe functional block diagram of the five-multiplier 300 according to some embodiments of the present disclosure shows that the five-multiplier 300 of fig. 3 together with the five-multiplier 100 of fig. 1 can implement a differential five-multiplier. Referring to fig. 1 and 3 together, in some embodiments, consistent with the scope and spirit of the present disclosure, the differential five-fold frequency divider can be implemented by using two single-ended five-fold frequency dividers, which include a first single-ended five-fold frequency divider and a second single-ended five-fold frequency divider, wherein the first single-ended five-fold frequency divider and the second single-ended five-fold frequency divider have the same circuit, but the corresponding signals are complementary. The first single-ended five-multiplier can be implemented as the five-multiplier 100 of fig. 1, and the second single-ended five-multiplier can be implemented as the five-multiplier 300 of fig. 3. The five-multiplier 300 of fig. 3 is similar to the five-multiplier 100 of fig. 1, except that the first phase signal S is replaced₀Is a first phase signal S'₀Replacing the second phase signal S₁Is a second phase signal S'₁Replacing the third phase signal S₂Is a third phase signal S'₂Replacing the fourth phase signal S₃Is a fourth phase signal S'₃Replacing the fifth phase signal S₄Is a fifth phase signal S'₄Replacing the first tri-state charge pump 110 with a first tri-state charge pump 310, replacing the second tri-state charge pump 120 with a second tri-state charge pump 320, replacing the third tri-state charge pump 130 with a third tri-state charge pump 330, replacing the fourth tri-state charge pump 140 with a fourth tri-state charge pump 340, replacing the fifth tri-state charge pump 150 with a fifth tri-state charge pump 350, replacing the first current I₀Is a first current l'₀Replacing the second current I₁Is a second current l'₁Replacing the third current I₂Is a third current l'₂Replacing the fourth current I₃Is a fourth current I'₃Replacing the fifth current I₄Is a fifth current I'₄Replacement of the total current I_SIs total current I'_SReplacement output node 101 as complementary output node 301, replacement load 160 as complementary load 360, and replacement output clock S_OUTIs output clock S'_OUT. Here, a first phase signal S'₀Is a logically inverted first phase signal S₀And a second phase signal S'₁For the logically inverted second phase signal S₁And a third phase signal S'₂Is a logically inverted third phase signal S₂And a fourth phase signal S'₃Is a logically inverted fourth phase signal S₃And a fifth phase signal S'₄Is a logically inverted fifth phase signal S₄. Thus, the first current I'₀Is a first current I of opposite phase₀And a second current I'₁A second current I of opposite phase₁And a third current I'₂The third current I being in opposite phase₂And a fourth current I'₃A fourth current I of opposite phase₃And a fifth current I'₄A fifth current I of opposite phase₄Therefore, clock S 'is output'_OUTBeing an inverted output clock S_OUT。

In some embodiments, the five-phase clock input to the five-multiplier 100 is generated by a five-stage delay lock loop (five-stage delay lock loop). The ability of a five-stage delay-locked loop to generate a five-phase clock is understood by those skilled in the art and therefore will not be explained in detail herein.

In some embodiments, the five-phase clock input to the five-multiplier 100 is generated by a five-stage ring oscillator (five-stage ring oscillator). The ability of a five-stage ring oscillator to generate a five-phase clock is well understood by those skilled in the art and therefore will not be explained in detail herein. In some embodiments, the five-stage ring oscillator is a voltage controlled oscillator controlled in a closed loop manner in a phase locked loop. Phase locked loops are understood by those skilled in the art and therefore will not be explained in detail herein. If the interference signal is at five times the frequency, the vco is not subject to the "vco pulling" effect.

In some embodiments, the five-phase clock input to the pentamultiplier 100 is obtained from a four-phase clock that performs phase interpolation. Phase interpolation is a method for generating any phase clock. Phase interpolation can be performed using a weighted sum (weighted sum) that is generated based on weights that determine the target phase after interpolation. One embodiment of phase interpolation using a weighted sum can be found in U.S. patent No. 10,270,456.

In some embodiments, a complete periodic signal covers 360 degrees of phase. Thus, the five-phase clock includes five phases at 72 degree intervals. If the first phase signal S₀Is 0 degrees, the second phase signal S₁Is 72 degrees, a third phase signal S₂Is 144 degrees, and a fourth phase signal S₃Is 216 degrees, and a fifth phase signal S₄Is 288 degrees. The inverted periodic signal assumes a phase shift of 180 degrees, hence the first phase signal S'₀Is 180 degrees, a second phase signal S'₁Is 252 degrees, and a third phase signal S'₂Is 324 degrees, and a fourth phase signal S'₃Is 36 degrees, and a fifth phase signal S'₄Is 108 degrees. Thus, the first phase signal S₀And a fourth phase signal S'₃A second phase signal S₁And a fifth phase signal S'₄A third phase signal S₂And a first phase signal S'₀A fourth phase signal S₃And a second phase signal S'₁A fifth phase signal S₄And a third phase signal S'₂Ten-phase clocks at 36-degree intervals are formed. In other words, the five-phase clock and its logic inversion form a ten-phase clock. As described previously, the differential five-multiplier can be implemented by a combination of the single-ended five-multiplier (the five-multiplier 100) of fig. 1 and the single-ended five-multiplier (the five-multiplier 300) of fig. 3, wherein the five-multiplier 100 is based on the first phase signal S₀A second phase signal S₁A third phase signal S₂A fourth phase signal S₃And a fifth phase signal S₄Output clock S_OUT. The five-time frequency converter 300 is based on the first phase signal S'₀And a second phase signal S'₁And a third phase signal S'₂And a fourth phase signal S'₃And a fifth phase signal S'₄Output clock S'_OUT. Therefore, it can also be described that the differential five-multiplier outputs the output clock S according to the ten-phase clock_OUTAnd output clock S'_OUTWherein the ten-phase clock comprises a first phase signal S₀And a fourth phase signal S'₃A second phase signal S₁And a fifth phase signal S'₄A third phase signal S₂And a first phase signal S'₀A fourth phase signal S₃And a second phase signal S'₁A fifth phase signal S₄And a third phase signal S'₂。

Fig. 4 is a flow chart of a method of frequency quintupling as shown in accordance with some embodiments of the present disclosure. Referring to fig. 4, in some embodiments, a quintupling method includes the steps of: receiving a five-phase clock, wherein the five-phase clock comprises a first phase signal S₀A second phase signal S₁A third phase signal S₂A fourth phase signal S₃And a fifth phase signal S₄(step 410); according to the first phase signal S of the five-phase clock₀And a third phase signal S of a five-phase clock₂Outputting a first current I using a first tri-state charge pump 110₀To output node 101 (step 420); second phase signal S according to a five-phase clock₁And a fourth phase signal S of the five-phase clock₃Outputting a second current I using a second tri-state charge pump 120₁To output node 101 (step 430); third phase signal S according to five-phase clock₂And a fifth phase signal S of the five-phase clock₄Outputting a third current I using a third tri-state charge pump 130₂To output node 101 (step 440); according to the fourth phase signal S of the five-phase clock₃And a first phase signal S of a five-phase clock₀Outputting a fourth current I using a fourth tri-state charge pump 140₃To output node 101 (step 450); according to the fifth phase signal S of the five-phase clock₄And a second phase signal S of a five-phase clock₁Outputting a fifth current I using a fifth tri-state charge pump 150₃To output node 101 (step 460); and, a load 160 is used to couple the output node 101 (step 470).

Although the present disclosure has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined by the appended claims.