阅读说明：本技术 用于单路径可逆扫描链的双向扫描单元 (Bidirectional scan cell for single path reversible scan chain ) 是由 郑武东 黄宇 于 2020-02-11 设计创作，主要内容包括：电路包括多个扫描链。多个扫描链包括双向扫描单元。每个双向扫描单元包括两个串行输入-输出端口,该串行输入-输出端口基于控制信号用作串行数据输入端口或者串行数据输出端口。多个扫描链中的每一个扫描链被配置为基于控制信号在第一方向或第二方向执行移位操作。第一方向与第二方向相反。(The circuit includes a plurality of scan chains. The plurality of scan chains includes bidirectional scan cells. Each bidirectional scan cell includes two serial input-output ports that function as either a serial data input port or a serial data output port based on a control signal. Each of the plurality of scan chains is configured to perform a shift operation in a first direction or a second direction based on a control signal. The first direction is opposite to the second direction.)

1. A circuit, comprising:

a plurality of scan chains including bidirectional scan cells, each of the bidirectional scan cells including two serial input-output ports, the serial input-output ports serving as a serial data input port or a serial data output port based on a control signal, each of the plurality of scan chains configured to perform a shift operation in a first direction or a second direction based on the control signal, the first direction being opposite to the second direction.

2. The circuit of claim 1, wherein each of the bidirectional scanning units further comprises two tri-state buffers, outputs of the two tri-state buffers are coupled to the two serial input-output ports of each of the bidirectional scanning units, respectively, and the two tri-state buffers are controlled by the control signal and an inverse of the control signal, respectively.

3. The circuit of claim 2, wherein the two tri-state buffers are in a demultiplexer.

4. The circuit of claim 2, wherein each of the bidirectional scanning units further comprises a multiplexer, two inputs of the multiplexer being coupled to the outputs of the two tri-state buffers, respectively.

5. The circuit of claim 2, wherein each of the scan cells further comprises a conventional scan cell having a serial output coupled to the inputs of the two tri-state buffers.

6. The circuit of claim 1, wherein each of the scan cells further comprises a multiplexer and a demultiplexer, two outputs of the demultiplexer being coupled to the two serial input-output ports, respectively, and two inputs of the multiplexer being coupled to the two serial input-output ports, respectively.

7. The circuit of claim 1, wherein each of the scan cells further comprises a first pair of tri-state buffers and a second pair of tri-state buffers controlled by the control signal and an inverse of the control signal, respectively, an output of one of the first pair of tri-state buffers coupled to one of the two serial input-output ports, and an output of one of the second pair of tri-state buffers coupled to the other of the two serial input-output ports.

8. One or more computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising:

creating a plurality of scan chains in a circuit design for testing a chip manufactured according to the circuit design, the plurality of scan chains comprising:

a bidirectional scan cell, each of the bidirectional scan cells including two serial input-output ports, the serial input-output ports serving as a serial data input port or a serial data output port based on a control signal, each of the plurality of scan chains configured to perform a shift operation in a first direction or a second direction based on the control signal, the first direction being opposite to the second direction.

9. The one or more computer-readable media of claim 8, wherein each of the bidirectional scanning units further comprises two tri-state buffers, outputs of the two tri-state buffers are coupled to the two serial input-output ports of each of the bidirectional scanning units, respectively, and the two tri-state buffers are controlled by the control signal and an inverse of the control signal, respectively.

10. The one or more computer-readable media of claim 9, wherein the two tri-state buffers are in a demultiplexer.

11. The one or more computer-readable media of claim 9, wherein each of the scan cells further comprises a multiplexer, two inputs of the multiplexer being coupled to outputs of the two tri-state buffers, respectively.

12. The one or more computer-readable media of claim 9, wherein each of the scan cells further comprises a regular scan cell having a serial output coupled to the inputs of the two tri-state buffers.

13. The one or more computer-readable media of claim 8, wherein each of the scan cells further comprises a multiplexer and a demultiplexer, two outputs of the demultiplexer are coupled to the two serial input-output ports, respectively, and two inputs of the multiplexer are coupled to the two serial input-output ports, respectively.

14. The one or more computer-readable media of claim 8, wherein each of the scan cells further comprises a first pair of tri-state buffers and a second pair of tri-state buffers controlled by the control signal and an inverse of the control signal, respectively, an output of one tri-state buffer of the first pair of tri-state buffers coupled to one serial input-output port of the two serial input-output ports, an output of one tri-state buffer of the second pair of tri-state buffers coupled to the other serial input-output port of the two serial input-output ports.

15. A bi-directional scanning unit, comprising:

two serial input-output ports serving as a serial data input port or a serial data output port based on a control signal;

two tri-state buffers, the outputs of the two tri-state buffers being coupled to the two serial input-output ports, respectively, the two tri-state buffers being controlled by the control signal and the inverse of the control signal, respectively; and

a status element, an output of the status element coupled to the inputs of the two tri-state buffers.

16. A bi-directional scanning unit as recited in claim 15, wherein said two tri-state buffers are in a demultiplexer.

17. The bi-directional scanning unit of claim 15, further comprising:

a multiplexer having two inputs coupled to outputs of the two tri-state buffers, respectively.

18. The bi-directional scanning unit of claim 15, further comprising:

two additional tri-state buffers having inputs coupled to the two serial input-output ports, respectively, the two additional tri-state buffers being controlled by the control signal and an inverse of the control signal, respectively.

19. The bidirectional scan cell of claim 15, wherein the status element is a flip-flop.

Technical Field

The presently disclosed technology relates to circuit testing. Various embodiments of the disclosed technology may be particularly useful for scan chain diagnostics.

Background

Building circuits on silicon as test chips can provide insight into how new manufacturing processes work. Traditionally, semiconductor manufacturers have relied primarily on SRAM (static random access memory) test chips to promote, verify and monitor new semiconductor manufacturing processes. However, the transistor and circuit geometries used on SRAM test chips represent only a small fraction of the transistor and circuit geometries found in actual products. In recent years, a test chip with a logic circuit part (hereinafter referred to as a logic test chip) has been frequently used in addition to or instead of the SRAM test chip. Although more closely representing chips with real circuit designs, logic test chips are not as easy to test or diagnose as SRAM test chips.

To check whether the logic test chip is manufactured as designed and to locate potential defects, scan testing is typically employed. In this technique, a series of known values (test stimuli or test patterns) are shifted into (or loaded into) a state element called a scan cell by their sequential input. These scan cells are interconnected into a scan chain for scan testing. The shifting-in is accomplished by placing the integrated circuit in a particular mode, called the shift mode, and then applying a series of clock pulses called "shift pulses" or "shift clock pulses". Each shift clock pulse pushes a test stimulus bit into a scan cell in each scan chain. This continues until all scan cells in the scan chain have filled the test mode bits. One or more clock pulses, referred to as "capture pulses" or "capture clock pulses", are then applied to the circuit as they would in normal operation. This is called the capture mode. After the test mode bits are injected into the circuit, the test results (test responses) are "captured" and stored in the scan cells. The circuit then returns to the shift mode and with each additional clock pulse, the test response bit is pushed out or shifted out as each bit of the new test mode is pushed in or shifted in. The shifted out test response is then compared to the expected result to determine and locate any errors. The shift mode and the capture mode are collectively referred to as a test mode.

The scan chains and their associated clock circuits themselves are a major source of circuit failure. Defects found on scan chains are reported to account for approximately 30% to 50% of all failed chips. Therefore, the scan chain needs to be tested and diagnosed first. As discussed in detail below, a failed scan chain may be detected by a relatively simple method. However, locating defective scan cells is challenging. Physical fault analysis instruments, in combination with testers, are sometimes used to search for defective responses along the scan chain. These hardware-based approaches typically rely on specially designed scan chains and scan cells. While effective in isolating scan chain defects, the requirement for additional hardware may be unacceptable in many practical products. Furthermore, it is difficult to apply these methods to chips with embedded compression circuits without using the bypass mode.

Software-based techniques use algorithmic diagnostic routines to identify the faulty scanning units. Which may use conventional scan chains with or without embedded compression to run chain diagnostics. Current software-based chain diagnostic techniques can be further divided into two categories: model-based algorithms and data-driven algorithms. In the model-based chain diagnostic process, fault models and mode simulations are used. In data-driven chain diagnostic processes, signal analysis, filtering and edge detection are applied. Each algorithm type has its own advantages and disadvantages. The two can also be combined to improve diagnostic resolution and diagnostic accuracy. While conventional approaches may yield satisfactory results for defects that behave exactly the same as modeled faults (e.g., a fixed 0 fault at the output of a scan cell), defects in scan chains typically exhibit unmodeled fault behavior (e.g., intermittent fault behavior). For unmodeled faults, both diagnostic accuracy and diagnostic resolution may drop significantly.

Song, a new scan architecture for improving scan chain diagnosis and delay fault coverage, was first proposed in the 9 th IEEE North Atlantic Test Workshop (NATW, North Atlantic Test Workshop) conference proceedings, 2000, pp.14-18. Com, 2007, 11.21, discusses a similar technique, a paper entitled "bidirectional scan chain for digital circuit testing". Us 9,222,978 and us 10,156,607 also disclose scan testing in both forward and reverse directions through reversible scan chains. All of the techniques in these publications have one common feature: the two opposite scan paths for the scan chain are partially separated outside the scan cells on the scan chain.

Fig. 1 shows an example of two block diagrams 110 and 120 of a reversible scan chain in accordance with the disclosed techniques. The scan chain includes three scan cells 130, 140, and 150 and four multiplexers 135, 145, 155, and 165. The control signal provided from port 160 serves as a selection signal for the four multiplexers 135-165. In block diagram 110, as shown by the solid line with arrows, the control signals enable a scan path that follows the order of multiplexer 135-scan cell 130-multiplexer 145-scan cell 140-multiplexer 155-scan cell 150-multiplexer 165. In block diagram 120, as shown by the solid lines with arrows, the control signals invert and enable the different scan path multiplexers 155-scan cell 150-multiplexer 145-scan cell 140-multiplexer 135-scan cell 130-multiplexer 165. Two paths do share a common segment, e.g., one segment between multiplexer 135 and scan cell 130, but many other segments are unique to either the forward path or the reverse path. The conventional architecture, while facilitating chain diagnostics, can cause too much silicon area overhead (silicon area overhead) and wire plugging.

Disclosure of Invention

Various aspects of the disclosed technology relate to chain testing and diagnostics in a reversible scan architecture. In one aspect, there is a circuit comprising: a circuit comprising a plurality of scan chains including bidirectional scan cells, each of the bidirectional scan cells comprising two serial input-output ports, the serial input-output ports serving as a serial data input port or a serial data output port based on a control signal, each of the plurality of scan chains being configured to perform a shift operation in a first direction or a second direction based on the control signal, the first direction being opposite to the second direction.

Each of the bidirectional scanning units may further include two tri-state buffers whose outputs are respectively coupled to the two serial input-output ports of each of the bidirectional scanning units, and which are respectively controlled by the control signal and an inversion of the control signal. The two tri-state buffers are in a demultiplexer. Each of the scan cells may further include a multiplexer, two inputs of the multiplexer being coupled to outputs of the two tri-state buffers, respectively. Each of the scan cells may further include a conventional scan cell having a serial output coupled to the inputs of the two tri-state buffers.

Alternatively, each of the scan cells may further include a multiplexer and a demultiplexer, two outputs of the demultiplexer being coupled to the two serial input-output ports, respectively, and two inputs of the multiplexer being coupled to the two serial input-output ports, respectively.

Alternatively, each of the scan cells further comprises a first pair of tri-state buffers and a second pair of tri-state buffers controlled by the control signal and an inverse of the control signal, respectively, an output of one of the first pair of tri-state buffers being coupled to one of the two serial input-output ports, and an output of one of the second pair of tri-state buffers being coupled to the other of the two serial input-output ports.

In another aspect, there are one or more computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising: creating a plurality of scan chains in a circuit design to test a chip manufactured according to the circuit design, the plurality of scan chains comprising: a bidirectional scan cell, each of the bidirectional scan cells including two serial input-output ports, the serial input-output ports serving as a serial data input port or a serial data output port based on a control signal, each of the plurality of scan chains configured to perform a shift operation in a first direction or a second direction based on the control signal, the first direction being opposite to the second direction.

In yet another aspect, there is a bi-directional scanning unit comprising: two serial input-output ports serving as a serial data input port or a serial data output port based on a control signal; two tri-state buffers, the outputs of the two tri-state buffers being coupled to the two serial input-output ports, respectively, the two tri-state buffers being controlled by the control signal and the inverse of the control signal, respectively; and a status element, an output of the status element coupled to the inputs of the two tri-state buffers.

The two tri-state buffers may be in a demultiplexer. The status element may be a flip-flop.

The bidirectional scanning unit may further include a multiplexer, two inputs of the multiplexer being coupled to outputs of the two tri-state buffers, respectively.

The bidirectional scanning unit may further comprise two additional tri-state buffers having inputs coupled to the two serial input-output ports, respectively, the two additional tri-state buffers being controlled by the control signal and an inverse of the control signal, respectively.

Certain inventive aspects are set forth in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features from the independent claims and features from other dependent claims as appropriate and not merely as explicitly set out in the claims.

Certain objects and advantages of the various inventive aspects have been described above. Of course, it is to be understood that not all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed techniques may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

Drawings

Fig. 1 shows two examples of block diagrams of a reversible scan chain comprising conventional scan cells showing two different scan directions, respectively.

FIG. 2A illustrates an example of a reversible scan chain including bidirectional scan cells in accordance with various embodiments of the disclosed technology.

FIG. 2B illustrates an example of a block diagram of a bi-directional scanning unit in accordance with various embodiments of the disclosed technology.

FIG. 3 illustrates an example of two block diagrams of reversible scan chains for two different scan directions, respectively, in accordance with various embodiments of the disclosed technology.

FIG. 4 illustrates another example of two block diagrams of reversible scan chains for two different scan directions, respectively, in accordance with various embodiments of the disclosed technology.

FIG. 5A illustrates yet another example of two block diagrams of reversible scan chains, one for each of two different scan directions, in accordance with various embodiments of the disclosed technology.

FIG. 5B illustrates an example of a block diagram of a demultiplexer that may be used in the bi-directional scan cell in FIG. 5A in accordance with various embodiments of the disclosed technology.

FIG. 6A shows an example of a pipeline unit inserted into a bidirectional scan cell for one scan direction.

FIG. 6B shows an example of a pipeline unit inserted into a bi-directional scan cell for two scan directions.

FIG. 7 illustrates a programmable computer system that can employ various embodiments of the disclosed technology.

Detailed Description

Aspects of the disclosed technology relate to chain testing and diagnostics in a reversible scan architecture. In the following description, for purposes of explanation, numerous details are set forth. However, one of ordinary skill in the art will recognize that the disclosed techniques can be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the disclosed technology.

Some of the techniques described herein may be implemented by software instructions stored on a computer-readable medium, executed on a computer, or a combination of both. For example, some of the disclosed techniques may be implemented as part of an Electronic Design Automation (EDA) tool. The method may be performed on a single computer or networked computers.

Although the operations of the disclosed methods are described in a particular order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example, operations described in order may in some cases be rearranged or performed concurrently. In addition, for the sake of simplicity, the disclosed flow charts and block diagrams generally do not show the various ways in which a particular method may be used in conjunction with other methods.

Detailed description of the methods or devices the terms "performing" or "performing" are sometimes used to describe disclosed method or device functions/structures. The term is a high level description. The actual operation or function/structure corresponding to these terms will vary depending on the particular implementation and is readily discernible by one of ordinary skill in the art.

Furthermore, as used herein, the term "design" is intended to encompass data describing an entire integrated circuit device. However, the data is also intended to encompass smaller sets of data describing one or more components of the overall device (e.g., a portion of an integrated circuit device).

As used in this application, the singular forms "a", "an" and "the" include the plural forms unless the context clearly dictates otherwise. Furthermore, the term "comprising" encompasses "including". Furthermore, the term "coupled" includes mechanical, electrical, magnetic, optical, and other practical ways of coupling or linking items together, and does not exclude the presence of intermediate elements between the coupled items. Further, as used herein, the term "and/or" means any one or combination of more than one of the phrase.

The reduction in feature size increases the likelihood that manufacturing defects in the integrated circuit will result in a faulty chip. Very small defects can result in faulty transistors or interconnect lines. Even a single failed transistor or wire may cause the entire chip to operate improperly. However, manufacturing defects are unavoidable whether the manufacturing process is in the prototype stage or the high volume manufacturing stage. Therefore, it is necessary to test the chip during the manufacturing process. It is also necessary to diagnose faulty chips to improve and maintain manufacturing yield.

Testing typically involves applying a set of test stimuli (test patterns) to the circuit under test and then analyzing the response generated by the circuit under test. Functional testing attempts to verify that the circuit under test is operating according to its functional specifications, while structural testing attempts to determine whether the circuit under test is correctly assembled from some of the low-level building blocks specified in the structural netlist, and whether these low-level building blocks and their wire connections are manufactured without defects. For structural testing, it is assumed that the circuit should function correctly if functional verification has indicated the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements. Structural testing has been widely adopted, at least in part, because it enables test (test mode) generation to focus on testing a limited number of relatively simple circuit elements without having to deal with the exponentially growing variety of functional states and state transitions.

To make it easier to develop and apply test patterns, certain testability features are added to the circuit design, which is called design for test (DFT) or design for testability. Scan testing is the most common DFT method. In a basic scan test scheme, all or most of the internal sequential state elements (latches, flip-flops, etc.) in a circuit design are controllable and observable through a serial interface. These functional state elements are often replaced by dual-purpose state elements called scan cells. The scan cells are connected together to form a scan chain-a serial shift register for shifting in test patterns and shifting out test responses. The scan cells may be run as originally intended for functional purposes (function/task mode) and may be scanned as cells in a scan chain (scan mode). A widely used type of scan cell includes edge triggered flip-flops with a bidirectional multiplexer for data input. The bi-directional multiplexer is typically controlled by a single control signal, called scanenable, which selects the input signal for the scan cell from either the scansignal input port or the system signal input port. The scan signal input port is typically connected to the output of another scan cell, while the system signal input port is connected to the functional logic. The scanning unit can be used as a control point and an observation point. The control point may be used to set certain logic values at some locations of the circuit under test, to fire (activate) faults and to propagate error values to the observation point. Scan testing enables test equipment to access the deeply embedded gates through the main input/outputs and/or some physical test points and eliminates the need for complex state transition sequences when attempting to control or observe what happens in some internal circuit elements.

Test patterns for scan testing are typically generated by an Automated Test Pattern Generation (ATPG) process. ATPG typically focuses on a set of faults derived from a gate-level fault model. A defect is an error caused in the device during the manufacturing process. The fault model is a description of how a defect changes the design behavior. That is, the defect is a fault or physical flaw that may lead to a failure. For a given target fault, ATPG consists of two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault site (site) that is opposite to the signal value generated by the fault. Fault propagation propagates the effect of a fault forward by sensitizing the path from the site of the fault to the scan cell or main output. If the test response value captured by the scan cell or the primary output is different from the expected value, then a fault at the site is said to be detected by the test mode. The goal of ATPG is to discover test patterns that, when applied to a circuit, enable a tester to distinguish between correct circuit behavior and faulty circuit behavior caused by one or more particular faults. The effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of vectors generated (test pattern count), which should be proportional to the test application time. Here, the fault coverage is defined as a ratio of the number of detected faults to the total number of faults.

The most popular fault model used in practice is the single fixed fault model. In this model, it is assumed that one of the signal lines in the circuit is fixed at a fixed logic value, regardless of the input provided to the circuit. The fixed fault model is a logical fault model because no delay information is associated with the fault definition. Delay faults cause errors in the functioning of the circuit based on its timing. Delay faults are caused by finite rise and fall periods of the signals in the gates and propagation delays of the interconnects between the gates. The transition fault is used for its simplicity to model point defects that affect the delay at the gate input or at the gate output. Under scan-based testing, a transition fault is associated with an additional delay that is large enough to cause the delay of any path through the fault site to exceed a time period. The cell internal fault model may be derived using transistor level circuit simulation (analog simulation). This method can accurately locate the defect position in the cell for various cell internal defects.

During circuit design and manufacturing, manufacturing tests screen out chips (dies) that contain defects. However, the testing itself does not identify the cause of unacceptably low or fluctuating yields that may be observed. Physical Failure Analysis (PFA) can inspect a failed chip to locate one or more defect sites and discover root causes. This process typically involves etching away certain layers and then imaging the silicon surface by scanning electron microscopy or focused ion beam systems. This PFA process is laborious and time consuming. To facilitate the PFA process, diagnostics (also referred to as scan diagnostics) are typically employed to narrow one or more possible defect sites based on analyzing a failure log (failure file, fault file, or fault report). The failure log typically contains information about when (e.g., tester cycles), where (e.g., at which tester channel), how (e.g., at what logic value) the test failed, and which test model generated the expected test response. Layout information for the circuit design may also be used to further reduce the number of suspected defects.

Diagnostics include logic diagnostics (sometimes referred to as scan diagnostics or diagnostics) and chain diagnostics. Logic diagnostics may use a fault dictionary or direct examination of syndromes (e.g., effects) of faulty chips to determine likely defect locations (suspected defects). The latter approach may include structure pruning (backtracking), fault injection and evaluation (fault simulation for both failed and pass test modes). The quality of the diagnosis can be measured by the diagnostic resolution (the number of actual defects versus the number of suspected defects). The diagnostic resolution is related not only to the algorithm used for the diagnosis but also to the test pattern used for the manufacturing test (manufacturing test pattern). To improve diagnostic quality, a diagnostic test pattern generation process may be used. The process generates a test pattern that may improve the set of suspected defects.

Chain diagnostics determine scan cells that may be defective. During chain diagnostics, two types of test patterns may be used. The first type is called chain mode. The chain mode is a mode used in a process including shift-in and shift-out without requiring pulse clock capture. The other type is commonly referred to as a scan mode. The scan patterns are patterns used in a process that includes a shift-in, one or more capture clock cycles, and a shift-out, and the scan patterns include patterns generated by ATPG for testing system logic, chain-specific diagnostic patterns generated only for diagnostic purposes of the scan chain, and some functional-specific patterns. The chain pattern may be used to test the integrity of the scan chain and/or determine a failure model associated with a failed scan chain, while the scan pattern may be used to inject certain values into some scan cells for locating defective scan cells.

Test applications in chip manufacturing testing are typically performed by Automated Test Equipment (ATE), a type of tester. Scan-based testing consumes a significant amount of memory and test time on ATE. The amount of data increases with the number of logic gates on the chip and is equally applicable to the number of scan cells. However, practical considerations and ATE specifications often limit both the number of available pins for scan in/scan out and the maximum scan frequency. It is highly desirable to reduce the amount of test data that needs to be loaded into the ATE and ultimately into the circuit-under-test. Fortunately, the test pattern is compressible, primarily because only 1% to 5% of the test pattern bits are typically referred to as bits (care bits), while the rest are non-designated bits (don't care bits). The unspecified bits may take any value without affecting fault coverage. Test compression may also take advantage of the fact that test multi-dimensional datasets (test cube) tend to be highly correlated. Testing a multidimensional dataset is a deterministic test pattern in which the don't care bits are not filled by ATPG. There is a dependency because faults are structurally related in the circuit.

Various test compression techniques have been developed. Typically, additional on-chip hardware is inserted before and after the scan chain. Hardware added before the scan chain (decompressor) is configured to decompress test stimuli from the ATE, while hardware added after the scan chain (compressor) is configured to compress test responses captured by the scan chain. The decompressor expands data from the n test channels to fill more than n scan chains. The increase in the number of scan chains shortens each scan chain and therefore reduces the number of clock cycles required to shift into each test pattern. Thus, test compression may not only reduce the amount of data stored on the tester, but may also reduce the test time for a given test data bandwidth.

All of the above processes, design insertion for testing, test pattern generation, and logic diagnostics are typically performed by various electronic design automation tools, such as those of the Tessent series software tools available from Mentor Graphics Corporation, Wilsonville, Oregon.

Fig. 2A illustrates an example of a reversible scan chain 200 in accordance with various embodiments of the disclosed technology. Reversible scan chain 200 includes bidirectional scan cells 230, 240, …, and 250. Each of these bidirectional scan cells 230, 240, …, and 250 includes two serial input-output ports that may be configured to act as either a serial data input or a serial data output based on the control signal 210. Thus, the reversible scan chain 200 can perform a shift operation in a left-to-right direction or in a right-to-left direction through the same scan path (rather than through a different path used by the scan chain shown in fig. 1) based on a control signal. Although bidirectional scan cells 230, 240, …, and 250 may include more components than conventional scan cells, additional wiring between multiplexers 135, 145, 155 and the scan cells shown in FIG. 1 is not required. Moreover, the bi-directional scanning unit can be designed and optimized to be not significantly larger than conventional scanning units. In general, the increase in silicon area overhead (as compared to conventional unidirectional scan chains) caused by a single-path reversible scan chain implemented in accordance with various embodiments of the disclosed technology may be less than the increase in silicon area overhead caused by conventional dual-path reversible scan chains.

Each of the bidirectional scan cells 230, 240, …, and 250 may further include two tri-state buffers. A tri-state buffer is a device whose output port has three states: high impedance state, logic 1 state, logic 0 state. The output port exhibiting the high impedance state effectively removes the output of the tri-state buffer from the circuit. Whether the output port assumes a logic 1 state or a logic 0 state depends on the signal at the input port. A control signal at the control port of the tri-state buffer determines whether the output port exhibits a high impedance state. Fig. 2B illustrates an example of a block diagram of such a bi-directional scanning unit 220, in accordance with various embodiments of the disclosed technology. The scan cell 220 includes two tri-state buffers 260 and 270. Tri-state buffer 260 is controlled by control signal 221 and tri-state buffer 270 is controlled by the inverse of control signal 221. The outputs of the two tri-state buffers 260 and 270 are coupled to the serial input-output ports 223 and 222, respectively, of the bidirectional scan cell 220. When control signal 210 is asserted, tri-state buffer 270 assumes a high impedance state, allowing serial input-output port 222 to serve as the serial input port of bi-directional scan cell 220; when the control signal 210 is inactive, the tri-state buffer 260 assumes a high impedance state, allowing the serial input-output port 223 to serve as the serial input port of the bi-directional scanning unit 220. Each of the bidirectional scanning units 230, 240, …, and 250 may further include a conventional scanning unit. The serial output of a conventional scan cell is coupled to the inputs of two tri-state buffers.

FIG. 3 illustrates an example of two block diagrams 300 and 305 of a reversible scan chain for two different scan directions, respectively, in accordance with various embodiments of the disclosed technology. The reversible scan chain includes three bidirectional scan cells 310, 320, 330. Each bidirectional scan cell 310, 320, 330 includes a scan element (311, 321, 331), a pair of tri-state buffers (312/313, 322/323, 332/333) controlled by a control signal 340, and a pair of tri-state buffers (314/315, 324/325, 334/335) controlled by an inverse of the control signal 340. Here, the scan element includes a status element such as a flip-flop.

In block diagram 300, control signal 340 is asserted. The tri-state buffer pair 312/313, 322/323, 332/333 is in a state that allows its output to follow its input, while the tri-state buffer pair 314/315, 324/325, 334/335 is in a high impedance state that blocks its output. Thus, the signal path in the shift operation follows the order of tristate buffer 312-scan element 311-tristate buffer 313-tristate buffer 322-scan element 321-tristate buffer 323-tristate buffer 332-scan element 331-tristate buffer 333. Thus, the direction of the shift operation is from left to right when control signal 340 is active.

In block 305, control signal 340 is deactivated. The tri-state buffer pair 314/315, 324/325, 334/335 is in a state that allows its output to follow its input, while the tri-state buffer pair 312/313, 322/323, 332/333 is in a high impedance state that blocks its output. Thus, the signal path in the shift operation follows the order of tri-state buffer 333-scan element 331-tri-state buffer 332-tri-state buffer 323-scan element 321-tri-state buffer 322-tri-state buffer 313-scan element 331-tri-state buffer 312. Thus, when the control signal 340 is inactive, the direction of the shift operation is from right to left.

FIG. 4 illustrates another example of two block diagrams 400 and 405 of reversible scan chains for two different scan directions, respectively, in accordance with various embodiments of the disclosed technology. The reversible scan chain includes three bidirectional scan cells 410, 420, 430. Each bidirectional scan cell 410, 420, 430 includes a scan element (411, 421, 431), a tri-state buffer (413, 423, 433) controlled by a control signal 440, a tri-state buffer (414, 424, 434) controlled by an inversion of the control signal 440, and a multiplexer (412, 422, 432) controlled by the control signal 440. Here, the scan element includes a status element such as a flip-flop.

In block diagram 400, control signal 440 is active. The tri-state buffers 413, 423, 433 are in a state allowing their outputs to follow their inputs, while the tri-state buffers 414, 424, 434 are in a high impedance state blocking their outputs. The multiplexers 412, 422, 432 select their first inputs (the top inputs in the figure) for output. Thus, the signal path in the shift operation follows the order of multiplexer 412-scan element 411-tri-state buffer 413-multiplexer 422-scan element 421-tri-state buffer 423-multiplexer 432-scan element 431-tri-state buffer 433. Thus, when control signal 440 is active, the direction of the shift operation is from left to right.

In block 405, control signal 440 is deactivated. The tri-state buffers 414, 424, 434 are in a state that allows their outputs to follow their inputs, while the tri-state buffers 413, 423, 433 are in a high impedance state that blocks their outputs. The multiplexers 412, 422, 432 select the second input (the input at the bottom in the figure) for output. Thus, the signal path in the shift operation follows the order of multiplexer 432-scan element 431-tristate buffer 434-multiplexer 422-scan element 421-tristate buffer 424-multiplexer 412-scan element 411-tristate buffer 414. Thus, when the control signal 440 is inactive, the direction of the shift operation is from right to left.

FIG. 5A illustrates yet another example of two block diagrams 500 and 505 of reversible scan chains, one for each of two different scan directions, in accordance with various embodiments of the disclosed technology. The reversible scan chain includes three bidirectional scan cells 510, 520, 530. Each bidirectional scanning unit 510, 520, 530 includes a scanning element (511, 521, 531), a multiplexer (512, 522, 532), and a demultiplexer (513, 523, 533). The multiplexers (512, 522, 532) and demultiplexers (513, 523, 533) are controlled by control signals 540. Here, the scan element includes a status element such as a flip-flop.

In block diagram 500, control signal 540 is asserted. Multiplexers 512, 522, 532 select their first inputs (the top most inputs in the figure) for output, and demultiplexers 513, 523, 533 output their input signals on their first outputs (the top most outputs in the figure). Thus, the signal path in the shift operation follows the order of multiplexer 512-scan element 511-demultiplexer 513-multiplexer 522-scan element 521-demultiplexer 523-multiplexer 532-scan element 531-demultiplexer 533. Thus, when control signal 540 is active, the direction of the shift operation is from left to right.

In block 505, control signal 540 is deactivated. Multiplexers 512, 522, 532 select their second inputs (the bottom inputs in the figure) for output, and demultiplexers 513, 523, 533 output their input signals on their second outputs (the bottom outputs in the figure). Thus, the signal path in the shift operation follows the order of multiplexer 532-scan element 531-demultiplexer 533-multiplexer 522-scan element 521-demultiplexer 523-multiplexer 512-scan element 511-demultiplexer 513. Thus, when control signal 540 is inactive, the direction of the shift operation is from left to right.

Fig. 5B illustrates an example of a block diagram of a demultiplexer 550 that may be used in the bi-directional scan cells 510, 520, 530 in fig. 5A, in accordance with various embodiments of the disclosed technology. The demultiplexer 550 includes two tri-state buffers 551, 552 and an inverter 553. The signal input 555 of the demultiplexer 550 is coupled to the inputs of the tri-state buffers 551, 552; a first signal output 557 of the demultiplexer 550 is coupled to the output of the tri-state buffer 551; and a second signal output 556 of the demultiplexer 550 is coupled to the output of the tri-state buffer 552. The control signal provided through the select port 554 of the demultiplexer directly controls the tri-state buffer 551 and indirectly controls the tri-state buffer 552 through the inverter 553. When the control signal is asserted, tri-state buffer 551 is in a state that allows first input 557 to follow input 555 while tri-state buffer 552 is in a high impedance state that blocks second output 556. When the control signal is inactive, tri-state buffer 552 is in a state that allows second input 556 to follow input 555, while tri-state buffer 551 is in a high impedance state that blocks first output 557.

The parallel data input and parallel data output of each bidirectional scanning unit shown in fig. 3, 4, 5A are not shown for ease of illustration. A multiplexer may be placed immediately before the data input of the flip-flop in the bidirectional scan cell for selecting either the serial data input or the parallel data input, and the output of the flip-flop may be directly coupled to the functional circuit. Those of ordinary skill in the art will appreciate that the scanning elements in the bi-directional scanning units shown in fig. 3, 4, 5A may be conventional uni-directional scanning units. One of ordinary skill in the art will also appreciate that although only three bidirectional scan cells are shown in each of fig. 3, 4, 5A, the disclosed techniques may be applied to scan chains containing various numbers of bidirectional scan cells.

The pipeline unit may be inserted into the bidirectional scanning unit for one scanning direction or two scanning directions. FIG. 6A shows an example of a pipeline unit 614 inserted into a bi-directional scan cell 600 for one scan direction. Bidirectional scanning unit 600 includes multiplexer 612, flip-flop 611, and demultiplexer 613. A pipeline unit 614 is interposed between the second output of the demultiplexer 613 and the second input of the multiplexer 612. Thus, the pipeline unit 614 acts on the right to left scan direction. FIG. 6B shows an example of a pipeline unit 615 inserted into the bi-directional scan cell 600 for both scan directions. Specifically, pipeline unit 615 is inserted between the output of multiplexer 612 and the input of flip-flop 611. Thus, the pipeline unit 615 works for both the right-to-left scan direction and the left-to-right scan direction.

Various examples of the disclosed technology can be implemented by a computing device (e.g., a programmable computer) executing software instructions. For example, a computing device may be caused to perform a method for creating a scan chain including bidirectional scan cells in a circuit design for testing a chip manufactured according to the circuit design. Thus, fig. 7 shows an illustrative example of a computing device 701. As seen in the figure, the computing device 701 includes a computing unit 703 having a processing unit 705 and a system memory 707. The processing unit 705 may be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. The system memory 707 may include both Read Only Memory (ROM)709 and Random Access Memory (RAM) 711. As will be appreciated by one of ordinary skill in the art, both Read Only Memory (ROM)709 and Random Access Memory (RAM)711 may store software instructions that are executed by processing unit 705.

The processing unit 705 and the system memory 707 are connected directly or indirectly to one or more peripheral devices through a bus 713 or an alternative communication structure. For example, the processing unit 705 or the system memory 707 can be directly or indirectly connected to one or more additional memory storage devices, such as a "hard" magnetic disk drive 715, a removable magnetic disk drive 717, an optical disk drive 719, or a flash memory card 721. The processing unit 705 and the system memory 707 can be directly or indirectly connected to one or more input devices 723 and one or more output devices 725. Input devices 723 may include, for example, a keyboard, a pointing device (e.g., a mouse, touch pad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. Output devices 725 may include, for example, a monitor display, a printer, and speakers. In various examples of computer 701, one or more of peripheral devices 715 and 725 may be housed internally with computing unit 703. Alternatively, one or more of the peripheral devices 715 and 725 may be external to the housing of the computing unit 703 and connected to the bus 713 by, for example, a Universal Serial Bus (USB) connection.

In some embodiments, the computing unit 703 may be directly or indirectly connected to the network interface 727 for communicating with other devices making up the network. The network interface 727 converts the data and control signals from the computing unit 703 into network messages according to one or more communication protocols, such as the Transmission Control Protocol (TCP) and the Internet Protocol (IP). Further, interface 727 may employ any suitable connection agent (or combination of agents) to connect to a network, including for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art and will not be discussed in further detail herein.

It should be understood that computing device 701 is shown by way of example only and is not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of computer 701 shown in FIG. 7, including only a subset of the components shown in FIG. 7, or alternate combinations of these components, including components not shown in FIG. 7. For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, multiple single-processor computers and/or multi-processor computers disposed in a network, or some combination of the two.

Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments to which the principles of the disclosed technology may be applied, it should be recognized that the illustrated embodiments are only preferred examples of the technology and should not be taken as limiting the scope of the disclosed technology. Rather, the scope of the disclosed technology is defined by the following claims and their equivalents. We therefore claim as our disclosed technology all that comes within the scope and spirit of these claims.