Three-dimensional memory device, method of manufacturing the same, and three-dimensional memory

文档序号：552634 发布日期：2021-05-14 浏览：17次中文

阅读说明：本技术 三维存储器件及其制造方法、以及三维存储器 (Three-dimensional memory device, method of manufacturing the same, and three-dimensional memory ) 是由胡思平于 2021-03-27 设计创作，主要内容包括：本发明提供一种三维存储器件及其制造方法、以及三维存储器。三维存储器件包括第一存储单元和依次堆叠于第一存储单元上的至少一个第二存储单元。每一存储单元包括第一组触点及堆叠设置且相互电连接的存储阵列器件和CMOS器件,第一组触点设于存储阵列器件背离CMOS器件的一侧并与CMOS器件电连接。第二存储单元还包括设于CMOS器件背离存储阵列器件的一侧并与CMOS器件电连接的第二组触点。第一存储单元的存储阵列器件与相邻的第二存储单元的CMOS器件接合,且第一存储单元的第一组触点与相邻的第二存储单元的第二组触点对应电连接。通过将至少两个存储单元堆叠设置,使得所述三维存储器件存储密度高,而且能提高空间利用率。(The invention provides a three-dimensional memory device, a manufacturing method thereof and a three-dimensional memory. The three-dimensional memory device includes a first memory cell and at least one second memory cell sequentially stacked on the first memory cell. Each storage unit comprises a first group of contacts, a storage array device and a CMOS device which are arranged in a stacked mode and electrically connected with each other, and the first group of contacts are arranged on one side, away from the CMOS device, of the storage array device and electrically connected with the CMOS device. The second memory cell also includes a second set of contacts disposed on a side of the CMOS device facing away from the memory array device and electrically connected to the CMOS device. The memory array device of a first memory cell is bonded to the CMOS device of an adjacent second memory cell, and the first set of contacts of the first memory cell is electrically connected to the second set of contacts of the adjacent second memory cell. By stacking at least two memory cells, the three-dimensional memory device has high storage density and improved space utilization.)

1. A three-dimensional memory device comprising at least two memory cells stacked in sequence, the at least two memory cells including a first memory cell and at least one second memory cell stacked on the first memory cell, each memory cell comprising:

the CMOS device comprises a storage array device and a CMOS device, wherein the storage array device and the CMOS device are stacked and electrically connected with each other; and

the first group of contacts are arranged on one side, away from the CMOS device, of the storage array device and are electrically connected with the CMOS device;

the second storage unit further comprises a second group of contacts, and the second group of contacts are arranged on one side, away from the storage array device of the second storage unit, of the CMOS device of the second storage unit and are electrically connected with the CMOS device of the second storage unit;

the memory array device of the first memory cell is bonded to the CMOS device of the adjacent second memory cell, and the first set of contacts of the first memory cell is electrically connected to the second set of contacts of the adjacent second memory cell;

when the number of the second storage units is one, the second storage units are outer layer second storage units stacked on the first storage units, and a first group of contacts of the outer layer second storage units are used for connecting external devices;

when the second storage units are multiple, the multiple second storage units are sequentially stacked on the first storage unit, in two adjacent second storage units, a first group of contacts close to the second storage unit of the first storage unit are correspondingly electrically connected with a second group of contacts far away from the second storage unit of the first storage unit, the second storage unit which is far away from the first storage unit along the stacking direction is defined as an outer layer second storage unit, and the first group of contacts of the outer layer second storage unit are used for connecting an external device.

2. The three-dimensional memory device of claim 1, further comprising an isolation layer and an array pad embedded in the isolation layer; the isolation layer covers one side that outer second memory cell deviates from first memory cell reaches the first group contact of outer second memory cell, the array pad with the corresponding electric connection of the first group contact of outer second memory cell, the array pad is used for connecting the external device.

3. The three-dimensional memory device of claim 2, further comprising a protective layer covering a side of the isolation layer facing away from the outer second memory cell;

the protective layer is provided with an opening at a position corresponding to the array bonding pad, and the array bonding pad is exposed through the opening and is used for connecting the external device.

4. The three-dimensional memory device of any one of claims 1 to 3, wherein the memory array device comprises an array substrate, the first set of contacts of each memory cell being provided on a side of the array substrate of the corresponding memory array device facing away from the corresponding CMOS device;

the CMOS device comprises a CMOS substrate, and the second group of contacts of the second storage unit are arranged on one side, away from the storage array device of the second storage unit, of the CMOS substrate of the second storage unit.

5. The three-dimensional memory device of claim 4, wherein each memory cell further comprises an interconnect via disposed in the memory array device and the CMOS device of the memory cell;

the interconnection channel is electrically connected with the first group of contacts of the storage unit and the CMOS device respectively, so that the first group of contacts are electrically connected with the CMOS device through the interconnection channel.

6. The three-dimensional memory device of claim 5, wherein the second memory cell further comprises a conductive via that extends through the CMOS substrate of the second memory cell and is electrically connected to the second set of contacts of the second memory cell and the CMOS device, respectively, such that the second set of contacts is electrically connected to the CMOS device of the second memory cell via the conductive via.

7. The three-dimensional memory device according to any one of claims 1 to 3, wherein the memory array device of the first memory cell and the memory array device of the second memory cell each include a predetermined number of memory layers, the predetermined number of memory layers being an integer greater than 0 and less than 500.

8. A method of fabricating a three-dimensional memory device, comprising:

providing a first storage unit and a second storage unit, wherein the first storage unit and the second storage unit respectively comprise a first group of contacts, a storage array device and a CMOS device which are arranged in a stacking mode and electrically connected with each other, and the first group of contacts are arranged on one side, away from the CMOS device, of the storage array device and are electrically connected with the CMOS device;

thinning one side of the CMOS device of the second storage unit, which is far away from the storage array device of the second storage unit;

forming a second set of contacts on a side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell, wherein the second set of contacts are electrically connected with the CMOS device of the second memory cell; and

and stacking the second storage unit on the side, facing away from the CMOS device of the first storage unit, of the storage array device of the first storage unit, and jointing the storage array device of the first storage unit with the CMOS device of the second storage unit, so that the first group of contacts of the first storage unit are correspondingly and electrically connected with the second group of contacts of the second storage unit.

9. The method of manufacturing a three-dimensional memory device according to claim 8, wherein the second memory cell is plural, the method of manufacturing a three-dimensional memory device comprising:

stacking one of the second memory cells on a side of the memory array device of the first memory cell facing away from the CMOS device of the first memory cell, and bonding the CMOS device of the one of the second memory cells with the memory array device of the first memory cell such that the second set of contacts of the one of the second memory cells are correspondingly electrically connected with the first set of contacts of the first memory cell;

stacking another second storage unit on the side, facing away from the CMOS device of the outer-layer second storage unit, of the storage array device of the outer-layer second storage unit, jointing the CMOS device of the another second storage unit with the storage array device of the outer-layer second storage unit, enabling the first group contact of the outer-layer second storage unit to be correspondingly and electrically connected with the second group contact of the another second storage unit, and repeating the step until a plurality of second storage units are sequentially stacked on the first storage unit, wherein the outer-layer second storage unit is the second storage unit which is stacked on the first storage unit and farthest away from the first storage unit along the stacking direction.

10. The method of manufacturing a three-dimensional memory device according to claim 8 or 9, wherein before the step of thinning a side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell, the method of manufacturing a three-dimensional memory device further comprises:

and providing a bearing sheet, and attaching the bearing sheet to one side of the storage array device of the second storage unit, which is far away from the CMOS device of the second storage unit, so that the bearing sheet covers one side of the storage array device of the second storage unit, which is far away from the CMOS device of the second storage unit, and the first group of contacts of the second storage unit.

11. The method of fabricating a three-dimensional memory device according to claim 10, wherein after stacking the second memory cell on other memory cells and bonding the CMOS device of the second memory cell with the memory array devices of the other memory cells, the method of fabricating a three-dimensional memory device further comprises:

removing the bearing sheet to expose the first group of contacts of the second storage unit;

wherein the other storage units are the first storage unit or the rest of the second storage units.

12. The method of fabricating a three-dimensional memory device according to claim 8 or 9, further comprising:

forming an isolation layer on one side, away from the CMOS device of the outer-layer second storage unit, of the storage array device of the outer-layer second storage unit, wherein the isolation layer covers one side, away from the CMOS device of the outer-layer second storage unit, of the storage array device of the outer-layer second storage unit and a first group of contacts of the outer-layer second storage unit, and the outer-layer second storage unit is a second storage unit which is stacked on the first storage unit and is farthest from the first storage unit along a stacking direction;

and embedding an array pad in the isolation layer, and correspondingly and electrically connecting the array pad with the first group of contacts of the outer-layer second storage unit.

13. The method of fabricating a three-dimensional memory device of claim 12, further comprising: and forming a protective layer with an opening on one side of the isolation layer, which is far away from the outer layer second storage unit, so that the protective layer covers the isolation layer, and the array bonding pad is exposed by the opening.

14. The method of claim 10, wherein attaching the carrier sheet to a side of the memory array device of the second memory cell facing away from the CMOS device of the second memory cell comprises:

coating any bonding glue of heating curing glue, ultraviolet light irradiation curing glue, heating decomposition glue or laser decomposition glue on one side of the bearing sheet facing the second storage unit and/or one side of the storage array device of the second storage unit, which is far away from the CMOS device of the second storage unit; and

and bonding the bearing sheet to the side, away from the CMOS device of the second storage unit, of the storage array device of the second storage unit through a temporary bonding process or a permanent bonding process.

15. The method of claim 8, wherein each memory cell further comprises an interconnect via disposed in the memory array device and the CMOS device of the memory cell and electrically connected to the first set of contacts of the memory cell and the CMOS device, respectively, the first set of contacts being electrically connected to the CMOS device through the interconnect via, wherein the CMOS device comprises a CMOS substrate;

the forming of the second group of contacts on the side of the CMOS device of the second memory cell away from the memory array device of the second memory cell specifically includes:

forming a through hole penetrating through the CMOS substrate of the second memory cell on the CMOS substrate, the through hole exposing at least a portion of the interconnection channel of the second memory cell;

filling a conductive medium in the through hole to form a conductive channel, wherein the conductive channel is electrically connected with the interconnection channel of the second storage unit; and

forming a second set of contacts of the second memory cell from an end of the conductive via remote from the interconnect via of the second memory cell such that the second set of contacts are electrically connected to the interconnect via of the second memory cell through the conductive via.

16. The method of fabricating a three-dimensional memory device according to claim 9, wherein the bonding between the memory array device of the first memory cell and the CMOS device of the first memory cell, the bonding between the memory array device of the second memory cell and the CMOS device of the second memory cell, the bonding between the memory array device of the first memory cell and the CMOS device of the second memory cell, and the bonding between the memory array device of the second memory cell and the CMOS device of the other second memory cell are performed by methods including an Xtacking bonding process.

17. A three-dimensional memory comprising the three-dimensional memory device according to any one of claims 1 to 7.

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to a three-dimensional memory device, a manufacturing method thereof and a three-dimensional memory comprising the three-dimensional memory device.

Background

The 3D NAND memory is an emerging three-dimensional memory type, and solves the problem of limited storage capacity of 2D or planar NAND memories by vertically stacking multiple data storage layers in a memory chip. The storage chip comprises a CMOS device and a storage array device with a step structure, wherein the CMOS device and the storage array device are respectively formed on a substrate, and the sides of the CMOS device and the storage array device, which are far away from the respective substrates, are electrically connected with each other.

With the increasing demand for high-density design of 3D NAND memories, the number of memory layers in memory array devices of memory chips is increasing. However, in the prior art, as the number of stacked layers of the storage layer increases, the number of step layers and the occupied area of the step structure of the storage array device correspondingly increase, so that the area of the substrate of the storage array device increases, and further, the substrate of the storage array device and the substrate of the CMOS device have an area mismatch condition, which leads to an idle condition of the utilization space of the storage chip, and is not favorable for the development and volume miniaturization of the next generation of 3D NAND memory.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a three-dimensional storage device, a manufacturing method thereof and a three-dimensional storage, wherein the three-dimensional storage device not only has high storage density, but also can improve the space utilization rate.

In order to achieve the above object, an aspect of the present invention provides a three-dimensional memory device including at least two memory cells stacked in sequence, the at least two memory cells including a first memory cell and at least one second memory cell stacked on the first memory cell, each memory cell including:

the CMOS device comprises a storage array device and a CMOS device, wherein the storage array device and the CMOS device are stacked and electrically connected with each other; and

the first group of contacts are arranged on one side, away from the CMOS device, of the storage array device and are electrically connected with the CMOS device;

In another aspect, the present invention further provides a method for manufacturing a three-dimensional memory device, including the steps of:

thinning one side of the CMOS device of the second storage unit, which is far away from the storage array device of the second storage unit;

In still another aspect of the present invention, a three-dimensional memory device is provided, which includes the three-dimensional memory device described above.

Compared with the prior art, the invention has the beneficial effects that: the three-dimensional memory device with high storage density can be formed by sequentially stacking at least two memory units and realizing the electrical connection between the at least two memory units through the corresponding first group of contacts and the second group of contacts, so that excessive memory layers do not need to be stacked in the memory array device of each memory unit, the substrate area of the memory array device of each memory unit is not too large, the memory array device of each memory unit and the respective substrate of the CMOS device are favorably arranged according to proper area ratio, the idle utilization space in each memory unit can be reduced, and the space utilization rate of the three-dimensional memory device is improved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a schematic cross-sectional view of a three-dimensional memory device provided by one embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of a three-dimensional memory device according to another embodiment of the invention.

Fig. 3 is a flowchart of a method of fabricating a three-dimensional memory device according to the present invention.

Fig. 4 to 7 are schematic views illustrating a process of forming a memory cell of a three-dimensional memory device, wherein fig. 4 is a schematic cross-sectional view of a memory array device and a CMOS device;

FIG. 5 is a schematic cross-sectional view of the memory array device and CMOS device of FIG. 4 after bonding;

FIG. 6 is a schematic cross-sectional view of the memory array device and CMOS device of FIG. 5 after thinning of the array substrate;

fig. 7 is a schematic cross-sectional view of the memory array device of fig. 6 with a first set of contacts formed on a side of the device facing away from the CMOS device and overlying the first bonding layer.

Fig. 8 is a schematic cross-sectional view of the second memory cell shown in fig. 7 after attaching a carrier sheet to a side of the memory array device facing away from the CMOS device and turning over the carrier sheet.

Fig. 9 is a schematic cross-sectional view of the second memory cell of fig. 8 after thinning of the CMOS substrate.

Fig. 10 is a schematic cross-sectional view of the second memory cell of fig. 9 having a conductive via formed in a CMOS substrate, the CMOS substrate being sequentially covered with a first insulating layer and a second insulating layer on a side thereof facing away from the memory array device.

FIG. 11 is a cross-sectional view of the second memory cell shown in FIG. 10 with a second set of contacts formed on the second insulating layer and overlying the second bonding layer.

Fig. 12 is a schematic cross-sectional view of the second memory cell of fig. 11 after being flipped over and bonded to the first memory cell.

Fig. 13 is a schematic cross-sectional view of the first memory cell and the second memory cell of fig. 12 with the carrier removed from the second memory cell and the first bonding layer thinned to expose the first set of contacts.

Description of the main element symbols:

first memory cell 100

Second memory cell 200

Memory array device 10

Array substrate 11

Storage layer 13

CMOS device 20

CMOS substrate 21

Interconnecting channel 30

First interconnect sub-channel 31

Second interconnect sub-channel 32

Interconnect structure 33

First interconnect contact 331

Second interconnect contact 332

First set of contacts 40

First conductive path 41

First bonding layer 42

Second set of contacts 50

Second bonding layer 52

Isolation layer 300

Array pad 400

Protective layer 500

Second conductive path 60

The following detailed description will further illustrate the invention in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Referring to fig. 1 and 2, the present invention provides a three-dimensional memory device including at least two memory cells sequentially stacked, wherein the at least two memory cells include a first memory cell 100 and at least one second memory cell 200 stacked on the first memory cell 100. Specifically, as shown in fig. 1, in one embodiment of the present invention, the number of the second memory cells 200 is one, and the first memory cell 100 and the second memory cell 200 are stacked to form a three-dimensional memory device 1000; as shown in fig. 2, in another embodiment of the present invention, the number of the second memory cells 200 is multiple (two or more), the multiple second memory cells 200 are sequentially stacked on the first memory cell 100, and the first memory cell 100 and the multiple second memory cells 200 are stacked to form a three-dimensional memory device 1000 b. The three-dimensional memory device provided by the invention is formed by stacking at least two memory cells, so that the memory density is high.

As shown in fig. 1 and 2, in some embodiments of the present invention, each memory cell includes a memory array device 10 and a CMOS device 20 stacked and electrically connected to each other, and a first set of contacts 40 disposed on a side of the memory array device 10 facing away from the CMOS device 20 and electrically connected to the CMOS device 20. Specifically, in some embodiments of the present invention, the memory array device 10 and the CMOS device 20 of each memory cell are preferably bonded to each other, so as to achieve electrical connection therebetween. Of course, in other embodiments, the memory array device 10 and the CMOS device 20 of each memory cell may be electrically connected in other ways, including but not limited to wire connections, conductive contact connections, plug connections, and the like.

The memory array device 10 includes an array substrate 11 and a memory array disposed on one side of the array substrate 11 close to the CMOS device 20, where the memory array has a data storage function, and includes a plurality of memory layers 13 and a plurality of memory strings penetrating and communicating with the memory layers 13. The first set of contacts 40 for each memory cell is provided on a side of the array substrate 11 facing away from the CMOS device 20. The CMOS device 20 includes a CMOS substrate 21 and a CMOS circuit disposed on one side of the CMOS substrate 21 close to the memory array device 10, where the CMOS circuit is used to implement logic control of the memory array device 10, read of stored data, and the like.

Further, as shown in fig. 1 and fig. 2, in some embodiments of the present invention, each memory cell further includes an interconnection channel 30, and the interconnection channel 30 is electrically connected to the first set of contacts 40 of the memory cell and the CMOS device 20, respectively, so that the first set of contacts 40 is electrically connected to the CMOS device 20 through the interconnection channel 30. Specifically, in some embodiments of the present invention, the interconnect channel 30 is disposed in the memory array device 10 and the CMOS device 20 of the memory cell, and is perpendicular to the array substrate 11 and the CMOS substrate 21. Of course, in other embodiments, the interconnection channel 30 may not be perpendicular to the array substrate 11 and the CMOS substrate 21, and may also be perpendicular to the array substrate 11 or the CMOS substrate 21.

It is important to note that in some embodiments of the present invention, each second memory cell 200 further includes a second set of contacts 50. Specifically, the second set of contacts 50 is disposed on a side of the CMOS device 20 of the second memory cell 200 facing away from the memory array device 10 of the second memory cell 200, and is electrically connected to the CMOS device 20 of the second memory cell 200.

As shown in fig. 1 and fig. 2, in some embodiments of the present invention, the memory array device 10 of the first memory cell 100 is bonded to the CMOS device 20 of the adjacent second memory cell 200, and the first set of contacts 40 of the first memory cell 100 is electrically connected to the second set of contacts 50 of the adjacent second memory cell 200, so that the first memory cell 100 is electrically connected to the adjacent second memory cell 200 through the corresponding first set of contacts 40 and the corresponding second set of contacts 50.

As shown in fig. 1, in one embodiment of the present invention, when there is only one second memory cell 200 in the three-dimensional memory device 1000, the second memory cell 200 is an outer layer second memory cell 200 stacked on the first memory cell 100, and the first set of contacts 40 of the outer layer second memory cell 200 is used for connecting an external device (e.g., a control device or a driving circuit), so as to implement functions of driving, controlling, and the like of the three-dimensional memory device 1000.

In another embodiment of the invention, as shown in fig. 2, when there are a plurality of second memory cells 200 in the three-dimensional memory device 1000b, the plurality of second memory cells 200 are sequentially stacked on the first memory cell 100, and in two adjacent second memory cells 200, the first set of contacts 40 of the second memory cell 200 close to the first memory cell 100 is correspondingly electrically connected to the second set of contacts 50 of the second memory cell 200 far from the first memory cell 100, so that the two adjacent second memory cells 200 are electrically connected through the corresponding first set of contacts 40 and second set of contacts 50, and further the first memory cell 100 is electrically connected to the plurality of second memory cells 200 sequentially stacked on the first memory cell 100. The second memory cell 200 farthest from the first memory cell 100 in the stacking direction is the outer layer second memory cell 200 stacked on the first memory cell 100, and the first set of contacts 40 of the outer layer second memory cell 200 is used for connecting an external device (e.g., a control device or a driving circuit), so as to implement functions of driving, controlling, and the like of the three-dimensional memory device 1000 b. It can be appreciated that the number of memory cells stacked in the three-dimensional memory device 1000b is greater compared to the three-dimensional memory device 1000, and thus the memory density of the three-dimensional memory device 1000b is higher.

In the embodiment of the invention, a three-dimensional memory device with high storage density can be formed by sequentially stacking at least two memory cells and realizing the electrical connection between the at least two memory cells through the corresponding first group of contacts 40 and the second group of contacts 50, so that excessive memory layers 13 do not need to be stacked in the memory array device 10 of each memory cell, the area of the array substrate 11 of each memory cell is not too large, the array substrate 11 and the CMOS substrate 21 of each memory cell are favorably arranged in a proper area ratio, the idle utilization space in each memory cell can be further reduced, and the space utilization rate of the three-dimensional memory device is improved.

Wherein, the array substrate 11 and the CMOS substrate 21 may each be made of a semiconductor material including, but not limited to, silicon, germanium, silicon germanium, gallium arsenide, silicon-on-insulator, germanium-on-insulator, or any suitable combination thereof, or a non-conductive material including, but not limited to, glass, plastic, or sapphire. In the embodiment of the present invention, the array substrate 11 and the CMOS substrate 21 are both silicon substrates. Here, the array substrate 11 and the CMOS substrate 21 of any memory cell in the three-dimensional memory device may be thinned in addition to the CMOS substrate 21 of the first memory cell 100, so as to facilitate reduction in volume of the three-dimensional memory device. The thinning means includes, but is not limited to, mechanical grinding, wet/dry etching, chemical mechanical grinding, or any combination thereof.

As shown in fig. 1 and 2, in each memory array device 10, a plurality of memory layers 13 are stacked on one side of an array substrate 11 in a step structure, and a plurality of memory strings (for example, NAND strings) penetrate through and communicate with the plurality of memory layers 13, so that the plurality of memory strings and the plurality of memory layers 13 together form a memory array with a memory function.

Specifically, each memory layer 13 extends in a lateral direction parallel to the surface of the array substrate 11; in a direction gradually away and perpendicular to the array substrate 11, every adjacent two of the several memory layers 13 are offset by the same distance and reduced by the same extension distance in a lateral direction. It will be appreciated that each two adjacent memory layers 13 may be level at one end and reduced by the same distance at the other end in the lateral direction, or may be reduced by the same distance at both ends in the lateral direction. As shown in fig. 1 and 2, in some embodiments of the present invention, two ends of each adjacent two storage layers 13 in the lateral direction are respectively reduced by the same distance. Each memory layer 13 may include one or more conductor/dielectric layer pairs, each of which includes a conductor layer and a dielectric layer, and the specific structures, functions, and materials of the conductor layer and the dielectric layer are the same as those of the conductor layer and the dielectric layer commonly used in the prior art, and therefore, the description thereof is omitted here.

Each of the memory strings includes a channel structure extending in a direction perpendicular to the array substrate 11 and penetrating the number of memory layers 13, the channel structure including a channel hole filled with a semiconductor material (as a semiconductor channel) and a dielectric material (as a memory film). The memory film may include a tunnel layer, a charge trapping/storage layer, and a blocking layer, and the semiconductor channel, the tunnel layer, the charge trapping/storage layer, and the blocking layer are sequentially disposed along a direction from a center of the memory string to an outside. It should be noted that the specific structure, function and material of the memory string are the same as those of a memory string commonly used in the prior art, and therefore, no further description is given here.

In the three-dimensional memory device provided by the present invention, each of the memory array devices 10 of the first memory cell 100 and the second memory cell 200 includes a plurality of memory layers 13. As described above, in order to avoid the area of the array substrate 11 from being too large, and the memory array device 10 of each memory cell does not need to stack too many memory layers 13, it is preferable that the three-dimensional memory device provided in the embodiment of the present invention includes a predetermined number of memory layers 13 in each memory array device 10 of the first memory cell 100 and the second memory cell 200, where the predetermined number of memory layers is an integer greater than 0 and less than 500, such as 32 layers, 64 layers, 96 layers, or 128 layers. The number of the memory layers 13 in the memory array device 10 of each of the first memory unit 100 and the second memory unit 200 may be the same or different, preferably the same, so as to facilitate mass production of the first memory unit 100 and the second memory unit 200 in the same process step.

It is understood that, in each memory unit, the memory array device 10 and the CMOS device 20 further include other elements, such as a stack layer covering the memory array or the CMOS circuit, a bonding structure (including but not limited to conductive structures such as wires, plugs, solder bumps, or pads) disposed on an inner surface of the stack layer, and a plurality of interconnected conductive channels that penetrate through the stack layer and are electrically connected to the bonding structure and the memory array or the CMOS circuit, respectively, where the stack layer includes at least one insulating layer covering the CMOS array or the CMOS circuit, and specific structures and functions of the memory array device 10 and the CMOS device 20 are substantially the same as those of the memory array device and the CMOS device in the prior art, and are not repeated herein because the structure and function are not related to the improvement and creation of the present invention.

In some embodiments of the present invention, as shown in fig. 1 and 2, the interconnect channel 30 includes a first interconnect sub-channel 31, a second interconnect sub-channel 32, and an interconnect structure 33 electrically connected between the first interconnect sub-channel 31 and the second interconnect sub-channel 32.

Specifically, the first interconnection sub-channel 31 is disposed in the memory array device 10 and located on the side of the memory array device 10 where the memory array is disposed, and the first interconnection sub-channel penetrates through the stacked layers of the memory array device 10; the second sub-interconnect channel 32 is disposed in the CMOS device 20 and located on a side of the CMOS device 20 where the CMOS circuit is disposed, and the second sub-interconnect channel 32 penetrates through the stacked layers of the CMOS device 20, where the second sub-interconnect channel 32 corresponds to the first sub-interconnect channel 31, and an end of the second sub-interconnect channel 32 away from the first sub-interconnect channel 31 is electrically connected to the CMOS circuit. It should be noted that the first interconnection sub-channel 31 and the second interconnection sub-channel 32 may be formed by a conventional method in the prior art, for example, in some embodiments of the present invention, a deep etching process may be performed on the stacked layers of the memory array device 10 and the CMOS device 20 to form a filling channel penetrating through the stacked layers, and then a conductive material, including but not limited to tungsten, cobalt, copper, aluminum, polysilicon, silicide or any combination thereof, preferably tungsten, may be filled into the filling channel to form the first interconnection sub-channel 31 and the second interconnection sub-channel 32, respectively. The number of the first interconnecting sub-channel 31 and the second interconnecting sub-channel 32 may be one or more, as long as the number of the first interconnecting sub-channel and the second interconnecting sub-channel is equal, and the number is not limited.

The interconnect structure 33 includes a first interconnect contact disposed on an inner (i.e., a side close to the CMOS device) surface of the stacked layers of the memory array device 10 and electrically connected to the first interconnect sub-channel 31, and a second interconnect contact disposed on an inner (i.e., a side close to the memory array device) surface of the stacked layers of the CMOS device 20 and electrically connected to the second interconnect sub-channel 32. The first interconnection contact and the second interconnection contact include, but are not limited to, conductive structures such as wires, plugs, solder bumps, or pads, and the structural forms of the first interconnection contact and the second interconnection contact may be the same or different. As shown in fig. 1 and fig. 2, in some embodiments of the present invention, the first interconnection contact is a plurality of solder bumps, and the number of solder bumps is equal to that of the first interconnection sub-channels 31 and the solder bumps are electrically connected in a one-to-one correspondence; the second interconnection contact is a bonding pad, one side surface of the bonding pad is correspondingly and electrically connected with the second interconnection sub-channel 32, the other side surface of the bonding pad is provided with a plurality of welding feet, and the welding feet are in one-to-one correspondence with the welding blocks of the first interconnection contact. It is understood that when the memory array device 10 and the CMOS device 20 of each memory cell are bonded face-to-face, the first interconnect contact and the second interconnect contact are bonded together to form the interconnect structure 33, such that the first interconnect sub-channel 31 and the second interconnect sub-channel 32 are electrically connected correspondingly through the interconnect structure 33 to form the interconnect channel 30 of the memory cell.

Referring to fig. 1 and fig. 2 again, in some embodiments of the invention, the first set of contacts 40 is disposed on an outer side of the array substrate 11 (i.e., a side facing away from the memory array), the array substrate 11 is provided with a plurality of first conductive vias 41 at positions corresponding to the first interconnection sub-vias 31 in the memory array device 10, and each of the first conductive vias 41 penetrates through two opposite sides of the array substrate 11 and is electrically connected to a corresponding one of the first interconnection sub-vias 31, so that the first set of contacts 40 is electrically connected to the first interconnection sub-vias 31 through the first conductive vias 41.

Where the first set of contacts 40 includes, but is not limited to, conductive structures such as wires, plugs, solder bumps, or solder pads, in some embodiments of the invention, the first set of contacts 40 are solder pads that are electrically connected to the first conductive paths 41.

The outer side surface of the array substrate 11 is further covered with a first bonding layer 42, and one end of the first conductive channel 41 away from the first interconnecting sub-channel 31 and the first group of contacts 40 are embedded in the first bonding layer 42. The first bonding layer 42 may be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The first bonding layer 42 includes at least one dielectric layer made of a dielectric material including, but not limited to, silicon oxide or silicon nitride, without limitation.

In some embodiments of the present invention, the first conductive via 41 may be formed by a conventional method such as a through silicon via (tsv) technique. Specifically, deep etching is performed on the first bonding layer 42 and the array substrate 11 at positions corresponding to the plurality of first interconnection sub-channels 31 to form a plurality of first vertical channels penetrating through the first bonding layer 42 and the array substrate 11, each of the first vertical channels exposes at least a portion of a corresponding first interconnection sub-channel 31, then a conductive material is filled into the first vertical channel until the conductive material partially exceeds the outer side surface of the array substrate 11, so that a first conductive channel 41 in contact with the first interconnection sub-channel 31 can be formed, and one end of the first conductive channel 41, which is far away from the first interconnection sub-channel 31, is located in the first bonding layer 42. By covering the first bonding layer 42 on the outer surface of the array substrate 11, the conductive material in the first vertical channel can be prevented from leaking during the process of the first conductive channel 41, and the pollution to other processes can be avoided.

Further, in some embodiments of the present invention, after the first conductive vias 41 are formed, the etching of the first bonding layer 42 is continued at positions corresponding to the first conductive vias 41 to form openings for exposing end portions of the first conductive vias 41 away from the first interconnection sub-vias 31, and then the first set of contacts 40 (i.e., pads) are disposed in the openings so that the first set of contacts 40 are electrically connected with the first conductive vias 41. Preferably, in some embodiments of the present invention, after the first set of contacts 40 is disposed in the opening of the first bonding layer 42, the opening may be filled with a dielectric material of the first bonding layer 42 again to cover the first set of contacts 40, so as to prevent the first set of contacts 40 from being exposed, thereby preventing the first set of contacts 40 from being damaged before being bonded with the corresponding second set of contacts 50, and facilitating to improve the reliability of the bonding connection between the first set of contacts 40 and the corresponding second set of contacts 50. Of course, in other embodiments, the first set of contacts 40 may be exposed. It will be appreciated that when the first set of contacts 40 within the opening of the first bonding layer 42 are covered with a dielectric material, the first bonding layer 42 may need to be thinned or etched to remove the dielectric material to expose the first set of contacts 40 within the opening before the first set of contacts 40 are bonded to the corresponding second set of contacts 50.

As shown in fig. 1 and fig. 2, in some embodiments of the present invention, the second set of contacts 50 of the second storage unit 200 is disposed on an outer side of the CMOS substrate 21 (i.e., a side facing away from the CMOS circuit), the CMOS substrate 21 is provided with a plurality of second conductive vias 60 at positions corresponding to the second interconnection sub-vias 32 in the CMOS device 20 where the CMOS substrate is located, and each second conductive via 60 penetrates through two opposite sides of the CMOS substrate 21 and is electrically connected to the second set of contacts 50 and the CMOS device of the CMOS device 20, so that the second set of contacts 50 is electrically connected to the CMOS circuit of the CMOS device 20 through the second conductive vias 60. Of course, in other embodiments, the second conductive via 60 may not correspond to the second interconnect sub-via 32, so long as the second conductive via 60 is electrically connected to the CMOS circuitry of the CMOS device 20.

The second set of contacts 50 includes, but is not limited to, conductive structures such as wires, plugs, solder bumps, or solder pads, and in some embodiments of the invention, the second set of contacts 50 are a plurality of solder bumps, and the plurality of solder bumps are electrically connected to the plurality of second conductive vias 60 in a one-to-one correspondence.

The outer surface of the CMOS substrate 21 of the second memory cell 200 is covered with a second bonding layer 52, and the end of the second conductive via 60 away from the second interconnecting sub-via 32 and the second set of contacts 50 are embedded in the second bonding layer 52. Similar to the first bonding layer 42, the second bonding layer 52 may also be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof; the second bonding layer 52 also includes at least one dielectric layer made of a dielectric material including, but not limited to, silicon oxide or silicon nitride, without limitation.

In some embodiments of the present invention, the second conductive via 60 and the first conductive via 41 are formed substantially in the same process, specifically, deep etching may be performed at a position where the second bonding layer 52 and the CMOS substrate 21 correspond to the plurality of second interconnection sub-vias 32 to form a plurality of second vertical vias penetrating through the second bonding layer 52 and the CMOS substrate 21, each of the second vertical vias exposes at least a portion of a corresponding second interconnection sub-via 32, and then the second vertical vias are filled with a conductive material until the conductive material partially exceeds the outer side surface of the CMOS substrate 21, so that the second conductive via 60 contacting the second interconnection sub-via 32 is formed, so that the second conductive via 60 is electrically connected to the CMOS circuit, and an end of the second conductive via 60 away from the second interconnection sub-via 32 is located in the second bonding layer 52. By covering the second bonding layer 52 on the outer surface of the CMOS substrate 21, the conductive material in the second vertical channel can be prevented from leaking during the process of forming the second conductive channel 60, thereby preventing contamination to other processes. The conductive material filled in the second vertical channel and the first vertical channel includes, but is not limited to, tungsten, copper, aluminum, polysilicon, silicide, or any combination thereof, and the conductive material filled in the first vertical channel and the second vertical channel may be the same or different. In some embodiments of the present invention, the conductive material filled in each of the first vertical channel and the second vertical channel is preferably tungsten.

It should be noted that in some embodiments of the present invention, the second set of contacts 50 is manufactured differently from the first set of contacts 40 in that: after the second conductive vias 60 are formed, a solder bump may be disposed directly within each of the second vertical vias of the second bonding layer 52, with the solder bumps within the second vertical vias forming the second set of contacts 50. Further, like the first set of contacts 40, in some embodiments of the present invention, the second set of contacts 50 may be covered or exposed, preferably covered, to prevent damage to the second set of contacts 50 prior to bonding with the corresponding first set of contacts 40, which may also be beneficial in improving the reliability of the bonding of the first set of contacts 40 with the corresponding second set of contacts 50. It will be appreciated that when the solder bumps in each of the second vertical channels of the second bonding layer 52 are covered by the dielectric material of the second bonding layer 52 (i.e., the second set of contacts 50 are covered), the second bonding layer 52 may need to be thinned or etched to remove the dielectric material in each of the second vertical channels and expose the solder bumps in each of the second vertical channels, i.e., to expose the second set of contacts 50 for bonding with the corresponding first set of contacts 40, before the first set of contacts 40 are bonded to the corresponding second set of contacts 50.

It is understood that, as shown in fig. 1 and 2, after the first group of contacts 40 of the memory cell located below and the second group of contacts 50 of the other memory cell located above are correspondingly bonded in any two adjacent memory cells, the CMOS circuits of the two adjacent memory cells are connected, and the first bonding layer 42 of the memory cell located below and the second bonding layer 52 of the other memory cell located above are bonded together.

Further, referring to fig. 1 and 2 again, in some embodiments of the invention, the three-dimensional memory device further includes an isolation layer 300 and an array pad 400 embedded in the isolation layer 300. Specifically, the isolation layer 300 covers a side of the outer layer of the second memory cell 200 facing away from the first memory cell 100 and the first set of contacts 40 of the outer layer of the second memory cell 200. The isolation layer 300 has a receiving cavity corresponding to at least a portion of the first set of contacts 40 of the outer second storage unit 200. The array pad 400 is disposed in the accommodating cavity of the isolation layer 300 and electrically connected to the first set of contacts 40 of the outer second memory unit 200, and the three-dimensional memory device is electrically connected to the external device through the array pad 400.

The accommodating cavity of the isolation layer 300 may be formed by etching or other common means, which is not described herein again; the array bonding pad 400, the aforementioned bonding pads, etc. can be prepared by conventional methods in the prior art, and therefore, are not described in detail.

Note that, similar to the first bonding layer 42 and the second bonding layer 52, the isolation layer 300 can also be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof; the isolation layer 300 may also include at least one dielectric layer made of a dielectric material including, but not limited to, silicon oxide or silicon nitride, without limitation.

The accommodating cavity of the isolation layer 300 may be a cavity with one end opening toward the outer layer second storage unit 200, so that the array pad 400 is covered by the isolation layer 300 before being connected to the external device, which is beneficial to protecting the array pad 400, but when the array pad 400 is electrically connected to the external device, the position of the isolation layer 300 corresponding to the accommodating cavity needs to be thinned or etched, so that the array pad 400 is exposed. Of course, the receiving cavity of the isolation layer 300 may also have a cavity structure with two open ends, such that the array pad 400 is exposed, so as to be electrically connected to the external device directly.

In some embodiments of the invention, as shown in fig. 1 and 2, the isolation layer 300 covers the outer side of the first bonding layer 42 of the second memory cell 200. It is to be understood that the isolation layer 300 and the first bonding layer 42 are both composed of a dielectric material, and thus, the materials of the isolation layer 300 and the first bonding layer 42 may be the same or different. That is, the isolation layer 300 and the first bonding layer 42 may be formed in different thin film deposition processes, or may be formed in the same thin film deposition process. Preferably, the isolation layer 300 and the first bonding layer 42 are formed in different thin film deposition processes, so that the first group of contacts 40 and the array pad 400 can be arranged in a divided manner in different thin film deposition processes, which is convenient to operate; furthermore, the first bonding layer 42 and the isolation layer 300 are formed in a stepwise manner, and when the first bonding layer 42 and the isolation layer 300 are etched respectively, the etching depth is small, which is beneficial to improving the etching efficiency and accuracy.

Further, as shown in fig. 1 and 2, in some embodiments of the invention, the three-dimensional memory device further includes a protective layer 500 stacked on an outer side surface of the isolation layer 300, the protective layer 500 covering the isolation layer 300 and having an opening at a position corresponding to the array pad 400, and at least a portion of the array pad 400 is exposed through the opening for connecting to the external device. Of course, in other embodiments, the protective layer 500 may also cover the array pad 400 to protect the array pad 400, but when electrically connecting the array pad 400 and the external device, the protective layer 500 needs to be thinned or etched at a position corresponding to the array pad 400 to expose the array pad 400.

By covering the protective layer 500 on the isolation layer 300, the isolation layer 300 can be protected, preventing the isolation layer 300 from being damaged, thereby preventing the array pad 400 from being loosened due to the damage of the isolation layer 300 and ensuring the connection reliability of the array pad 400.

The protection layer 500 may be made of silicon nitride or silicon oxide, and the second through hole is opened by common means such as etching, which is not described herein.

Referring to fig. 3, the present invention further provides a method for manufacturing the three-dimensional memory device, which includes the following steps:

step S1, providing a first memory cell and a second memory cell, where the first memory cell and the second memory cell each include a first set of contacts, and a memory array device and a CMOS device stacked and electrically connected to each other, where the first set of contacts are disposed on a side of the memory array device facing away from the CMOS device and electrically connected to the CMOS device.

Specifically, referring to fig. 4 to 7, the manufacturing process of the memory cell is as follows:

in a first step, a memory array device 10 and a CMOS device 20 are provided. As shown in fig. 4, the memory array device 10 includes an array substrate 11, a memory array disposed inside the array substrate 11 (i.e., on a side close to the CMOS device 20), a first interconnection sub-channel 31 disposed in the memory array, and a first interconnection contact 331 disposed on an inner surface of the memory array device 10 and electrically connected to the first interconnection sub-channel 31, wherein the memory array includes a plurality of memory layers 13 in a step structure and a plurality of memory strings penetrating and communicating the plurality of memory layers 13; as shown in fig. 4, the CMOS device 20 includes a CMOS substrate 21, a CMOS circuit disposed inside the CMOS substrate 21 (i.e., on a side close to the memory array device 10), a second interconnection sub-channel 32 disposed on a side of the CMOS circuit and electrically connected to the CMOS circuit, and a second interconnection contact 332 disposed on an inner side surface of the CMOS device 20 and electrically connected to the second interconnection sub-channel 32. It should be noted that specific features, functions, or forming processes of the array substrate 11, the memory layers 13, the memory strings, the CMOS substrate 21, the first interconnection sub-channel 31, the second interconnection sub-channel 32, the first interconnection contact 331, and the second interconnection contact 332 may refer to corresponding contents in the three-dimensional memory device, and are not described herein again. In addition, the memory array device 10 and the CMOS device 20 respectively include other elements, and the specific structures and functions of the two elements are substantially the same as those of the existing memory array device and CMOS device, and therefore are not related to the improvement and creation of the present invention, and are not described herein again.

In a second step, the memory array device 10 and the CMOS device 20 are bonded face to face. As shown in fig. 5, after the memory array device 10 and the CMOS device 20 are bonded in a pair-wise manner, the first interconnection contact 331 and the second interconnection contact 332 (shown in fig. 4) are bonded together to form an interconnection structure 33, so that the first interconnection sub-channel 31 and the second interconnection sub-channel 32 are correspondingly electrically connected through the interconnection structure 33 to form an interconnection channel 30 of the memory cell, and the interconnection channel 30 is electrically connected to the first group of contacts 40 of the memory cell and the CMOS device 20, respectively, so that the first group of contacts 40 is electrically connected to the CMOS device 20 through the interconnection channel 30.

In a third step, as shown in fig. 6, the outer side of the array substrate 11 of the memory array device 10 (i.e. the side facing away from the memory array) is thinned. The thinning means includes, but is not limited to, mechanical grinding, wet/dry etching, chemical mechanical grinding, or any combination thereof.

Fourth, a first set of contacts 40 is formed on the outside of the memory array device 10 such that the first set of contacts 40 are electrically connected to the first interconnect sub-channel 31. Specifically, as shown in fig. 7, in some embodiments of the present invention, the outer side surface of the array substrate 11 is covered with a first bonding layer 42, a first conductive via 41 penetrating through the array substrate 11 and electrically connected to the first interconnection sub-via 31 can be formed by conventional technical means, one end of the first conductive via 41 away from the first interconnection sub-via 31 and the first group of contacts 40 are embedded in the first bonding layer 42, and the first group of contacts 40 are electrically connected to the first interconnection sub-via 31 through the first conductive via 41. Similarly, the specific features, functions, or forming processes of the first bonding layer 42 and the first conductive via 41 can be referred to the corresponding contents in the above three-dimensional memory device, and are not described herein again.

Through the steps of the first to fourth steps, the same portions of the first memory cell 100 and the second memory cell 200 as the first memory cell 100 can be prepared.

And step S2, thinning the side of the CMOS device of the second storage unit, which is far away from the storage array device of the second storage unit. I.e. the side of the CMOS substrate of the second memory cell facing away from the CMOS circuitry, is thinned by means including, but not limited to, mechanical grinding, wet/dry etching, chemical mechanical grinding, or any combination thereof.

Referring to fig. 8 and 9 together, in some embodiments of the present invention, before step S2, the method for manufacturing the three-dimensional memory device further includes the steps of: and providing a bearing sheet, and attaching the bearing sheet to one side of the storage array device of the second storage unit, which is far away from the CMOS device of the second storage unit, so that the bearing sheet covers one side of the storage array device of the second storage unit, which is far away from the CMOS device of the second storage unit, and the first group of contacts of the second storage unit.

Specifically, as shown in fig. 8 and 9, the second memory cell 200 is turned over to make the memory array device 10 of the second memory cell 200 located below, then the carrier sheet 600 is attached to the outer side of the memory array device 10 of the second memory cell 200 (i.e. the side away from the CMOS device 20 of the second memory cell 200), so that the carrier sheet 600 covers the outer side of the memory array device 10 of the second memory cell 200 and the first group of contacts 40, and finally the CMOS substrate 21 of the second memory cell 200 is thinned. The bearing sheet 600 is attached to the outer side of the memory array device 10 of the second memory unit 200, so that the second memory unit 200 can be supported, and the deformation of the second memory unit 200 in the transferring or thinning process of the CMOS substrate 21 can be reduced or even avoided.

The carrier sheet 600 may be made of glass, sapphire or a semiconductor material, but is not limited thereto.

The step of attaching the carrier sheet 600 to the outer side of the memory array device 10 of the second memory cell 200 further includes the following steps:

first, any one of a heat curing adhesive, an ultraviolet light irradiation curing adhesive, a heat decomposition adhesive, or a laser decomposition adhesive is applied to one side of the carrier sheet 600 facing the second memory cell 200 and/or the outer side of the memory array device 10 of the second memory cell 200. Preferably, a side of the carrier sheet 600 facing the second memory cell 200 and an outer side of the memory array device 10 of the second memory cell 200 are coated with a bonding paste to enhance adhesion between the carrier sheet 600 and the outer side of the memory array device 10 of the second memory cell 200.

Then, the carrier sheet 600 is bonded to the outer side of the memory array device 10 of the second memory cell 200 through a temporary bonding process or a permanent bonding process. The temporary bonding process refers to a process means that the carrier sheet 600 is bonded to the outer side of the memory array device 10 of the second memory unit 200, and the carrier sheet 600 can be easily removed from the outer side of the memory array device 10 when needed, so that the removal of the carrier sheet 600 is easy; the permanent bonding process refers to a process method for bonding the carrier sheet 600 to the outer side of the memory array device 10 of the second memory cell 200, but the carrier sheet 600 needs to be removed from the outer side of the memory array device 10 by adding a larger outer side, so that the bonding connection between the carrier sheet 600 and the memory array device 10 of the second memory cell 200 is firmer.

It is understood that in some embodiments of the present invention, the outer side of the memory array device 10 of the second memory unit 200 is covered with the first bonding layer 42, and thus, the carrier sheet 600 is bonded to the outer side of the first bonding layer 42.

Step S3, forming a second set of contacts on a side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell, wherein the second set of contacts are electrically connected to the CMOS device of the second memory cell.

Referring to fig. 10 and 11, in some embodiments of the invention, the step S3 of the method for manufacturing a three-dimensional memory device includes the following steps:

forming a via (i.e., the aforementioned second vertical via) through the CMOS substrate 21 of the second memory cell 200 on the CMOS substrate 21, the via exposing at least a portion of the interconnect via 30 (i.e., at least a portion of the aforementioned second interconnect sub-via 32) of the second memory cell 200;

filling the via with a conductive medium to form a conductive via (i.e., the aforementioned second conductive via 60), which is electrically connected to the interconnect via 30 of the second memory cell 200;

a second set of contacts 50 of the second memory cell 200 are formed from the end of the conductive via remote from the interconnect via 30 of the second memory cell 200 (i.e., the end of the second conductive via 60 remote from the second interconnect sub-via 32) such that the second set of contacts 50 are electrically connected to the interconnect via 30 of the second memory cell 200 through the conductive via.

As shown in fig. 10 and 11, before forming the second group of contacts 50, the outer side (i.e., the side facing away from the CMOS circuit) surface of the CMOS substrate 21 of the second memory cell 200 is covered with the second bonding layer 52, and then a second conductive via 60 penetrating through the CMOS substrate 21 and electrically connected to the second interconnection sub-via 32 may be formed by a common technical means, wherein an end of the second conductive via 60 away from the second interconnection sub-via 32 and the second group of contacts 50 are embedded in the second bonding layer 52, and the second group of contacts 50 are electrically connected to the CMOS circuit of the CMOS device 20 through the second conductive via 60 and are electrically connected to the second interconnection sub-via 32 of the interconnection via 30. Similarly, the specific features, functions, or forming processes of the second bonding layer 52 and the second conductive via 60 can be found in the three-dimensional memory device described above, and are not described herein again.

After forming the second set of contacts 50 on the outer side of the CMOS device 20 of the second memory cell 200 (i.e., the side facing away from the memory array device 10, i.e., the outer side of the CMOS substrate), the method for fabricating the three-dimensional memory device further includes step S4: and stacking the second storage unit on the side, facing away from the CMOS device of the first storage unit, of the storage array device of the first storage unit, and jointing the storage array device of the first storage unit with the CMOS device of the second storage unit, so that the first group of contacts of the first storage unit are correspondingly and electrically connected with the second group of contacts of the second storage unit.

Specifically, referring to fig. 12, after the carrier sheet 600 is bonded to the outer side of the memory array device 10 of the second memory cell 200, the second memory cell 200 is turned over, so that the CMOS device 20 of the second memory cell 200 faces the memory array device 10 of the first memory cell 100, and then the CMOS device 20 of the second memory cell 200 and the memory array device 10 of the first memory cell 100 are bonded face to face, so that the first set of contacts 40 of the first memory cell 100 are correspondingly electrically connected to the second set of contacts 50 of the second memory cell 200, and further, the first memory cell 100 and the second memory cell 200 are electrically connected through the corresponding first set of contacts 40, the second set of contacts 50, and the respective interconnect channels 30 of each memory cell. At this time, the first bonding layer 42 of the first memory cell 100 is bonded to the second bonding layer 52 of the second memory cell 200.

Referring to fig. 13, in some embodiments of the invention, when the carrier sheet 600 is bonded to the outer side of the memory array device 10 of the second memory cell 200, after the second memory cell 200 is stacked on the first memory cell 100 and the CMOS device 20 of the second memory cell 200 is bonded to the memory array device 10 of the first memory cell 100, the method for manufacturing the three-dimensional memory device further includes: the carrier sheet 600 is removed to expose the first set of contacts 40 of the second memory cell 200.

Further, referring to fig. 1, in some embodiments of the present invention, after bonding the CMOS device 20 of the second memory cell 200 to the memory array device 10 of the first memory cell 100 and exposing the first set of contacts 40 of the second memory cell 200, the method for manufacturing a three-dimensional memory device further includes the following steps:

forming an isolation layer 300 on a side of the memory array device 10 of the outer layer second memory cell 200, which is away from the CMOS device 20 of the outer layer second memory cell 200, wherein the isolation layer 300 covers the side of the memory array device 10 of the outer layer second memory cell 200, which is away from the CMOS device 20 of the outer layer second memory cell 200, and the first group of contacts 40 of the outer layer second memory cell 200, wherein the outer layer second memory cell 200 is the second memory cell 200 stacked on the first memory cell 100 and farthest from the first memory cell 100 along the stacking direction;

arranging an array pad 400 in the isolation layer 300, and correspondingly and electrically connecting the array pad 400 with the first group of contacts 40 of the outer second memory cell 200;

a protective layer 500 having an opening is formed on a side of the isolation layer 300 facing away from the outer second memory cell 200, such that the protective layer 500 covers the isolation layer 300 and the opening exposes the array pad 400.

The isolation layer 300 covers a side of the first bonding layer 42 of the outer layer second storage unit 200 away from the array substrate 11, the exposed array pad 400 is used for connecting an external device (e.g., a control device or a driving circuit), the protective layer 500 is used for protecting the isolation layer 300 from being damaged to ensure connection reliability of the array pad 400, and specific features, functions, or forming processes of the isolation layer 300, the array pad 400, and the protective layer 500 may refer to corresponding contents in the three-dimensional memory device, which is not described herein again.

Through the above steps, in some embodiments of the present invention, the first memory cell 100 and the second memory cell 200 may be stacked to form the three-dimensional memory device 1000 with a higher storage density (as shown in fig. 1), so that it is not necessary to stack too many memory layers 13 in the memory array device 10 of each memory cell, and the area of the array substrate 11 of each memory cell is not too large, which is beneficial to disposing the array substrate 11 and the CMOS substrate 21 of each memory cell with a proper area ratio, and thus, the unused space in each memory cell can be reduced, and the space utilization rate of the three-dimensional memory device can be improved.

Preferably, in the three-dimensional memory device 1000, each of the memory array devices 10 of the first memory unit 100 and the second memory unit 200 includes a predetermined number of memory layers 13, which is an integer greater than 0 and less than 500, such as 32, 64, 96, or 128 layers. The number of the memory layers 13 in the memory array device 10 of each of the first memory unit 100 and the second memory unit 200 may be the same or different, preferably the same, so as to facilitate mass production of the first memory unit 100 and the second memory unit 200 in the same process step.

Referring to fig. 2, in other embodiments of the present invention, the number of the second memory cells 200 may be set to be a plurality, and the method for manufacturing the three-dimensional memory device includes the following steps:

stacking one of the second memory cells 200 on a side of the memory array device 10 of the first memory cell 100 facing away from the CMOS device 20 of the first memory cell 100, and bonding the CMOS device 20 of the one of the second memory cells 200 with the memory array device 10 of the first memory cell 100, such that the second set of contacts 50 of the one of the second memory cells 200 is electrically connected with the first set of contacts 40 of the first memory cell 100 correspondingly;

stacking another second memory cell 200 on the side of the memory array device 10 of the outer second memory cell 200, which is away from the CMOS device 20 of the outer second memory cell 200, bonding the CMOS device 20 of the another second memory cell 200 with the memory array device 10 of the outer second memory cell 200, electrically connecting the first set of contacts 40 of the outer second memory cell 200 with the second set of contacts 50 of the another second memory cell 200 correspondingly, and repeating the step until a plurality of second memory cells 200 are sequentially stacked on the first memory cell 100, wherein the outer second memory cell 200 is the second memory cell 200 stacked on the first memory cell 100 and farthest away from the first memory cell 100 in the stacking direction.

It should be noted that, in order to avoid the deformation of the second memory cells 200, the carrier sheet 600 is preferably bonded to the side of the memory array device 10 of each second memory cell 200 away from the CMOS device 20, and therefore, before each second memory cell 200 is bonded to another memory cell (the first memory cell 100 or another second memory cell 200), a step of removing the carrier sheet 600 is required. The carrier sheet 600 bonded to one side of the memory array device 10 of the second memory cells 200 may be the same carrier sheet 600, that is, after the carrier sheet 600 is removed from the memory array device 10 of one second memory cell 200, the carrier sheet 600 is bonded to the outer side of the memory array device 10 of the next second memory cell 200 to be stacked, and the number of the carrier sheets 600 can be reduced by repeatedly using the carrier sheet 600, thereby reducing the cost. Of course, the outer side of the memory array device 10 of each second memory cell 200 may be bonded with a different carrier sheet 600.

Through the above steps, in other embodiments of the present invention, the first memory cell 100 and the plurality of second memory cells 200 may be sequentially stacked to form the three-dimensional memory device 1000b (as shown in fig. 2), and compared to the three-dimensional memory device 1000, the number of memory cells of the three-dimensional memory device 1000b is greater, so that the storage density of the three-dimensional memory device 1000b is higher, and it is not necessary to stack too many memory layers 13 in the memory array device 10 of each memory cell of the three-dimensional memory device 1000b, thereby improving the space utilization of the three-dimensional memory device 1000 b.

Preferably, in the manufacturing process of the three-dimensional memory device, the method for bonding the memory array device 10 of the first memory cell 100 and the CMOS device 20 thereof, the bonding the memory array device 10 of the second memory cell 200 and the CMOS device 20 thereof, the bonding the memory array device 10 of the first memory cell 100 and the CMOS device 20 of the second memory cell 200, and the bonding the memory array device 10 of the second memory cell 200 and the CMOS device 20 of the other second memory cell 200 includes an Xtacking bonding process. The Xtacking bonding process is to realize the para-bonding of bonding structures between different devices in the same process step, so as to realize the electrical connection of the two devices. By using the XBacking bonding process, the memory array device and the CMOS device can be manufactured respectively by selecting more advanced manufacturing processes, and the complexity of the manufacturing process is reduced, so that the three-dimensional memory device can obtain higher I/O transmission speed, higher density and smaller volume.

Furthermore, the present invention further provides a three-dimensional memory, where the three-dimensional memory includes any one of the three-dimensional memory devices described above, and the three-dimensional memory has the advantages of high storage density and high space utilization rate of the three-dimensional memory device, and also has other structural features and functions of the three-dimensional memory device, which are not described herein again.

While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

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Three-dimensional memory device, method of manufacturing the same, and three-dimensional memory

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