阅读说明：本技术 4h-sic mosfet器件及其制造方法 (4H-SIC MOSFET device and manufacturing method thereof ) 是由 M·G·萨吉奥 E·扎内蒂 A·瓜尔内拉 于 2020-11-16 设计创作，主要内容包括：本公开的各实施例涉及4H-SIC MOSFET器件及其制造方法。MOSFET器件包括具有第一面和第二面的半导体主体。MOSFET器件的源极端子包括掺杂区域和金属层,掺杂区域在半导体主体的第一面处延伸,并且金属层电耦合到该掺杂区域的金属层。漏极端子在半导体主体的第二面处延伸。掺杂区域包括第一子区域和第二子区域,第一子区域具有第一掺杂水平和第一深度,并且第二子区域具有第二掺杂水平和第二深度的第二子区域。第二掺杂水平和第二最大深度中间的至少一项具有比第一掺杂水平和第一最大深度的相应值高的值。金属层唯一地通过第二子区域与源极端子电接触。(Embodiments of the present disclosure relate to 4H-SIC MOSFET devices and methods of making the same. The MOSFET device includes a semiconductor body having a first side and a second side. The source terminal of the MOSFET device includes a doped region extending at the first face of the semiconductor body and a metal layer electrically coupled to the metal layer of the doped region. The drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth and a second sub-region having a second doping level and a second depth. At least one of the second doping level and the second maximum depth has a higher value than the corresponding value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second subregion.)

1. A MOSFET device, comprising:

a semiconductor body having a first face and a second face opposing each other along a direction;

a source terminal comprising a doped region extending at the first face of the semiconductor body and a metal layer electrically coupled to the doped region; and

a drain terminal extending at the second face of the semiconductor body,

wherein the doped region comprises a first subregion having a first doping concentration and a first maximum depth in the semiconductor body and a second subregion having a second doping concentration and a second maximum depth in the semiconductor body, and

wherein at least one of the second doping concentration and the second maximum depth has a respective value that is higher than the values of the first doping concentration and the first maximum depth, respectively,

the metal layer is in electrical contact with the source terminal solely through the second sub-region, the metal layer being in direct physical contact with the source terminal only at the second sub-region of the source terminal.

2. The MOSFET device of claim 1, wherein:

the first doping concentration is 1-10¹⁸Atom/cm³-1·10²⁰Atom/cm³Has a value in the range of 1 · 10, the second doping concentration being higher than the first doping concentration¹⁹Atom/cm³-1·10²⁰Atom/cm³Has a value in the range of 0.2-0.4 μm and the second maximum depth has a value in the range of 0.6-0.7 μm.

3. The MOSFET device of claim 1, wherein:

the first doping concentration is 1-10¹⁸Atom/cm³-2·10¹⁹Atom/cm³Has a value in the range of 1 · 10, the second doping concentration being higher than the first doping concentration¹⁹Atom/cm³-1·10²⁰Atom/cm³And in the range of 0.2 μm-0.4 μm, the first maximum depth is equal to the second maximum depth.

4. The MOSFET device of claim 1, wherein:

the first doping concentration is 1-10¹⁹Atom/cm³-1·10²⁰Atom/cm³A value within the range ofThe second doping concentration is equal to the first doping concentration, the first maximum depth has a value in the range of 0.1-0.2 μm, and the second maximum depth is higher than the first maximum depth and has a value in the range of 0.2-0.4 μm.

5. The MOSFET device of claim 1, wherein:

the first doping concentration is 1-10¹⁸Atom/cm³-2·10¹⁹Atom/cm³Has a value in the range of 1 · 10, the second doping concentration being higher than the first doping concentration¹⁹Atom/cm³-1·10²⁰Atom/cm³Has a value in the range of 0.1-0.4 μm and the second maximum depth has a value in the range of 0.2-0.4 μm.

6. The MOSFET device of claim 1, wherein:

the first doping concentration is 1-10¹⁸Atom/cm³-2·10¹⁹Atom/cm³Has a value in the range of 1 · 10, the second doping concentration being higher than the first doping concentration¹⁹Atom/cm³-1·10²⁰Atom/cm³Has a value in the range of 0.1-0.4 μm and the second maximum depth has a value in the range of 0.6-0.7 μm.

7. The MOSFET device of claim 1, wherein the first and second sub-regions are in direct electrical contact with each other.

8. The MOSFET device of claim 1, further comprising a gate structure on the first side of the semiconductor body, the gate structure comprising:

a gate dielectric layer;

a metal gate layer on the gate dielectric layer; and

an insulating layer at least partially surrounding the metal gate layer, the first sub-region extending completely under the gate structure.

9. The MOSFET device of claim 1, wherein the semiconductor body is 4H-SiC.

10. A method for fabricating a MOSFET device, comprising:

forming a source terminal comprising:

implanting a doped region at a first face of the semiconductor body, and

a metal layer formed on the first side of the semiconductor body and electrically coupled to the doped region; and

forming a drain terminal at a second face of the semiconductor body opposite the first face in a direction,

wherein implanting the doped region comprises forming a first sub-region having a first doping concentration and a first maximum depth in the semiconductor body and forming a second sub-region having a second doping concentration and a second maximum depth in the semiconductor body,

wherein at least one of the second doping level and the second maximum depth has a higher value than the respective values of the first doping level and the first maximum depth, and

forming the metal layer includes forming the metal layer in electrical contact with the source terminal solely through the second sub-region, the metal layer in direct physical contact with the source terminal only at the second sub-region of the source terminal.

11. The method of claim 10, wherein:

the first doping concentration is 1-10¹⁸Atom/cm³-1·10²⁰Atom/cm³A second doping concentration higher than the first doping concentration,and has a molecular weight in the range of 1.10¹⁹Atom/cm³-1·10²⁰Atom/cm³Has a value in the range of 0.2-0.4 μm and the second maximum depth has a value in the range of 0.6-0.7 μm.

12. The method of claim 10, wherein:

the first doping concentration is 1-10¹⁸Atom/cm³-2·10¹⁹Atom/cm³Has a value in the range of 1 · 10, the second doping concentration being higher than the first doping concentration¹⁹Atom/cm³-1·10²⁰Atom/cm³And in the range of 0.2 μm-0.4 μm, the first maximum depth is equal to the second maximum depth.

13. The method of claim 10, wherein:

the first doping concentration is 1-10¹⁹Atom/cm³-1·10²⁰Atom/cm³The second doping concentration being equal to the first doping concentration, the first maximum depth having a value in the range of 0.1-0.2 μm, and the second maximum depth being higher than the first maximum depth and having a value in the range of 0.2-0.4 μm.

14. The method of claim 10, wherein:

the first doping concentration is 1-10¹⁸Atom/cm³-2·10¹⁹Atom/cm³Has a value in the range of 1 · 10, the second doping concentration being higher than the first doping concentration¹⁹Atom/cm³-1·10²⁰Atom/cm³Has a value in the range of 0.1-0.4 μm and the second maximum depth has a value in the range of 0.2-0.4 μm.

15. The method of claim 10, wherein:

the first doping concentration is 1-10¹⁸Atom/cm³-2·10¹⁹Atom/cm³Has a value in the range of 1 · 10, the second doping concentration being higher than the first doping concentration¹⁹Atom/cm³-1·10²⁰Atom/cm³Has a value in the range of 0.1-0.4 μm and the second maximum depth has a value in the range of 0.6-0.7 μm.

16. The method of claim 10, wherein forming the first sub-region comprises: a first implantation of a dopant species having a first conductivity type is performed at a first implantation energy, and

wherein forming the second sub-region comprises: the first implantation is performed and then a second implantation of a dopant species having the first conductivity type is performed at a second implantation energy higher than the first implantation energy.

17. The method of claim 10, wherein the first and second sub-regions are formed in direct electrical contact with each other.

18. The method of claim 10, further comprising forming a gate structure on the first side of the semiconductor body, the forming the gate structure comprising:

forming a gate dielectric layer;

forming a metal gate layer on the gate dielectric layer; and

and completely surrounding the upper surface and the side surface of the metal gate layer by an insulating layer, wherein the gate structure completely covers the first subregion.

19. The method of claim 6, wherein the semiconductor body is 4H-SiC.

20. An apparatus, comprising:

a semiconductor body having a first surface;

a source terminal comprising a doped region extending from the first surface into the semiconductor body and a metal layer electrically coupled to the doped region, the doped region comprising:

a first sub-region having a first doping concentration and a first maximum depth in the semiconductor body, an

A second sub-region having a second doping concentration and a second maximum depth in the semiconductor body, the first sub-region extending laterally outward from opposite sides of the second sub-region;

a drain terminal extending at a second face of the semiconductor body; and

an insulating layer on the first subregion of the doped region,

wherein at least one of the second doping concentration and the second maximum depth has a respective value that is higher than the values of the first doping concentration and the first maximum depth, respectively, and

the metal layer extends from a first side edge of the insulating layer to a second side edge of the insulating layer in direct contact with the second subregion of the doped region.

Technical Field

The invention relates to a MOSFET device and a method of manufacturing the same.

Background

Fig. 1 shows the basic structure of a vertical MOSFET device 1 in a side view and a three-axis reference system of orthogonal axes X, Y, Z. In a conventional embodiment, the MOSFET device 1 comprises a plurality of these basic structures, which work together, sharing the same drain terminal (D), wherein all gate terminals (G) are connected together by a deposited polysilicon net (not shown), and all of the source terminals (S) are electrically connected and linked by an upper metal layer 10.

As shown in fig. 1, the MOSFET device 1 comprises a semiconductor body 2 (which comprises a substrate and optionally one or more epitaxial layers) of semiconductor material having an upper surface 2a and a lower surface 2 b. The semiconductor body 2 is for example N-doped. At the lower surface 2b, a drain region 4 is formed, for example by implantation of N-type (N + doped) dopant species. At the upper surface 2a, a body region 5 (P-doped) surrounds a source region 8(N + -doped). A gate structure 6 comprising a stack of a gate conductive layer 6a and a gate dielectric layer 6b extends over the upper surface 2a, partly overlapping the source region 8. A corresponding spacer 9 covers the gate structure 6.

The upper metal layer 10 is in electrical contact with the source region 8 and the body region 5 at the surface layer portions 16 and 17, respectively, in order to bias the source region 8 and the body region 5 at the same bias voltage during use.

In order to improve electrical contact between the upper metal layer 10 and the body region 5, P-well regions (P + doping) 14 are formed in some of the body regions 5, and face the upper surface 2a in regions corresponding to the surface layer portions 17. Typically, a silicide interface layer (not shown) is formed at the surface layer portion 17 to form an ohmic contact between the metal 10 and the implanted P-well region 14. The P-well region 14 is formed only at the position where the metal layer 10 is designed to be the contact region 5. In the respective body regions 5, P-well regions 14 are arranged between the source regions 8.

Wherein by design it has been decided to form a contact between the upper metal layer 10 and the source region 8, i.e. at the surface layer region 16, the respective source region 8 extending continuously within the body region 5 accommodating it, facing the upper surface 2a in correspondence with the surface layer region 16. Further layers may be formed in a manner known per se and not shown to enhance the electrical contact between the metal 10 and the source electrode 8.

During the on-state of the MOSFET device 1, when the gate-source voltage V is applied_DSAbove the threshold value, the conduction current is located in the drain region 4 and in the region of the semiconductor body 2 (channel 18) below the gate structure 6. During the off-state of the MOSFET device 1, the voltage drop across the drain D and the source S is maintained by the PN junction being in reverse bias, and very little current (leakage) flows through the PN junction. If the voltage increases too much and the electric field reaches a critical value, the PN junction will break down and current starts to flow through the body region 5. If an overvoltage is applied to the PN junction, current flows through the PN junction and the MOSFET device 1 limits the actual drain-source Breakdown Voltage (BV)_DS). The breakdown mechanism itself is not destructive to the PN junction. However, unless sufficient heat dissipation is provided, overheating due to high breakdown current and voltage can damage the PN junction.

Considering the structure of the MOSFET in more detail, it can be seen that the PN junction is not a "perfect diode". The diode is the collector-base junction of a Bipolar Junction Transistor (BJT), also known as a parasitic transistor, which is made up of an N + source 8, a P/P + body 5 and an N + drain 4, with the base shorted to the emitter by a metal layer 10. The ability of the MOSFET to withstand avalanche conditions takes these issues into account.

Generally, the avalanche capability of a device is evaluated by using a circuit that performs a non-clamped inductive switching (UIS) operation. During testing, two kinds of failures occur: one related to current and the other related to power consumption. In the former, the fault is caused by the latching of the parasitic bipolar resulting from the current flowing through its base resistance multiplied by the gain. The second case is reached when the junction temperature rises to a critical value that causes the formation of hot spots by regenerative thermal runaway, with an average temperature of about 650 ℃ peaking at about 1000 ℃, which in turn triggers extremely fast device destruction.

It is known that the semiconductor device has a wide forbidden band width (particularly, an energy value Eg having a forbidden band width of more than 1.1 eV), an on-resistance (R)_ON) Semiconductor materials that are low, have high thermal conductivity values, high operating frequencies, and high velocity saturation of charge carriers are ideal for producing electronic components such as diodes or transistors, particularly for power applications. One material having the above properties and designed for use in the manufacture of electronic components is silicon carbide (SiC). In particular, silicon carbide in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC) is preferred over silicon for the properties listed previously.

Electronic devices provided on silicon carbide substrates exhibit many advantageous characteristics, such as low output resistance in conduction, low leakage current, high operating temperature, and high operating frequency, compared to similar devices provided on silicon substrates.

However, the above problems cannot be completely overcome by the use of SiC and, in order to improve the avalanche capability of MOSFET devices, the usual solutions foresee edge structures with much higher breakdown threshold with respect to the active region. However, this goal is not always feasible due to efficiency limitations at the edges of the device.

Furthermore, since the source resistance depends on the doping value of the source region 8, the resistance in the on-state is also affected.

Disclosure of Invention

In various embodiments, the present disclosure provides MOSFET devices and methods of fabricating the same that overcome the disadvantages of the prior art.

According to the present disclosure, a MOSFET device and a method of manufacturing the same are provided.

In at least one embodiment, the present disclosure provides a MOSFET device that includes a semiconductor body having a first face and a second face opposite one another along a direction. The source terminal includes a doped region extending at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. The drain terminal extends at the second face of the semiconductor body. The doped region comprises a first subregion having a first doping concentration and a first maximum depth in the semiconductor body and a second subregion having a second doping concentration and a second maximum depth in the semiconductor body. At least one of the second doping concentration and the second maximum depth has a respective value that is higher than the value of the first doping concentration and the first maximum depth, respectively. The metal layer is in electrical contact with the source terminal solely through the second sub-region, and the metal layer is in direct physical contact with the source terminal only at the second sub-region of the source terminal.

In at least one embodiment, the present disclosure provides a method for fabricating a MOSFET device, the method comprising forming a source terminal. Forming the source terminal includes: implanting a doped region at the first face of the semiconductor body, and forming a metal layer on the first face of the semiconductor body and electrically coupled to the doped region. The method further includes forming a drain terminal along a direction at a second face of the semiconductor body opposite the first face. Implanting the doped region includes forming a first sub-region having a first doping concentration and a first maximum depth in the semiconductor body and a second sub-region having a second doping concentration and a second maximum depth in the semiconductor body. At least one of the second doping level and the second maximum depth has a higher value than the respective values of the first doping level and the first maximum depth. Forming the metal layer includes forming the metal layer in electrical contact with the source terminal solely through the second sub-region, the metal layer in direct physical contact with the source terminal only at the second sub-region of the source terminal.

In at least one embodiment, the present disclosure provides a device comprising: a semiconductor body having a first surface; and a source terminal comprising a doped region extending from the first surface into the semiconductor body and a metal layer electrically coupled to the doped region. The doped region includes: a first sub-region having a first doping concentration and a first maximum depth in the semiconductor body; and a second subregion having a second doping concentration and a second maximum depth in the semiconductor body. The first sub-region extends laterally outward from opposite sides of the second sub-region. The drain terminal extends at the second face of the semiconductor body, and the insulating layer is arranged on the first subregion of the doped region. At least one of the second doping concentration and the second maximum depth has a respective value that is higher than the value of the first doping concentration and the first maximum depth, respectively. The metal layer extends from the first side edge of the insulating layer to the second side edge of the insulating layer in direct contact with the second subregion of the doped region.

Drawings

For a better understanding of the present disclosure, preferred embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

fig. 1 shows a MOSFET device of known type;

fig. 2 illustrates a MOSFET device according to one embodiment of the present disclosure;

fig. 3A-3C show process steps for fabricating the MOSFET device of fig. 2; and

fig. 4 shows a MOSFET device according to further embodiments of the present disclosure.

Detailed Description

Fig. 2 shows a MOSFET device 100 according to one embodiment of the present disclosure.

Fig. 2 is a cross-sectional view in the tri-axial reference system of orthogonal axis X, Y, Z of fig. 1.

As already discussed with reference to fig. 1, the MOSFET structure shown in fig. 2 may be an infrastructure or "cell", which may be used to develop the actual MOSFET device 100 by replicating the infrastructure a desired number of times; this infrastructure works together, sharing a common drain terminal (D), a common gate terminal (G) and a common source terminal (S).

It will be apparent to those skilled in the art that when the structure of fig. 2 is replicated, minimal changes may be introduced in the base structure, for example, to comply with one or more of design requirements, area footprints, electrical requirements, manufacturing requirements, and the like.

As shown in fig. 2, MOSFET device 100 includes a semiconductor body 102 of semiconductor material (which includes a substrate and, optionally, one or more epitaxial layers) having an upper surface 102a and a lower surface 102b opposite each other along the Z-axis.

In particular, the semiconductor body 102 is made of silicon carbide (SiC), more particularly 4H-SiC. In one embodiment, the semiconductor body 102 is N-doped.

Facing lower surface 102b is a drain region 104 formed, for example, by implanted N-type dopant species (N + doping). A body region 105 (P-doped) is arranged at the upper surface 102 a; in particular, the body region 105 faces the upper surface 102 a.

A source region 108(N + doped) is formed by implantation in the body region 105 in the semiconductor body 102, facing the upper surface 102 a. Thus, the body regions 105 surround the respective source regions 108 formed therein.

The gate structure 106 extends on the upper surface 102a and includes a stack formed of a gate conductive layer 106a (e.g., of a metallic material) and a gate dielectric layer 106b (of an insulating or dielectric material). A respective isolation layer 109 covers each gate structure 106 to electrically isolate the gate structure 106 from the metal layer 110. The gate structure 106 partially overlaps the source region 8; in a manner known per se, during use, a respective channel region 118 is formed in a region of the semiconductor body 102 below the gate structure 106 (between the body region 105/the source region 108). The current path is shown in dashed lines in fig. 2 and flows from the source region 108 to the drain region 104 (vertical conduction).

The active area of the MOSFET device 100 is the area where current conduction occurs, in particular the area where the channel is formed. Typically, not shown and known per se, the active region is completely or partially surrounded by an edge termination region. The edge termination region is for example an implanted region having a P conductivity type.

In a manner not shown in detail and known to the person skilled in the art, all gate structures 106 are electrically connected together (e.g. by a deposited polysilicon net) and all source regions 108 are electrically connected together and/or to each other within the semiconductor body 102.

Upper metal layer 110 is in electrical contact with source region 108 and body region 105 at respective select regions to bias source region 108 and body region 105 at the same bias voltage during use.

To improve the electrical contact between the upper metal layer 110 and the body regions 105, P-well regions (P + doping) 114 are formed at the upper surface 2a in one or more of the body regions 105, and corresponding electrical contact interfaces 117 are formed. Typically, each electrical contact interface 117 also includes a silicide interface layer (not shown) to form an ohmic contact between upper metal layer 110 and the corresponding P-well region 114. A P-well region 114 is formed where the metal layer 110 reaches the upper surface 102a to contact the body region 105. P-well region 114 is disposed between source regions 108 extending in the same body region 105.

According to one aspect of the present disclosure, an electrical contact interface 116 is defined between the upper metal layer 110 and a region of the semiconductor body in which, by design, it has been determined that a contact between the upper metal layer 110 and the source region 108 is formed.

The electrical contact between the source regions 108 and the upper metal layer 110 is ensured by an intermediate electrical contact region 120, the intermediate electrical contact region 120 being in direct electrical contact with at least one source region 108 on one side and with the upper metal layer 110 on the other side (in any case one or more interfacial layers for improving the ohmic contact may be formed between the intermediate electrical contact region 120 and the upper metal layer 110). In other words, the electrical contact between the upper metal layer 110 and the source region 108 is exclusively made through (or by means of) the intermediate electrical contact region 120.

In one embodiment, the intermediate electrical contact region 120 is an implanted region of N-type having a higher doping level (or dose) than the doping level (or dose) of the source region 108. Furthermore, the intermediate electrical contact region 120 extends into the semiconductor body 102 to a depth D_I(measured from the upper surface 102a along the Z-axis) is greater than the depth D reached by the source region 108_S(measured from the upper surface 102a along the Z-axis).

Thus, the intermediate electrical contact region 120 is in direct lateral electrical contact with the source region 108 extending within the same body region 105 (i.e., along the X-axis, the intermediate electrical contact region 120 is in direct electrical contact with the source region 108). More specifically, the intermediate electrical contact region 120 and the source region 108 extending within the same body region 105 are electrically continuous.

In accordance with the present disclosure, the doping level (i.e., doping concentration) of the intermediate electrical contact region 120 is higher than the doping level (i.e., doping concentration) of the source region 108.

In one embodiment, the doping level of the intermediate electrical contact region 120 is 1 · 10¹⁹Atom/cm³-1·10²⁰Atom/cm³And the doping level of the source region 108 is in the range of 1 · 10¹⁸Atom/cm³-1·10²⁰Atom/cm³Within the range of (1). The actual values are selected within the specified range and do not overlap. Furthermore, in this embodiment, the depth D of the intermediate electrical contact region 120_IA depth D higher than the source region 108_S. For example, the depth D of the source region 108_SIn the range of 0.2 μm to 0.4 μm, and a depth D of the intermediate electrical contact region 120_IIn the range of 0.6 μm to 0.7. mu.m. According to this embodiment, the punch-through of the junction n-/p/n + (the element with reference 102/105/120 in the figure) results in a uniform avalanche condition in the active region (under UIS test and in static conditions).

In another embodiment, 1 · 10¹⁹Atom/cm³-1·10²⁰Atom/cm³In the range of (a), the doping levels of the intermediate electrical contact region 120 and the source region 108 are the same or approximately the same. Furthermore, in this embodiment, the depth D of the intermediate electrical contact region 120_IA depth D higher than the source region 108_S. For example, the depth D of the source region 108_SIn the range of 0.1 μm to 0.2 μm, and a depth D of the intermediate electrical contact region 120_IAbove 0.2 μm (e.g., in the range of 0.2 μm and 0.4 μm). The actual values are selected in such a way that they do not overlap. This embodiment has been found to increase robustness during short circuit testing. In effect, this configuration allows the saturation current of the MOSFET device 120 to be modulated with minimal impact on the output resistance of the MOSFET device 120.

In yet another embodiment, the doping level of the intermediate electrical contact region 120 is 1 · 10¹⁹Atom/cm³-1·10²⁰Atom/cm³And the doping level of the source region 108 is in the range of 1 · 10¹⁸Atom/cm³-2·10¹⁹Atom/cm³In the range of (generally, the doping level of region 108 is 1% to 20% of the doping level of region 120). The actual values are selected within the specified range and do not overlap. Furthermore, in this embodiment, the depth D of the intermediate electrical contact region 120_IIn the range of 0.2 μm to 0.4 μm, and the depth D of the source region 108_SIn the range of 0.1 μm to 0.4 μm (in general, D_SIs D_I25% to 100%). This embodiment has been found to increase robustness during short circuit testing. In practice, this structure allows the saturation current of the MOSFET device 120 to be modulated without undesirably affecting the output resistance of the MOSFET device 120.

In yet another embodiment, the doping level of the intermediate electrical contact region 120 is 1 · 10¹⁹Atom/cm³-1·10²⁰Atom/cm³And the doping level of the source region 108 is in the range of 1 · 10¹⁸Atom/cm³-2·10¹⁹Atom/cm³In the range of (generally, the doping level of region 108 is 1% to 20% of the doping level of region 120). The actual values are selected within the specified range and do not overlap. Furthermore, in this embodiment, the depth D of the intermediate electrical contact region 120_IIn the range of 0.6 μm to 0.7 μm, and the depth D of the source region 108_SIn the range of 0.1 μm to 0.4 μm (in general, D_SIs D_I15% to 60%). According to this embodiment, the punch-through of the junction n-/p/n + (the element with reference 102/105/120 in the figure) results in a uniform avalanche state (under UIS test) in the active region. Furthermore, this embodiment was also found to increase robustness during short circuit testing.

It should be noted that in any case the depth of the intermediate electrical contact region 120 is lower than the depth of the body region 105 in which the intermediate electrical contact region 120 is contained. In other words, the intermediate electrical contact region 120 is surrounded by the body region 105 in which it is accommodated.

The use of a region 120 that is deeper and has a higher doping level than the source 108 solves the problems of the prior art for the following reasons. At a given voltage (fixed by physical parameters such as body doping level, thickness of substrate/epitaxial layer 102, and depth difference between region 120 and body 105), the electric field during use can cause punch-through of junction n-/p/n + (the element with reference 102/105/120 in the figure) resulting in a uniform avalanche state in the active region. This voltage is lower than the breakdown voltage BV that the body-drain junction can withstand according to design. As such, Unclamped Inductive Switching (UIS) operation involves the entire active region. As the area involved in the breakdown voltage BV phenomenon (e.g., the entire active area) increases, the MOSFET device 100 is more robust under UIS operation, thereby helping to reduce the current density at the breakdown voltage BV.

The breakdown mechanism for embodiments where intermediate electrical contact region 120 is deeper than source region 108 is different than if intermediate electrical contact region 120 and source region 108 were at the same depth. More particularly, with the intermediate electrical contact region 120 at the same depth as the source region 108, the electric field reaches a critical value at the corners of the body-drain junction, leading to hole generation by impact ionization phenomena. The induced current is dominated by holes. In contrast, in embodiments where the intermediate electrical contact region 120 is deeper than the source region 108, the electric field is below a critical value. Thus, the breakdown mechanism is dominated by punch-through, resulting in electron current flowing from the drain to the source.

As such, embodiments of the present disclosure (where the intermediate electrical contact region 120 is deeper than the source region 108) facilitate control of the breakdown voltage BV in the active region of the MOSFET device 100, for example, by optimizing residual body charge and moving the breakdown voltage BV phenomenon from impact ionization to punch-through. The breakdown voltage BV is for example moved from the edge termination to each elementary cell of the active area, which provides a higher robustness of the MOSFET device 100 at UIS. With regard to the manufacturing process of the intermediate electrical contact region 120, reference is made to fig. 3A-3C, which illustrate a portion of a semiconductor wafer, limited to features of the semiconductor wafer that are useful for understanding the present disclosure. Elements that are common to those already described with reference to fig. 2 are indicated with the same reference numerals and will not be described further.

Referring to fig. 3A, after body region 105 is formed by implantation of P-dopant species, a first blanket implant of N-type species (e.g., antimony, arsenic, or phosphorous) is performed to form first implant regions 121 within body region 105. The first implantation is performed with an implantation energy in the range of 20keV-200keV (shown by the arrows in fig. 3A). The mask 123 for this implantation is only schematically depicted in fig. 3A and leaves exposed surface layer portions of the semiconductor body 102 corresponding to the regions where the source regions 108 and the intermediate electrical contact regions 120 are to be formed.

Then, in fig. 3B, a second masked implant of an N-type species (e.g., antimony, arsenic or phosphorous) is performed to form a second implant region 122 within body region(s) 105 designed to receive intermediate electrical contact region 120. This second implant (illustrated by the arrows in fig. 3B) is carried out with an implant energy (up to 300keV) higher than the energy used for the first implant of fig. 3A. The mask 127 for the second implantation leaves an exposed surface layer portion of the semiconductor body 102 corresponding to the region where only the intermediate electrical contact region 120 is to be formed. Due to the higher implantation energy, the implanted species reach a higher depth in the semiconductor body 102 than that reached during the first implantation.

Then, in fig. 3C, an annealing step is carried out to promote the diffusion of all the implanted species of the regions 121, 122, thereby forming the source regions 108 and the intermediate electrical contact regions 120. The annealing is carried out at a temperature in the range 1600 ℃ to 1800 ℃.

After the annealing step, the first and second implanted regions 121, 122 form one single implanted and diffused region, which in turn forms an intermediate electrical contact region 120, the intermediate electrical contact region 120 being in direct electrical contact with the two source regions 108 on opposite sides thereof along the X-direction.

According to a further embodiment, not shown, after the first implantation for forming the source region 108, a first annealing step is carried out to diffuse the dopant species thus implanted. Then, a second implantation is performed, and a further second annealing step is performed to diffuse the dopant species thus implanted.

It is apparent that the source regions 108 and the intermediate electrical contact regions 120 may be formed by a higher number of implantations than has been described. For example, the source region 108 may be formed by more than two subsequent implants, and the intermediate electrical contact region 120 may be formed by more than three subsequent implants (where at least two of the subsequent implants are common to the formation of the source region 108).

The advantages it provides are evident by examining the characteristics of the present disclosure provided in accordance with the present disclosure.

In particular, by introducing an internal voltage clamp in the basic cell of the MOSFET structure, it is possible to make the breakdown phenomenon occur in the whole active area, thus maximizing the area involved in all cases when the device is required to operate in avalanche mode.

When the avalanche mode is reached, the electric field is lower than in the standard solution, allowing better avalanche performance.

Furthermore, the breakdown voltage is more uniform across the MOSFET structure because it overcomes the variability of the breakdown voltage values typically experienced at the edge layers of the device.

Finally, it is clear that modifications and variations can be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure, as defined in the annexed claims.

For example, the previously disclosed embodiments relate to N-channel MOSFETs. However, it will be apparent to those skilled in the art that the present disclosure may also be applied to P-channel MOSFETs.

In a further embodiment shown in fig. 4, a MOSFET device 120 is shown. Elements of fig. 4 that are common to those of fig. 2 are denoted with the same reference numerals and will not be described further.

In the MOSFET device 120, the intermediate electrical contact region 120 and the source region(s) 108 extend to the same depth (i.e., D) in the semiconductor body 102_I＝D_SOr D_I≈D_S). However, the intermediate electrical contact region 120 has a higher doping level (doping concentration) than the source region 108.

The doping level of the intermediate electrical contact region 120 is 1 · 10¹⁹Atom/cm³-1·10²⁰Atom/cm³And the doping level of the source region 108 is in the range of 1 · 10¹⁸Atom/cm³-2·10¹⁹Atom/cm³Within the range of (1). In general, the doping level of the source region 108 is 1% to 20% of the doping level of the intermediate electrical contact region 120. The actual values are selected within the specified range and do not overlap. Also, as noted, in this embodiment, the depth D of the intermediate electrical contact region 120_IAnd depth D of source region 108_SThe same is true. E.g. depth D_SAnd D_IIn the range of 0.2 μm to 0.4. mu.m.

This embodiment has been found to increase robustness during short circuit testing. In fact, the structure of fig. 4 allows for modulation of the saturation current of the MOSFET device 120 without undesirably affecting the output resistance of the MOSFET device 120.

The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.