阅读说明：本技术 鳍式场效应管及其制作方法 (Fin type field effect transistor and manufacturing method thereof ) 是由 陈尚志 张玉静 杨忙 于 2020-12-31 设计创作，主要内容包括：本发明公开了一种鳍式场效应管输入输出器件及其制作方法,所述鳍式场效应管输入输出器件包括：半导体衬底,具有第一表面,第一表面包括多个器件区；位于器件区表面上的多个鳍形结构；同一器件区表面上的鳍形结构的掺杂浓度相同；位于半导体衬底具有所述鳍形结构一侧表面的浅沟道隔离层,浅沟道隔离层的厚度低于鳍形结构的高度,浅沟道隔离层上方的鳍形结构表面上具有预设厚度的栅极介电层；设置在栅极介电层表面的栅极,栅极与器件区一一对应设置,所述栅极相互绝缘；至少两个所述栅极的金属功函数不同,和/或,至少两个所述器件区表面上的所述鳍形结构的掺杂浓度不同。本技术方案为鳍式场效应管输入输出器件具有多种阈值电压的设计。(The invention discloses a fin field effect transistor input and output device and a manufacturing method thereof, wherein the fin field effect transistor input and output device comprises: a semiconductor substrate having a first surface, the first surface including a plurality of device regions; a plurality of fin structures located on a surface of the device region; the doping concentration of the fin-shaped structures on the surface of the same device region is the same; the shallow trench isolation layer is positioned on the surface of one side, provided with the fin-shaped structure, of the semiconductor substrate, the thickness of the shallow trench isolation layer is lower than the height of the fin-shaped structure, and a grid dielectric layer with preset thickness is arranged on the surface of the fin-shaped structure above the shallow trench isolation layer; the grid electrodes are arranged on the surface of the grid electrode dielectric layer and are in one-to-one correspondence with the device areas, and the grid electrodes are mutually insulated; the metal work functions of at least two of the grid electrodes are different, and/or the doping concentrations of the fin-shaped structures on the surfaces of at least two of the device areas are different. The technical scheme is that the input and output devices of the fin field effect transistor have various threshold voltages.)

1. A FinFET input-output device, comprising:

a semiconductor substrate; the semiconductor substrate has a first surface including a plurality of device regions;

a plurality of fin structures located on a surface of the device region; the doping concentration of the fin-shaped structures on the surface of the same device region is the same;

the shallow channel isolation layer is positioned on the surface of one side, provided with the fin-shaped structure, of the semiconductor substrate, the thickness of the shallow channel isolation layer is lower than the height of the fin-shaped structure, and a grid dielectric layer with preset thickness is arranged on the surface of the fin-shaped structure above the shallow channel isolation layer;

the grid electrodes are arranged on the surface of the grid electrode dielectric layer, the grid electrodes and the device areas are arranged in a one-to-one correspondence mode, and the grid electrodes are mutually insulated;

and the metal work functions of at least two grid electrodes are different, and/or the doping concentrations of the fin-shaped structures on the surfaces of at least two device areas are different.

2. The finfet input-output device of claim 1, wherein at least two of the gates have different metal layer thicknesses such that the metal work functions of the at least two gates are different.

3. The finfet input-output device of claim 2, wherein the metal layers of the gates have different thicknesses such that the metal work functions of all the gates are different from each other.

4. The finfet input-output device of claim 1, wherein the fin structures on all of the device region surfaces have different doping concentrations from each other.

5. The finfet input-output device of claim 1, wherein the device region has a well region within a surface thereof;

the semiconductor substrate is doped in a P type mode, the well region and the fin-shaped structure are doped in an N type mode, and the grid electrode is an N type metal work function layer.

6. The FinFET input-output device of claim 5, wherein the N-type metal work function layer comprises an Al composition.

7. The finfet input-output device of claim 1, wherein the device region has a well region within a surface thereof;

the semiconductor substrate is doped in an N type or a P type, the well region and the fin-shaped structure are doped in a P type, and the gate is a P type metal work function layer.

8. The finfet input-output device of claim 7, wherein the P-type metal work function layer comprises a TiN composition.

9. The FinFET I/O device of claim 1, wherein the gate dielectric layer is an oxide layer, a high-k dielectric layer, or a stack of an oxide layer and a high-k dielectric layer.

10. The finfet input-output device of any of claims 1-9, wherein the fin structure extends in a first direction in a direction parallel to the first surface;

the gate extends along a second direction, the second direction being perpendicular to the first direction;

and dummy gates are respectively arranged on two sides of the gate and are prepared from the same metal layer.

11. A method of fabricating the finfet input-output device according to any of claims 1-10, wherein the method comprises:

providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface, and the first surface comprises a plurality of device areas;

forming a plurality of fin-shaped structures in the device region, wherein the doping concentration of the fin-shaped structures on the surface of the same device region is the same;

forming a shallow channel isolation layer on one side, provided with the fin-shaped structure, of the semiconductor substrate, wherein the thickness of the shallow channel isolation layer is lower than the height of the fin-shaped structure, and a grid dielectric layer with a preset thickness is arranged on the surface of the fin-shaped structure above the shallow channel isolation layer;

forming gates on the surface of the gate dielectric layer, wherein the gates and the device regions are arranged in a one-to-one correspondence manner, and the gates are insulated from each other;

and the metal work functions of at least two grid electrodes are different, and/or the doping concentrations of the fin-shaped structures on the surfaces of at least two device areas are different.

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to a fin type field effect transistor input and output device and a manufacturing method thereof.

Background

With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following moore's law is continuously reduced, in order to adapt to the reduction of process nodes, the channel length of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) needs to be continuously shortened, and the shortening of the channel length has the advantages of increasing the die density of a chip, increasing the switching speed of the MOSFET and the like.

In order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually beginning to transition from planar structures to more power efficient three-dimensional structures, such as fin field effect transistors (finfets). The gate in the FinFET can control the ultrathin body (fin part) from at least two sides, the control capability of the gate on a channel is stronger than that of a planar MOSFET, the short channel effect can be well inhibited, and the FinFET has better compatibility with the existing integrated circuit manufacturing method compared with other devices.

In the existing FINFET Core device, there are various threshold voltage device designs available, for example, a high-speed circuit may select a low threshold voltage FINFET Core device, and a low-power circuit may select a high threshold voltage FINFET Core device. However, current designs are limited to providing a threshold voltage for FINFET input/output devices (FINFET IO devices) that incorporate the input/output circuitry.

Disclosure of Invention

In order to solve the problems, the input and output assembly of the fin field effect transistor with various threshold voltages is designed, and can be matched with a high-speed or low-power-consumption core assembly, and the input and output assembly which can be matched is adopted.

In view of this, the present application provides a fin field effect transistor input/output device and a method for manufacturing the same, and the scheme is as follows:

a finfet input-output device, comprising:

a semiconductor substrate; the semiconductor substrate has a first surface including a plurality of device regions;

a plurality of fin structures located on a surface of the device region; the doping concentration of the fin-shaped structures on the surface of the same device region is the same;

the shallow channel isolation layer is positioned on the surface of one side of the semiconductor substrate, which is provided with the fin-shaped structure, the thickness of the shallow channel isolation layer is lower than the height of the fin-shaped structure, and the surface of the fin-shaped structure above the shallow channel isolation layer has a preset thickness (electrical thickness)>) A gate dielectric layer;

the grid electrodes are arranged on the surface of the grid electrode dielectric layer, the grid electrodes and the device areas are arranged in a one-to-one correspondence mode, and the grid electrodes are mutually insulated;

and the metal work functions of at least two grid electrodes are different, and/or the doping concentrations of the fin-shaped structures on the surfaces of at least two device areas are different.

Preferably, in the finfet input-output device, the metal layer thicknesses of at least two of the gates are different, so that the metal work functions of at least two of the gates are different.

Preferably, in the finfet input-output device, the metal layers of the gates have different thicknesses, so that the metal work functions of all the gates are different from each other.

Preferably, in the finfet input-output device, doping concentrations of the fin structures on surfaces of all the device regions are different from each other.

Preferably, in the finfet input/output device, a well region is formed in a surface of the device region;

the semiconductor substrate is doped in a P type mode, the well region and the fin-shaped structure are doped in an N type mode, and the grid electrode is an N type metal work function layer.

Preferably, in the finfet input-output device, the N-type metal work function layer includes an Al component.

Preferably, in the finfet input/output device, a well region is formed in a surface of the device region;

the semiconductor substrate is doped in an N type or a P type, the well region and the fin-shaped structure are doped in a P type, and the gate is a P type metal work function layer.

Preferably, in the finfet input-output device, the P-type metal work function layer includes a TiN component.

Preferably, in the finfet input/output device, the gate dielectric layer is an oxide layer, a high-K value dielectric layer, or a stack of an oxide layer and a high-K dielectric layer. Because the input/output device is a fin field effect transistor input/output device and is required to bear high enough input/output voltage, the electrical thickness of the input/output device is larger than that of a core device (electrical thickness)<) Thickness from (electrical thickness)>) So as to ensure that the device can work normally without being damaged.

Preferably, in the finfet input-output device, the fin structure extends in a first direction in a direction parallel to the first surface;

the gate extends along a second direction, the second direction being perpendicular to the first direction;

dummy gates (Dummy gates) are respectively arranged on two sides of the gate, and the Dummy gates and the gate are prepared from the same metal layer.

The invention also provides a manufacturing method of any one of the fin field effect transistor input and output devices, which comprises the following steps:

providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface, and the first surface comprises a plurality of device areas;

forming a plurality of fin-shaped structures in the device region, wherein the doping concentration of the fin-shaped structures on the surface of the same device region is the same;

forming a shallow channel isolation layer on one side of the semiconductor substrate, which is provided with the fin-shaped structure, wherein the thickness of the shallow channel isolation layer is lower than the height of the fin-shaped structure, and the surface of the fin-shaped structure above the shallow channel isolation layer has a preset thickness (electrical thickness)>) A gate dielectric layer;

forming gates on the surface of the gate dielectric layer, wherein the gates and the device regions are arranged in a one-to-one correspondence manner, and the gates are insulated from each other;

and the metal work functions of at least two grid electrodes are different, and/or the doping concentrations of the fin-shaped structures on the surfaces of at least two device areas are different.

As can be seen from the above description, in the fin field effect transistor input/output Device (FINFET IO Device) and the manufacturing method thereof provided in the technical solution of the present invention, the fin field effect transistor input/output Device includes: a semiconductor substrate; the semiconductor substrate has a first surface including a plurality of device regions; a plurality of fin structures located on a surface of the device region; the doping concentration of the fin-shaped structures on the surface of the same device region is the same; a shallow trench isolation layer on the surface of one side of the semiconductor substrate having the fin-shaped structure, the shallow trench isolation layer having a thickness lower than the height of the fin-shaped structure, the fin-shaped structure above the shallow trench isolation layer having a predetermined thickness (electrically thick)) A gate dielectric layer; the grid electrodes are arranged on the surface of the grid electrode dielectric layer, the grid electrodes and the device areas are arranged in a one-to-one correspondence mode, and the grid electrodes are mutually insulated; and the metal work functions of at least two grid electrodes are different, and/or the doping concentrations of the fin-shaped structures on the surfaces of at least two device areas are different. Thus, the Threshold Voltage (Vt) of the finfet input/output device has multiple kinds, and the gate of any metal work function and the fin of any doping concentration can be selectedAnd (4) constructing input and output devices of the fin field effect transistors with different threshold voltages by structure combination.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

The structure, proportion, size and the like shown in the drawings are only used for matching with the content disclosed in the specification, so that the person skilled in the art can understand and read the description, and the description is not used for limiting the limit condition of the implementation of the invention, so the method has no technical essence, and any structural modification, proportion relation change or size adjustment still falls within the scope of the technical content disclosed by the invention without affecting the effect and the achievable purpose of the invention.

FIG. 1 is a top view of a FinFET input-output device;

FIG. 2 is a cross-sectional view of the FinFET input/output device of FIG. 1 in the A-A' direction;

FIG. 3 is a cross-sectional view of the FinFET input/output device of FIG. 1 in the direction B-B';

fig. 4 is a top view of a finfet input/output device according to an embodiment of the present invention;

FIG. 5 is a cross-sectional view of the FinFET input-output device of FIG. 4 in the A-A' direction;

fig. 6 is a cross-sectional view of the finfet input-output device of fig. 4 in the direction of B-B'.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As shown in fig. 1-3, fig. 1 is a top view of a finfet input/output device, fig. 2 is a cross-sectional view of the finfet input/output device shown in fig. 1 in a-a 'direction, fig. 3 is a cross-sectional view of the finfet input/output device shown in fig. 1 in a B-B' direction, the finfet input/output device includes a semiconductor substrate 11 having a well region 12 in a surface thereof, the well region 12 having a plurality of fin structures 13 on a surface thereof, the semiconductor substrate 11 having a shallow trench isolation layer 14 on a surface thereof, the shallow trench isolation layer 14 having a thickness lower than a height of the fin structures 13. The shallow trench isolation 14 has a gate dielectric layer on its surface, which includes: an Interface Layer (IL) 15, wherein the interface layer 15 covers the fin-shaped structure 13 exposed out of the shallow trench isolation layer 14; and the high-dielectric-coefficient dielectric layer 16 is positioned on the surface of the interface layer 15, and the high-dielectric-coefficient dielectric layer 16 also covers the surface of the shallow trench isolation layer 14. A gate electrode 17 is provided on the surface of the gate dielectric layer. The interface layer 15 may be silicon oxide or other insulating layer, dummy gates 18 that are the same layer as the gate 17 are respectively disposed on two sides of the gate 17, and a connection line 19 is disposed between the dummy gates 18 and the gate 17. Below the connection line 19 there is an epitaxial Layer (epitaxiy Layer)10, the epitaxial Layer 10 comprising a source region and a drain region.

In the finfet input/output devices of fig. 1-3, the threshold voltage (Vt) of the finfet transistor has only one single mode with only one metal work function gate 17 and one doping concentration fin 13.

The conventional input and output device of the fin field effect transistor only has one grid electrode and one fin-shaped structure with doping concentration, and in order to realize the input and output devices of the fin field effect transistor with different threshold voltages, different grid electrode metal work functions and different doping concentrations of the fin-shaped structures in a plurality of input and output devices of the fin field effect transistor are needed.

In view of the above problems, embodiments of the present invention provide a finfet input/output device and a method for manufacturing the same, in which multiple device regions are designed in the same finfet input/output device, each device region has a separate gate and multiple fin structures, metal work functions of at least two gates are different, and/or doping concentrations of the fin structures on the surfaces of at least two device regions are different, so that multiple threshold voltages can be obtained in the same finfet input/output device.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

As shown in fig. 4 to fig. 6, fig. 4 is a top view of a finfet input/output device according to an embodiment of the present invention, fig. 5 is a cross-sectional view of the finfet input/output device shown in fig. 4 in a direction a-a ', and fig. 6 is a cross-sectional view of the finfet input/output device shown in fig. 4 in a direction B-B', the finfet input/output device including: a semiconductor substrate 21; the semiconductor substrate 21 has a first surface including a plurality of device regions; a plurality of fin structures 23 on a surface of the device region; the doping concentration of the fin-shaped structures 23 on the surface of the same device region is the same; a shallow trench isolation layer 24 located on the surface of one side of the semiconductor substrate 21 having the fin-shaped structure 23, wherein a gate dielectric layer is arranged on the surface of the fin-shaped structure 23 above the shallow trench isolation layer 24; and gate electrodes 27 disposed on the surface of the gate dielectric layer 23, the gate electrodes 27 being insulated from each other.

The thickness of the shallow trench isolation layer 24 is lower than the height of the fin structure 23, so that the top of the fin structure 23 is exposed out of the shallow trench isolation layer 24. The gate 27 and the device regions are arranged in a one-to-one correspondence manner, if there are M device regions, each device region is correspondingly provided with one gate 27, which has M gates, where M is a positive integer greater than 1, each device region is correspondingly provided with a plurality of fin structures 23, and the number of the fin structures 23 arranged in the device region may be set based on requirements, and is not limited to four shown in the drawings.

The metal work functions of at least two of the gates are different, and at this time, the doping concentrations of the fin structures 23 in different device regions may be the same or may not be the same, and/or the doping concentrations of the fin structures 23 on the surfaces of at least two of the device regions are different, and at this time, the metal work functions of the gates and the metal work functions may be the same or may not be the same. The fin structure 23 with different doping concentrations corresponds to the threshold voltage implantation region Vt IMP with different ion doping concentrations under the gate 27, so as to form channels with different threshold voltages.

The fin structure 23 may be doped by an ion implantation process, which typically includes anti-channel-conduction ion implantation (APT IMP), threshold voltage ion implantation (Vt IMP), Well-type ion implantation (Well IMP), or other ion implantation.

In the embodiment of the present invention, if the gate of the device region has x metal work functions, the device region has y fin structures 23 with different doping concentrations. The kinds of threshold voltages that can be generated are x y kinds. Therefore, the input and output device of the fin field effect transistor can have various threshold voltage implementation modes. The finfet input/output device may be selected for one use based on use requirements or for use with circuit interconnections (series and/or parallel) of structures in multiple device regions.

Wherein each device region shares the same substrate 21 and the same shallow trench isolation layer 24. The semiconductor substrate 21 may be a silicon substrate, or may be a substrate made of other semiconductor materials, such as germanium, silicon carbide, or gallium arsenide.

The thickness of the metal layer of at least two of the gate electrodes 27 is set to be different so that the metal work function of at least two of the gate electrodes 27 is different. Gate 27 with different metal work functions can be achieved by setting the metal layer thickness of gate 27. If the thicknesses of the metal layers of the gate electrodes 27 are set to be different from each other, so that the metal work functions of all the gate electrodes 27 are different from each other, and if M gate electrodes 27 are provided, the thicknesses of the metal layers of the M gate electrodes 27 are different from each other, which corresponds to the gate electrodes 27 having M different metal work functions.

In the embodiment of the present invention, the doping concentrations of the fin structures 23 on the surfaces of all the device regions are different from each other, and if there are M device regions, the fin structure 23 having one doping concentration on the surface of each device region has M fin structures 23 having different doping concentrations.

As shown in fig. 5, the surface of the device region has a well region 22 therein, the semiconductor substrate is P-type doped, the well region 22 and the fin structure 23 are N-type doped, and the gate 27 is an N-type metal work function layer, wherein the N-type metal work function layer includes an Al component. Alternatively, the semiconductor substrate 21 is N-type doped or P-type doped, the well region 22 and the fin-shaped structure 23 are P-type doped, and the gate 27 is a P-type metal work function layer, where the P-type metal work function layer includes TiN.

In the input/output device of the fin field effect transistor in the embodiment of the invention, the gate dielectric layer is an oxide layer, or a high-dielectric-coefficient dielectric layer, or a lamination of the oxide layer and the high-dielectric-coefficient dielectric layer. In the manner shown in fig. 3, the gate dielectric layer includes an interfacial layer 25 and a high-k dielectric layer 26. The interface layer 25 covers the part of the fin-shaped structure 23 exposed out of the shallow trench isolation layer 24, if the semiconductor substrate 21 is a silicon substrate, and the fin-shaped structure 23 is formed based on an etching process, an oxide layer can be directly formed on the part of the surface of the fin-shaped structure 23 exposed out of the shallow trench isolation layer 24 through an oxidation process to serve as the interface layer 25. A high-k dielectric layer 26 covers the interfacial layer 25 and covers the shallow trench isolation layer 24. The high-k dielectric layer 26 may be the same dielectric layer in each device region.

As shown in fig. 4, in a direction parallel to the first surface, the fin structure 23 extends along a first direction; the gate electrode 27 extends in a second direction, which is perpendicular to the first direction; dummy gates 28 are respectively disposed on two sides of the gate 27, and the dummy gates 28 and the gate 27 are made of the same metal layer. By providing the dummy gate 28, a loading effect (loading effect) can be reduced, and the growth quality of the epitaxial layer 20 (source drain region) can be improved. There is also a connection line 29 disposed in the same layer between the dummy gate 28 and the gate 27 for electrode interconnection in the device. The dummy gate 28 and the gate 27 are formed in the same layer and made of the same metal, and the connection line 29 is formed of another metal. The epitaxial layer 20 is connected to a connection line 29 to realize electrode interconnection.

In one implementation, all of the gates 27 have the same metal work function, and include fin structures 23 with different doping concentrations, where the number of threshold voltages is equal to the number of gates 27 with different metal work functions, e.g., x × 1 for gates with x different metal work functions.

Alternatively, the fin structures 23 in each device region have the same doping concentration, and include at least two gates 27 with different metal work functions, where the number of threshold voltages is equal to the number of fin structures 23 with different doping concentrations, and the number of threshold voltages is y × 1 if there are y fin structures 23 with different doping concentrations.

In another way, the metal work functions of the gates 27 are not completely the same, and the doping concentrations of the fin structures 23 in the device regions are not completely the same, for example, if there are x gates with different metal work functions and there are y fin structures 23 with different doping concentrations, the number of threshold voltages is x y.

As can be seen from the above description, the finfet input/output device according to the embodiments of the present invention can have various threshold voltage implementations. The finfet input/output device may be selected for one use based on use requirements or for use with circuit interconnections (series and/or parallel) of structures in multiple device regions.

The fin field effect transistor input-output device provided by the embodiment of the invention realizes a multi-threshold voltage scheme through a plurality of gates with different metal work functions and a plurality of fin structures with different doping concentrations.

In the input and output device of the fin field effect transistor, the grid can preferably multiplex the grid of the core device of the fin field effect transistor, and the grid of the core device can not be multiplexed if the grid is in special requirements. The fin doping process preferably multiplexes and de-multiplexes the ion implantation process in the core assembly if desired. Other elemental ions may be added at the time of ion implantation, for example, for reliability of the device.

The fin field effect transistor provided by the embodiment of the invention is used as an input/output device and can be used together with a core device of the fin field effect transistor, for example, in a high-performance circuit, the fin field effect transistor is used for a high-speed input/output device of a high-speed core device, and an input/output assembly has low power consumption threshold voltage; for example, in a low power consumption circuit, a low power consumption input/output component is used for a core device with low power consumption, and the input/output device has a high threshold voltage.

Based on the foregoing embodiment, another embodiment of the present invention further provides a manufacturing method of the finfet input/output device in the foregoing embodiment, where the manufacturing method includes:

step S11: a semiconductor substrate is provided, the semiconductor substrate having a first surface, the first surface including a plurality of device regions.

Step S12: and forming a plurality of fin-shaped structures in the device region, wherein the doping concentration of the fin-shaped structures on the surface of the same device region is the same.

Step S13: and forming a shallow channel isolation layer on one side of the semiconductor substrate with the fin-shaped structure, wherein the thickness of the shallow channel isolation layer is lower than the height of the fin-shaped structure, so that the top of the fin-shaped structure is exposed out of the shallow channel isolation layer, and a grid dielectric layer is arranged on the surface of the fin-shaped structure above the shallow channel isolation layer.

Step S14: and forming gates on the surface of the gate dielectric layer, wherein the gates and the device regions are arranged in a one-to-one correspondence manner, and the gates are insulated from each other.

The grid electrodes and the device regions are arranged in a one-to-one correspondence mode, if M device regions are provided, each device region is correspondingly provided with one grid electrode, M grid electrodes are provided, M is a positive integer larger than 1, each device region is correspondingly provided with a plurality of fin-shaped structures, and the number of the fin-shaped structures arranged in the device regions can be set based on requirements and is not limited to four shown in the drawing.

And the metal work functions of at least two grid electrodes are different, and/or the doping concentrations of the fin-shaped structures on the surfaces of at least two device areas are different. The fin structure 23 may be doped by an ion implantation process including anti-channel-on ion implantation (APT IMP), threshold voltage ion implantation (Vt IMP), or other methods that may be used.

The metal layer thicknesses of at least two of the grid electrodes are set to be different, so that the metal work functions of at least two of the grid electrodes are different. The thickness of the metal layer of the grid can be set, so that the grids with different metal work functions can be realized. If the metal layers of the gates have different thicknesses, so that the metal work functions of all the gates are different from each other, and if M gates are provided, the metal layers of the M gates have different thicknesses and correspond to the gates having M different metal work functions. And setting the doping concentrations of the fin-shaped structures on the surfaces of all the device regions to be different from each other, wherein if M device regions are provided, the fin-shaped structure with one doping concentration on the surface of each device region has M fin-shaped structures with different doping concentrations.

Based on the manufacturing method, the structure of the finally formed finfet input-output device may be as described in the above embodiments. If there are M device regions, corresponding to M gates, the M gates have x metal work functions, x being a positive integer no greater than M. The M device regions correspond to fin-shaped structures with y different doping concentrations, and y is a positive integer not greater than M. The kind of threshold voltage is x y. Therefore, the input and output device of the fin field effect transistor can have various threshold voltage implementation modes. The finfet input/output device may be selected for one use based on use requirements or for use with circuit interconnections (series and/or parallel) of structures in multiple device regions.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. As for the manufacturing method disclosed in the embodiment, since it corresponds to the finfet input/output device disclosed in the embodiment, the description is relatively simple, and the relevant points can be described with reference to the corresponding parts of the finfet input/output device.

It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or component in question must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.