阅读说明：本技术 一种耐短路电流冲击的沟槽mosfet器件及制造方法 (Trench MOSFET device resistant to short-circuit current impact and manufacturing method ) 是由 刘锋 殷允超 刘秀梅 于 2021-02-04 设计创作，主要内容包括：本发明涉及一种耐短路电流冲击的沟槽MOSFET器件,包括有源区,其特征在于,所述有源区包括若干个呈条形或格形排布的有源电流区和分布在所述有源电流区间的虚拟电流区,所述有源电流区包括若干个呈阵列排布的格形有源器件元胞单元,所述虚拟电流区包括若干个呈阵列排布的格形虚拟器件元胞单元,所述格形有源器件元胞单元和格形虚拟器件元胞单元的尺寸均为L；本发明在现有格形栅的基础上,通过优化版图设计,既能保证器件有较低的导通电阻,又能提升抗电流冲击能力,同时不增加任何成本。(The invention relates to a trench MOSFET device resistant to short-circuit current impact, which comprises an active area and is characterized in that the active area comprises a plurality of active current areas which are arranged in a strip shape or a grid shape and virtual current areas which are distributed in an active current interval, the active current areas comprise a plurality of grid-shaped active device cell units which are arranged in an array shape, the virtual current areas comprise a plurality of grid-shaped virtual device cell units which are arranged in an array shape, and the sizes of the grid-shaped active device cell units and the grid-shaped virtual device cell units are L; on the basis of the existing grid-shaped grid, the invention can ensure that the device has lower on-resistance and improve the current impact resistance by optimizing the layout design without increasing any cost.)

1. The trench MOSFET device resistant to short-circuit current impact comprises an active area and is characterized in that the active area comprises a plurality of active current areas (1) which are arranged in a strip shape or a grid shape and virtual current areas (2) which are distributed among the active current areas (1), the active current areas (1) comprise a plurality of grid-shaped active device cell units (101) which are arranged in an array shape, the virtual current areas (2) comprise a plurality of grid-shaped virtual device cell units (201) which are arranged in an array shape, and the sizes of the grid-shaped active device cell units (101) and the grid-shaped virtual device cell units (201) are L.

2. The trench MOSFET device of claim 1, wherein: the distance D between the adjacent active current areas (1) is at least the width L of one cell unit (201) of the lattice-shaped virtual device, and D is larger than or equal to L.

3. The trench MOSFET device of claim 1, wherein: when the active current region (1) is in a strip shape, the width W of the active current region (1) is at least the width of two lattice-shaped active device cell units (101), and W is more than or equal to 2L.

4. The trench MOSFET device of claim 1, wherein: when the active current region (1) is in a grid shape, the width and the length of the active current region (1) are the same as W, the width of at least two grid-shaped active device cell units (101) is equal to or larger than 2L.

5. The trench MOSFET device of claim 1, wherein: the distance S between the edge of the active current region (1) and the edge of the active region is at least the width of 5 grid-shaped virtual device cell units (201), and is smaller than the width of 10 grid-shaped virtual device cell units (201), and S is more than or equal to 5L and less than or equal to 10L.

6. A manufacturing method of a trench MOSFET device resistant to short-circuit current impact comprises the following steps:

a. providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region (4) and a first conduction type substrate (3) positioned below the first conduction type drift region (4), and the upper surface of the first conduction type drift region (4) is a first main surface (001) of the semiconductor substrate;

b. depositing a hard mask layer on the first main surface (001) of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window (5);

c. etching the first main surface (001) under the masking of the first hard mask window (5) to obtain a plurality of grooves (8) positioned in the active region, wherein the grooves (8) are distributed in a first conductive type drift region (4) in a grid shape;

d. growing an oxide layer and depositing conductive polycrystalline silicon on the first main surface (001) of the semiconductor substrate, etching the conductive polycrystalline silicon and the oxide layer in turn, and only keeping the oxide layer and the conductive polycrystalline silicon in the groove (8) to obtain a gate oxide layer (9) positioned on the side wall of the groove (8) and gate conductive polycrystalline silicon (10) wrapped by the gate oxide layer (9);

e. implanting second conductivity type ions into the first main surface (001) of the semiconductor substrate, and annealing to obtain second conductivity type well regions (6) located between the trenches (8);

f. depositing a hard mask layer on the first main surface (001) of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned second hard mask window (7);

g. under the shielding of a second patterned hard mask window (7), selectively injecting first conductive type ions to obtain a first conductive type source region (11) positioned in a second conductive type well region (6), wherein the injection region of the first conductive type source region (11) is an active current region (1), and the non-injection region of the first conductive type source region is a virtual current region (2);

h. depositing an insulating medium (12) on the first main surface (001) of the semiconductor substrate, and etching the insulating medium (12) to obtain a plurality of metal contact holes;

i. and depositing metal in the metal contact hole and on the insulating medium, and etching the metal to obtain source metal (13).

7. The method of claim 6, wherein the trench MOSFET device is characterized by: the second patterned hard mask windows (7) are distributed in a strip shape or a grid shape.

8. The method of claim 6, wherein the trench MOSFET device is characterized by: the virtual current areas (2) are distributed among the active current areas (1), the active current areas (1) comprise a plurality of grid-shaped active device cell units (101) which are arranged in an array, and the virtual current areas (2) comprise a plurality of grid-shaped virtual device cell units (201) which are arranged in an array.

9. The method of claim 6, wherein the trench MOSFET device is characterized by: in the active current region (1), the source metal (13) passes through an insulating medium and is in ohmic contact with a first conduction type source region (11) and a second conduction type well region (6) respectively; within the dummy current region (2), the source metal (13) is in ohmic contact with the second conductivity type well region (6) through an insulating medium.

10. The trench MOSFET device and method of claim 1 or 6, wherein: for an N-type trench MOSFET device structure, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type trench MOSFET device structure, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.

Technical Field

The invention relates to a power semiconductor device, in particular to a trench MOSFET device resistant to short-circuit current impact and a manufacturing method thereof, belonging to the technical field of power semiconductor devices.

Background

The strip-shaped grid has small channel density, small saturation current, small short-circuit current and strong current impact resistance,

the power trench gate MOSFET is widely applied to the fields of lithium battery protection, quick charge, flyback power supply, solar controller, inverter, brushless brush motor and the like with excellent small volume and low conduction loss. The trench gate MOSFET is mainly divided into two types of design structures, namely a lattice grid (a Chinese character 'pin' shaped grid, a square grid and a hexagonal grid) and a bar grid structure, wherein the lattice grid has lower on-resistance due to higher channel density than the bar grid, and is more widely applied in the fields of lithium battery protection, quick charging and the like, but the lattice grid has large saturation current and weaker current impact resistance, a circuit can generate larger impact current when in short circuit, and an MOSFET device used as palm tube power output can generate a large amount of heat to burn, so that the trench gate MOSFET is less applied in the fields of electric vehicles, handheld electric drills, motors of fascial guns and the like;

as shown in fig. 1, the conventional lattice grid structure is shown, and as shown in fig. 2, the conventional lattice grid structure is shown.

Disclosure of Invention

The invention aims to overcome the defects in the prior grid power MOSFET device technology and provide a trench MOSFET device resistant to short-circuit current impact and a manufacturing method thereof.

In order to achieve the technical purpose, the technical scheme of the invention is as follows: the trench MOSFET device resistant to short-circuit current impact comprises an active area and is characterized in that the active area comprises a plurality of active current areas which are arranged in a strip shape or a grid shape and virtual current areas which are distributed in the active current areas, the active current areas comprise a plurality of grid-shaped active device cell units which are arranged in an array shape, the virtual current areas comprise a plurality of grid-shaped virtual device cell units which are arranged in an array shape, and the sizes of the grid-shaped active device cell units and the grid-shaped virtual device cell units are L.

Furthermore, the distance D between the adjacent active current intervals is at least the width L of a cellular unit of the lattice-shaped virtual device, and D is larger than or equal to L.

Further, when the active current region is in a strip shape, the width W of the active current region is at least the width of the cell units of the two lattice-shaped active devices, and W is more than or equal to 2L.

Further, when the active current region is in a lattice shape, the width and the length of the active current region are the same as W, the width of at least two cell units of the lattice-shaped active device is equal to or larger than 2L.

Furthermore, the distance S between the edge of the active current region and the edge of the active region is at least the width of 5 lattice-shaped virtual device cell units, and is less than the width of 10 lattice-shaped virtual device cell units, and S is more than or equal to 5L and less than or equal to 10L.

In order to further achieve the above technical object, the present invention further provides a method for manufacturing a trench MOSFET device resistant to short-circuit current surge, comprising the following steps:

a. providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region and a first conduction type substrate positioned below the first conduction type drift region, and the upper surface of the first conduction type drift region is a first main surface of the semiconductor substrate;

b. depositing a hard mask layer on the first main surface of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window;

c. etching the first main surface under the masking of the first hard mask window to obtain a plurality of grooves positioned in the active region, wherein the grooves are distributed in a grid shape in the first conduction type drift region;

d. growing an oxide layer and depositing conductive polycrystalline silicon on the first main surface of the semiconductor substrate, etching the conductive polycrystalline silicon and the oxide layer in turn, and only keeping the oxide layer and the conductive polycrystalline silicon in the groove to obtain a gate oxide layer positioned on the side wall of the groove and gate conductive polycrystalline silicon wrapped by the gate oxide layer;

e. implanting second conductivity type ions into the first main surface of the semiconductor substrate, and annealing to obtain a second conductivity type well region located between the trenches;

f. depositing a hard mask layer on the first main surface of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned second hard mask window;

g. under the shielding of a graphical second hard mask window, selectively injecting first conductive type ions to obtain a first conductive type source region positioned in a second conductive type well region, wherein the injection region of the first conductive type source region is an active current region, and the non-injection region of the first conductive type source region is a virtual current region;

h. depositing an insulating medium on the first main surface of the semiconductor substrate, and etching the insulating medium to obtain a plurality of metal contact holes;

i. and depositing metal in the metal contact hole and on the insulating medium, and etching the metal to obtain the source metal.

Further, the second patterned hard mask windows are distributed in a strip shape or a grid shape.

Further, the virtual current region is distributed in the active current region, the active current region includes a plurality of lattice-shaped active device cell units arranged in an array, and the virtual current region includes a plurality of lattice-shaped virtual device cell units arranged in an array.

Further, in the active current region, the source metal is in ohmic contact with the first conduction type source region and the second conduction type well region through the insulating medium respectively; and in the virtual current region, the source metal is in ohmic contact with the second conduction type well region through an insulating medium.

Further, for an N-type trench MOSFET device structure, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type trench MOSFET device structure, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.

Compared with the prior art, the invention has the following advantages:

1) according to the trench MOSFET device resistant to short-circuit current impact, the saturation current is reduced and the current impact resistance of the whole device is improved by optimizing the layout design (namely optimizing the second hard mask window 7); meanwhile, in the active current region, the device also has higher channel density, so that the on-resistance cannot be reduced;

3) compared with the existing process manufacturing method, the process manufacturing method does not increase the number of photoetching layers, is compatible with the existing process manufacturing method, and is suitable for mass popularization.

Drawings

Fig. 1 is a schematic top view of a conventional trench MOSFET device with a stripe gate.

Fig. 2 is a schematic diagram of a prior art trench MOSFET device grid structure from above.

Fig. 3 is a schematic top view of the structure (forming active current regions and dummy current regions) in embodiment 1 of the present invention.

Fig. 4 is a schematic top view of the structure (forming active current regions and dummy current regions) in embodiment 2 of the present invention.

Fig. 5 is a schematic top view of the structure (forming active current regions and dummy current regions) in embodiment 3 of the present invention.

FIG. 6 is a cross-sectional structural diagram of a semiconductor substrate formed in an embodiment of the invention.

FIG. 7 is a cross-sectional structural diagram illustrating formation of a first hard mask window in an embodiment of the invention.

Fig. 8 is a schematic cross-sectional structure diagram of forming a trench in an embodiment of the present invention.

FIG. 9 is a schematic cross-sectional structure of an embodiment of the present invention after growing an oxide layer and depositing polysilicon.

Fig. 10 is a schematic cross-sectional structure diagram of the formation of a gate oxide layer and conductive polysilicon in an embodiment of the invention.

Fig. 11 is a schematic cross-sectional view illustrating the formation of a second conductivity type well region according to an embodiment of the invention.

FIG. 12 is a cross-sectional structural view of forming a second hard mask window in an embodiment of the invention.

FIG. 13 is a schematic diagram illustrating a top view of a second hard mask window in an embodiment of the invention.

Fig. 14 is a schematic cross-sectional structure diagram of forming a first conductive type source region in an embodiment of the invention.

Fig. 15 is a schematic cross-sectional structure diagram of forming an insulating medium in an embodiment of the invention.

Fig. 16 is a schematic cross-sectional structure diagram of forming a source metal in an embodiment of the invention.

Description of reference numerals: 001-first major face; 1-active current region; 101-lattice active device cell units; 2-a virtual current region; 201-lattice virtual device cell units; a 3-N type substrate; a 4-N type drift region; 5-a first hard mask window; a 6-P type well region; 7-a second hard mask window; 8-a trench; 9-a gate oxide layer; 10-gate conductive polysilicon; 11-N type source region; 12-an insulating medium; 13-source metal.

Detailed Description

The present invention will be further described with reference to the following specific examples.

In the following embodiments, an N-type trench gate MOSFET is taken as an example, the N-type is an N-type, and the P-type is a P-type;

example 1:

as shown in fig. 3, a trench MOSFET device resistant to short-circuit current impact includes an active area, where the active area includes a plurality of active current areas 1 arranged in a stripe shape and virtual current areas 2 distributed among the active current areas 1, the active current areas 1 include a plurality of lattice active device cell units 101 arranged in an array, the virtual current areas 2 include a plurality of lattice virtual device cell units 201 arranged in an array, and the sizes of the lattice active device cell units 101 and the lattice virtual device cell units 201 are both L;

the distance D between the adjacent active current regions 1 is at least the width L of the cellular unit 201 of the lattice-shaped virtual device, and D is more than or equal to L; the width W of the active current region 1 is at least the width of the cell units 101 of the two lattice-shaped active devices, W is more than or equal to 2L, and the length of the active current region 1 is far greater than the width W; the distance S between the edge of the active current region 1 and the edge of the active region is at least the width of 5 lattice-shaped virtual device cell units 201, and is less than the width of 10 lattice-shaped virtual device cell units 201, and S is not less than 5L and not more than 10L.

In embodiment 1 of the present invention, the active current region 1 includes 6 × 2 lattice active device cell units 101, and a distance D between adjacent active current regions 1 is a width L of one lattice virtual device cell unit 201, that is, D is equal to L; the width W of the active current region 1 is the width of two lattice-shaped active device cell units 101, that is, W is 2L, and the length P of the active current region 1 is the width of six lattice-shaped active device cell units 101, that is, P is 6L; the distance S between the edge of the active current region 1 and the edge of the active region is the width of 5 lattice-shaped dummy device cell units 201, that is, S is 5L.

Example 2:

as shown in fig. 4, a trench MOSFET device resistant to short-circuit current impact includes an active area, where the active area includes a plurality of active current areas 1 arranged in a grid and virtual current areas 2 distributed among the active current areas 1, the active current areas 1 arranged in a grid are distributed in regular rows and columns, the active current areas 1 include a plurality of grid active device cell units 101 arranged in an array, the virtual current areas 2 include a plurality of grid virtual device cell units 201 arranged in an array, and the sizes of the grid active device cell units 101 and the grid virtual device cell units 201 are both L;

the distance D between the adjacent active current regions 1 is at least the width L of the cellular unit 201 of the lattice-shaped virtual device, and D is more than or equal to L; when the active current region 1 is in a lattice shape, the width and the length of the active current region 1 are the same as W, the width of at least two cell units 101 of the lattice-shaped active device is equal to or larger than 2L; the distance S between the edge of the active current region 1 and the edge of the active region is at least the width of 5 lattice-shaped virtual device cell units 201, and is less than the width of 10 lattice-shaped virtual device cell units 201, and S is not less than 5L and not more than 10L.

In embodiment 2 of the present invention, the active current region 1 includes 2 × 2 lattice active device cell units 101, and a distance D between adjacent active current regions 1 is a width L of one lattice virtual device cell unit 201, that is, D is equal to L; the width W and the length P of the active current region 1 are the same and are the widths of two lattice-shaped active device cell units 101, that is, W is 2L; the distance S between the edge of the active current region 1 and the edge of the active region is the width of 6 lattice-shaped dummy device cell units 201, that is, S is 6L.

Example 3:

as shown in fig. 5, a trench MOSFET device resistant to short-circuit current impact includes an active area, where the active area includes a plurality of active current regions 1 arranged in a lattice shape and virtual current regions 2 distributed between the active current regions 1, the active current regions 1 arranged in three adjacent lattice shapes are distributed in a delta shape, the active current regions 1 include a plurality of lattice active device cell units 101 arranged in an array, the virtual current regions 2 include a plurality of lattice virtual device cell units 201 arranged in an array, and the sizes of the lattice active device cell units 101 and the lattice virtual device cell units 201 are both L;

the distance D between the adjacent active current regions 1 is at least the width L of the cellular unit 201 of the lattice-shaped virtual device, and D is more than or equal to L; when the active current region 1 is in a lattice shape, the width and the length of the active current region 1 are the same as W, the width of at least two cell units 101 of the lattice-shaped active device is equal to or larger than 2L; the distance S between the edge of the active current region 1 and the edge of the active region is at least the width of 5 lattice-shaped virtual device cell units 201, and is less than the width of 10 lattice-shaped virtual device cell units 201, and S is not less than 5L and not more than 10L.

In embodiment 3 of the present invention, the active current region 1 includes 3 × 3 lattice active device cell units 101, and a distance D between adjacent active current regions 1 is a width L of one lattice virtual device cell unit 201, that is, D is equal to L; the width W and the length P of the active current region 1 are the same and are the widths of three lattice-shaped active device cell units 101, that is, W is equal to P is equal to 3L; the distance S between the edge of the active current region 1 and the edge of the active region is the width of 5 lattice-shaped dummy device cell units 201, that is, S is 5L.

The method for manufacturing the trench MOSFET device resistant to short-circuit current surge in the above embodiment includes the following steps:

as shown in fig. 6, a, providing a semiconductor substrate, where the semiconductor substrate includes an N-type drift region 4 and an N-type substrate 3 located below the N-type drift region 4, and an upper surface of the N-type drift region 4 is a first main surface 001 of the semiconductor substrate;

as shown in fig. 7, b, depositing a hard mask layer on the first main surface 001 of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window 5;

as shown in fig. 8, c, etching the first main surface 001 under the masking of the first hard mask window 5 to obtain a plurality of trenches 8 located in the active region, where the trenches 8 are distributed in a lattice shape in the N-type drift region 4;

as shown in fig. 9 and 10, d, growing an oxide layer and depositing conductive polysilicon on the first main surface 001 of the semiconductor substrate, and etching the conductive polysilicon and the oxide layer in turn, and only remaining the oxide layer and the conductive polysilicon in the trench 8 to obtain a gate oxide layer 9 on the side wall of the trench 8 and gate conductive polysilicon 10 wrapped by the gate oxide layer 9;

as shown in fig. 11, e, P-type ions are implanted into the first main surface 001 of the semiconductor substrate and annealed to obtain P-type well regions 6 located between the trenches 8;

as shown in fig. 12, f, depositing a hard mask layer on the first main surface 001 of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned second hard mask window 7;

the graphical second hard mask windows 7 are distributed in a strip shape or a grid shape;

as shown in fig. 13, the second hard mask windows 7 patterned in embodiment 3 are distributed in a grid shape;

as shown in fig. 14, g, under the masking of the patterned second hard mask window 7, selectively implanting N-type ions to obtain an N-type source region 11 located in the P-type well region 6, where an implantation region of the N-type source region 11 is an active current region 1, and an unimplanted region of the N-type source region is a dummy current region 2;

the virtual current areas 2 are distributed among the active current areas 1, the active current areas 1 comprise a plurality of lattice-shaped active device cell units 101 which are arranged in an array, and the virtual current areas 2 comprise a plurality of lattice-shaped virtual device cell units 201 which are arranged in an array;

as shown in fig. 15, h, depositing an insulating medium 12 on the first main surface 001 of the semiconductor substrate, and etching the insulating medium 12 to obtain a plurality of metal contact holes;

as shown in fig. 16, i, depositing metal in the metal contact hole and on the insulating medium, and etching the metal to obtain a source metal 13;

in the cell unit 101 of the lattice-shaped active device in the active current region 1, the source metal 13 is in ohmic contact with the N-type source region 11 and the P-type well region 6 through an insulating medium; in the lattice-shaped dummy device unit cell 201 of the dummy current region 2, the source metal 13 is in ohmic contact with the P-type well region 6 through an insulating medium.

The breakdown voltage of the trench MOSFET device resistant to short-circuit current impact is 20V-100V, and the low-voltage device is mainly applied to lithium battery protection, quick charging, flyback power supplies, solar controllers, inverters, brushless brush motors and the like.