阅读说明：本技术 薄膜晶体管器件的制作方法、薄膜晶体管器件及显示装置 (Manufacturing method of thin film transistor device, thin film transistor device and display device ) 是由 孙松 周佑联 许哲豪 于 2020-12-29 设计创作，主要内容包括：一种薄膜晶体管器件的制作方法、薄膜晶体管器件及显示装置,其包括设于基板上的栅极,设置于栅极和基板上的绝缘层,设于绝缘层上的有源层,其中,有源层中掺杂有锂元素,有源层包括顶层有源层和底层有源层,底层有源层为掺杂锂元素的氧化锌铟,顶层有源层为掺杂锂元素的氧化锌锡,底层有源层覆盖于绝缘层上,顶层有源层覆盖于底层有源层上,顶层有源层上设置有源极和漏极,绝缘保护层设于源极和漏极上,通过在有源层中掺杂锂元素,以置换有源层中的锌,从而降低了有源层的退火温度,提升了薄膜晶体管器件的的载流子迁移率、开关比,解决了传统薄膜晶体管器件存在的有源层退火温度高、制备条件苛刻的问题。(A manufacturing method of a thin film transistor device, the thin film transistor device and a display device comprise a grid electrode arranged on a substrate, an insulating layer arranged on the grid electrode and the substrate, and an active layer arranged on the insulating layer, wherein lithium element is doped in the active layer, the active layer comprises a top active layer and a bottom active layer, the bottom active layer is made of zinc indium oxide doped with lithium element, the top active layer is made of zinc tin oxide doped with lithium element, the bottom active layer covers the insulating layer, the top active layer covers the bottom active layer, a source electrode and a drain electrode are arranged on the top active layer, an insulating protective layer is arranged on the source electrode and the drain electrode, and zinc in the active layer is replaced by doping lithium element in the active layer, so that the annealing temperature of the active layer is reduced, the carrier mobility and the on-off ratio of the thin film transistor device are improved, and the problems that the annealing temperature of the active layer is high, the annealing temperature of the active layer, The preparation conditions are harsh.)

1. A thin film transistor device, comprising:

a substrate;

a gate disposed on the substrate;

the insulating layer is arranged on the grid electrode and the substrate, and the grid electrode is positioned between the substrate and the insulating layer;

the active layer comprises a top active layer and a bottom active layer, wherein the bottom active layer is zinc indium oxide doped with lithium elements, the top active layer is zinc tin oxide doped with lithium elements, the bottom active layer covers the insulating layer, and the top active layer covers the bottom active layer;

a source electrode;

the source electrode and the drain electrode are arranged on the top layer active layer;

and the insulating protection layer is arranged on the source electrode and the drain electrode.

2. The thin film transistor device of claim 1, wherein a thickness of the bottom active layer is less than a thickness of the top active layer.

3. The thin film transistor device of claim 1, wherein the bottom active layer has a thickness of 8-12nm and the top active layer has a thickness of 35-45 nm.

4. The thin film transistor device according to claim 1, wherein the insulating layer and the insulating protective layer are at least one of silicon nitride and silicon oxide.

5. The thin film transistor device of claim 1, wherein the source and drain are molybdenum, or a molybdenum/aluminum/molybdenum composite structure.

6. The thin film transistor device of claim 1, wherein the gate electrode is one of molybdenum, aluminum, and a molybdenum/aluminum/molybdenum composite structure.

7. A method for fabricating a thin film transistor device, the method comprising:

preparing a grid electrode on a substrate;

depositing an insulating layer on the gate;

preparing a bottom active layer on the insulating layer, wherein the bottom active layer is zinc indium oxide doped with lithium;

preparing a top active layer on the bottom active layer, wherein the top active layer is zinc tin oxide doped with lithium;

preparing a source electrode and a drain electrode on the top active layer;

and depositing an insulating protection layer on the source electrode and the drain electrode.

8. The method of fabricating the thin film transistor device of claim 7, wherein the fabricating the underlying active layer on the insulating layer comprises:

and depositing a bottom active layer on the insulating layer by adopting a magnetron sputtering mode.

9. The method of fabricating the thin film transistor device of claim 7, wherein after fabricating the top active layer on the bottom active layer, comprising:

and annealing the top active layer and the bottom active layer at a temperature of 350-450 ℃.

10. A display device, comprising: a display panel; and the thin film transistor device according to any one of claims 1 to 6, which drives the display panel.

Technical Field

The application belongs to the technical field of semiconductor devices, and particularly relates to a manufacturing method of a thin film transistor device, the thin film transistor device and a display device.

Background

With the rapid development of display technologies, in order to meet higher user experience requirements, the development of a flat panel display with high resolution and large size will become an inevitable development trend, a conventional silicon-based Thin Film Transistor (TFT) is gradually difficult to meet market requirements, and a metal oxide TFT becomes the most powerful competitor in the development of display technologies due to its advantages of high mobility, large area, good uniformity, high aperture ratio, and the like.

However, in order to obtain an active layer with high mobility, the active layer generally needs to be annealed at high temperature, and the preparation conditions are harsh, which is not favorable for industrial production.

Disclosure of Invention

The application aims to provide a manufacturing method of a thin film transistor device, the thin film transistor device and a display device, and aims to solve the problems of high annealing temperature of an active layer and harsh preparation conditions of a traditional thin film transistor device.

A first aspect of an embodiment of the present application provides a thin film transistor device, including:

a substrate;

a gate disposed on the substrate;

the insulating layer is arranged on the grid electrode and the substrate, and the grid electrode is positioned between the substrate and the insulating layer;

the active layer comprises a top active layer and a bottom active layer, wherein the bottom active layer is zinc indium oxide doped with lithium elements, the top active layer is zinc tin oxide doped with lithium elements, the bottom active layer covers the insulating layer, and the top active layer covers the bottom active layer;

a source electrode;

the source electrode and the drain electrode are arranged on the top layer active layer;

and the insulating protection layer is arranged on the source electrode and the drain electrode so as to protect the source electrode and the drain electrode.

Optionally, the thickness of the bottom active layer is smaller than the thickness of the top active layer.

Optionally, the thickness of the bottom active layer is 8-12nm, and the thickness of the top active layer is 35-45 nm.

Optionally, the insulating layer and the insulating protection layer are at least one of silicon nitride and silicon oxide.

Optionally, the source and the drain are molybdenum or a molybdenum/aluminum/molybdenum composite structure.

Optionally, the gate is one of molybdenum, aluminum and a molybdenum/aluminum/molybdenum composite structure.

A second aspect of an embodiment of the present application provides a method for manufacturing a thin film transistor device, where the method for manufacturing a thin film transistor device includes:

preparing a grid electrode on a substrate;

depositing an insulating layer on the gate;

preparing a bottom active layer on the insulating layer, wherein the bottom active layer is zinc indium oxide doped with lithium;

preparing a top active layer on the bottom active layer, wherein the top active layer is zinc tin oxide doped with lithium;

preparing a source electrode and a drain electrode on the top active layer;

and depositing an insulating protection layer on the source electrode and the drain electrode.

Optionally, the preparing a bottom active layer on the insulating layer includes:

and depositing a bottom active layer on the insulating layer by adopting a magnetron sputtering mode.

Optionally, after the top active layer is prepared on the bottom active layer, the method includes:

and annealing the top active layer and the bottom active layer at a temperature of 350-450 ℃.

A third aspect of an embodiment of the present application provides a display device, including: a display panel; and a thin film transistor device as claimed in any one of the preceding claims, the thin film transistor device driving the display panel.

In the method for manufacturing a thin film transistor device, the thin film transistor device and the display device provided in the embodiments of the present application, the thin film transistor device includes a gate electrode disposed on a substrate, an insulating layer disposed on the gate electrode and the substrate, an active layer disposed on the insulating layer, wherein the active layer is doped with lithium element, the active layer comprises a top active layer and a bottom active layer, the bottom active layer covers the insulating layer, the top active layer covers the bottom active layer, the top active layer is provided with a source electrode and a drain electrode, the insulating protective layer is arranged on the source electrode and the drain electrode, and the active layer is doped with lithium element to replace zinc in the active layer, therefore, the annealing temperature of the active layer is reduced, the carrier mobility and the on-off ratio of the thin film transistor device are improved, and the problems of high annealing temperature of the active layer and harsh preparation conditions of the traditional thin film transistor device are solved.

Drawings

Fig. 1 is a schematic structural diagram of a thin film transistor device provided in an embodiment of the present application;

fig. 2 is a schematic flow chart illustrating a method for fabricating a thin film transistor device according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Fig. 1 is a schematic structural diagram of a thin film transistor device provided in an embodiment of the present application, and referring to fig. 1, the thin film transistor device in the embodiment includes: a substrate 1; a gate electrode 2 disposed on the substrate 1; an insulating layer 3 deposited on the gate 2; the active layer comprises a bottom active layer 4 and a bottom active layer 5, wherein the bottom active layer 4 covers the insulating layer 3, the top active layer 5 covers the bottom active layer 4, and a source electrode 6 and a drain electrode 7 are arranged on the top active layer 5; and an insulating protective layer 8 disposed on the source electrode 6 and the drain electrode 7.

In the present embodiment, the underlying active layer 4 is zinc indium oxide (InZnO) doped with lithium (Li) element; the top active layer 5 is zinc tin oxide (SnZnO) doped with lithium element, and zinc in the active layer is replaced by doping the lithium element in the active layer, so that the annealing temperature of the active layer is reduced, the carrier mobility and the on-off ratio of the thin film transistor device are improved, and the problems of high annealing temperature and harsh preparation conditions of the active layer in the traditional thin film transistor device are solved.

In one of the embodiments, the thickness of the bottom active layer 4 is less than the thickness of the top active layer 5. In this embodiment, under the condition that performance is not reduced, part of the indium zinc oxide may be replaced by tin zinc oxide, which may reduce annealing temperature and difficulty in manufacturing thin film transistor devices.

In one embodiment, the bottom active layer 4 has a thickness of 8-12nm and the top active layer 5 has a thickness of 35-45 nm.

In the embodiment, the material adopted by the bottom active layer 4 is InZnO doped with Li element, the thickness is 8-12nm, the material adopted by the top active layer 5 is SnZnO doped with Li element, and the thickness is 35-45 nm; the active layer is prepared by adopting InZnO and SnZnO which are doped with Li, the doped Li can replace zinc in the active layer, the carrier concentration of the active layer is reduced, and the performance of the thin film transistor device is improved.

In this embodiment, a double-layer active layer structure is prepared by using InZnO and SnZnO doped with a Li element, the doped Li element can replace zinc in the active layer, so that the carrier concentration of the active layer is reduced, and the performance of the thin film transistor device is improved.

In one embodiment, the insulating layer and the insulating protective layer are made of silicon nitride (SiNx), silicon oxide (SiOx), or a combination of silicon nitride and silicon oxide.

In the embodiment, the relative dielectric constant of the silicon nitride, or the silicon oxide, or the combination of the silicon nitride and the silicon oxide is large, so that the silicon nitride, the silicon oxide, or the combination of the silicon nitride and the silicon oxide has good compactness and insulating property, and can form a good insulating isolation surface with the active layer.

In one embodiment, the source electrode and the drain electrode are made of molybdenum or a molybdenum/aluminum/molybdenum (Mo/Al/Mo) composite structure.

In one embodiment, the single-layer molybdenum (Mo) is used as the source and drain of the device to effectively reduce the leakage current, but the molybdenum is a rare metal which is expensive, corrosion-resistant and difficult to etch, and the device adopting the single-layer molybdenum has a longer production period and higher cost, so that the molybdenum/aluminum/molybdenum composite structure is adopted to reduce the consumption of the molybdenum, and the production period and the cost are reduced.

In one embodiment, the gate electrode 2 is one of molybdenum, aluminum, and a molybdenum/aluminum/molybdenum composite structure.

In one embodiment, the substrate 1 may be a panel structure made of glass with a thickness of 0.5mm to 0.7mm for providing a support and fixing platform for electrodes to make a metal oxide TFT device.

In one embodiment, the gate electrode 2 is a metal conductive electrode, which is a thin film structure and is disposed in the middle of the substrate 1 for controlling current flow between the source electrode 5 and the drain electrode 6.

In one embodiment, the gate electrode 2 is made of one of Mo, Al and a Mo/Al/Mo composite structure.

Further, the material used for the gate 2 may also be one or a stacked combination of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu). The gate electrode 2 is made of metal to have a conductive function. Of course, other materials may be used to fabricate the gate 2 according to specific requirements, and are not limited in this application.

In one embodiment, an insulating layer 3 is deposited on the gate electrode 2 while covering the substrate 1 for isolating the gate electrode 2 from the outside to prevent the TFT from operating abnormally due to voltage instability of the gate electrode 2 caused by leakage. Wherein, the edge of the insulating layer 3 is completely overlapped and attached with the edge of the substrate 1.

In one embodiment, the bottom active layer 4 covers the insulating layer 3 and is completely overlapped and attached to the insulating layer 3, the top active layer 5 covers the bottom active layer 4, the bottom active layer 4 and the top active layer 5 jointly form an active layer, and the active layer is used for generating an inversion layer under the control of the voltage of the gate 2 to form a conductive channel between the gate 2 and the source 6 and between the gate 2 and the drain 7.

In this embodiment, because the annealing temperature of SnZnO is lower, the active layer is set to be a double-layer structure including a top layer and a bottom layer, the active layer on the top layer is set to be SnZnO, the bottom layer is set to be InZnO, and the active layer replaces part of InZnO with SnZnO under the condition that performance is not reduced, so that the annealing temperature can be reduced, and difficulty in preparing the thin film transistor device is reduced.

Further, a magnetron sputtering mode is adopted to sequentially form lithium-doped zinc indium oxide and lithium-doped zinc tin oxide, after the preparation of the zinc indium oxide and the zinc tin oxide is completed, the active layer is processed at the annealing temperature of 350-450 ℃ and the annealing time of 30-60min, and the TFT with the double-layer active layer structure has high carrier mobility, on-off ratio and lower subthreshold swing.

In one embodiment, the source electrode 6 and the drain electrode 7 are arranged on two sides of the top active layer 5, the source electrode 6 and the drain electrode 7 are symmetrically arranged, and the source electrode 6 and the drain electrode 7 are not in contact with each other. The source electrode 6 and the drain electrode 7 are both metal conductive electrodes and are of thin film structures. The source electrode 6 and the drain electrode 7 can be controlled to be switched on or switched off by the voltage between the grid electrode 2 and the drain electrode 6.

In a specific application embodiment, the source electrode 6 and the drain electrode 7 adopt a Mo/Al/Mo composite structure. The Mo/Al/Mo composite structure comprises at least three metal films, namely two Mo layers and an Al layer sandwiched between the two Mo layers. The single-layer Mo can effectively reduce leakage current by being used as a source electrode and a drain electrode of the metal oxide TFT device, but the Mo is a rare metal and is expensive in price, corrosion-resistant and difficult to etch, so that the production period is long and the cost is high. In one specific application example, the source electrode 6 and the drain electrode 7 are made of a Mo/Al/Mo composite structure, and the production cost of the source electrode and the drain electrode is reduced and the production period is shortened by adding an Al layer to effectively replace a part of Mo. Of course, the source electrode 6 and the drain electrode 7 may be made of other materials according to specific requirements, and are not limited in this application.

Further, in one embodiment, the thickness of the Mo layer contacting the insulating layer 3 is set to be appropriate to improve the flatness of the conductive channel interface, reduce the leakage current, and thus improve the display quality of the metal oxide TFT device. Wherein the thickness of the Mo layer in contact with the insulating layer 3 is 14nm to 29 nm. The thickness of the underlying Mo layer provided in this embodiment enables isolation of Al from the Si element in the insulating layer 3 with a smaller Mo layer thickness.

In one embodiment, the thickness of the active layer at the bottom layer is 8-12nm, the adopted material is InZnO doped with Li element, the thickness of the top layer is 35-45nm, the adopted material is SnZnO doped with Li element, if the materials adopted by the active layer at the bottom layer and the top layer are both InZnO doped with Li element, the increase of the thickness of the active layer can increase the grain size of the active layer, and the roughness of the surface of the active layer is reduced, so that the performance of the metal oxide TFT device is better, but the performance of the metal oxide TFT device tends to be stable along with the increase of the thickness after the active layer exceeds a certain thickness.

In one embodiment, Li element is doped to form the bottom active layer 4 in the process of forming InZnO, then the sputtering material is replaced by SnZnO, and doping of Li element is kept, so that the thickness of the active layer is in a smaller range on the premise of ensuring better performance of the TFT device.

Fig. 2 is a schematic flow chart of a method for manufacturing a thin film transistor device according to an embodiment of the present disclosure, and with reference to fig. 1 and fig. 2, the method for manufacturing a TFT device according to the present embodiment includes steps S201 to step 206.

S201: a gate electrode 2 is prepared on a substrate 1.

In one embodiment, a metal layer of the gate electrode 2 is first deposited on the substrate 1, and then a photoresist is coated on the metal layer, and an exposure and development process is performed using the photoresist to form the position and shape of the gate electrode so that the gate electrode 2 is disposed at the middle position of the substrate 1.

S202: an insulating layer 3 is deposited on the gate 2.

In one embodiment, an insulating material is deposited on the gate 2 such that the gate 2 is exposed to form a thin film protective layer, i.e., an insulating layer 3, isolating the gate 2 from the outside. In one embodiment, the insulating material is SiNx, SiOx or a combination of SiNx and SiOx, and because SiOx and SiNx have relatively large relative dielectric constants and relatively good compactness and insulation, the insulating layer 3 made of SiOx or SiNx or a combination of SiOx and SiNx can form a relatively good insulating isolation surface with the underlying active layer 4.

S203: a bottom active layer 4 is prepared on the insulating layer 3, wherein the bottom active layer 4 is indium zinc oxide doped with lithium element.

In this embodiment, the material used for the bottom active layer 4 is InZnO doped with Li, and the thickness of the bottom active layer 4 is 8-12 nm.

In one embodiment, a semiconductor material is deposited on the insulating layer 3, and the shape of the active layer lower active layer 4 is formed on the insulating layer 3 through a patterning process, wherein the semiconductor material is InZnO doped with Li element.

S204: and preparing a top active layer 5 on the bottom active layer 4, wherein the top active layer 5 is zinc tin oxide doped with lithium element.

In the present embodiment, the top active layer 5 is prepared on the bottom active layer 4, and in one embodiment, the material used for the bottom active layer 5 is SnZnO doped with Li element and has a thickness of 35-45 nm.

In one embodiment, a semiconductor material is deposited on the active layer lower active layer 4, and the shape of the active layer lower active layer 5 is formed on the active layer lower active layer 4 through a patterning process, wherein the semiconductor material is SnZnO doped with Li element.

S205: a source electrode 6 and a drain electrode 7 are fabricated on the top active layer 5.

In one embodiment, the source electrode 6 and the drain electrode 7 are formed on both sides of the top active layer 5, the source electrode 6 and the drain electrode 7 are symmetrically disposed, the source electrode 6 and the drain electrode 7 are formed by the same process as the gate electrode 2, which will not be described herein,

s206: an insulating protective layer 8 is deposited over the source 6 and drain 7 electrodes.

In this embodiment, the process of fabricating the insulating protection layer 8 is the same as that of the insulating layer 3, and is not described herein again.

In one embodiment, preparing an underlying active layer on an insulating layer includes: and depositing a bottom active layer on the insulating layer by adopting a magnetron sputtering mode.

In one embodiment, step S206 is followed by: the active layer underlying active layer 4 and the underlying active layer 5 are annealed.

Specifically, the substrate 1 having the active layer underlying active layer 4 and the underlying active layer 5 prepared is placed in an annealing furnace, and the active layer underlying active layer 4 and the underlying active layer 5 are annealed.

In one embodiment, the annealing temperature of the annealing treatment is 350-450 ℃. In one embodiment, the annealing time is 30-60 minutes. The performance of the metal oxide TFT device fabricated at the annealing temperature set forth in this example was optimized. The surface roughness of the bottom active layer 4 and the bottom active layer 5 can be reduced by adjusting the annealing temperature, and the surface defect state density at the conductive channel of the top active layer 5 can be reduced, so that the mobility, the threshold voltage, the on-off ratio and the sub-threshold swing of the metal oxide TFT device can reach the optimal values.

In this example, a TFT device with comparable performance can be obtained with a lower annealing temperature for the dual active layers (InZnO: Li and ZnSn 0: Li) than for the single active layer InZnO: Li and the single active layer InZnO: Li, with an annealing temperature of about 900 ℃, ZnSn 0: the annealing temperature of Li is about 600 ℃.

In one embodiment, oxygen is introduced during the preparation of the bottom active layer 4 and the bottom active layer 5. In the embodiment, the flow of the introduced oxygen is 2SCCM-4 SCCM. The performance of the metal oxide TFT device fabricated with the oxygen flow set forth in this example is optimal. A certain amount of oxygen is introduced in the preparation process of the active layer, so that the surface defect state density of the bottom active layer 4 and the bottom active layer 5 is reduced, the carrier concentration in the bottom active layer 4 and the bottom active layer 5 is reduced, and the comprehensive performance of the metal oxide TFT device is improved.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

An embodiment of the present application further provides a display device, including: a display panel; and the thin film transistor device according to any one of the above embodiments, which drives the display panel.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.