阅读说明：本技术 一种滤波器组 (Filter bank ) 是由 吴树辉 吕磊 于 2020-12-23 设计创作，主要内容包括：本申请公开了一种滤波器组,滤波器组包括：装置本体和设置在装置本体内的N个滤波器；其中,一个滤波器分别包括M组谐振器,一组谐振器中包括相互平行设置的Q个谐振器,一组谐振器与其他组谐振器并联放置,其他组谐振器为M组谐振器中除一组谐振器外的；每组谐振器均与滤波器组的输入端和输出端连接。本申请实施例提供的滤波器组,可以解决PCB布局设计难度较大的问题。(The application discloses filter bank, filter bank includes: the filter comprises a device body and N filters arranged in the device body; one filter comprises M groups of resonators respectively, one group of resonators comprises Q resonators arranged in parallel, one group of resonators is arranged in parallel with other groups of resonators, and the other groups of resonators are except one group of resonators in the M groups of resonators; and each group of resonators is connected with the input end and the output end of the filter bank. The filter bank provided by the embodiment of the application can solve the problem that the PCB layout design difficulty is large.)

1. A filter bank, characterized in that the filter bank comprises: the filter comprises a device body and N filters arranged in the device body;

one filter comprises M groups of resonators respectively, one group of resonators comprises Q resonators arranged in parallel, one group of resonators is arranged in parallel with other groups of resonators, and the other groups of resonators are except the group of resonators in the M groups of resonators; and each group of resonators is connected with the input end and the output end of the filter bank.

2. The filter bank of claim 1, wherein a first resonator of each group of resonators is connected to an input of the filter bank, and a last resonator of each group of resonators is connected to an output of the filter bank.

3. The filter bank of claim 2, wherein a first tap is provided on the intermediate layer conductor of a first resonator of each group of resonators, and a second tap is provided on the intermediate layer conductor of a last resonator of each group of resonators.

4. Filter bank according to any of the claims 1 to 3, wherein the device body is made of LTCC material.

5. The filter bank of claim 1, further comprising: a switching circuit; the switching circuit is disposed within the device body.

6. The filter bank of claim 5, wherein the switch circuit is disposed on an upper layer of the N filters, and a ground plate is disposed between the switch circuit and the N filters.

7. Filter bank according to claim 5 or 6, wherein the switching circuit comprises a first chip and a second chip; the N filters comprise a first filter, a second filter, a third filter, a fourth filter and a fifth filter;

the first chip 14pin is connected with the first filter, and the second chip 24pin is connected with the first filter; the first chip 11pin is connected with the second filter, and the second chip 2pin is connected with the second filter; the first chip 8pin is connected with the third filter, and the second chip 5pin is connected with the third filter; the first chip 5pin is connected with the fourth filter, and the second chip 8pin is connected with the fourth filter; the first chip 2pin is connected with the fifth filter, and the second chip 11pin is connected with the fifth filter.

Technical Field

The embodiment of the application relates to the technical field of communication, in particular to a filter bank.

Background

At present, a Low Temperature Cofired Ceramic (LTCC) technology is gradually applied to the communication and aerospace fields due to the advantages of good packaging degree, high integration level, stable and reliable performance, good radio frequency performance and the like. Generally, in radio frequency circuits of S and C wave bands, a band-pass filter is generally realized in a mode that an independent SAW filter is attached to a PCB substrate, and the band-pass filter integrates a plurality of filters and two radio frequency switches and covers a plurality of 5G main common frequency bands. Since the insertion loss of the SAW filter is large, it cannot be used for a high frequency band. And the filter is bulky, thereby causing the layout design difficulty of the PCB to increase greatly.

Disclosure of Invention

The application provides a filter bank, which can solve the problem that the PCB layout design difficulty is large.

In order to solve the technical problem, the following technical scheme is adopted in the application:

in a first aspect of the present application, a filter bank is provided, the filter bank comprising: the filter comprises a device body and N filters arranged in the device body; one filter comprises M groups of resonators respectively, one group of resonators comprises Q resonators arranged in parallel, one group of resonators is arranged in parallel with other groups of resonators, and the other groups of resonators are except one group of resonators in the M groups of resonators; and each group of resonators is connected with the input end and the output end of the filter bank.

Optionally, in this embodiment of the application, a first resonator in each group of resonators is connected to the input end of the filter bank, and a last resonator in each group of resonators is connected to the output end of the filter bank.

Optionally, in this embodiment of the application, the intermediate layer conductor of the first resonator in each group of resonators is provided with a first tap, and the intermediate layer conductor of the last resonator in each group of resonators is provided with a second tap.

Optionally, in this application embodiment, the device body is made of LTCC material.

Optionally, in this embodiment of the application, the filter bank further includes: a switching circuit; the switch circuit is arranged in the device body.

Optionally, in this embodiment of the application, the switch circuit is disposed on an upper layer of the N filters, and a ground plate is further disposed between the switch circuit and the N filters.

Optionally, in this embodiment of the present application, the switch circuit includes a first chip and a second chip; the N filters comprise a first filter, a second filter, a third filter, a fourth filter and a fifth filter; the first chip is connected with the first filter, and the second chip is connected with the first filter; the first chip is connected with the second filter, and the second chip is connected with the second filter; the first chip is connected with the third filter, and the second chip is connected with the third filter; the first chip is connected with the fourth filter, and the second chip is connected with the fourth filter; the first chip is connected with the fifth filter, and the second chip is connected with the fifth filter.

The application provides a filter bank, this filter bank includes: the filter comprises a device body and N filters arranged in the device body; one filter comprises M groups of resonators respectively, one group of resonators comprises Q resonators arranged in parallel, one group of resonators is arranged in parallel with other groups of resonators, and the other groups of resonators are except one group of resonators in the M groups of resonators; and each group of resonators is connected with the input end and the output end of the filter bank. Five filters and two PQC6064 switch chips are integrated to form a single-chip integrated switch filter bank, and layout arrangement layout is designed. The final layout has a finished volume of only 20mm x 30mm x 1.116 mm. The center frequency of the first filter is 2.59GHz, the bandwidth is 0.2GHz, the insertion loss in a pass band is better than 2.6dB, the out-of-band rejection is more than 30dB in the stop band range which is less than 2.28GHz and more than 2.9GHz, and the standing-wave ratio is better than 1.13. The center frequency of the second filter is 1,795GHz, the bandwidth is 0.17GHz, the insertion loss in a passband of a passband is better than 2.38dB, the out-of-band rejection is more than 30dB in the stop band range which is less than 1.38GHz and more than 2.08GHz, and the in-band standing wave ratio is better than 1.49; the center frequency of the third filter is 4.7GHz, the bandwidth is 0.6GHz, the insertion loss in a pass band is better than 2.15dB, the out-of-band rejection is better than 30dB in the stop band range which is less than 4.06GHz and more than 5.45GHz, and the in-band standing-wave ratio is 1.33; the center frequency of the fourth filter is 2.054GHz, the bandwidth is 0.2GHz, the insertion loss in a pass band is better than 2.02dB, the out-of-band rejection is better than 30dB in the stop band range which is less than 1.62GHz and more than 2.68GHz, and the in-band standing wave ratio is 1.51; the center frequency of the fifth filter is 3.75GHz, the bandwidth is 0.5GHz, the insertion loss in a pass band is better than 1.4dB, the out-band rejection is better than 30dB in the stop band range which is less than 2.58GHz and is more than 4.32GHz, and the in-band standing wave ratio is 1.49. The multi-band antenna integrates the filters and the radio frequency switches, covers a plurality of 5G main common frequency bands, and only comprises two radio frequency interfaces and 6 logic interfaces except a power supply, so that the difficulty of PCB layout design is greatly reduced.

Drawings

Fig. 1 is a schematic structural diagram of a filter bank according to an embodiment of the present disclosure;

fig. 2A is a schematic perspective view of a filter bank according to an embodiment of the present disclosure;

fig. 2B is a schematic top view of a filter bank according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an equivalent lumped parameter model in an embodiment of the present application;

fig. 4 is a schematic diagram of a simulation result in the equivalent lumped parameter model ADS in the embodiment of the present application;

FIG. 5 is a schematic diagram of the physical structure of a five-layer UIR resonator in an embodiment of the present application;

FIG. 6 is a diagram illustrating a simulation result of the relationship between the resonant frequency of the resonator and a in the embodiment of the present application;

fig. 7 is a second schematic top view of a filter bank according to an embodiment of the present application;

FIG. 8 is a diagram illustrating an initial simulation result of a 2490-2690MHz filter model in an embodiment of the present application;

FIG. 9 is a schematic diagram of the phase shift of the third order coupling filter in the embodiment of the present application;

FIG. 10 is a diagram illustrating simulation results after optimization of 2490-2690MHz filters in the embodiment of the present application;

FIG. 11 is a schematic diagram of a filter bank in an embodiment of the present application;

fig. 12A is a schematic diagram of a simulation curve of parameters of a five-way filter S21 in the embodiment of the present application;

fig. 12B is a schematic diagram of a parameter simulation curve of the five-way filter S11 in the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first" and "second," and the like, in the description and in the claims of the embodiments of the present application are used for distinguishing between different objects and not for describing a particular order of the objects.

In the description of the embodiments of the present application, the meaning of "a plurality" means two or more unless otherwise specified. For example, a plurality of elements refers to two elements or more.

The term "and/or" herein is an association relationship describing an associated object, and means that there may be three relationships, for example, a display panel and/or a backlight, which may mean: there are three cases of a display panel alone, a display panel and a backlight at the same time, and a backlight alone. The symbol "/" herein denotes a relationship in which the associated object is or, for example, input/output denotes input or output.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

The application provides a filter bank, this filter bank includes: the filter comprises a device body and N filters arranged in the device body; one filter comprises M groups of resonators respectively, one group of resonators comprises Q resonators arranged in parallel, one group of resonators is arranged in parallel with other groups of resonators, and the other groups of resonators are except one group of resonators in the M groups of resonators; and each group of resonators is connected with the input end and the output end of the filter bank. Five filters and two PQC6064 switch chips are integrated to form a single-chip integrated switch filter bank, and layout arrangement layout is designed. The final layout has a finished volume of only 20mm x 30mm x 1.116 mm. The center frequency of the first filter is 2.59GHz, the bandwidth is 0.2GHz, the insertion loss in a pass band is better than 2.6dB, the out-of-band rejection is more than 30dB in the stop band range which is less than 2.28GHz and more than 2.9GHz, and the standing-wave ratio is better than 1.13. The center frequency of the second filter is 1.795GHz, the bandwidth is 0.17GHz, the insertion loss in a passband of a pass band is better than 2.38dB, the out-band rejection is more than 30dB in the stop band range which is less than 1.38GHz and more than 2.08GHz, and the in-band standing wave ratio is better than 1.49; the center frequency of the third filter is 4.7GHz, the bandwidth is 0.6GHz, the insertion loss in a pass band is better than 2.15dB, the out-of-band rejection is better than 30dB in the stop band range which is less than 4.06GHz and more than 5.45GHz, and the in-band standing-wave ratio is 1.33; the center frequency of the fourth filter is 2.054GHz, the bandwidth is 0.2GHz, the insertion loss in a pass band is better than 2.02dB, the out-of-band rejection is better than 30dB in the stop band range which is less than 1.62GHz and more than 2.68GHz, and the in-band standing wave ratio is 1.51; the center frequency of the fifth filter is 3.75GHz, the bandwidth is 0.5GHz, the insertion loss in a pass band is better than 1.4dB, the out-band rejection is better than 30dB in the stop band range which is less than 2.58GHz and is more than 4.32GHz, and the in-band standing wave ratio is 1.49. The multi-band antenna integrates the filters and the radio frequency switches, covers a plurality of 5G main common frequency bands, and only comprises two radio frequency interfaces and 6 logic interfaces except a power supply, so that the difficulty of PCB layout design is greatly reduced.

The filter bank provided by the embodiment of the application can be applied to a filter.

A filter bank provided in the embodiments of the present application is described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.

Fig. 1 shows a schematic structural diagram of a filter bank provided in an embodiment of the present application. As shown in fig. 1, a filter bank of an embodiment of the present application includes: the filter comprises a device body 10 and N filters (such as a filter 11, a filter 12, a filter 13, a filter 14 and a filter 15) arranged in the device body 10, wherein one filter comprises M groups of resonators respectively, one group of resonators comprises Q resonators arranged in parallel, one group of resonators is arranged in parallel with the other groups of resonators, and the other groups of resonators are except one group of resonators in the M groups of resonators; and each group of resonators is connected with the input end and the output end of the filter bank.

In order to clearly illustrate the structure of the filter bank according to the embodiment of the present application, fig. 2A and 2B illustrate one filter as an example.

As shown in fig. 2A and 2B, each of the filters includes M groups of resonators (e.g., resonator group 16, resonator group 17, and resonator group 18), one group of resonators includes Q resonators arranged in parallel with each other, one group of resonators is arranged in parallel with the other groups of resonators, and the other groups of resonators are the M groups of resonators except for one group of resonators; and each group of resonators is connected with the input end and the output end of the filter bank. The first resonator in each group of resonators is connected with the input end of the filter bank respectively, and the last resonator in each group of resonators is connected with the output end of the filter bank respectively.

Optionally, in this embodiment of the present application, the middle layer conductor of the first resonator in each group of resonators is provided with a first tap, and the middle layer conductor of the last resonator in each group of resonators is provided with a second tap 2.

Optionally, in this application embodiment, the device body is made of an LTCC material.

How the embodiments of the present application are designed for each filter will be described in detail below.

1. Circuit structure of selective filter

Bandpass filters are typically constructed by exchanging energy between adjacent resonators at each stage in the form of electrical or magnetic coupling. This summary mainly introduces the design method of the coupling resonance band-pass filter, and uses the ElectroMagnetic (EM) simulation tool to extract the key design information of the filter design such as resonance point, external Q value, coupling coefficient, etc. Designing UIR filters generally involves the following four main steps:

(1) and determining the order of the filter and the response function of the filter according to the index requirement. (2) And integrating the coupling matrix [ M ], K or J circuit converter model to realize an ideal filter function. (3) And determining the type of the filter (waveguide, coaxial or micro-strip and the like) according to the required indexes such as size, Q value, power capacity and the like. (4) The physical size of the filter is finalized.

2. Filter design

And calculating a coupling matrix by using CST Filter design 3D according to the requirement of a design index to obtain the resonance frequency of each resonator, the coupling coefficient between each stage and the loaded Q value. Then, an appropriate physical model is designed in the HFSS, and an appropriate resonance point is obtained. And (4) simulating by using a tap coupling mode to obtain a proper loaded Q value. And finally, enabling the two resonators to gradually approach to obtain two obvious detuning vibration points, further obtaining a coupling coefficient, adjusting the size of the coupling coefficient according to the coupling matrix, and finally forming the whole circuit. The whole filter can be regarded as that a plurality of resonators are directly connected in series after being phase-shifted by 90 degrees.

TABLE 1 design index

Here, the first filter 11 is explained as an example. Each resonator may be equivalent to a parallel connection of a capacitor and an inductor. The N-order UIR filter includes N resonators, and energy is transmitted therebetween by capacitive coupling, and fig. 3 shows an equivalent lumped parameter model thereof. Where C1 ═ C2 ═ 7pF, L1 ═ L2 ═ 0.5nH, C6 ═ C8 ═ 0.98pF, L3 ═ 0.6nH, and C3 ═ 4.5 pF. Because the filter belongs to Chebyshev response, the structure is symmetrical, the three resonators can be completely identical, and can also be slightly changed according to the symmetrical structure, so that the design of the filter is more flexible. FIG. 4 is the simulation result of the ADS model with such an equivalent set total parameter. Observing fig. 4, this filter operates at a center frequency of 2.59GHz, an absolute passband bandwidth of 200MHz, a return loss in the passband of better than 20dB, and an out-of-band rejection of more than 30dB at less than 2GHz and greater than 3.2 GHz. The overall comprehensive performance is close to the requirement of design indexes, which also shows the correctness of the design idea of carrying out the initial equivalent circuit of the band-pass filter by using ADS.

The first filter was simulated with five-layer UIR resonators, three-dimensional as shown in FIG. 5, in HFSS simulation software using tap-feedThe resonance point of the resonator is about 2.4GHz, and the reason that the resonance point of a single resonator is slightly lower than the passband range is that the detuned resonance point generated after the two resonators with tap feeding are coupled can move to a high frequency position. The width W of the coupling strip line in the resonator is 0.4mm, the length L is 4mm, and the overlapping length L-a of the coupling strip line in the adjacent layer is 3.8 mm. Formula of calculation with resonant frequencyTherefore, the resonance frequency can be increased by the equivalent capacitance of the smaller resonator. The simulation is carried out for the value of a, and the larger a is, the higher the resonant frequency is without changing L. Fig. 6 is a simulation result of changing the value of a to adjust the resonant frequency of the resonator.

A plurality of resonators are placed in parallel, as shown in fig. 7 for a three-stage resonator configuration. A tap 19 is added to the intermediate layer conductors of the first and last resonators, respectively, this tap 19 acting as a signal feed structure for the filter. The position of the tap 19 can be adjusted back and forth in the length direction of the resonator, the position is used for adjusting the loaded Q value, the length of the tap 19 needs to be well grasped, the influence of the tap 19 on the resonance point of the input and output stage resonator can be weakened due to the short length of the tap 19, however, the too short tap 19 can cause the model port to be too close to the resonator, the feeding of the model port cannot be guaranteed to be a weak coupling mode, and therefore the simulation error is caused due to the fact that the actual performance is influenced by the simulation setting problem. The distance between the resonators is set as a variable for adjusting the coupling strength. Except the input and output surfaces, the other four surfaces are provided with grounding shielding layers.

The LTCC dielectric is selected from green ceramic slurry with the model of DuPont951, the relative dielectric constant is [email protected], the loss tangent is [email protected], and the inner conductor material is silver paste doped with glass fibers. The glass fiber is doped to improve the fluidity of the metal slurry and reduce the shrinkage rate; the negative effect is a decrease in conductivity. The initial modeling was analyzed for the same three resonators, a 1.9mm and the resonator pitch gap 0.6 mm. The tap 19 position coord is-0.5 mm, i.e. the distance of the tap 19 from the resonator midpoint in the horizontal direction as shown in fig. 7. The simulation results are shown in FIG. 8. Compared with the figure 4, the amplitude-frequency response trend of the filter is shown, the central frequency point is shifted by nearly 10 percent to 2.3GHz, and the central frequency of the filter can be adjusted by adjusting the value of a. The two transmission poles are not very distinct in the passband and are very close in frequency, depending on the coupling coefficient k_ijThe calculation formula (2) shows that the coupling coefficient is small, and the value of gap needs to be reduced to increase the coupling coefficient.

After adjusting a to 1.3mm, gap to 0.5mm and coord to-0.4 mm according to the above description of the optimization concept, the simulation result is shown in fig. 9.

From simulation results, the insertion loss of the first filter 10 at the central frequency point is 2.1dB, the out-of-band rejection is greater than 30dB in the stop band range of 2GHz, the transmission zero appears at the 3.1GHz, the out-of-band rejection is greater than 30dB at 2.98GHz, the return loss is superior to 25dB, and the optimized result has a certain difference from the design index in low-frequency rejection. The filter size is 4.3mm x 2.8mm x 0.85mm, and since the filter is integrated in the whole switched filter bank, no peripheral related test pads and no grounding structures are designed.

Comparing fig. 7 with fig. 4, the return loss in the passband is optimized and is better than the simulation result of the ADS schematic diagram, but the insertion loss is obviously increased to 2.1dB, the limited Q value is the main reason for the great increase of the insertion loss, and the doping of the metal slurry aggravates the trend. Transmission zeros do not appear in the schematic diagram, but instead, transmission zeros appear in the simulation of the physical model at 3.1GHz, because the cross-coupling between the first-stage resonators and the third-stage resonators occurs, thereby generating transmission zeros outside the higher order band. The principle of its generation is shown in fig. 8.

In the figure, C12 and C23 are used for indicating that energy is exchanged between the resonators in a form of electric coupling, and L13 indicates that energy is exchanged between the resonators in a form of magnetic coupling. The additionally generated cross coupling L13 is the generation cause of the transmission zero point. C12, C23 are electrically coupled, the transmission phase shift of the capacitively coupled pair signal is +90 °, L13 is magnetically coupled, and the transmission phase shift of the inductively coupled pair signal is-90 °. For the resonator itself, the resonator imparts a phase shift of +90 ° to the signal in the frequency portion above the resonance point and a phase shift of-90 ° to the signal in the frequency portion below the resonance point. In order to analyze the cause and position of the transmission zero point, a phase transition diagram is generally used to characterize the phase variation relationship in practical design. The circles at the three vertices of the triangle and their internal numbers in fig. 9 represent the nth resonator, and the sides of the triangle are formed by the capacitance and inductance between the circles, where the capacitance represents the electrical coupling between the resonators at the respective stages with a +90 ° phase shift, and the inductance represents the magnetic coupling between the resonators at the respective stages with a-90 ° phase shift.

TABLE 2 phase relationship of different frequencies to the passband

When the phase difference is lower than the resonance frequency, the phase difference between the main signal propagation flow and the cross coupling signal propagation flow is observed, and when the phase difference is lower than the resonance frequency, the phase difference is 360 degrees and is in phase with the main signal, so that no transmission zero point is generated at a transition band lower than a pass band; above the resonant frequency, the phase difference is 180 °, in anti-phase with the main signal, and a transmission zero is generated at the transition band above the pass band.

In order to solve the problem that the out-of-band rejection does not reach the design index, the order is determined to be increased, a fourth-order UIR resonance band-pass filter is designed, the 30dB rejection required by the design target is achieved at 2.28GHz, the insertion loss in a pass band is increased to 2.6dB, the return loss is better than 25dB, the volume is 4.3mm multiplied by 3.4mm multiplied by 0.85mm, and the longitudinal length is increased by 0.5 mm. The simulation results for the third and fourth order filters are shown in fig. 10.

Optionally, in this embodiment of the application, the filter bank further includes: a switching circuit; the switching circuit is disposed in the device body 10.

Optionally, in this embodiment of the application, the switch circuit is disposed on an upper layer of the N filters, and a ground plate is further disposed between the switch circuit and the N filters.

In the embodiment of the present application, in order to implement a switching filter bank that is freely switched among five paths, a switching chip with appropriate performance needs to be selected to construct a switching circuit. The characteristics of various switch chips are described in the foregoing, and the correct selection is made according to the characteristics of each process, which is the key point of the design of the whole switch filter bank. In view of the usage scenario of the switch chip, low loss is the first requirement, and flat in-band ripple and isolation are considered. Based on the above considerations, we select QPC6064 six-channel switch chip of Qorvo corporation. The chip is an SP6T absorption switch chip based on Silicon On Insulator (SOI) CMOS process. The frequency covers a wide band range of 5MHz-6 GHz. The chip has smaller insertion loss.

TABLE 3 QPC6064 switch chip Main index

Due to the adoption of +/-6V power supply, the voltage of-0.2V-6V is used for logic control and is compatible with the CMOS logic level of 1.8V, and because of the absorption switch, the CMOS logic level circuit has excellent return loss even when the full-off function is turned on. The chip is packaged by standard method, and the overall size is 4mm multiplied by 0.75 mm. Because the highest frequency band of the filter designed at this time is 4.4GHz-5GHz, the chip completely covers the frequency range, the characteristics of low insertion loss and high isolation completely meet the system requirements, and the chip is packaged in a miniaturized standard and has a very simple peripheral circuit, and the size and the performance of the whole filter bank are greatly improved by matching with the monolithic integration design of LTCC.

The switch filter bank schematic diagram of fig. 11 is designed according to the selected switch chips, wherein U1 and U2 represent QPC6064 switch chips, and U3, second filter, third filter, fourth filter, fifth filter and U8 are filters designed this time. Radio frequency signals are led in from a 22PIN (PIN) of the U1 chip, the levels of the V1, the V2 and the V3 PIN are controlled to select an appropriate channel, and the radio frequency signals are led out from the 22PIN of the U2 chip. The peripheral capacitors of the switch chip are all 0402 standard packaged decoupling capacitors with capacitance value of 100 pF.

Optionally, in this embodiment of the present application, the switch circuit includes a first chip and a second chip; the N filters comprise a first filter, a second filter, a third filter, a fourth filter and a fifth filter;

the first chip U1 is connected to the first filter (i.e., the filter 11), and the second chip U2 is connected to the first filter (i.e., the filter 11); the first chip U1 is connected to the second filter (i.e., filter 12), and the second chip U2 is connected to the second filter (i.e., filter 12); the first chip U1 is connected to the third filter (i.e., filter 13), and the second chip U2 is connected to the third filter (i.e., filter 13); the first chip U1 is connected to the fourth filter (i.e., filter 14), and the second chip U2 is connected to the fourth filter (i.e., filter 14); the first chip U1 is connected to the fifth filter (i.e., filter 15) and the second chip U2 is connected to the fifth filter (i.e., filter 15).

Considering the pin definition of the QPC6064 switch chip and its asymmetric peripheral structure, the truth table in table 4 is not symmetric, and the connection of the filter and the switch chips with the bit numbers of the first chip U1 and the second chip U2 is designed as shown in fig. 11. The 14 th (RF1) pin of the switch chip with the bit number of the first chip U1 is connected with the 1 port of the first filter, and the 24 th (RF6) pin of the switch chip with the bit number of the second chip U2 is connected with the 2 port of the first filter. Similarly, the 11 th (RF2) pin of the first chip U1 is connected to the 1 st port of the second filter, and the 2 nd (RF5) pin of the second chip U2 is connected to the 2 nd port of the second filter. The 8 th (RF3) pin of the first chip U1 is connected to the 1 st port of the third filter, and the 5 th (RF4) pin of the second chip U2 is connected to the 2 nd port of the third filter. The 5 th (RF4) pin of the first chip U1 is connected to the 1 st port of the fourth filter, and the 8 th (RF3) pin of the second chip U2 is connected to the 2 nd port of the fourth filter. The 2 nd (RF5) pin of the first chip U1 is connected to the 1 st port of the fifth filter, and the 11 th (RF2) pin of the second chip U2 is connected to the 2 nd port of the fifth filter.

As can be seen from the circuit schematic, the logic control portions of the two switches are processed separately, for a total of 6-bit binary numbers. The advantage of this layout is that the RF lines do not cross in the whole module, the design of the interconnections between boards is simplified, and the worst is to control the doubling of the pins. It is also possible to consider using a logic circuit to perform coding and decoding to control two switches simultaneously, but the circuit design is more complicated, the top layer area of the filter bank is limited, and the layout is not easy. If a mode that two switch chips share logic control is adopted, radio frequency wires are crossed certainly during layout, and a layer of strip line needs to be designed between a filter and a switch circuit of the whole switch filter bank to realize the crossing of the radio frequency wires.

The QPC6064 switch chip truth table is shown in table 4. Wherein "1" represents high level, and the voltage threshold range is 1.1V to VDD, and "0" represents low level corresponding to the voltage threshold range is 0 to 0.63V, compatible with CMOS level.

TABLE 4 QPC6064 switch chip truth table

Referring to the truth table of the QPC6064 switch chip and the switch filter bank schematic, the 6-bit truth table of the entire switch filter bank is shown in table 5.

Table 5 switch filter bank 6-bit truth table

The LTCC process and the printing process have good compatibility, and a printed circuit adopting the LTCC medium base material can be obtained by slightly changing the PCB process. The switching circuit portion based on the LTCC substrate is designed according to the flow when designing the PCB.

It will be appreciated that the entire switching circuit section is stacked above the filter bank, separated by a ground plane, to avoid signal cross talk and leakage. The filter part is composed of 10 layers of dielectric substrates. In order to normally transmit radio frequency signals, strip lines with characteristic impedance of 50 omega are adopted for input and output of the filter, and metal through holes are densely distributed at two ends of the strip lines. The metal through holes can play a good shielding role, can avoid the high-order mode parasitism of the strip line and inhibit the crosstalk among all channels. The strip line terminal is connected with a metal through hole and leads to the upper layer switch chip part. Simulation verification shows that the smaller the diameter of the metal through hole for connecting the strip line and the microstrip line is, the larger the window of the anti-pad on the upper floor of the strip line, namely the microstrip line floor is, the smaller the influence on the radio frequency signal is. Combining the process limit and the convenience of arranging the cloth plate, after comprehensive consideration, the diameter of the metal through hole is set to be 0.088mm, and the diameter of the window of the floor reverse bonding pad is 0.4 mm.

The application provides a filter bank, this filter bank includes: the filter comprises a device body and N filters arranged in the device body; one filter comprises M groups of resonators respectively, one group of resonators comprises Q resonators arranged in parallel, one group of resonators is arranged in parallel with other groups of resonators, and the other groups of resonators are except one group of resonators in the M groups of resonators; and each group of resonators is connected with the input end and the output end of the filter bank. Five filters and two PQC6064 switch chips are integrated to form a single-chip integrated switch filter bank, and layout arrangement layout is designed. The final layout has a finished volume of only 20mm x 30mm x 1.116 mm. The center frequency of the first filter is 2.59GHz, the bandwidth is 0.2GHz, the insertion loss in a pass band is better than 2.6dB, the out-of-band rejection is more than 30dB in the stop band range which is less than 2.28GHz and more than 2.9GHz, and the standing-wave ratio is better than 1.13. The center frequency of the second filter is 1,795GHz, the bandwidth is 0.17GHz, the insertion loss in a passband of a passband is better than 2.38dB, the out-of-band rejection is more than 30dB in the stop band range which is less than 1.38GHz and more than 2.08GHz, and the in-band standing wave ratio is better than 1.49; the center frequency of the third filter is 4.7GHz, the bandwidth is 0.6GHz, the insertion loss in a pass band is better than 2.15dB, the out-of-band rejection is better than 30dB in the stop band range which is less than 4.06GHz and more than 5.45GHz, and the in-band standing-wave ratio is 1.33; the center frequency of the fourth filter is 2.054GHz, the bandwidth is 0.2GHz, the insertion loss in a pass band is better than 2.02dB, the out-of-band rejection is better than 30dB in the stop band range which is less than 1.62GHz and more than 2.68GHz, and the in-band standing wave ratio is 1.51; the center frequency of the fifth filter is 3.75GHz, the bandwidth is 0.5GHz, the insertion loss in a pass band is better than 1.4dB, the out-band rejection is better than 30dB in the stop band range which is less than 2.58GHz and is more than 4.32GHz, and the in-band standing wave ratio is 1.49. The specific results are shown in fig. 12A and 12B. The multi-band antenna integrates the filters and the radio frequency switches, covers a plurality of 5G main common frequency bands, and only comprises two radio frequency interfaces and 6 logic interfaces except a power supply, so that the difficulty of PCB layout design is greatly reduced.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling an electronic device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present application.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.