阅读说明：本技术 集成电路装置中的抖动补偿 (Jitter compensation in integrated circuit devices ) 是由 陈继凯 唐永辉 饶远 黄焕章 范岩力 于 2020-10-19 设计创作，主要内容包括：本申请案涉及集成电路装置中的抖动补偿。一种抖动补偿电路(104)响应于数据的高到低转变及数据的低到高转变而在第一导电状态中操作。所述电路在不存在数据转变时在第二导电状态中操作。所述电路在所述第一导电状态中向电压供应补偿电荷,借此减小因数据转变造成的电压下降。(The application relates to jitter compensation in integrated circuit devices. Jitter compensation circuit 104) In a first conductive state in response to a high-to-low transition of data and a low-to-high transition of data And (4) carrying out the operation. The circuit is in a second conductive state in the absence of a data transition And (4) carrying out the operation. The circuit supplies a compensation charge to a voltage in the first conductive state, thereby reducing the contribution to data transitionsVoltage drop of 。)

1. A jitter compensation circuit, comprising:

a first transistor having a first terminal coupled to a first voltage supply and having a second terminal coupled to a second voltage supply, the first transistor having a gate terminal driven by a first gate voltage in response to a high-to-low transition of data to operate in a first conductive state and to operate in a second conductive state in the absence of a high-to-low transition of data;

a second transistor having a first terminal coupled to the first voltage supply and having a second terminal coupled to the second voltage supply, the second transistor having a gate terminal driven by a second gate voltage in response to a low-to-high transition of data to operate in the first conductive state and to operate in the second conductive state in the absence of a low-to-high transition of data;

a third transistor having a first terminal coupled to the first voltage supply and having a second terminal connected to a gate terminal;

a comparator having a first input coupled to the second voltage supply and having a second input coupled to a reference voltage, the comparator configured to generate a feedback control signal in response to the second voltage supply and the reference voltage; and

a current source coupled between the third transistor and ground, the current source configured to conduct a control current in response to the feedback control signal.

2. The jitter compensation circuit of claim 1, further comprising:

a first R-C circuit configured to generate the first gate voltage in response to the high-to-low transition of data and coupled to apply the first gate voltage to the gate terminal of the first transistor; and

a second R-C circuit configured to generate the second gate voltage in response to the low-to-high transition of data and coupled to apply the second gate voltage to the gate terminal of the second transistor.

3. The jitter compensation circuit of claim 2, wherein the first R-C circuit comprises a first resistor coupled to a first capacitor, and wherein the first R-C circuit is configured to control a duration of the first conductive state in response to the high-to-low transition of data.

4. The jitter compensation circuit of claim 2, wherein the second R-C circuit comprises a second resistor coupled to a second capacitor, and wherein the second R-C circuit is configured to control the duration of the first conductive state in response to the low-to-high transition of data.

5. The jitter compensation circuit of claim 1, wherein the first transistor and the second transistor are biased to operate in a linear region during the first conductive state and the second conductive state.

6. The jitter compensation circuit of claim 1, wherein the first transistor and the second transistor are biased to operate in a linear region, and wherein the first transistor and the second transistor conduct more current in the first conductive state than in the second conductive state.

7. The jitter compensation circuit of claim 1, wherein the comparator is configured to adjust the control current to cause the first transistor to operate in the second conductive state when there is no high-to-low transition of data and to cause the second transistor to operate in the second conductive state when there is no low-to-high transition of data.

8. The jitter compensation circuit of claim 1, wherein the first resistor is coupled between the gate terminal of the first transistor and the gate terminal of the third transistor, and wherein the second resistor is coupled between the gate terminal of the second transistor and the gate terminal of the third transistor.

9. The jitter compensation circuit of claim 1, wherein the first transistor and the second transistor mirror current in the third transistor when there are no data transitions.

10. The jitter compensation circuit of claim 1, wherein the first and second transistors mirror current in the third transistor when a voltage across the first and second resistors is zero.

11. The jitter compensation circuit of claim 1, wherein the low-to-high transition is a rising edge of the data transition, and wherein the high-to-low transition is a falling edge of the data transition.

12. A jitter compensation circuit, comprising:

a first MOSFET having a first terminal coupled to a first voltage supply and having a second terminal coupled to a second voltage supply, the first MOSFET having a gate terminal driven by a first gate voltage in response to a high-to-low transition of data to cause the first MOSFET to operate in a first conductive state and to operate in a second conductive state in the absence of a high-to-low transition of data;

a second MOSFET having a first terminal coupled to the first voltage supply and having a second terminal coupled to the second voltage supply, the second MOSFET having a gate terminal driven by a second gate voltage in response to a low-to-high transition of data to cause the second MOSFET to operate in the first conductive state and to operate in the second conductive state in the absence of a low-to-high transition of data;

a third MOSFET having a first terminal coupled to the first voltage supply and having a second terminal connected to a gate terminal;

a comparator having a first input coupled to the second voltage supply and having a second input coupled to a reference voltage, the comparator configured to generate a feedback control signal in response to the second voltage supply and the reference voltage;

a current source coupled between the third MOSFET and ground, the current source configured to conduct a control current in response to the feedback control signal;

a first resistor coupled between the gate terminal of the first MOSFET and the gate terminal of the third MOSFET;

a second resistor coupled between the gate terminal of the second MOSFET and the gate terminal of the third MOSFET,

wherein during the second conductive state the first and second MOSFETs mirror current in the third MOSFET, and wherein during the first conductive state current through the first and second MOSFETs charges the second voltage supply.

13. The jitter compensation circuit of claim 12, further comprising:

a first R-C circuit configured to generate the first gate voltage in response to the high-to-low transition of data and coupled to apply the first gate voltage to the gate terminal of the first MOSFET; and

a second R-C circuit configured to generate the second gate voltage in response to the low-to-high transition of data and coupled to apply the second gate voltage to the gate terminal of the second MOSFET.

14. The jitter compensation circuit of claim 13, wherein the first R-C circuit comprises a first capacitor coupled to the first resistor, and wherein the first R-C circuit is configured to control a duration of the first conductive state in response to the high-to-low transition of data.

15. The jitter compensation circuit of claim 13, wherein the second R-C circuit comprises a second capacitor coupled to the second resistor, and wherein the second R-C circuit is configured to control the duration of the first conductive state in response to the low-to-high transition of data.

16. The jitter compensation circuit of claim 13, wherein the comparator is configured to control current to operate the first MOSFET in the second conductive state when there is no high-to-low transition of data and to operate the second MOSFET in the second conductive state when there is no low-to-high transition of data.

17. The jitter compensation circuit of claim 13, wherein the low-to-high transition is a rising edge of a data transition, and wherein the high-to-low transition is a falling edge of the data transition.

18. A jitter compensation system, comprising:

a voltage regulator coupled to receive a first voltage supply and configured to generate a second voltage supply;

a closed-loop control circuit having a first input coupled to the second voltage supply and having a second input coupled to receive a reference voltage, the closed-loop control circuit configured to generate a feedback control signal in response to the second voltage supply and the reference voltage;

a charge compensation circuit having a first input coupled to receive a first gate voltage in response to a high-to-low transition of data and configured to operate in a first conductive state in response to the first gate voltage and a second conductive state in the absence of a high-to-low transition of data,

the charge compensation circuit has a second input coupled to receive a second gate voltage in response to a low-to-high transition of data, and is configured to operate in the first conductive state in response to the second gate voltage and in the second conductive state in the absence of a low-to-high transition of data,

the charge compensation circuit has a third input coupled to the first voltage supply and has a fourth input coupled to receive the feedback control signal,

the charge compensation circuit is configured to charge the second voltage supply during the first conductive state.

19. The jitter compensation system of claim 18, wherein the charge compensation circuit comprises:

a first MOSFET having a first terminal coupled to a first voltage supply and having a second terminal coupled to the second voltage supply, the first MOSFET having a gate terminal driven by the first gate voltage in response to the high-to-low transition of data such that the first MOSFET operates in the first conductive state and operates in the second conductive state in the absence of a high-to-low transition of data;

a second MOSFET having a first terminal coupled to the first voltage supply and having a second terminal coupled to the second voltage supply, the second MOSFET having a gate terminal driven by the second gate voltage in response to the low-to-high transition of data such that the second MOSFET operates in the first conductive state and operates in the second conductive state in the absence of a low-to-high transition of data;

a first resistor coupled between the gate terminal of the first MOSFET and a gate terminal of a third MOSFET;

a second resistor coupled between the gate terminal of the second MOSFET and the gate terminal of the third MOSFET,

wherein during the second conductive state the first and second MOSFETs mirror current through the third MOSFET, and wherein during the first conductive state current through the first and second MOSFETs charges the second voltage supply.

20. The jitter compensation system of claim 18, wherein the closed-loop control circuit comprises:

a comparator having a first input coupled to the second voltage supply and having a second input coupled to a reference voltage, the comparator configured to generate the feedback control signal in response to the second voltage supply and the reference voltage;

a current source coupled between the third MOSFET and ground, the current source configured to conduct a control current in response to the feedback control signal,

wherein a current in the third MOSFET is adjusted based on the control current, and wherein the first transistor and the second transistor mirror the current in the third MOSFET during the second conductive state.

21. The jitter compensation system of claim 20, further comprising:

a first R-C circuit configured to generate the first gate voltage in response to the high-to-low transition of data and coupled to apply the first gate voltage to the gate terminal of the first MOSFET; and

a second R-C circuit configured to generate the second gate voltage in response to the low-to-high transition of data and coupled to apply the second gate voltage to the gate terminal of the second MOSFET.

22. The jitter compensation system of claim 20, wherein the first R-C circuit comprises a first capacitor coupled to the first resistor, and wherein the first R-C circuit is configured to control the duration of the first conductive state in response to the high-to-low transition of data.

23. The jitter compensation system of claim 20, wherein the second R-C circuit comprises a second capacitor coupled to the second resistor, and wherein the second R-C circuit is configured to control the duration of the first conductive state in response to the low-to-high transition of data.

Technical Field

The present disclosure relates generally to jitter compensation in integrated circuit devices.

Background

High speed electrical devices such as USB 3, HDMI, and displayport are used in high speed data links. These high speed electrical devices are typically powered by a regulated power supply that provides a stable voltage supply (e.g., 5V, 3.3V, 1.8V) under ideal conditions. However, when a data transition occurs (e.g., low-to-high or high-to-low), the device requires an increased amount of current from the power supply. A sudden increase in current demand causes a transient load in the power supply. Since the power supply cannot meet the sudden rise in current demand, the supply voltage typically drops but later recovers, causing the supply voltage to fluctuate. Fluctuations in the supply voltage cause data transmission jitter. In high speed devices, jitter causes data transmission and reception uncertainty, which can lead to errors and system failures. One way to reduce jitter is to couple a large capacitor at the output of the power supply. However, large capacitors are expensive to implement in integrated circuits.

Disclosure of Invention

Aspects of the present invention are directed to a jitter compensation circuit. In one aspect, a jitter compensation circuit includes a first transistor having a first terminal coupled to a first voltage supply and having a second terminal coupled to a second voltage supply. The first transistor has a gate terminal driven by a first gate voltage in response to a high-to-low transition of data to operate in a first conductive state and operates in a second conductive state when there is no high-to-low transition of data. The circuit further includes a second transistor having a first terminal coupled to the first voltage supply and having a second terminal coupled to the second voltage supply. The second transistor has a gate terminal driven by a second gate voltage in response to a low-to-high transition of data to operate in the first conductive state and to operate in the second conductive state when there is no low-to-high transition of data. The circuit also includes a third transistor having a first terminal coupled to the first voltage supply and having a second terminal connected to a gate terminal. The circuit also includes a comparator having a first input coupled to the second voltage supply and having a second input coupled to a reference voltage. The comparator generates a feedback control signal in response to the second voltage supply and the reference voltage. The circuit also includes a current source coupled between the third transistor and ground. The current source conducts a control current in response to the feedback control signal. The circuit also includes a first R-C circuit configured to generate the first gate voltage in response to the high-to-low transition of data. The first R-C circuit is coupled to apply the first gate voltage to the gate terminal of the first transistor. The circuit also includes a second R-C circuit configured to generate the second gate voltage in response to the low-to-high transition of data. The second R-C circuit is coupled to apply the second gate voltage to the gate terminal of the second transistor. The first R-C circuit comprises a first resistor coupled to a first capacitor, wherein the first R-C circuit is configured to control a duration of the first conductive state in response to the high-to-low transition of data. The second R-C circuit comprises a second resistor coupled to a second capacitor, wherein the second R-C circuit is configured to control a duration of the first conductive state in response to the low-to-high transition of data. The first resistor is coupled between the gate terminal of the first transistor and the gate terminal of the third transistor. The second resistor is coupled between the gate terminal of the second transistor and the gate terminal of the third transistor. When there is no data transition, the first and second transistors mirror current in the third transistor.

In an additional aspect of the disclosure, a jitter compensation system includes a voltage regulator coupled to receive a first voltage supply and configured to generate a second voltage supply. The system further includes a closed loop control circuit having a first input coupled to the second voltage supply and having a second input coupled to receive a reference voltage. The closed loop control circuit generates a feedback control signal in response to the second voltage supply and the reference voltage. The system also includes a charge compensation circuit having a first input coupled to receive a first gate voltage in response to a high-to-low transition of data, and configured to operate in a first conductive state in response to the first gate voltage and a second conductive state in the absence of a high-to-low transition of data. The charge compensation circuit has a second input coupled to receive a second gate voltage in response to a low-to-high transition of data, and is configured to operate in the first conductive state in response to the second gate voltage and in the second conductive state in the absence of a low-to-high transition of data. The charge compensation circuit has a third input coupled to the first voltage supply and has a fourth input coupled to receive the feedback control signal. The charge compensation circuit charges the second voltage supply during the first conductive state.

Drawings

Fig. 1 is a block diagram of a jitter compensation system.

Fig. 2 is a schematic diagram of a compensation circuit.

Fig. 3 shows a voltage waveform of the regulated power supply.

Fig. 4 illustrates an eye diagram without and with the aid of a compensation circuit.

Detailed Description

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein some, but not all embodiments are shown. Indeed, in this document, the concepts may be embodied in different forms and should not be construed as limiting. Rather, these descriptions are provided so that this disclosure will satisfy applicable requirements.

Fig. 1 is a block diagram of a jitter compensation system 100 according to an exemplary embodiment. The jitter compensation system 100 includes a compensation circuit 104 coupled to a voltage regulator 108. In response to a high-to-low or low-to-high transition of data, the compensation circuit 104 compensates for the charge by providing a current to the output of the voltage regulator 108, thereby reducing the sudden voltage drop due to the data transition.

Referring to FIG. 1, the compensation circuit 104 has a first input 112, the first input 112 being coupled to receive a first gate voltage generated in response to a high-to-low transition of data. The compensation circuit 104 is configured to operate in a first conductive state in response to a first gate voltage and is configured to operate in a second conductive state when a high-to-low transition of data does not occur. A high-to-low transition of data refers to the falling edge of a data transition.

The compensation circuit 104 also has a second input 116, the second input 116 being coupled to receive a second gate voltage generated in response to a low-to-high transition of the data. The compensation circuit 104 is configured to operate in a first conductive state in response to a second gate voltage and is configured to operate in a second conductive state when no low-to-high transition of data occurs. A low-to-high transition of data refers to the rising edge of the data transition.

The compensation circuit 104 also has a third input 120 coupled to a first voltage supply 124 that may be provided by a power supply. The power supply may be an external power supply configured to power an Integrated Circuit (IC) or may be an internal supply built inside the IC.

With continued reference to fig. 1, the voltage regulator 108 has an input coupled to receive a first voltage supply 124. The voltage regulator 108 may be, for example, a dc-dc switching regulator that outputs a second voltage supply 132.

The system 100 includes a closed loop control circuit 136 having a first input 140 coupled to the second voltage supply 132. The closed loop control circuit 136 has a second input 144 coupled to receive a reference voltage 148. The closed loop control circuit 136 generates a feedback control signal 152 in response to the second voltage supply 132 and the reference voltage 148.

The compensation circuit 104 also has a fourth input 128 coupled to receive the feedback control signal. The feedback control signal biases the compensation circuit 104 to operate in the second conductive state in the absence of a low-to-high or high-to-low transition of data. When there is a data transition, the compensation circuit 104 operates in the first conductive state to replenish charge by providing current to the voltage regulator output, thus reducing the sudden voltage drop at the second voltage supply 132.

Fig. 2 is a more detailed schematic diagram of an exemplary jitter compensation circuit 104. The circuit 104 includes a transistor Q1 (e.g., a PMOS transistor), a transistor Q1 having a first terminal 204 (e.g., a source terminal) coupled to the first voltage supply 220 and having a second terminal 208 (e.g., a drain terminal) coupled to the second voltage supply 224. The transistor Q1 has a gate terminal 212 driven by a first gate voltage in response to a high-to-low transition of data. When a first gate voltage is applied to the gate terminal 212 in response to a high-to-low transition of data, the transistor Q1 operates in a first conductive state. When there is no high-to-low transition of the data, the first gate voltage is not applied to the gate terminal 212, and thus the first transistor Q1 operates in the second conductive state.

The circuit 104 also includes a transistor Q2 (e.g., a PMOS transistor), the transistor Q2 having a first terminal 230 (e.g., a source terminal) coupled to the first voltage supply 220 and having a second terminal 234 (e.g., a drain terminal) coupled to the second voltage supply 224. Transistor Q2 has a gate terminal 238 driven by a second gate voltage in response to a low-to-high transition of data. When the second gate voltage is applied to the gate terminal 238 of the transistor Q2 in response to a low-to-high transition of data, the transistor Q2 operates in a first conductive state. When there is no low-to-high transition of the data, the second gate voltage is not applied to the gate terminal 238, and thus the transistor Q2 operates in the second conductive state.

The circuit 104 also includes a transistor Q3 (e.g., a PMOS transistor), the transistor Q3 having a first terminal 240 (e.g., a source terminal) coupled to the first voltage supply 220 and having a second terminal 244 (e.g., a drain terminal) connected to its gate terminal 248.

The circuit 104 also includes a comparator 252, the comparator 252 having a first input 256 coupled to the second voltage supply 224 and having a second input 260 coupled to a reference voltage 264. The comparator 252 generates the feedback control signal 268 in response to the second voltage supply 224 and the reference voltage 264. The circuit 104 also includes a current source 272 coupled between the transistor Q3 and ground. The current source 272 conducts a control current in response to the feedback control signal 268.

With continued reference to FIG. 2, the circuit 104 also includes a first R-C circuit 276, the first R-C circuit 276 including a capacitor C1 and a resistor R1. The first R-C circuit 276 may be coupled to data via a buffer 278. The first R-C circuit 276 generates a first gate voltage in response to a high-to-low transition of data. More specifically, the high-to-low transition of the data reverse biases the gate-to-source voltage of transistor Q1 (a PMOS transistor), causing transistor Q1 to operate in a first conductive state. The first R-C circuit 276 has a decay time determined by R1 and C1 that determines the duration (i.e., time period) of the first conductive state of the transistor Q1.

The circuit 104 also includes a second R-C circuit 280, the second R-C circuit 280 including a capacitor C2 and a resistor R2. The second R-C circuit 280 may be coupled to data via an inverting buffer 282. The second R-C circuit 280 generates a second gate voltage in response to a low-to-high transition of data. More specifically, the low-to-high transition of the data reverse biases the gate-to-source voltage of transistor Q2 (a PMOS transistor), causing transistor Q2 to operate in a first conductive state. The second R-C circuit 280 has a decay time determined by R2 and C2 that determines the duration (i.e., time period) of the first conductive state of the transistor Q2.

According to an embodiment of the present invention, the resistor R1 is coupled between the gate terminal 212 of the transistor Q1 and the gate terminal 248 of the transistor Q3, and the resistor R2 is coupled between the gate terminal 238 of the transistor Q2 and the gate terminal 248 of the transistor Q3. If no high-to-low or low-to-high transition of the data occurs, the voltage across resistors R1 and R2 remains close to zero. Thus, when no data transition occurs, the three gate terminals 212, 238 and 248 remain at approximately the same potential, causing transistors Q1 and Q2 to mirror the current in transistor Q3. Since the current in transistor Q3 is regulated by current source 272, the current in transistors Q1 and Q2 is controlled by current source 272 when no data transition occurs.

According to an embodiment of the present invention, both the first and second conductive states are in the linear operating region of the PMOS transistor. However, the transistors Q1 and Q2 conduct more current in the first conductive state in response to the data transition than in the second conductive state when no data transition occurs.

Thus, without data transitions, both transistors Q1 and Q2 operate in the second conductive state, and in the second conductive state, transistors Q1 and Q2 mirror the current in transistor Q3. When a high-to-low transition of data occurs, transistor Q1 operates in the first conductive state and outputs a supplemental charge to the voltage regulator, which reduces the sudden voltage drop. Similarly, when a low-to-high transition of data occurs, transistor Q2 operates in the first conductive state and outputs a supplemental charge to the voltage regulator to reduce the sudden voltage drop. However, the duration of the first conductive state of transistors Q1 and Q2 is limited by the decay time of the R-C circuits 276 and 280. Specifically, the decay time of the first R-C circuit 276 limits the duration of the first conductive state of the transistor Q1, causing the transistor Q1 to return to the second conductive state. Similarly, the decay time of the second R-C circuit 280 limits the duration of the first conductive state of the transistor Q2, causing the transistor Q2 to return to the second conductive state.

FIG. 3 shows the output voltage waveform of a regulated power supply without a compensation circuit and with the assistance of a compensation circuit. At a data rate of 10Gbps, low-to-high and high-to-low transitions of data cause the output voltage to drop excessively without the help of compensation circuits. However, when the compensation circuit is added, the output voltage drop is greatly reduced.

Fig. 4 illustrates the eye diagram of the dither without the compensation circuit and the eye diagram of the dither with the aid of the compensation circuit. Without the compensation circuit, the jitter is about 10.1ps, but with the addition of the compensation circuit, the jitter is reduced to 7.1 ps.

Various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. While the described functionality may be implemented in varying ways for each particular application, such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

For simplicity and clarity, the full structure and operation of all systems suitable for use with the present invention is not depicted or described herein. Instead, only the portions of the system that are unique to the present invention or necessary for an understanding of the present invention are depicted and described.