阅读说明：本技术 横向双扩散金属氧化物半导体器件 (Lateral double-diffused metal oxide semiconductor device ) 是由 祝靖 朱桂闯 何乃龙 张森 李少红 孙伟锋 时龙兴 于 2019-10-21 设计创作，主要内容包括：本发明涉及一种横向双扩散金属氧化物半导体器件包括：漂移区,具有第一导电类型；第一体区,设于所述漂移区上,具有第二导电类型；所述第一导电类型和第二导电类型为相反的导电类型；第一导电类型区,设于所述第一体区内；第二体区,设于所述第一导电类型区内,具有第二导电类型；源极区,设于所述第二体区内,具有第一导电类型；接触区,设于所述第一体区内,具有第二导电类型。本发明解决了LDMOS的体二极管在反向恢复期间,因寄生NPN开启导致的反向恢复失效问题,并且不需要设置沟槽隔离结构。(The invention relates to a lateral double-diffused metal oxide semiconductor device, comprising: a drift region having a first conductivity type; the first body region is arranged on the drift region and has a second conduction type; the first conductivity type and the second conductivity type are opposite conductivity types; a first conductive type region disposed in the first body region; the second body region is arranged in the first conduction type region and has a second conduction type; a source region disposed in the second body region and having a first conductivity type; and the contact region is arranged in the first body region and has a second conduction type. The invention solves the problem of reverse recovery failure caused by the turn-on of the parasitic NPN during the reverse recovery period of the body diode of the LDMOS, and does not need to be provided with a trench isolation structure.)

1. A lateral double diffused metal oxide semiconductor device, comprising:

a drift region having a first conductivity type;

the first body region is arranged on the drift region and has a second conduction type; the first conductivity type and the second conductivity type are opposite conductivity types;

a first conductive type region disposed in the first body region;

the second body region is arranged in the first conduction type region and has a second conduction type;

a source region disposed in the second body region and having a first conductivity type;

and the contact region is arranged in the first body region and has a second conduction type.

2. The laterally double diffused metal oxide semiconductor device of claim 1 further comprising a drain region disposed on the drift region.

3. The laterally double diffused metal oxide semiconductor device of claim 2 further comprising a buffer region disposed on the drift region, the buffer region having the first conductivity type, the buffer region being disposed within the drift region.

4. The LDMOS device of claim 2 or 3, further comprising a gate disposed between the source and drain regions.

5. The laterally double diffused metal oxide semiconductor device of claim 4 further comprising a field oxide layer disposed between the source and drain regions, the gate comprising a polysilicon gate extending from over the source region to over the field oxide layer.

6. The laterally double diffused metal oxide semiconductor device of claim 4 wherein the first conductivity type is N-type and the second conductivity type is P-type.

7. The ldmos device set forth in claim 6 wherein said device is equivalent to having a first MOS transistor, a second MOS transistor, a body diode and a parasitic NPN transistor, the gates of said first and second MOS transistors comprising said polysilicon gate, the sources of said first and second MOS transistors comprising said first conductivity type region, the drain of said first MOS transistor comprising said drain region, the source of said second MOS transistor comprising said source region, the cathode of said body diode comprising said drift region, the anode of said body diode comprising said first body region, the base of said parasitic NPN transistor comprising said first body region, the collector comprising said drift region, the emitter comprising said first conductivity type region.

8. The lateral double diffused metal oxide semiconductor device of claim 3 wherein the drift and buffer regions have a doping concentration lower than the source and drain regions.

9. The laterally double diffused metal oxide semiconductor device of claim 1 further comprising a substrate of a second conductivity type and a buried oxide layer on the substrate, the drift region being disposed on the buried oxide layer.

10. The lateral double diffused metal oxide semiconductor device of claim 1 wherein the doping concentration of the first body region is lower than the doping concentration of the contact region.

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a lateral double-diffusion metal oxide semiconductor device.

Background

A body diode is present inside an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device. However, during the reverse recovery of the body diode, when the holes in the drift region are pumped back to the source electrode through the P-body and the source region P +, a certain voltage drop is generated between the P-body and the source region N + due to the resistance of the P-body region, and when the voltage drop is larger than the forward conduction voltage drop of the PN junction formed by the P-body and the source region N +, the parasitic NPN formed by the source region N +, the P-body and the N-drift is turned on, so that the current is increased sharply, and the phenomenon of reverse recovery failure occurs. As shown in fig. 4, the broken line indicates reverse recovery normal, and the solid line indicates reverse recovery failure.

If the device is failed in reverse recovery, other devices may be damaged in the application of the circuit, and the safety and reliability of the device and the circuit are seriously affected.

Disclosure of Invention

Based on this, it is necessary to provide a lateral double-diffused metal oxide semiconductor device capable of solving the problem of reverse recovery failure.

A lateral double diffused metal oxide semiconductor device comprising: a drift region having a first conductivity type; the first body region is arranged on the drift region and has a second conduction type; the first conductivity type and the second conductivity type are opposite conductivity types; a first conductive type region disposed in the first body region; the second body region is arranged in the first conduction type region and has a second conduction type; a source region disposed in the second body region and having a first conductivity type; and the contact region is arranged in the first body region and has a second conduction type.

In one embodiment, the transistor further comprises a drain region arranged on the drift region.

In one embodiment, the drift region further comprises a buffer region disposed on the drift region, the buffer region having the first conductivity type, the buffer region being disposed in the drift region.

In one embodiment, the semiconductor device further comprises a gate electrode arranged between the source region and the drain region.

In one embodiment, the field oxide layer is disposed between the source region and the drain region, and the gate includes a polysilicon gate extending from above the source region to above the field oxide layer.

In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

In one embodiment, the device is equivalent to a device having a first MOS transistor, a second MOS transistor, a body diode and a parasitic NPN transistor, gates of the first and second MOS transistors include the polysilicon gate, a source of the first MOS transistor and a drain of the second MOS transistor include the first conductivity-type region, the drain of the first MOS transistor includes the drain region, the source of the second MOS transistor includes the source region, a cathode of the body diode includes the drift region, an anode of the body diode includes the first body region, a base of the parasitic NPN transistor includes the first body region, a collector of the parasitic NPN transistor includes the drift region, and an emitter of the parasitic NPN transistor includes the first conductivity-type region.

In one embodiment, the doping concentration of the drift region and the buffer region is lower than the doping concentration of the source region and the drain region.

In one embodiment, the semiconductor device further comprises a substrate of the second conduction type and a buried oxide layer on the substrate, wherein the drift region is arranged on the buried oxide layer.

In one embodiment, the doping concentration of the first body region is lower than the doping concentration of the contact region.

In the lateral double-diffused metal oxide semiconductor device, the source region is separated from the first body region by the second body region and the first conductive type region. Therefore, during the reverse recovery period of the body diode of the LDMOS, even if a certain voltage drop is generated between the first body region and the source region when holes in the drift region are extracted back to the source electrode through the first body region and the contact region, electrons cannot be injected into the first body region through the source region; and holes can be extracted back to the source electrode through the contact region, and a parasitic NPN formed by the source region, the first body region and the drift region cannot be started, so that the problem of reverse recovery failure caused by the startup of the parasitic NPN during the reverse recovery period of the body diode of the LDMOS is solved.

Drawings

For a better understanding of the description and/or illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and/or examples, and the presently understood best modes of these inventions.

FIG. 1 is a schematic cross-sectional view of an exemplary lateral double diffused metal oxide semiconductor device;

FIG. 2 is an equivalent circuit diagram of the device shown in FIG. 1;

FIG. 3 is a schematic cross-sectional view of an exemplary lateral double diffused metal oxide semiconductor device;

FIG. 4 is an exemplary current curve for body diode reverse recovery normal and reverse recovery failure of the LDMOS;

FIG. 5 is an equivalent circuit diagram of the device shown in FIG. 3;

FIG. 6 is a graph of voltage withstand characteristics of the present application and a conventional lateral double diffused metal oxide semiconductor device;

FIG. 7 is a graph of turn-on capability characteristics of the present application and a conventional lateral double diffused metal oxide semiconductor device;

FIG. 8 is the reverse recovery current (I) at the same freewheel current value_DS) Curve over time.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

For a device with a large working current, the requirement on the on-resistance is high, and the resistance of the device needs to be reduced under the condition of ensuring the breakdown voltage. Generally, the on-resistance is reduced by adjusting the doping concentration of the drift region, but the increase of the doping concentration may cause the breakdown voltage to decrease, so that an additional structure is required to ensure the breakdown voltage, such as a field plate and an STI (shallow trench isolation) technology; in addition, the current flow path in the drift region can be adjusted by reducing the length of the drift region even if the current path in the drift region is shortened. Many related novel structures are derived from these aspects, such as RESURF (reduced surface electric field) technology and piecewise linear doping technology. However, these structures reduce the on-resistance and also reduce the breakdown voltage, and extra measures are required to ensure that both reach the design index, so that the overall structure of the device is greatly modified.

Fig. 1 is a schematic cross-sectional view of an exemplary lateral double diffused metal oxide semiconductor device, and fig. 2 is an equivalent circuit diagram of fig. 1. An exemplary lateral double-diffused metal oxide semiconductor device comprises a P-type substrate (P-sub), a buried oxide layer (BOX), a drift region (N-drift), a body region (P-body), a buffer region (N-buffer), a drain region N +, a source region N + and a source region P +. Referring to fig. 2, a gate, a source, and a drain of the LDMOS are denoted by g, s, and D, respectively, and a body diode D formed by a body region and a drift region plays a dominant role during a freewheeling period of the device, however, during a reverse recovery period of the body diode D, when holes in the drift region are extracted back to a source electrode through the body region and a source region P +, a certain voltage drop is generated between the body region and a source region N + due to the existence of a body region resistor Rs, and when the voltage drop is greater than a forward conduction voltage drop of a PN junction formed by the body region and the source region N +, a parasitic NPN formed by the source region N +, the body region, and the drift region is turned on, so that a current is increased sharply, and a reverse recovery failure occurs, as shown. An exemplary solution is to use trench isolation technology, however, the device size becomes large, the process is costly and complex, and the condition limitation is sometimes difficult to achieve.

Fig. 3 is a schematic cross-sectional view of an embodiment of a lateral double diffused mos device, which includes a drift region 3, a first body region 10, a first conductivity type region 13, a second body region 12, a source region 11, and a contact region 9. The drift region 3 has a first conductivity type. The first conductivity type region 13 is disposed within the first body region 10. The second body region 12 is provided in the first conductive type region 13, and has a second conductive type. The source region 11 is disposed in the second body region 12 and has the first conductivity type. The contact region 9 is arranged in the first body region 10 and has the second conductivity type.

In the embodiment shown in fig. 3, the first conductivity type is N-type and the second conductivity type is P-type; specifically, the drift region 3 is an N-type drift region N-drift, the first body region 10 and the second body region 12 are both P-type body regions, the first conductive type region 13 is an N-type isolation layer capable of performing an isolation function in the present application, the source region 11 is a source region N-type heavily doped N + region, and the contact region 9 is a source region P-type heavily doped P + region. In another embodiment, the first conductivity type may be P-type and the second conductivity type may be N-type.

In the above-described lateral double-diffused metal oxide semiconductor device, the source region 11 is isolated from the first body region 10 by the second body region 12 and the first conductivity type region 13. Thus, during the body diode reverse recovery of the LDMOS, even if a certain voltage drop is generated between the first body region 10 and the source region 11 when holes in the drift region 3 are extracted back to the source via the first body region 10 and the contact region 9, electrons cannot be injected into the first body region 10 via the source region 11; and holes can be extracted back to the source electrode through the contact region 9, and a parasitic NPN formed by the source region 11, the first body region 10 and the drift region 3 cannot be started, so that the problem of reverse recovery failure caused by the startup of the parasitic NPN during the reverse recovery period of the body diode of the LDMOS is solved.

In the embodiment shown in fig. 3, the lateral double diffused metal oxide semiconductor device further comprises a drain region 5 provided on the drift region 3. Specifically, the drain region 5 is a drain region N-type heavily doped N + region.

In the embodiment shown in fig. 3, the ldmos device further comprises a buffer region 4 disposed on the drift region 3, the buffer region 4 being disposed in the drift region 3, the buffer region 4 having the first conductivity type.

In the embodiment shown in fig. 3, the lateral double diffused metal oxide semiconductor device further comprises a substrate 1 of the second conductivity type and a buried oxide layer 2 on the substrate, the drift region 3 being provided on the buried oxide layer. In particular, the substrate 1 is P-sub.

In one embodiment, the lateral double diffused metal oxide semiconductor device further comprises a gate electrode provided between the source region 11 and the drain region 5. In the embodiment shown in fig. 3, the ldmos device further comprises a field oxide layer 7 disposed between the source region 11 and the drain region 5, and the gate comprises a polysilicon gate 8 extending from above the source region 11 to above the field oxide layer 7. The polysilicon gate 8 passes from the source region 11, over the second body region 12, over the first conductivity type region 13, over the first body region 10, and then extends over the field oxide layer 7. In the embodiment shown in fig. 3, the contact region 9 is separated from the first conductivity type region 13 by the first body region 10.

In one embodiment, the doping concentration of the drift region 3 and the buffer region 4 is lower than the doping concentration of the source region 11 and the drain region 5.

In an embodiment the doping concentration of the first body region 10 is lower than the doping concentration of the contact region 9.

Referring to fig. 5, in this embodiment, the ldmos device is equivalent to a device having a first MOS transistor, a second MOS transistor, a body diode D and a parasitic NPN transistor. Referring to fig. 3, the polysilicon gate 8 serves as the gate g of the first MOS transistor and the second MOS transistor, the first conductive type region 13 serves as the source S1 of the first MOS transistor, the drain D2 of the second MOS transistor, and the emitter of the parasitic NPN transistor, the drain region 5 serves as the drain D1 of the first MOS transistor, the source region 11 serves as the source S2 of the second MOS transistor, the drift region 3 serves as the cathode of the body diode D and the collector of the parasitic NPN transistor, and the first body region 10 serves as the anode of the diode D and the base of the parasitic NPN transistor. The first body region 10 is also equivalent to a body resistance Rs. When the grid electrode of the device is connected with a high potential, the drain electrode of the device is connected with a high potential, and the source electrode of the device is connected with a low potential, the first body region 10 and the second body region 12 below the polysilicon gate 8 can be inverted normally to form an electronic channel, so that the LDMOS can be turned on in the forward direction. When the grid electrode is connected with a low potential, the drain electrode is connected with a high potential, and the source electrode is connected with a low potential, the channel is cut off, and the body diode D formed by the first body region 10 and the drift region 3 in the device carries out voltage resistance. When the grid electrode and the source electrode are in short circuit with high potential, the drain electrode is connected with low potential, a body diode D formed by the first body region 10 and the drift region 3 in the device is conducted, and the device can carry out follow current. In summary, the operation state and operation condition of the lateral double-diffused metal oxide semiconductor device are completely consistent with those of the conventional LDMOS.

FIG. 6 is a graph of voltage withstanding characteristics of the LDMOS device of the present application and the conventional LDMOS device, with the abscissa and ordinate representing the voltage V across the drain and source terminals of the channel turn-off_DSAnd the current I flowing through_DS(ii) a FIG. 7 is a graph of the turn-on capability of the LDMOS device of the present application and the conventional LDMOS device, with the abscissa and ordinate representing the voltage V across the drain and source with the channel turned on_DSAnd the current I flowing through_DS. It can be seen that the conduction capability and the voltage withstanding characteristic of the lateral double-diffused metal oxide semiconductor device are hardly sacrificed on the premise of solving the problem of reverse recovery failure of the body diode. Compared with the scheme that the problem of reverse recovery failure of the body diode is solved by arranging the trench isolation structure, the method and the device have the advantages that the trench isolation structure is not required to be arranged, the process is simple, the process compatibility is high, and the size of the device is reduced. FIG. 8 shows the reverse recovery current (I) at the same freewheeling current_DS) The time-varying curve, di/dt 105A/mus, is a conventional ldmos device, and it can be seen that the conventional structure suffers from reverse recovery failure when di/dt 105A/mus. The other three curves are the lateral double-diffused metal oxide semiconductor device of the present application, and it can be seen that no reverse recovery failure occurs when di/dt is 536A/μ s, and the reverse recovery robustness of the LDMOS body diode is greatly improved.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.