阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 黄崇祐 林柏青 曹太和 于 2019-11-04 设计创作，主要内容包括：一种半导体装置,包含一有源区结构、至少一栅极及至少一隔离结构。有源区结构沿第一方向设置。至少一栅极配置在有源区结构之上并沿第二方向延伸。第二方向不同于第一方向。至少一隔离结构配置在有源区结构之内。在第二方向上,至少一隔离结构的长度小于有源区结构的宽度。(A semiconductor device comprises an active region structure, at least one grid and at least one isolation structure. The active region structure is disposed along a first direction. At least one gate is disposed over the active region structure and extends along a second direction. The second direction is different from the first direction. At least one isolation structure is disposed within the active region structure. In the second direction, the length of at least one isolation structure is smaller than the width of the active region structure.)

1. A semiconductor device, comprising:

an active region structure arranged along a first direction;

at least one gate electrode disposed on the active region structure and extending along a second direction different from the first direction; and

at least one isolation structure disposed within the active region structure, wherein a length of the at least one isolation structure is less than a width of the active region structure in the second direction.

2. The semiconductor device according to claim 1, further comprising:

at least one first metal structure configured above the active region structure as a source of a transistor; and

at least one second metal structure configured above the active region structure as a drain of the transistor;

wherein the at least one gate and the at least one isolation structure are located between the at least one first metal structure and the at least one second metal structure.

3. The semiconductor device of claim 1, wherein a portion of the at least one isolation structure is located below the at least one gate.

4. The semiconductor device according to claim 1, further comprising:

and the at least one polysilicon structure is arranged on the active region structure, is mutually connected with the at least one isolation structure and spans two sides of the active region structure parallel to the first direction.

5. The semiconductor device of claim 1, wherein the active region structure comprises a first region having a surface covered with silicide and at least a second region having a surface uncovered with silicide, wherein the at least a second region is interconnected with the at least an isolation structure and spans two sides of the active region structure parallel to the first direction.

6. The semiconductor device of claim 1, further comprising at least one polysilicon structure disposed over the active area structure, the active area structure comprising a first region having a surface covered with silicide and at least one second region having a surface not covered with silicide, wherein the at least one second region, the at least one polysilicon structure and the at least one isolation structure are interconnected and span both sides of the active area structure parallel to the first direction.

7. The semiconductor device of claim 6, wherein the at least one isolation structure, the at least one polysilicon structure, and the at least one second region are not aligned with one another in the second direction.

8. The semiconductor device of claim 1, wherein said at least one isolation structure comprises:

a plurality of isolation structures, the isolation structures not connected to each other.

9. The semiconductor device of claim 1, wherein the active region structure comprises:

a first well of a first type;

a second well of a second type adjacent to the first well;

a first doped region of the second type located within the first well; and

a second doped region of the second type located within the second well;

wherein the at least one gate is located above the first well and the second well, the at least one isolation structure is located in the second well, and a surface of the second doped region is not completely covered with silicide.

10. A semiconductor device, comprising:

an active region structure arranged along a first direction;

at least one gate electrode disposed on the active region structure and extending along a second direction different from the first direction;

at least one first metal structure configured above the active region structure as a source of a transistor;

at least one second metal structure configured above the active region structure as a drain of the transistor; and

at least one polysilicon structure disposed over the active region structure;

the active area structure comprises a first area with a surface covered with silicide and at least one second area with a surface uncovered with silicide, wherein the at least one second area and the at least one polysilicon structure are connected with each other and cross two sides of the active area structure parallel to the first direction.

Technical Field

The present disclosure relates to semiconductor devices, and more particularly, to Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices.

Background

As the process advances, the conventional mosfet structure has insufficient voltage endurance for the integrated application of power chips. Laterally Diffused Metal Oxide Semiconductors (LDMOS) are widely used for semiconductor integrated circuits due to their high power and high voltage characteristics.

However, the on-state current of the ldmos is low and the resistance is high, which often requires more area to compensate. Therefore, how to design the ldmos under the condition of limited size is an important issue.

Disclosure of Invention

One aspect of the present disclosure relates to a semiconductor device including an active region structure, at least one gate, and at least one isolation structure. The active region structure is disposed along a first direction. At least one gate is disposed over the active region structure and extends along a second direction. The second direction is different from the first direction. At least one isolation structure is disposed within the active region structure. In the second direction, the length of at least one isolation structure is smaller than the width of the active region structure.

Another aspect of the present disclosure relates to another semiconductor device including an active region structure, at least one gate, at least one first metal structure, at least one second metal structure, and at least one polysilicon structure. The active region structure is arranged along a first direction. At least one gate is disposed over the active region and extends along a second direction. The second direction is different from the first direction. At least one first metal structure is configured above the active region structure and used as a source electrode of the transistor. At least one second metal structure is configured above the active region structure and used as a drain electrode of the transistor. At least one polysilicon structure is disposed over the active region structure. The active area structure comprises a first area with the surface covered with silicide and at least one second area with the surface uncovered with silicide. The at least one second region and the at least one polysilicon structure are connected to each other and cross two sides of the active region structure parallel to the first direction.

Drawings

Fig. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of another semiconductor device according to an embodiment of the present disclosure.

Fig. 3, 4 are cross-sectional views of the semiconductor device of fig. 2, according to embodiments of the present disclosure.

Fig. 5A, 5B, and 5C are schematic views of another semiconductor device according to an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of another semiconductor device according to an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of a method for fabricating the semiconductor device of fig. 6, in accordance with an embodiment of the present disclosure.

Fig. 8 is a schematic diagram of another semiconductor device according to an embodiment of the present disclosure.

Fig. 9 is a cross-sectional view of the semiconductor device in fig. 2, in accordance with an embodiment of the present disclosure.

Fig. 10 is a schematic diagram of another semiconductor device according to an embodiment of the present disclosure.

Fig. 11 is a schematic diagram of another semiconductor device according to an embodiment of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. Repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Additionally, spatially relative terms, such as "below … …," "below … …," "below," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Please refer to fig. 1. Fig. 1 is a schematic diagram of a semiconductor device 100a according to an embodiment of the disclosure. As shown in fig. 1, the semiconductor device 100a includes an active region structure 110, gate electrodes 121 and 122, and metal structures 151, 152, and 153. Gate electrodes 121 and 122 and metal structures 151, 152 and 153 are disposed over active region structure 110. Gate 121 is located between metal structures 151 and 152 and gate 122 is located between metal structures 152 and 153. In some embodiments, metal structures 151 and 153 serve as sources of transistors, and metal structure 152 serves as a drain of transistors. In the present disclosure, a line direction of a source and a drain of a transistor is defined as a first direction. In other words, the first direction is the direction of the on-current of the transistor.

In some embodiments, as shown in fig. 1, the first direction is an X direction, the active region structure 110 is disposed along the first direction, and the gates 121 and 122 extend along a second direction different from the first direction. In some embodiments, the second direction and the first direction are perpendicular to each other, such as the X direction and the Y direction are perpendicular to each other as shown in fig. 1, but the invention is not limited thereto.

Specifically, the active region structure 110 includes a first active region 111 of a first type, and a second active region 112 of a second type. The gates 121 and 122 are disposed above the junction of the first active region 111 and the second active region 112 and extend from one S1 to the other S2 on two sides of the active region structure 110 parallel to the first direction.

For example, as shown in fig. 1, a first active region 111 of a first type includes regions 101 and 105. A second active region 112 of a second type comprises regions 102, 103 and 104. The region 101 of the first active region 111 is disposed at the left side of the gate electrode 121. Regions 102, 103 and 104 of second active region 112 are disposed between the right side of gate 121 and the left side of gate 122. While the region 105 of the first active region 111 is disposed to the right of the gate 122. Furthermore, metal structure 151 is disposed over region 101, metal structure 152 is disposed over region 103, and metal structure 153 is disposed over region 105.

In some embodiments, the first type is P-type and the second type is N-type. However, the disclosure is not limited to the above types, and it is within the scope of the disclosure to configure the first type and the second type with other suitable types. In addition, in some embodiments, the gate is made of polysilicon material.

In some embodiments, the semiconductor device 100a further includes isolation (STI) structures 131a and 132 a. As shown in fig. 1, the isolation structures 131a and 132a are disposed within the active area structure 110. The isolation structure 131a is disposed between the gate 121 and the metal structure 152, and the isolation structure 132a is disposed between the gate 122 and the metal structure 152. Specifically, the length L1 of the isolation structures 131a and 132a in the second direction is less than the width L0 of the active area structure 110 in the second direction.

In this way, the isolation structures 131a and 132a can improve the breakdown voltage of the semiconductor device 100a, and since the length of the isolation structures 131a and 132a is smaller than the width of the active region structure 110 in the second direction, the current between the source and the drain is not completely blocked in the first direction, and a part of the current can pass through the part where no isolation structure is provided, so that the overall on-state current can be improved.

In some embodiments, the semiconductor device 100a further includes polysilicon (polysilicon) structures 141 a-144 a. As shown in fig. 1, polysilicon structures 141 a-144 a are disposed over active region structure 110. The polysilicon structures 141a, 143a and the isolation structure 131a are connected to each other, disposed between the gate 121 and the metal structure 152, and extend from one S1 to the other S2 on two sides of the active region structure 110 parallel to the first direction. Similarly, the polysilicon structures 142a, 144a and the isolation structure 132a are connected to each other, disposed between the gate 122 and the metal structure 152, and extend from one S1 to the other S2 on two sides of the active region structure 110 parallel to the first direction. Specifically, the polysilicon structure 141a is connected between the isolation structure 131a and the side S1 of the active area structure 110. The polysilicon structure 143a is connected between the isolation structure 131a and the other side S2 of the active area structure 110.

As such, the polysilicon structures 141a, 143a and the isolation structure 131a will partition the surface of the active area structure 110 into the regions 102 and 103 along the second direction, and the polysilicon structures 142a, 144a and the isolation structure 132a will partition the surface of the active area structure 110 into the regions 103 and 104 along the second direction. In other words, the left side of the isolation structure 131a and the right side of the gate 121 are the regions 102. Between the right side of isolation structure 131a and the left side of isolation structure 132a is region 103. Between the right side of the isolation structure 132a and the left side of the gate 122 is a region 104.

Since the isolation structure or the polysilicon structure is formed without Silicide (Silicide), when the conduction current is concentrated to the position without the isolation structure 131a or 132a (i.e. under the polysilicon structures 141 a-144 a), the conduction current will not be attracted by the Silicide surface with better conductivity. In other words, by interconnecting the isolation structure and the polysilicon structure in the second direction and crossing the two sides S1 and S2 of the active region structure 110, the structure can be prevented from being damaged by over-concentrated current due to silicide attraction.

It is noted that the isolation structures 131a, 132a and the polysilicon structures 141 a-144 a shown in fig. 1 are for illustration only and are not intended to limit the present invention. The shape, size, location and number of the isolation structures and the polysilicon structures included in the semiconductor device 100a may be adjusted and designed according to actual requirements, as will be described in the following paragraphs. For simplicity of description, components in the following embodiments similar to those in the embodiment of fig. 1 are denoted by the same reference numerals, and the content thereof is not repeated by the description in the previous paragraphs. In addition, when the following embodiments are left-right symmetrical structures, only one side will be described, and the structure of the other side will not be described again.

In some embodiments, as shown in FIG. 2, the semiconductor device 100b may include a plurality of isolation structures 131 b-134 b and associated polysilicon structures 141 b-146 b. Specifically, the polysilicon structures 141b, 143b, and 145b and the isolation structures 131b and 133b are staggered and connected to each other and cross both sides S1 and S2 of the active area structure 110. Wherein polysilicon structure 141b connects one side S1 of source region structure 110 and isolation structure 131 b. Polysilicon structure 145b connects isolation structures 131b and 133 b. The polysilicon structure 143b connects the isolation structure 133b and the other side S2 of the active area structure 110.

As such, since the sum of the lengths of the isolation structures 131b and 133b (L2+ L3) is less than the width L0 of the active region structure 110 in the second direction. Therefore, in the first direction, a part of the current can pass through the portion where the isolation structures 131b and 133b are not disposed (i.e., below the polysilicon structures 141b, 143b, and 145 b), so that the overall on-current can be increased. In addition, since the length and position distribution of the isolation structures 131b and 133b and the polysilicon structures 141b, 143b and 145b in the second direction are more uniform, the distribution of the on-current may be more uniform.

In further detail, please refer to fig. 3 and 4. Fig. 3 and 4 are cross-sectional views of the semiconductor device 100B taken along cut lines a1-a1 'and B1-B1', respectively, in the embodiment of fig. 2 according to the present disclosure. As shown in fig. 3, the active region structure 110 of the semiconductor device 100b includes a first well W1 having a first type, a second well W2 adjacent to the first well W1 and having a second type, a third well W3 adjacent to the second well W2 and having the first type, a first doped region D1 located in the first well W1 and having the second type, a second doped region D2 located in the second well W2 and having the second type, and a third doped region D3 located in the third well W3 and having the second type. The gate 121 is formed on the first well W1 and the second well W2, and the gate 122 is formed on the second well W2 and the third well W3. A metal structure 151 is formed on the first doped region D1, a metal structure 152 is formed on the second doped region D2, and a metal structure 153 is formed on the third doped region D3.

In addition, the isolation structures 131b and 132b of the semiconductor device 100b are located within the second well W2 of the active region structure 110. Specifically, the isolation structures 131 and 132 are surrounded by the second doped region D2. In some embodiments, as shown in fig. 3, the depth of the isolation structures 131b and 132b is greater than the second doping region D2. The on current can pass through under the isolation structures 131b and 132 b. As shown in fig. 4, the polysilicon structures 145b and 146b of the semiconductor device 100b are located above the second well W2 of the active area structure 110. Since there is no isolation structure under polysilicon structures 145b and 146b, the on current can pass through it more easily.

In addition, as shown in fig. 3 and 4, since the region where the isolation structure or the polysilicon structure is formed has no silicide, the silicide concentration along the surface where the on-current is large can be avoided by connecting the isolation structure and the polysilicon structure in the second direction and crossing both sides S1 and S2 of the active region structure 110. In other words, in some embodiments, the isolation structure and the polysilicon structure may not be aligned in the second direction. For example, in the embodiment of fig. 5A, the isolation structures 131c and 133c are disposed closer to the gate 121 in the semiconductor device 100c than in the embodiment of fig. 2 where the isolation structures 131b and 133b and the polysilicon structures 141b, 143b and 145b are aligned in the second direction (i.e., equidistant from the gate 121 in the first direction). The isolation structures 131c and 133c and the polysilicon structures 141c, 143c and 145c are different in distance between the gate electrode 121 and the first direction. However, the top surfaces of isolation structures 131c and 133c on both sides in the first direction are connected to portions of the bottom surfaces of polysilicon structures 141c, 143c, and 145c on both sides in the first direction, respectively, still enabling the silicide to be divided into regions 102 and 103.

Furthermore, in some embodiments, the isolation structure may be located from below the gate 121, where it is connected, to beside the metal structure 152, but not connected thereto, as shown in the range W0. For example, as shown in fig. 5B, in the semiconductor device 100d, portions of the isolation structures 131d and 133d are located below the gate electrode 121, and the right sides of the top surfaces of the isolation structures 131d and 133d in the second direction are connected to the left side of the bottom surface of the polysilicon structure 141d in the second direction, so that the silicide is divided into the regions 102 and 103.

In addition, in other embodiments, as shown in fig. 5C, in the semiconductor device 100e, a portion of the polysilicon structure 141e may cover the isolation structures 131e and 133e in the top view direction (Z direction). In other words, portions of the top surfaces of the isolation structures 131e and 133e connect portions of the bottom surface of the polysilicon structure 141e, so that the silicide is divided into regions 102 and 103.

In addition to the polysilicon structure, in some embodiments, a portion of the region may be uncovered by the silicide by the mask, so as to prevent the current from being attracted by the silicide and concentrated. Specifically, please refer to fig. 6. Fig. 6 is a schematic diagram of another semiconductor device 100f according to an embodiment of the present disclosure. In the embodiment of fig. 6, the second active region 112 of the active region structure 110 of the semiconductor device 100f includes first regions (e.g., regions 102, 103, and 104) having silicide coverage and second regions (e.g., regions 161a, 162a, 163a, and 164a) not having silicide coverage.

As shown in fig. 6, the second regions 161a and 163a and the isolation structure 131a, which are not covered with silicide, are connected to each other and cross both sides S1 and S2 of the active region 110. Specifically, the second region 161a not covered with silicide connects the one side S1 of the source region structure 110 and the isolation structure 131 a. The second region 163a not covered with silicide connects the isolation structure 131a and the other side S2 of the active region structure 110. In this way, in the first direction, a part of the current can pass through the part (the regions 161a and 163a) where the isolation structure is not provided with ease, and since the regions 161a and 163a are not covered with the silicide, the on-current is not concentrated too much to damage the structure.

Please refer to fig. 7. Fig. 7 is a schematic diagram of a method for fabricating the semiconductor device 100f of fig. 6, in accordance with an embodiment of the present disclosure. As shown in fig. 7, when the semiconductor device 100f is fabricated, masks (SABs) 171, 172, 173 and 174 are disposed above the active region structure 110, so that the underlying masked regions are not silicided, thereby resulting in the regions 161 a-164 a not covered by silicide as shown in fig. 6.

In some embodiments, the area of the shields 171-174 is greater than the area of the corresponding regions 161 a-164 a, respectively. Specifically, in the top view direction (Z direction), the shields 171 and 173 cover portions of the gate 121 and the isolation structure 131a to ensure that the regions 161a and 163a not covered with silicide connect the isolation structure 131a and are adjacent to the gate 121.

In addition, in other embodiments, as shown in fig. 8, the semiconductor device 100g may include a plurality of isolation structures 131 b-134 b similar to those shown in fig. 2, and a plurality of regions 161 b-166 b not covered by silicide. Specifically, the silicide-uncovered region 161b connects one side S1 of the active region structure 110, the isolation structure 131b, and the gate 121, the silicide-uncovered region 165b connects the isolation structures 131b, 133b, and the gate 121, and the silicide-uncovered region 163b connects the gate 121, the isolation structure 133b, and the other side S2 of the active region structure 110.

In further detail, please refer to fig. 9. Fig. 9 is a cross-sectional view of the semiconductor device 100g taken along cut line C1-C1' in the embodiment of fig. 8 according to the present disclosure. As shown in fig. 9, on the surface of the second doped region D2 of the second well W2, a portion adjacent to the gate 121 (i.e., corresponding to the region 165b in fig. 8) is not covered with silicide, and a portion of silicide is adjacent to the metal structure 152 (i.e., corresponding to the right side of the region 165b in fig. 8).

In this way, in the first direction, part of the current can pass through the regions 161b, 163b and 165b more easily, and since the silicide is not covered here, the on-current is not concentrated too much to damage the structure. In addition, since the length and position distribution of the isolation structures 131b and 133b and the regions 161b, 163b, and 165b in the second direction are more uniform, the distribution of the on-current may be more uniform.

In some other embodiments, the region not covered by silicide on the surface may not be adjacent to the gate, and is only connected to the isolation structure and crosses the two sides S1 and S2 of the active region structure 110. Furthermore, in some embodiments, as shown in fig. 10, in the semiconductor device 100h, similar to the embodiment of fig. 5B, portions of the isolation structures 131d to 134d may be located under the gate 121. The surface of the region 161c between the isolation structures 131d and 133d is not covered with silicide.

Please refer to fig. 11. Fig. 11 is a schematic diagram of another semiconductor device 100i according to an embodiment of the present disclosure. In some embodiments, as shown in FIG. 11, the semiconductor device 100i includes polysilicon structures 141 b-146 b and regions 161 d-164 d not covered by silicide. Specifically, the polysilicon structures 141b, 143b, and 145b and the regions 161d and 163d not covered with silicide are staggered and connected to each other and cross both sides S1 and S2 of the active region structure 110. Wherein polysilicon structure 141b connects one side S1 of source region structure 110 and region 161d not covered by silicide. The polysilicon structure 145b connects the regions 161d and 163d that are not covered with silicide. The polysilicon structure 143b connects the region 163d not covered with silicide and the other side S2 of the active region structure 110.

Since there is no isolation structure in the embodiment of fig. 11, the on-current is large. In addition, the regions 102 and 103 are divided by the interconnection of the polysilicon structure and the regions whose surfaces are not covered with silicide, so that the on-current is uniform to avoid the structure from being concentrated and damaged.

In summary, by adjusting the ratio between the total length of the isolation structure and the width of the active region structure in the second direction, the magnitude of the on-current can be controlled without excessively affecting the degree of breakdown voltage. The shorter the total length of the isolation structure, the greater the on-current. In addition, it should be noted that the polysilicon structure and the area not covered by the silicide may be mixed, and those skilled in the art can design the structure according to the actual requirement with reference to the above description, and will not be described herein again.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[ notation ] to show

100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i semiconductor device

110 active region structure

111 first active region

112 second active region

101. 102, 103, 104, 105 areas

121. 122 grid

131 a-132 a, 131 b-134 b, 131 c-134 c, 131 d-134 d and 131 e-134 e isolation structure

141 a-144 a, 141 b-146 b, 141 c-146 c, 141 d-142 d, 141 e-142 e polysilicon structure

151. 152, 153 metal structure

Regions 161a to 164a, 161b to 166b, 161c to 162c, and 161d to 164d

171. 172, 173, 174 shield

L0, L1, L2, L3 Length

W0 range

W1 first well

W2 second well

W3 third well

D1, D2 and D3 doped regions

S1, S2 lateral side

X, Y, Z direction

A1-A1 ', B1-B1 ', C1-C1 ' are tangent lines.