阅读说明：本技术 横向扩散金属氧化物半导体(ldmos)晶体管 (Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor ) 是由 C·C·马 于 2020-10-20 设计创作，主要内容包括：本发明题为“横向扩散金属氧化物半导体晶体管”。在一般方面,横向扩散金属氧化物半导体(LDMOS)晶体管可包括：第一导电类型的衬底；设置在该衬底中的第二导电类型的埋入式阱区；设置在该埋入式阱区上的该第一导电类型的主体区、设置在该主体区中的该第二导电类型的漂移区、设置在该漂移区中的该第二导电类型的漏极注入物；设置在该主体区中的该第二导电类型的源极注入物；以及设置在该漂移区上的栅极结构。该栅极结构可包括：包括RESURF介电层的场板；栅极介电层；和栅极电极,该栅极电极设置在该场板和该栅极介电层上。LDMOS晶体管还可包括漏极触点,该漏极触点延伸穿过该场板并限定与该漏极注入物的欧姆触点。(The invention provides a lateral diffusion metal oxide semiconductor transistor. In a general aspect, a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor may include: a substrate of a first conductivity type; a buried well region of a second conductivity type disposed in the substrate; a body region of the first conductivity type disposed over the buried well region, a drift region of the second conductivity type disposed in the body region, a drain implant of the second conductivity type disposed in the drift region; a source implant of the second conductivity type disposed in the body region; and a gate structure disposed on the drift region. The gate structure may include: a field plate comprising a RESURF dielectric layer; a gate dielectric layer; and a gate electrode disposed on the field plate and the gate dielectric layer. The LDMOS transistor may further comprise a drain contact extending through the field plate and defining an ohmic contact to the drain implant.)

1. A Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor, comprising:

a substrate of a first conductivity type;

a buried well region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type;

a body region of the first conductivity type disposed over the buried well region;

a drift region of the second conductivity type disposed in the body region;

a drain implant of the second conductivity type disposed in the drift region;

a source implant of the second conductivity type disposed in the body region;

a gate structure disposed on the drift region, the gate structure comprising:

a field plate comprising a RESURF dielectric layer;

a gate dielectric layer; and

a gate electrode disposed on the field plate and the gate dielectric layer; and

a drain contact extending through the field plate and defining an ohmic contact with the drain implant.

2. Laterally diffused metal oxide semiconductor transistor according to claim 1, wherein the body region comprises:

a buried body region disposed on the buried well region;

a surface body region; and

a body-tie region disposed between the buried body region and the surface body region,

the RESURF dielectric layer includes:

a first thermal oxide layer disposed on the drift region and the drain implants; and

a deposited oxide layer disposed on the first thermal oxide layer, and

the gate dielectric layer includes a second thermal oxide layer.

3. The ldmos transistor set forth in claim 1 further including:

a heavy body implant of the first conductivity type disposed in the body region, the heavy body implant being adjacent to the source implant; and

a shallow trench isolation dielectric disposed in the body region, the shallow trench isolation dielectric adjacent to the heavy body implant.

4. The ldmos transistor set forth in claim 1 further including:

a heavy body implant of the first conductivity type disposed in the body region, the heavy body implant being adjacent to the source implant; and

a source contact defining an ohmic contact to the source implant, the body region, and the heavy body implant.

5. The laterally diffused metal oxide semiconductor transistor of claim 1 wherein:

the RESURF dielectric layer is arranged on an accumulation region of the LDMOS transistor; and is

The RESURF dielectric layer includes an inclined portion extending from an upper surface of the RESURF dielectric layer to the gate dielectric layer.

6. Laterally diffused metal oxide semiconductor transistor according to claim 1, further comprising a connection implant of the second conductivity type, the connection implant being arranged in the body region,

the drain implant is shared between a first section of the LDMOS transistor and a second section of the LDMOS transistor.

7. A Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor, comprising:

a substrate of a first conductivity type;

a buried well region of a second conductivity type, the second conductivity type being opposite to the first conductivity type;

a body region of the first conductivity type disposed over the buried well region;

a drift region of the second conductivity type disposed in the body region;

a drain implant of the second conductivity type disposed in the drift region;

a first source implant of the second conductivity type disposed in the body region, the first source implant defining a source region of a first segment of the LDMOS transistor;

a second source implant of the second conductivity type disposed in the body region, the second source implant defining a source region of a second segment of the LDMOS transistor;

a gate structure disposed on the drift region, the gate structure comprising:

a field plate comprising a RESURF dielectric layer;

a gate dielectric layer; and

a gate electrode disposed on the field plate and the gate dielectric layer, the gate electrode comprising a first gate electrode portion of the first section of the LDMOS transistor and a second gate electrode portion of the second section of the LDMOS transistor; and

a drain contact extending through the field plate between the first gate electrode portion and the second gate electrode portion, the drain contact and the drain implant being shared between the first section of the LDMOS transistor and the second section of the LDMOS transistor.

8. The laterally diffused metal oxide semiconductor transistor of claim 7 further comprising:

a first source contact to the first source implant; and

a second source contact to the second source implant,

the drain contact comprises a first silicide material, an

The first source contact and the second source contact comprise a second silicide material different from the first silicide material.

9. The ldmos transistor set forth in claim 7 wherein said RESURF dielectric layer is disposed on respective accumulation regions of said first segment of said ldmos transistor and said second segment of said ldmos transistor.

10. A method for forming a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor, the method comprising:

forming a buried well region of a second conductivity type in a substrate of a first conductivity type, the second conductivity type being opposite to the first conductivity type;

forming a deep body region of the first conductivity type in the substrate over the buried well region;

forming a drift region of the second conductivity type over the deep body region;

forming a gate structure on the drift region, the gate structure comprising:

a field plate comprising a RESURF dielectric layer;

a gate dielectric layer; and

a gate electrode disposed on the field plate and the gate dielectric layer;

forming in the drift region:

a surface body region of the first conductivity type; and

a body tie region of the first conductivity type disposed between the surface body region and the deep body region;

forming a drain implant of the second conductivity type in the drift region;

forming a source implant of the second conductivity type in the body region; and

forming a drain contact extending through the field plate, the drain contact defining an ohmic contact with the drain implant.

11. The method of claim 10, wherein forming the source and drain implants comprises:

forming the source implant using a first implant energy and a second implant energy, the second implant energy being greater than the first implant energy; and

forming the drain implant through the field plate using the second implant energy.

12. The method of claim 10, further comprising:

forming shallow trench isolation regions of the LDMOS transistor prior to forming the buried well region, an

Forming a connection implant of the second conductivity type, the connection implant being disposed in the body region, prior to forming the drain implant and the source implant.

Technical Field

The present description relates to Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor devices and associated fabrication methods.

Background

Producing Laterally Diffused Metal Oxide Semiconductors (LDMOS), such as low voltage LDMOS transistors, poses many challenges. For example, it is desirable to reduce the cell pitch of an LDMOS for cost and performance considerations. However, as cell pitch decreases, the creation of LDMOS transistors with small cell pitch may result in an increase in the gate charge (Qg) and associated quality factor (FoMv (e.g., drain-to-source on-resistance multiplied by Qg) of the transistor.

Disclosure of Invention

In a general aspect, a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor can include a substrate of a first conductivity type and a buried well region of a second conductivity type. The second conductivity type may be opposite to the first conductivity type. The LDMOS transistor may further include a body region (body region) of the first conductivity type, wherein the body region may be disposed on the buried well region. The LDMOS transistor may further comprise a drift region of the second conductivity type, wherein the drift region is arranged in the body region. The LDMOS transistor may further include a drain implant (implant) of the second conductivity type, wherein the drain implant may be disposed in the drift region. The LDMOS transistor may further comprise a source implant of the second conductivity type, wherein the source implant may be disposed in the body region. The LDMOS transistor may further include a gate structure disposed on the drift region. The gate structure may include: a field plate comprising a RESURF dielectric layer, a gate dielectric layer, and a gate electrode disposed on the field plate and the gate dielectric layer. The LDMOS transistor may further comprise a drain contact extending through the field plate and defining an ohmic contact to the drain implant.

Drawings

Fig. 1 is a diagram illustrating a cross-sectional view of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor having a RESURF dielectric layer field plate.

Fig. 2 is a graph showing a comparison of the gate charge of an LDMOS transistor having a RESURF dielectric layer field plate and the gate charge of a current LDMOS having a flat gate and a field plate.

Fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8A, fig. 8B, fig. 9A, fig. 9B, fig. 10A, fig. 10B, fig. 11A, fig. 11B, fig. 12A, fig. 12B, fig. 13A, fig. 13B, fig. 14A and fig. 14B are a series of cross-sectional views illustrating the operation of a semiconductor fabrication process that may be used to produce an embodiment of an LDMOS transistor, such as the LDMOS transistor of fig. 1.

Fig. 15 is a flow chart illustrating a method that may be used to implement the semiconductor manufacturing process shown in fig. 3-14B.

The same reference numbers in different drawings identify the same and/or similar elements. Elements shown in the various figures are illustrated by way of example and may not necessarily be drawn to scale. In addition, the various drawings may differ from one another in scale, depending at least in part on the particular views shown.

The reference characters in the various drawings are provided for purposes of illustration and discussion. Reference characters to the same elements may not be repeated for similar elements in the same view. In addition, reference characters shown in one view for a given element may be omitted for that element in the associated view. For example, reference characters for a given element shown in different views may not necessarily be discussed with respect to each of these views, or may in some cases be referenced with different reference characters.

Detailed Description

The present disclosure relates to Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors (LDMOS devices) and associated fabrication methods. The LDMOS devices described herein may be implemented with comparable cell pitch to current devices and may have reduced gate charge compared to those devices. Such gate charge reduction may be achieved by embodiments of one or more RESURF dielectric (RESURF oxide) field plates disposed over (above, over, vertically aligned with) an accumulation region of the LDMOS device or LDMOS segment (e.g., for each segment of the associated LDMOS device).

In some embodiments, the devices and processing methods described herein may be implemented using non-epitaxial processes (e.g., semiconductor fabrication processes that do not include the formation of an epitaxial semiconductor layer). The methods described herein can be used to produce fully isolated LDMOS devices. For example, in some embodiments, the LDMOS devices described herein may be isolated from other types of devices, such as bipolar devices and/or complementary mos (cmos) devices that may be generated (on the same semiconductor die) using hybrid semiconductor manufacturing processes, for example, using Shallow Trench Isolation (STI). For example, such isolated LDMOS devices may be produced using a Bipolar CMOS DMOS (BCD) hybrid semiconductor fabrication process platform.

The LDMOS devices described herein may have a plurality of self-aligned features. For example, in some embodiments, LDMOS devices according to the methods described herein may have a self-aligned drift region, wherein the drift region may be co-implanted (e.g., implanted using the same lithographic mask) with a deep body implant. In an embodiment, an LDMOS device described herein may have a drain implant contact (e.g., formed by a RESURF dielectric field plate) that includes self-aligned Ti/Si formed over a drain implant.

As indicated above, the LDMOS devices described herein may be implemented using a field plate(s) comprising a RESURF dielectric layer. In an exemplary embodiment, such a field plate (which may be part of the gate structure of an associated LDMOS device) may be placed over an accumulation region of the LDMOS (e.g., an accumulation region of a segment of an LDMOS device). The use of RESURF dielectric field plates can reduce gate charge compared to LDMOS implementations without adversely affecting device breakdown voltage, device on-resistance (e.g., drain to source on-resistance), or Hot Carrier Injection (HCI) performance. That is, simulation results indicate breakdown, on-resistance, and HCI performance (e.g., based on impact ionization location) consistent with current devices, but with reduced gate charge.

The depletion of STI oxide in other device regions, such as CMOS devices that may be produced using a BCD semiconductor fabrication process platform in conjunction with LDMOS devices, may be prevented using the processing methods described herein. In some embodiments, producing such LDMOS devices may be accomplished with limited additional processing added to an existing semiconductor process flow (such as a process flow used to produce CMOS devices). For example, in an exemplary embodiment, the CMOS process flow may be modified by adding an operation for forming the body region of the LDMOS, including the deep body region (e.g., buried body region), and an operation for forming the RESURF dielectric layer (structure, etc.) that may be used to form the RESURF dielectric layer field plate of the LDMOS device, in order to form the LDMOS device.

Fig. 1 is a diagram illustrating a cross-sectional view of an LDMOS transistor (device) 100 that includes a RESURF dielectric field plate. In some embodiments, LDMOS device 100 may be implemented as an n-channel (n-type) LDMOS (nldmos) device. In some embodiments, LDMOS device 100 may be implemented as a p-channel (p-type) LDMOS (pldmos) device, where the conductivity type of each region and implant is inverted compared to an NLDMOS device implementation. That is, the p-type material in the NLDMOS is inverted to the n-type material in the PLDMOS. Also, the n-type material in the NLDMOS is inverted to the p-type material in the PLDMOS.

In some embodiments, the LDMOS device 100 of fig. 1 may be produced using a semiconductor process, such as using a BCD hybrid semiconductor manufacturing process platform. Exemplary embodiments of such fabrication processes are discussed herein with respect to fig. 3-15, where fig. 3-14B are cross-sectional views of semiconductor process operations that may be used to produce the LDMOS 100. Fig. 15 is a flow diagram illustrating a method that may be implemented using the process operations of fig. 3-14B in some embodiments. The structure of the LDMOS100 is generally described, and further details regarding the elements of the LDMOS100 and the methods for producing embodiments of the LDMOS100 are discussed further below.

As shown in fig. 1, the LDMOS may include adjacent segments (segment 100a (left side) and segment 100b (right side)). The LDMOS100 shown in fig. 1 may be referred to as an LDMOS unit cell, in which a plurality of LDMOS unit cells may be combined to form a larger LDMOS device. It should be appreciated that the structure of the LDMOS device 100 of fig. 1 may be extended into and/or out of the page of fig. 1 in order to establish the channel width of the LDMOS regions 100a and 100 b. Since the exemplary embodiment of fig. 1 shows adjacent sections 100a and 100b of the LDMOS100, the following discussion describes elements included in each section, and additional discussion is made regarding some elements shared between the sections 100a and 100 b.

As shown in fig. 1, the LDMOS100 may be formed in a substrate 102, wherein the substrate 102 has a first conductivity type. For example, for NLDMOS, the substrate 102 may be a p-type substrate, while for PLDMOS, the substrate 102 may be an n-type substrate. The LDMOS100 may include a deep or buried well region 104 of a second conductivity type disposed in a substrate 102. The second conductivity type may be opposite to the first conductivity type, e.g., n-type for NLDMOS devices and p-type for PLDMOS.

The LDMOS100 of fig. 1 may include a body region of a first conductivity type (e.g., p-type for NLDMOS), wherein the body region is disposed on the buried well region 104. In this example, the body region of the LDMOS100 may include a buried (deep) body region 106 disposed on the buried well region 104, a surface body region 110 for each of the sections 100a and 100b, and a connecting body region (linking body region)112 for each of the sections of the LDMOS 100. As shown in fig. 1, a body region 112 is provided between the buried (deep) body region 106 and the surface body region 110 in order to connect the body regions of the first conductivity type to form a continuous body region of the first conductivity type of the LDMOS 100.

The exemplary LDMOS100 of fig. 1 also includes a drift region 108 of a second conductivity type (e.g., n-type for NLDMOS). As shown in fig. 1, the drift region 108 may be disposed in (within) the body region, but in some embodiments, the drift region 108 may be formed before at least one or more portions of the body region. For example, in some embodiments, the surface body regions 110 and the connecting body regions 112 may be formed after the drift region 108 and described as being disposed in the drift region 108. In the LDMOS100, the segments 100a and 100b (and the LDMOS100 as a whole) may be isolated (e.g., using STI regions) from adjacent devices (e.g., in different device regions, such as bipolar and/or CMOS device regions) formed in the same semiconductor die.

As further shown in fig. 1, for each of the regions 100a and 100b, the LDMOS100 may include a source implant 122 of the second conductivity type disposed in the body region. The LDMOS100 may further include a drain implant 124 of the second conductivity type disposed in the drift region 108. In some embodiments (such as the LDMOS of fig. 1), the drain implant 124 may be shared by the region 100a and the region 100 b. That is, the drain implant 124 may be a common drain implant for the region of the LDMOS 100.

The LDMOS100 may further include a gate structure disposed on the drift region 108, wherein the gate structure is formed across the two segments 100a and 100b and a respective gate electrode for each segment is defined from the gate structure. In the exemplary embodiment of fig. 1, the gate structure includes: a field plate 130 comprising a RESURF dielectric layer, a gate dielectric layer 152 (thermal oxide layer), and a gate electrode 150 disposed on the field plate and the gate dielectric layer. In some embodiments, the RESURF dielectric layer of the field plate may include a thermal oxide layer 130b (which may be different from the gate oxide layer 152) and a deposited oxide layer 130 a. As shown in fig. 1, the field plate 130 may be disposed over (e.g., on, vertically aligned with, etc.) a respective accumulation region (e.g., near or at the drain implant 124) of each of the segments 100a and 100b, which may reduce the overall gate charge of the LDMOS100 compared to an LDMOS device having a flat gate and field plate structure.

The LDMOS100 of this example also includes a drain contact 170 extending through the field plate 130, which may define an ohmic contact with the drain implant 124, such as using the methods described herein. As with the drain implant 124, the drain contact 170 may be shared by (shared by) the LDMOS regions 100a and 100 b. As shown in fig. 1, drain contact 170 includes a contact fill portion 170a (e.g., tungsten) and a metallization portion 170 b. For each of the segments 100a and 100b, the filling portion 170a may be disposed between respective portions of the gate electrode 150.

As shown in fig. 1, the LDMOS100 may include a heavy body implant 120 of a first conductivity type (e.g., p-type for an NLDMOS device) for each of the regions 100a and 100 b. As shown in fig. 1, the heavy body implants 120 may be adjacent to respective source implants 122. Contacts 160 (e.g., ohmic contacts) may be formed to the source implants 122, heavy body implants 120, and surface body regions 110. The contacts 160 may include a silicide material 160a (such as cobalt silicide, etc.), a fill material 160b (e.g., tungsten, etc.), and a metallization material 160c (e.g., aluminum, copper, alloys, etc.). As shown in fig. 1, the contact fill materials 170a and 160b may extend through the interlayer dielectric material 140.

As also shown in fig. 1, and as more clearly shown in, for example, fig. 7, each of the sections 100a and 100b may include a connection (source connection) implant 126 of a second conductivity type (e.g., n-type for NLDMOS). The connecting implants 126 may reduce the resistance in the respective conductive paths between the channel regions of the segments 100a and 100b and their respective source implants 122. As further shown in fig. 1, the LDMOS100 may include gate electrode sidewall spacers 154 that may be formed in combination with sidewall spacers formed in other device regions (e.g., CMOS regions such as LDMOS for production in a hybrid process such as a BCD platform).

Fig. 2 is a graph 200 illustrating a comparison of the gate charge of an LDMOS transistor including a RESURF dielectric field plate (such as the dielectric field plate described herein) to the gate charge of a current LDMOS transistor having a flat gate and a field plate. In graph 200, lines 210 and 210a correspond to LDMOS transistors with RESURF dielectric field plates, and lines 220 and 220a correspond to LDMOS transistors with flat gates and field plates. In graph 200, time is represented on the x-axis and gate voltage is represented on the y-axis. Lines 210 and 220 represent the respective gate voltage versus time for a given gate current. Lines 210a and 220b indicate the respective amount of time it takes for each device to reach the gate voltage (e.g., the operating gate voltage) of Vg.

As can be seen in graph 200, the LDMOS device (210) with a RESURF dielectric field plate reaches a gate voltage of Vg in a shorter time than the LDMOS device (220) with a flat field plate. Since Qg is given by the gate current times time, it can be seen that the gate charge associated with line 210a (RESURF dielectric field plate device) is less than the gate charge associated with line 220a (flat field plate device). In fact, in this example, the simulation results shown represent Qg for devices of lines 210 and 210a that are more than 25% less than Qg for devices of lines 220 and 220 a. In other words, an LDMOS device (e.g., an embodiment of LDMOS 100) having a RESURF dielectric layer field plate exhibits a reduction in Qg of more than 25% compared to an LDMOS device having a flat field plate (e.g., having comparable device dimensions such as channel width and length).

Fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8A, fig. 8B, fig. 9A, fig. 9B, fig. 10A, fig. 10B, fig. 11A, fig. 11B, fig. 12A, fig. 12B, fig. 13A, fig. 13B, fig. 14A and 14B (fig. 3-14B) are a series of cross-sectional views illustrating the operation of a semiconductor fabrication process that may be used to produce an embodiment of an LDMOS transistor, such as the LDMOS transistor 100 of fig. 1. In some embodiments, the operations may be performed in an order corresponding to the order of the figures, or may be performed in a different order as appropriate for a given manufacturing process.

In fig. 3 through 14B, two different process flows are shown, where in these examples, the two process flows diverge from each other starting from the operations shown by fig. 8A and 8B. That is, for both exemplary process flows of fig. 3 through 14B, the process flow operations shown by fig. 3 through 7 are the same for both processes. Furthermore, the process operations illustrated in fig. 3-14B (except for fig. 9A and 9B) are process operations that specifically involve forming an isolated (STI isolated) LDMOS device using a hybrid semiconductor process platform (e.g., a BCD process). It should be appreciated that certain elements (such as photolithographic masks formed in other device regions) may not be shown in fig. 3-14B, and that the process operations performed to define the LDMOS device may be performed in sequence or using additional process operations so as not to adversely affect the devices in the other device regions (e.g., without etching the RESURF dielectric field plate as shown in fig. 8A, or using an additional photomask to etch the RESURF dielectric field plate as shown in fig. 8B so as not to cause STI loss in the CMOS device regions).

Further, while separate illustrations of the process operations of these exemplary embodiments are shown beginning with fig. 8A and 8B through fig. 14A and 14B, some of the operations shown in those figures are very similar and thus may be described together. Furthermore, although the operations of the process flow of fig. 3-14B may be used to produce an n-channel (n-type) LDMOS transistor, or a p-channel (p-type) LDMOS transistor, for purposes of illustration and clarity, fig. 3-14B will be generally described with respect to producing an NLDMOS transistor (device). It should be appreciated, however, that the PLDMOS device may also be produced using the process flow of fig. 3-14B by reversing the respective polarities of each of the regions and implants described with respect to producing the NLDMOS device (i.e., replacing n-type with p-type and replacing p-type with n-type). Additionally, the operations of fig. 3-14B are further discussed with respect to the method 1500 shown in fig. 15, and described further below.

Referring to fig. 3, the fabrication process for producing an LDMOS device (and in particular, an NLDMOS device in these examples) may begin with the formation of STI regions 115 (e.g., STI oxide) in a p-type substrate 102. As also shown in fig. 3, a screen oxide layer 310 may be formed on the surface of the substrate 102. After forming STI regions 115 and screen oxide layer 310, deep (buried) n-well (DNW) regions 104 may be formed in substrate 102. In some embodiments, forming the DNW regions 104 may include forming a photolithographic mask (not shown) that is used as an implant mask to define the DNW regions 104. After forming the DNW regions 104 (e.g., using a high energy implant through the screen oxide 310), an anneal operation may be performed that may activate the implantation of the DNW regions 104 and repair damage to the substrate 102 caused by the high energy implant operation.

Referring to fig. 4, the photolithographic mask used to define the DNW region 104 may be removed and another photolithographic mask (not shown) may be formed, wherein a new mask may be used to define the regions where the p-type deep body regions 106 and the n-type drift (n-drift) regions 108 are to be formed (e.g., for LDMOS devices and/or other devices produced). In the operation illustrated in fig. 4, the deep p-body regions 106 and the n-drift region 108 are formed using the same lithographic mask in this example embodiment. Thus, the deep p-body region 106 and the n-drift region 108 may be referred to as being co-implanted, but in this example they are formed using respective p-type and n-type implants through the screen oxide 310. In some embodiments, another anneal may be performed after forming the deep p-body regions 106 and the n-drift region 108.

Referring to fig. 5, an operation for forming the RESURF dielectric field plate 130 is illustrated. These operations may include removing (etching) the screen oxide 310, growing a thermal oxide layer 130b (which may be part of a pad oxide layer, for example), and forming a deposited oxide layer 130a on the thermal oxide layer 130 b. Photolithography and etching operations may then be performed to pattern the field plate 130 (e.g., depositing the oxide layer 130a and the thermal oxide layer 130 b). In some implementations (such as the example of fig. 5), the deposited oxide layer 130a can etch at a faster rate than the thermal oxide layer 130 b. This difference in etch rates can result in a sloped profile 510 shown at the ends of the field plate 130 (e.g., the left and right ends of the field plate 130 in the orientation of fig. 5).

Referring to fig. 6, a thermal oxide may be grown to form a gate dielectric layer 152. As shown in fig. 6, in this example, the gate dielectric layer 152 and the thermal oxide layer 130b of the field plate 130 can form a continuous dielectric (e.g., thermal oxide) layer. As further shown in fig. 6, polysilicon may be deposited to form polysilicon portions 150a for the gate electrode of the NLDMOS. In some embodiments, an implant (p-type in this example) may be performed to dope the polysilicon that defines the polysilicon portion 150a of the gate dielectric so that the polysilicon has a high sheet resistance, such as for forming a polysilicon resistor in other area devices of a semiconductor die (such as may be produced using a BCD process) that also includes an LDMOS device. As also shown in fig. 6, a photolithographic mask 610 may be formed and the polysilicon may be etched to form (define, pattern, etc.) the polysilicon portion 150a of the gate electrode 150.

In some embodiments, the thickness of the field plate 130 (along line D in fig. 6) can be adjusted to achieve the desired Qg, on-resistance, and breakdown voltage. For example, in an exemplary embodiment, the total thickness of the field plate 130 may be about 1000 angstroms, wherein the thermal oxide layer 130b may be, for example, about 150 angstroms, and the deposited oxide layer 130a may be, for example, about 850 angstroms.

As shown in fig. 7, the photolithographic mask 610 of fig. 6 may be used as an implantation mask when performing the respective implantations to form the surface p body region 110, the connection p body region 112 and the source n connection implant 126. In some embodiments, the surface p-body region 110a may be formed using a large angled implant such that the surface p-body region 110 extends below the gate dielectric 152 and the gate electrode. The connecting p-body region 112 may be implanted such that it is disposed between the surface p-body region 110 and the deep p-body region 106, for example, in order to form a continuous p-body region for an LDMOS device. As shown in fig. 6, n-connection implant 126 may be configured to provide an n-type diffusion connection between the channel region of the LDMOS (e.g., under the gate dielectric in the surface p-body region) and source implant 122 and/or source contact 160 (to be formed later).

As described above, the exemplary semiconductor manufacturing processes of fig. 3 to 14B diverge from the operations of fig. 8A and 8B. In both fig. 8A and 8B, the polysilicon portion 150a (of the gate electrode 150) is patterned to define respective gate electrode portions for adjacent regions of the LDMOS, such as the LDMOS regions 100a and 100B shown in fig. 1. In the exemplary embodiment shown in fig. 8A, the field plate 130 is not etched. However, in the exemplary embodiment shown in fig. 8B, a photolithographic mask 810 is defined and the field plate 130 may be etched through the deposited oxide 130a of the RESURF dielectric layer field plate 130 to the thermal oxide layer 130B (e.g., in the area where the drain implant 124 is to be formed) using the mask 810. In some embodiments, the drain implant 124 (such as shown in fig. 1) may be formed as a self-aligned tilted (angled) drain implant through the thermal oxide 130b, for example, depositing the oxide 130a using the lithography mask 810 and the etching of the field plate 130 to define such a self-aligned drain implant. Such methods may be used to produce an adaptive RESURF LDMOS device, such as the LDMOS100 of fig. 1. In some embodiments, the photolithographic mask may be removed after forming the self-aligned drain implant.

Fig. 9A and 9B illustrate process operations that may be performed in a CMOS device region associated with the described LDMOS region, such as in the same semiconductor die produced using a hybrid semiconductor manufacturing process, such as a BCD process. For example, fig. 9A illustrates the formation of a p-well 910 and the formation of an n-type lightly doped drain region (NLDD)915, which may be used to form an n-type CMOS transistor. Likewise, fig. 9B illustrates the formation of a p-well 920 and p-type lightly doped drain region (PLDD)925, which may be used to form p-type CMOS transistors. Furthermore, as shown in both fig. 9A and 9B, spacers 154 (e.g., gate electrode sidewall dielectric spacers) may also be formed on the sidewalls of the gate electrodes of the formed n-type and p-type MOS transistors. Likewise, spacers 154 (shown, for example, in fig. 10A and 10B) of an LDMOS device can be formed using the same process operations used to form spacers 154 shown in fig. 9A and 9B.

Referring to fig. 10A and 10B, a source implant 122 and a shared or common drain implant 124 may be formed. For example, as discussed herein, the drain implant 124 may be shared by adjacent LDMOS regions (e.g., the regions 100a and 100b of the LDMOS device 100 of fig. 1). As shown in both fig. 10A and 10B, in these example embodiments, a photolithographic mask 1010 may be formed and one or more blanket implantations may then be performed to define the source implants 122 and the (shared) drain implants 124. In the exemplary embodiment of fig. 10A, in which the field plate 130 is not etched in the region of the drain implant 124, a chain implant (implant with two different energies) may be performed. For example, the chain implant of fig. 10A may include a first blanket n-type implant at a first energy (e.g., 50keV) and a second blanket n-type implant at a second higher energy (e.g., 100 keV). In fig. 10A, since the field plate is not etched, only the second implant may have sufficient implant energy to penetrate the field plate to form the drain implant 124, wherein both the first n-type implant and the second n-type implant form the source implant 122 (since only the gate dielectric 152 is disposed on the source implant region). Thus, in the embodiment of fig. 10A, the source implant 122 may have a depth along line D that is greater than the depth of the drain implant.

In the embodiment of fig. 10B, in which the field plate 130 is etched in the region of the drain implant 124, a single energy n-type implant (e.g., 50keV) may be performed to form both the source implant 122 and the drain implant 124. In such embodiments, the source implant 122 and the drain implant 124 may have the same depth (about the same depth) along line D.

Referring to fig. 11A and 11B, the photolithographic mask 1010 of fig. 10A and 10B may be removed, and a photolithographic mask 1110 may be formed. In these exemplary embodiments, the photolithographic mask 1110 may be used as an implantation mask to define the heavy p-body implants 120, which may be formed as blanket p-type implants through the gate dielectric 152, wherein the heavy p-body implants 120 are adjacent to respective source implants 122 (and the channel regions that are LDMOS device regions are on respective opposite sides of the source implants).

Referring to fig. 12A and 12B, the photolithographic mask 1110 of fig. 11A and 11B may be removed. A silicide blocking oxide may be deposited and then patterned using photolithography. In this example, the patterned silicide blocking oxide may block (mask) silicon (including polysilicon) regions where silicide formation is not desired. After deposition and patterning of the silicide blocking oxide, in the embodiment of fig. 12A and 12B, a silicide 1210 (e.g., cobalt silicide (CoSi)) (e.g., where the silicide 1210 may implement the silicide 160a of the LDMOS100 in fig. 1) may be formed. For example, in the embodiment of fig. 12A and 12B, a silicide 1210 (e.g., CoSi) may be formed on the source implants 122, the heavy body implants 120, and the surface body regions 110. Furthermore, as shown in fig. 12A and 12B, silicide 1210 may also be formed on the polysilicon of the gate electrode 150 (e.g., the gate electrode portions of the segments 100a and 100B), which may reduce the gate resistance of the associated NLDMOS device. In the embodiment of fig. 12B, where the deposited portion 130a of the field plate 130 is etched in the region of the drain implant 124, a silicide 1210 (e.g., CoSi) may also be formed on the drain implant 124.

In the exemplary embodiment of fig. 13A and 13B, an interlayer dielectric layer 140 may be formed and planarized (e.g., using CMP), and contact openings 142 may be defined (etched) in the interlayer dielectric 140. In the embodiment of fig. 13A and 13B, the etching process performed to form the contact opening 142 may be configured to terminate at the silicide formed on the source implant and the heavy p-body implant. In the embodiment of fig. 13A, the etch process used to form the contact opening 142 may be further configured to terminate at the silicon (e.g., of the drain implant 124). In the embodiment of fig. 13B, the etch process for forming the contact opening 142 may also be terminated on the silicide formed on the drain implant 124, as may the silicide of the source implant and the heavy body implant.

Fig. 14A and 14B illustrate operations for completing contact formation and metallization for these exemplary embodiments. Fig. 14A and 14 also show two regions 100a and 100B of an LDMOS transistor formed using the exemplary semiconductor fabrication process embodiment shown in fig. 3-14B, as with the LDMOS100 of fig. 1.

In the exemplary embodiment of fig. 14A and 14B, a barrier metal (e.g., titanium (Ti)/titanium nitride (TiN)) layer may be formed (deposited, sputtered, etc.) in the contact opening 142, wherein the barrier metal layer may facilitate forming high quality ohmic contacts to the source, body and drain implants and prevent material diffusion between the silicide and the contact fill material (e.g., tungsten). A rapid thermal anneal may then be performed to reduce the contact resistance and cause a reaction (e.g., a reaction that forms a diffusion barrier) between the barrier layer and the underlying material. Furthermore, in the embodiment of fig. 14A, the anneal may form a self-aligned titanium silicide TiSi in the contact opening 142 of the drain implant 124.

For the exemplary embodiment of both fig. 14A and 14B, a tungsten fill of the contact opening 142 (160B for the source/body contact and 170a for the drain contact) may be performed, and then the tungsten fill may be planarized (e.g., using CMP) so that the top of the tungsten fill is coplanar with the upper surface of the interlayer dielectric layer 140 (in the orientation of fig. 14A and 14B). For the embodiments of both fig. 14A and 14B, metallization (160 c for the source/body contact and 170B for the drain contact) may be formed to provide electrical connection to the contact tungsten fill, which may complete the formation of the LDMOS device with regions 100a and 100B.

Fig. 15 is a flow chart illustrating a method 1500 that may be used to implement the semiconductor fabrication process shown in fig. 3-14B. Thus, for purposes of illustration, further reference will be made to fig. 3 through 14B in the discussion of method 1500. However, it should be noted that in some embodiments, the operations of method 1500 may be implemented using other methods and/or in a different order than shown in fig. 15 or fig. 3-14B. Furthermore, for purposes of illustration, method 1500 will generally be described with reference to producing an n-type (n-channel) LDMOS transistor (NLDMOS). In some embodiments, the method 1500 may be used to produce a p-type (p-channel) ldmos (pldmos) transistor, such as by inverting the conductivity types of the various regions and implants of an exemplary NLDMOS device.

In method 1500, in some embodiments, the operations of blocks 1505 and 1510 may correspond to the illustration shown in fig. 3. For example, at block 1505, shallow trench isolations 115 for LDMOS transistors may be formed in the substrate 102 (e.g., a p-type substrate for NLDMOS transistors). Additionally, at block 1505, the screen oxide layer 310 of fig. 3 may be formed. At block 1510, a deep well region (e.g., a deep n-well) 104 may be formed, wherein a photolithographic mask may be used to define a region (e.g., an active region) of the LDMOS device such that the photolithographic mask may prevent the formation of the deep well region 104 outside the defined region. After forming the deep well region 104 (e.g., using a high energy implant), an anneal operation may be performed that may activate the implant of the deep well region 104 and repair damage to the substrate 102 caused by the implant operation.

In the method 1500, the operations at block 1515 may correspond to the illustration shown in fig. 4. For example, the photolithographic mask used to form the deep well region 104 may be removed and another photolithographic mask may be formed to define the regions (e.g., for LDMOS devices and/or other devices produced) where the deep body region 106 (e.g., deep p body region) and the drift region 108 (e.g., n drift region) are to be formed. As discussed above, because in this example embodiment the deep body regions 106 and the drift regions 108 are formed using the same lithographic mask, they may be referred to as being co-implanted, even though they are formed using respective p-type and n-type implants. In some embodiments, another anneal may be performed after forming the deep body regions 106 and the drift region 108.

Operations at block 1520 of method 1500 may correspond to the illustration of fig. 5. For example, forming the RESURF dielectric field plate 130 at block 1520 may include removing the screen oxide 310, growing the thermal oxide 130b (e.g., pad oxide), and forming a deposited oxide layer 130a on the thermal oxide layer 130 b. Photolithography and etching operations may then be performed to pattern the field plate 130. As described above, the deposited oxide layer 130a may etch at a faster rate than the thermal oxide layer 130b, which may therefore produce a sloped profile 510 at the ends (e.g., left and right ends in the orientation of fig. 5) of the field plate 130.

Blocks 1525 and 1530 of method 1500 may correspond to the illustration of fig. 6. In this example embodiment, at block 1525, a thermal oxide may be grown to form the gate dielectric layer 152 such that the gate dielectric layer 152 and the thermal oxide layer 130b of the field plate 130 form a continuous dielectric (e.g., thermal oxide) layer, such as shown in fig. 6. At block 1530, polysilicon may be deposited to form the polysilicon portion 150a of the gate electrode 150 (e.g., as shown in fig. 1). Further, at block 1530, in some embodiments, an implant (p-type) may be performed to dope polysilicon with a high sheet resistance, such as for forming a polysilicon resistor in other regions of a semiconductor die (produced using method 1500) that also includes LDMOS devices (e.g., such as in a CMOS region of a semiconductor die produced using a hybrid semiconductor process). As shown in fig. 6, a photolithographic mask 610 may be formed at block 1530 and the polysilicon may be etched to form the polysilicon portion 150a of the gate electrode 150.

At block 1535 of method 1500, the photolithographic mask 610 of fig. 6 may be retained and used as an implantation mask, such as shown in fig. 7, to perform corresponding implantations to form the surface body (e.g., p-body) regions 110 (e.g., using angled implants), the connecting body regions 112, and the source connection (n-connection) implants 126. As described herein, the connecting body region 112 may be disposed between the surface body region 110 and the deep body region 106 to form a continuous body region. Also as described herein, connection implants 126 may connect the channel region of the LDMOS with source implant 122 and/or source contact 160.

In method 1500, block 1540 may correspond to the diagram of fig. 8A or the diagram of fig. 8B. For example, the polysilicon portion 150a (of the gate electrode 150) may be patterned to define respective gate electrode portions for adjacent regions of the LDMOS, such as the LDMOS regions 100a and 100B shown in fig. 1 and 14A and 14B. In some implementations (such as the example shown in fig. 8A), the field plate 130 is not etched at block 1540. In some implementations, such as that shown in fig. 8B, a photolithographic mask 810 may be formed at block 1540 and the field plate 130 may be etched through the RESURF dielectric layer 130a to the thermal oxide layer 130B (e.g., in the region where the drain implant 124 is to be formed).

Although not shown in fig. 15, in some implementations, such as in a hybrid semiconductor manufacturing process, p-well and n-well formation may be performed, for example after block 1540 and before 1545, such as shown in fig. 9A and 9B (e.g., for CMOS devices). In addition, spacers 154 (e.g., gate electrode sidewall spacers) may also be formed (as discussed with respect to fig. 9A and 9B), including spacers 154 of the LDMOS device produced using method 1500.

At block 1545 (which may correspond to the illustration of fig. 10A or the illustration of fig. 10B), a source implant 122 and a drain implant 124 (shared or common) may be formed. For example, the drain implant 124 may be shared by adjacent LDMOS regions (e.g., regions 100a and 100b described herein). As shown in fig. 10A and 10B, a photolithographic mask 1010 may be formed and one or more blanket implants may be performed to define the source implant 122 and the (shared) drain implant 124. In the embodiment of fig. 10A, where the field plate 130 is not etched in the region of the drain implant 124, at block 1545 a chain implant (implant with two different energies) may be performed, such as described above with respect to fig. 10A. In the embodiment of fig. 10B, where the field plate 130 is etched in the region of the drain region 124, at block 1545 a single energy implant may be performed to form the source implant 122 and the drain implant 124, such as described above with respect to fig. 10B.

At block 1550 of the method 1500 (which may correspond to the illustration of fig. 11A or the illustration of fig. 11B), the lithography mask 1010 may be removed and a lithography mask 1110 may be formed, wherein the lithography mask 1110 may be used as an implantation mask to define the heavy body (heavy p-body) implants (heavy body regions) 120, as shown in fig. 11A and 11B.

At block 1555 of the method 1500 (which may correspond to the illustration of fig. 12A or the illustration of fig. 12B), a silicide 1210 may be formed (e.g., where the silicide 1210 may realize the silicide 160a of the LDMOS100 in fig. 1). For example, in the embodiment of fig. 12A and 12B, a silicide 1210 (e.g., CoSi) may be formed on the source implants 122, the heavy body implants 120, and the surface body regions 110. In addition, as shown in fig. 12A and 12B, a silicide 1210 may also be formed on the gate electrode 150 (e.g., the gate electrode portion), for example, to reduce gate resistance. In the embodiment of fig. 12B, where the field plate 130 is etched in the region of the drain implant 124, a silicide 1210 (e.g., CoSi) may also be formed on the drain implant 124.

Blocks 1560 and 1565 of method 1500 may correspond to the diagram of fig. 13A or the diagram of fig. 13B. In these exemplary embodiments, the interlayer dielectric layer 140 may be formed and planarized (e.g., using CMP) at block 1560, and the contact openings 142 in the interlayer dielectric 140 may be defined at block 1565. In the embodiment of fig. 13A and 13B, the etch process performed to form the contact openings 142 may be configured to terminate at the silicide formed on the source and heavy body regions (e.g., at block 1555). In the embodiment of fig. 13A, the etch process used to form the contact opening 142 may be further configured to terminate at the silicon (e.g., of the drain implant). In the embodiment of fig. 13B, the etch process for forming the contact opening 142 may also be terminated on the silicide formed on the drain implant, as well as the silicide of the source and heavy body regions.

Blocks 1570-1585 of method 1500 may correspond to the diagram of FIG. 14A or the diagram of FIG. 14B. Fig. 14A and 14 also show two regions 100a and 100b of an LDMOS transistor formed using the method of fig. 15, as with the LDMOS100 of fig. 1. In these example embodiments, at block 1570, a barrier metal (e.g., Ti/TiN) layer may be formed (deposited, sputtered, etc.) in the contact opening 142, wherein the barrier metal may facilitate forming high quality ohmic contacts to the source, body, and drain implants. A rapid thermal anneal may then be performed at block 1575 to reduce contact resistance. Further, in the embodiment of fig. 14A, the anneal of block 1575 may form self-aligned TiSi in the contact opening 142 for the drain implant. At block 1580 (for the embodiments of both fig. 14A and 14B), a tungsten fill of the contact opening 142 (160B for the source/body contact and 170a for the drain contact) may be performed, which may then be planarized (e.g., using CMP) to be coplanar with the upper surface of the interlayer dielectric layer 140 (in the orientation of fig. 14A and 14B). At block 1585, metallization (160 c for the source/body contact and 170b for the drain contact) may be formed to provide electrical connections to the contact tungsten fill formed at block 1580, which may complete the formation of the LDMOS device with regions 100a and 100 b.

The various devices and techniques described herein may be implemented using various semiconductor processing and/or packaging techniques. Some embodiments may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), and the like.

It will also be understood that when an element such as a layer, region or substrate is referred to as being on, connected to, electrically connected to, coupled to or electrically coupled to another element, it can be directly on, connected to or coupled to the other element or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intervening elements or layers present.

Elements shown as directly on, directly connected to, or directly coupled to the element may be referred to in this manner, although the terms directly on …, directly connected to …, or directly coupled to … may not be used throughout the detailed description. The claims of the present application may be amended to recite exemplary relationships that are described in the specification or illustrated in the accompanying drawings.

As used in this specification, the singular forms can include the plural forms unless the context clearly dictates otherwise. In addition to the orientations shown in the figures, spatially relative terms (e.g., above …, above …, above …, below …, below …, below …, below …, etc.) are intended to encompass different orientations of the device in use or operation. In some embodiments, relative terms above … and below … may include vertically above … and vertically below …, respectively. In some embodiments, the term adjacent can include laterally adjacent (or laterally adjacent), vertically adjacent (or vertically adjacent), or horizontally adjacent (or horizontally adjacent), where adjacent can indicate that an intermediate element can be disposed between elements described as adjacent.

While certain features of the described embodiments have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments. It is to be understood that such modifications and variations are presented by way of example only, and not limitation, and that various changes in form and details may be made. Any portion of the devices and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The embodiments described herein can include various combinations and/or subcombinations of the functions, components and/or features of the different embodiments described.