阅读说明：本技术 差分输入缓冲电路、差分信号缓冲电路及fpga芯片 (Differential input buffer circuit, differential signal buffer circuit and FPGA chip ) 是由 罗杰 梁爱梅 温长清 于 2021-01-06 设计创作，主要内容包括：本申请实施例提供了一种分输入缓冲电路、差分信号缓冲电路及FPGA芯片,涉及集成电路技术领域,可扩大共模和差模输入范围。该差分输入缓冲电路包括：差分输入电路包括第一子差分输入电路和第二子差分输入电路,第一子差分输入电路在第一控制电压端的控制下输出放大的第一电流,第二子差分输入电路在第二控制电压端的控制下输出放大的第二电流；差分输出电路包括第一子差分输出电路和第二子差分输出电路,第一子差分输出电路接收第一电流后输出第一电平,第二子差分输出电路接收第二电流后输出第二电平；第一电平与第二电平相反,第一控制电压端输入至第一子差分输入电路的电压和第二控制电压端输入至第二子差分输入电路的电压为不相等任意值。(The embodiment of the application provides a branch input buffer circuit, a differential signal buffer circuit and an FPGA chip, relates to the technical field of integrated circuits, and can enlarge the common mode and differential mode input range. The differential input buffer circuit includes: the differential input circuit comprises a first sub differential input circuit and a second sub differential input circuit, wherein the first sub differential input circuit outputs an amplified first current under the control of a first control voltage end, and the second sub differential input circuit outputs an amplified second current under the control of a second control voltage end; the differential output circuit comprises a first sub-differential output circuit and a second sub-differential output circuit, the first sub-differential output circuit receives the first current and then outputs a first level, and the second sub-differential output circuit receives the second current and then outputs a second level; the first level is opposite to the second level, and the voltage input to the first sub-differential input circuit from the first control voltage end and the voltage input to the second sub-differential input circuit from the second control voltage end are unequal to any value.)

1. A differential input buffer circuit, comprising:

the differential input circuit comprises a first sub differential input circuit and a second sub differential input circuit, wherein the first sub differential input circuit outputs an amplified first current under the control of a first control voltage end, and the second sub differential input circuit outputs an amplified second current under the control of a second control voltage end;

the differential output circuit comprises a first sub-differential output circuit and a second sub-differential output circuit, the first sub-differential output circuit receives the first current and outputs a first level, and the second sub-differential output circuit receives the second current and outputs a second level;

the first level is opposite to the second level, and the voltage input to the first sub-differential input circuit from the first control voltage terminal and the voltage input to the second sub-differential input circuit from the second control voltage terminal are unequal to any value.

2. The differential input buffer circuit of claim 1, wherein the first sub-differential input circuit comprises a first N-type transistor, a first P-type transistor, and a second P-type transistor, and the second sub-differential input circuit comprises a second N-type transistor, a third P-type transistor, and a fourth P-type transistor;

the grid electrode of the first N-type transistor is electrically connected with a first control voltage end, the first electrode of the first N-type transistor is electrically connected with the grid electrode of the first P-type transistor, the grid electrode of the second P-type transistor is electrically connected with the second electrode, and the second electrode of the first N-type transistor is grounded;

the grid electrode of the second N-type transistor is electrically connected with a second control voltage end, the first electrode of the second N-type transistor is electrically connected with the grid electrode of the third P-type transistor, the grid electrode of the fourth P-type transistor is electrically connected with the second electrode, and the second electrode of the second N-type transistor is grounded;

the first electrode of the first P-type transistor, the first electrode of the second P-type transistor, the first electrode of the third P-type transistor and the first electrode of the fourth P-type transistor are electrically connected with a first voltage end;

the second pole of the first P-type transistor is electrically connected with the first sub-differential output circuit;

a second pole of the third P-type transistor is electrically connected with the second sub-differential output circuit;

the voltage of the first voltage end is greater than the voltages of the first control voltage end and the second control voltage end.

3. The differential input buffer circuit of claim 2, wherein the first sub-differential output circuit comprises a third N-type transistor and the second sub-differential output circuit comprises a fourth N-type transistor;

the grid electrode and the first electrode of the third N-type transistor are electrically connected with the second electrode of the first P-type transistor, and the second electrode is grounded;

and the grid electrode and the first electrode of the fourth N-type transistor are electrically connected with the second electrode of the third P-type transistor, and the second electrode is grounded.

4. The differential input buffer circuit of claim 3, wherein the first sub-differential output circuit further comprises a fifth P-type transistor, and the second sub-differential output circuit further comprises a sixth P-type transistor;

the grid electrode of the fifth P-type transistor is electrically connected with a second control voltage end, the first electrode of the fifth P-type transistor is electrically connected with a second voltage end, and the second electrode of the fifth P-type transistor is electrically connected with the grid electrode and the first electrode of the third N-type transistor;

the gate of the sixth P-type transistor is electrically connected to the first control voltage terminal, the first electrode is electrically connected to the second voltage terminal, and the second electrode is electrically connected to the gate and the first electrode of the fourth N-type transistor.

5. The differential input buffer circuit of any of claims 1-4, wherein the first N-type transistor is the same size as the second N-type transistor, the first P-type transistor is the same size as the third P-type transistor, the second P-type transistor is the same size as the fourth P-type transistor, and the third N-type transistor is the same size as the fourth N-type transistor.

6. A differential signal buffer circuit comprising a comparator circuit and the differential input buffer circuit of any one of claims 1-5;

the comparison circuit comprises a first input end and a second input end, the first input end receives a first level input by the first sub-differential output circuit, and the second input end receives a second level input by the second sub-differential output circuit;

the comparison circuit is configured to output a comparison result according to the first level and the second level.

7. The differential signal buffer circuit of claim 6, wherein in a case where the first sub-differential output circuit includes a third N-type transistor and the second sub-differential output circuit includes a fourth N-type transistor, the comparison circuit further includes a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a seventh P-type transistor, an eighth P-type transistor, a ninth P-type transistor, and a first inverter;

the grid electrode of the fifth N-type transistor is electrically connected with the grid electrode and the first electrode of the fourth N-type transistor, the first electrode of the fifth N-type transistor is electrically connected with the grid electrode of the eighth P-type transistor, the grid electrode of the seventh P-type transistor and the second electrode of the seventh P-type transistor, and the second electrode of the seventh P-type transistor is grounded;

the grid electrode of the sixth N-type transistor is electrically connected with the grid electrode and the first electrode of the third N-type transistor, the first electrode is electrically connected with the first node, and the second electrode is grounded;

the grid electrode of the seventh N-type transistor is electrically connected with the grid electrode and the first electrode of the fourth N-type transistor, the first electrode is electrically connected with the second node, and the second electrode is grounded;

a gate of the eighth N-type transistor is electrically connected to a third control voltage terminal, a first electrode is electrically connected to the first node, and a second electrode is grounded;

the first electrode of the seventh P-type transistor is electrically connected with the third voltage end;

a first electrode of the eighth P-type transistor is electrically connected to the third voltage terminal, and a second electrode of the eighth P-type transistor is electrically connected to the first node;

a gate of the ninth P-type transistor is electrically connected to the first node, a first electrode of the ninth P-type transistor is electrically connected to the third voltage terminal, and a second electrode of the ninth P-type transistor is electrically connected to the second node;

an input terminal of the first inverter is electrically connected to the second node, and the first inverter is configured to output a comparison result of the comparison circuit.

8. The differential signal buffer circuit of claim 6 or 7, wherein the comparison circuit further comprises a hysteresis circuit, an input of the hysteresis circuit being electrically connected with an output of the first inverter, the hysteresis circuit being configured to hysteresis output the comparison result.

9. The differential signal buffer circuit of claim 8, wherein the hysteresis circuit comprises a second inverter, a third inverter, a ninth N-type transistor, and a tenth N-type transistor; the input end of the second inverter is electrically connected with the output end of the first inverter and the grid electrode of the ninth N-type transistor, and the output end of the second inverter is electrically connected with the input end of the third inverter and the grid electrode of the tenth N-type transistor;

the third inverter is configured to output a comparison result of the comparison circuit;

a first pole of the ninth N-type transistor is electrically connected with the first pole of the second N-type transistor, and a second pole of the ninth N-type transistor is grounded;

the first pole of the tenth N-type transistor is electrically connected with the first pole of the first N-type transistor, and the second pole of the tenth N-type transistor is grounded.

10. An FPGA chip comprising the differential signal buffering circuit of any one of claims 6-9.

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and more particularly, to a differential input buffer circuit, a differential signal buffer circuit, and an FPGA chip.

Background

The traditional differential signal input circuit is directly realized by adopting an N-type MOS (metal oxide semiconductor) differential input pair tube or a P-type MOS differential input pair tube, and when the comparison circuit is applied to high-speed single-ended input standard, the input common-mode level range is limited, and the comparison circuit is only suitable for inputting a high level meeting a high voltage threshold or a low level meeting a low voltage threshold.

For high speed differential input standards, such as LVDS _25, LVDSEXT _25, HT _25, etc., a wider common mode input range and differential mode input range are required.

Disclosure of Invention

The embodiment of the application provides a differential input buffer circuit, a differential signal buffer circuit and an FPGA chip so as to solve the problems.

In a first aspect, a differential input buffer circuit is provided, comprising: a differential input circuit and a differential output circuit. And the differential input circuit comprises a first sub differential input circuit and a second sub differential input circuit, wherein the first sub differential input circuit outputs an amplified first current under the control of a first control voltage end, and the second sub differential input circuit outputs an amplified second current under the control of a second control voltage end. The differential output circuit comprises a first sub-differential output circuit and a second sub-differential output circuit, the first sub-differential output circuit receives the first current and outputs a first level, and the second sub-differential output circuit receives the second current and outputs a second level; the first level is opposite to the second level, and the voltage input to the first sub-differential input circuit from the first control voltage end and the voltage input to the second sub-differential input circuit from the second control voltage end are unequal to any value.

In a second aspect, a differential signal buffer circuit is provided, which includes a comparison circuit and the differential input buffer circuit of the first aspect. The comparison circuit comprises a first input end and a second input end, the first input end receives a first level input by the first sub-differential output circuit, and the second input end receives a second level input by the second sub-differential output circuit; the comparison circuit is configured to output a comparison result according to the first level and the second level.

In a third aspect, an FPGA chip is provided, which includes the differential signal buffer circuit of the second aspect.

In the differential input buffer circuit, the differential signal buffer circuit and the FPGA chip provided in the embodiments of the present application, the differential input buffer circuit includes a differential input circuit and a differential output circuit, the differential input circuit includes a first sub-differential input circuit and a second sub-differential input circuit, and the differential output circuit includes a first sub-differential output circuit and a second sub-differential output circuit. The first sub-differential input circuit outputs an amplified first current under the control of a first control voltage terminal IN _ N, then inputs the amplified first current to the first sub-differential output circuit, and outputs the amplified first current IN the form of a large voltage (a first level PRE _ OUT _ N); the second sub differential input circuit outputs the amplified second current under the control of the second control voltage terminal IN _ P, and then inputs the amplified second current to the second sub differential output circuit, and outputs the amplified second current as a large voltage (the second level PRE _ OUT _ P), and since the voltage input to the first sub differential input circuit by the first control voltage terminal IN _ N and the voltage input to the second sub differential input circuit by the second control voltage terminal IN _ P are not equal, the first level PRE _ OUT _ N and the second level PRE _ OUT _ P are amplified to different degrees, the difference between the first level PRE _ OUT _ N and the second level PRE _ OUT _ P increases, and the first level PRE _ OUT _ N can be regarded as a high level and the second level PRE _ OUT _ P can be regarded as a low level, or the first level PRE _ OUT _ N can be regarded as a low level and the second level PRE _ OUT _ P can be regarded as a high level. IN this way, as long as the voltage input to the first sub-differential input circuit from the first control voltage terminal IN _ N and the voltage input to the second control voltage terminal IN _ P from the second sub-differential input circuit are any unequal values, the differential input buffer circuit of the present application can output the first level PRE _ OUT _ N and the second level PRE _ OUT _ P which are opposite to each other, thereby expanding the common mode input range and the differential mode input range. On the basis, the first level PRE _ OUT _ N and the second level PRE _ OUT _ P can also be used as a power supply circuit of a next-stage circuit to provide an operating voltage for the next-stage circuit, so that the power consumption of the whole circuit is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a block diagram of a differential input buffer circuit according to an embodiment of the present disclosure;

fig. 2 is a circuit diagram of a differential input buffer circuit according to an embodiment of the present application;

fig. 3 is a block diagram of a differential signal buffer circuit according to an embodiment of the present disclosure;

fig. 4 is a circuit diagram of a differential signal buffer circuit according to an embodiment of the present application;

fig. 5 is a circuit diagram of a differential signal buffer circuit according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.

As shown in fig. 1, the present embodiment provides a differential input buffer circuit, which includes a differential input circuit 10 and a differential output circuit 20. The differential input circuit 10 includes a first sub-differential input circuit 11 and a second sub-differential input circuit 12. The differential output circuit 20 includes a first sub-differential output circuit 21 and a second sub-differential output circuit 22.

The first sub-differential input circuit 11 outputs the amplified first current under the control of the first control voltage terminal IN _ N, and the first sub-differential output circuit 21 receives the first current and outputs the first level PRE _ OUT _ N. The second sub-differential input circuit 12 outputs the amplified second current under the control of the second control voltage terminal IN _ P, and the second sub-differential output circuit 22 receives the second current and outputs the second level PRE _ OUT _ P.

The first level PRE _ OUT _ N is opposite to the second level PRE _ OUT _ P, and the voltage inputted to the first sub-differential input circuit 11 from the first control voltage terminal IN _ N and the voltage inputted to the second sub-differential input circuit 12 from the second control voltage terminal IN _ P are unequal to arbitrary values.

Specifically, as shown in fig. 2, the first sub-differential input circuit 101 includes a first N-type transistor N1, a first P-type transistor P1, and a second P-type transistor P2, and the second sub-differential input circuit 102 includes a second N-type transistor N2, a third P-type transistor P3, and a fourth P-type transistor P4. The first sub-differential output circuit 201 includes a third N-type transistor N3, and the second sub-differential output circuit 202 includes a fourth N-type transistor N4.

The gate of the first N-type transistor N1 is electrically connected to the first control voltage terminal IN _ N, the first pole is electrically connected to the gate of the first P-type transistor P1, the gate of the second P-type transistor P2 and the second pole, and the second pole is grounded. The gate of the second N-type transistor N2 is electrically connected to the second control voltage terminal IN _ P, the first pole is electrically connected to the gate of the third P-type transistor P3, the gate of the fourth P-type transistor P4 and the second pole, and the second pole is grounded. A first electrode of the first P-type transistor P1, a first electrode of the second P-type transistor P2, a first electrode of the third P-type transistor P3, and a first electrode of the fourth P-type transistor P4 are connected to the first voltage terminal electric potential V1, and a second electrode of the first P-type transistor P1 is electrically connected to the first sub-differential output circuit 201. The second pole of the third P-type transistor P3 is electrically connected to the second sub-differential output circuit 202. Wherein, the voltage of the first voltage terminal V1 is greater than the voltages of the first control voltage terminal IN _ N and the second control voltage terminal IN _ P.

The gate and first pole of the third N-type transistor N3 are electrically connected to the second pole of the first P-type transistor P1, which is grounded. The gate and first pole of the fourth N-type transistor N4 are electrically connected to the second pole of the third P-type transistor P3, which is grounded.

Assuming that the level of the first control voltage terminal IN _ N is low, the level of the second control voltage terminal IN _ P is high, and the voltage inputted from the first voltage terminal V1 is large.

Under the control of the first control voltage terminal IN _ N, the first N-type transistor N1 is turned off, the first P-type transistor P1 and the second P-type transistor P2 are also turned off, the current does not flow from the first P-type transistor P1 to the third N-type transistor N3, the current on the third N-type transistor N3 is almost zero, and therefore, the first level PRE _ OUT _ N output from the third N-type transistor N3 is also zero, and the first level PRE _ OUT _ N can be regarded as a low level.

Under the control of the second control voltage terminal IN _ P, the second N-type transistor N2 is turned on, the second pole of the second N-type transistor N2 is grounded, the second N-type transistor N2 tends to be pulled down, further, the voltage of the first pole of the second N-type transistor N2 is decreased, when the voltage of the first pole of the second N-type transistor N2 is decreased to a low level, the third P-type transistor P3 and the fourth P-type transistor P4 are turned on, the third P-type transistor P3 converts the voltage of the first voltage terminal V1 into a current to be sent to the fourth N-type transistor N4, and since the voltage of the first voltage terminal V1 is a large voltage, the current flowing to the fourth N-type transistor N4 is a large current. The fourth N-type transistor N4 may be equivalent to a resistor, and the fourth N-type transistor N4 may output the second level PRE _ OUT _ P in the form of a voltage after receiving a large current sent by the third P-type transistor P3, where the second level PRE _ OUT _ P may be regarded as a high level.

Assuming that the level of the first control voltage terminal IN _ N and the level of the second control voltage terminal IN _ P are neither high level nor low level, and the voltage of the first control voltage terminal IN _ N is greater than the voltage of the second control voltage terminal IN _ P, the voltage inputted from the first voltage terminal V1 is a large voltage.

Under the control of the second control voltage terminal IN _ N, the first N-type transistor N1 is turned on, the second pole of the first N-type transistor N1 is grounded, the first N-type transistor N1 tends to be pulled down, further, the voltage of the first pole of the first N-type transistor N1 is decreased, when the voltage of the first pole of the first N-type transistor N1 is decreased to a low level, the first P-type transistor P1 and the second P-type transistor P2 are turned on, the first P-type transistor P1 converts the voltage of the first voltage terminal V1 into a current to be sent to the third N-type transistor N3, and since the voltage of the first voltage terminal V1 is a large voltage, the current flowing to the third N-type transistor N3 is a large current. The third N-type transistor N3 may be equivalent to a resistor, and the third N-type transistor N3 may output the second level PRE _ OUT _ N in the form of a voltage after receiving a large current sent by the first P-type transistor P1.

Under the control of the second control voltage terminal IN _ P, the second N-type transistor N2 is turned on, the second pole of the second N-type transistor N2 is grounded, the second N-type transistor N2 tends to be pulled down, further, the voltage of the first pole of the second N-type transistor N2 is decreased, when the voltage of the first pole of the second N-type transistor N2 is decreased to a low level, the third P-type transistor P3 and the fourth P-type transistor P4 are turned on, the third P-type transistor P3 converts the voltage of the first voltage terminal V1 into a current to be sent to the fourth N-type transistor N4, and since the voltage of the first voltage terminal V1 is a large voltage, the current flowing to the fourth N-type transistor N4 is a large current. The fourth N-type transistor N4 may be equivalent to a resistor, and the fourth N-type transistor N4 may output the second level PRE _ OUT _ P in the form of a voltage after receiving a large current sent by the third P-type transistor P3.

As shown IN fig. 2, the differential input buffer circuit further includes an eleventh N-type transistor N11, the eleventh N-type transistor N11 is turned on under the control of the voltage terminal NN _ BIAS, and since the voltage of the first control voltage terminal IN _ N is greater than the voltage of the second control voltage terminal IN _ P, the current of the eleventh N-type transistor N11 is more drawn by the first N-type transistor N1, and the current of the first N-type transistor N1 is greater than the current of the second N-type transistor N2. Further, the current of the first P-type transistor P1 is larger than the current of the third P-type transistor P3, and the voltage of the first P-type transistor P1 divided from the first voltage terminal V2 is more than that of the third P-type transistor P3, that is, the first current is larger than the second current, the first current flows to the third N-type transistor N3 and then is converted into the first level PRE _ OUT _ N, the second current flows to the fourth N-type transistor N4 and then is converted into the second level PRE _ OUT _ P, and since the first level PRE _ OUT _ N and the second level PRE _ OUT _ P are both amplified levels, the difference between the first level PRE _ OUT _ N and the second level PRE _ OUT _ P increases, the first level PRE _ OUT _ N can be regarded as a high level, and the second level PRE _ OUT _ P can be regarded as a low level.

IN this case, for the first voltage terminal V1 to be greater than the voltages of the first control voltage terminal IN _ N and the second control voltage terminal IN _ P, it should be understood by those skilled IN the art that, for the transistor, the voltage input to the first pole is much greater than the voltage input to the gate, so that the voltage of the first voltage terminal V1 is a large voltage compared to the voltages of the first control voltage terminal IN _ N and the second control voltage terminal IN _ P, and when the third P-type transistor P3 operates IN the saturation region, the voltage of the first voltage terminal V1 can be output IN the form of a large current through the first pole and the second pole of the third P-type transistor P3.

Of course, the level of the first control voltage terminal IN _ N may be high, and the level of the second control voltage terminal IN _ P may be low, IN which case the first level PRE _ OUT _ N output by the third N-type transistor N3 is high, and the second level PRE _ OUT _ P output by the fourth N-type transistor N4 is low. Alternatively, assuming that the level of the first control voltage terminal IN _ N and the level of the second control voltage terminal IN _ P are neither a high level nor a low level, and the voltage of the first control voltage terminal IN _ N is smaller than the voltage of the second control voltage terminal IN _ P, IN this case, the first level PRE _ OUT _ N may be regarded as a low level, and the second level PRE _ OUT _ P may be regarded as a high level.

In some embodiments, a person skilled in the art typically sets a high level threshold and a low level threshold, with voltages above the high level threshold being high and voltages below the low level threshold being low. The high level threshold is not equal to the low level threshold, and the level of the first control voltage terminal IN _ N and the voltage of the second control voltage terminal IN _ P may be high level, low level, or neither high level nor low level.

In some embodiments, the first pole is a source and the second pole is a drain; alternatively, the first pole is a drain and the second pole is a source. As long as the first pole is one pole of the input and the second pole is one pole of the output.

In some embodiments, the first N-type transistor N1, the first P-type transistor P1, and the second P-type transistor P2, the second sub-differential input circuit 102 including the second N-type transistor N2, the third P-type transistor P3, and the fourth P-type transistor P4 may be field effect transistors, and the field effect transistors are used for converting a large voltage input from the first voltage terminal V1 into a large current output.

The embodiment of the application provides a differential input buffer circuit, which comprises a differential input circuit 10 and a differential output circuit 20, wherein the differential input circuit 10 comprises a first sub-differential input circuit 11 and a second sub-differential input circuit 12, and the differential output circuit 20 comprises a first sub-differential output circuit 21 and a second sub-differential output circuit 22. The first sub-differential input circuit 11 outputs the amplified first current under the control of the first control voltage terminal IN _ N, then inputs to the first sub-differential output circuit 21, and outputs IN the form of a large voltage (first level PRE _ OUT _ N); the second sub-differential input circuit 12 outputs the amplified second current under the control of the second control voltage terminal IN _ P, and then is input to the second sub-differential output circuit 22, and is output IN the form of a large voltage (second level PRE _ OUT _ P), since the voltage input to the first sub-differential input circuit 11 from the first control voltage terminal IN _ N and the voltage input to the second sub-differential input circuit 12 from the second control voltage terminal IN _ P are not equal, therefore, the first level PRE _ OUT _ N and the second level PRE _ OUT _ P are amplified to different degrees, the difference between the first level PRE _ OUT _ N and the second level PRE _ OUT _ P increases, further, the first level PRE _ OUT _ N can be regarded as a high level and the second level PRE _ OUT _ P as a low level, alternatively, the first level PRE _ OUT _ N is regarded as a low level, and the second level PRE _ OUT _ P is regarded as a high level. IN this way, as long as the voltage input to the first sub-differential input circuit 11 from the first control voltage terminal IN _ N and the voltage input to the second control voltage terminal IN _ P from the second sub-differential input circuit 12 are any values that are not equal to each other, the differential input buffer circuit of the present invention can output the first level PRE _ OUT _ N and the second level PRE _ OUT _ P that are opposite to each other, thereby expanding the common mode input range and the differential mode input range. On the basis, the first level PRE _ OUT _ N and the second level PRE _ OUT _ P can also be used as a power supply circuit of a next-stage circuit to provide an operating voltage for the next-stage circuit, so that the power consumption of the whole circuit is reduced.

Optionally, as shown in fig. 2, the first sub-differential output circuit 21 further includes a fifth P-type transistor P5, and the second sub-differential output circuit 22 further includes a sixth P-type transistor P6. The gate of the fifth P-type transistor P5 is electrically connected to the second control voltage terminal V2, the first pole is electrically connected to the second voltage terminal V2, and the second pole is electrically connected to the gate and the first pole of the third N-type transistor N3. The gate of the sixth P-type transistor P6 is electrically connected to the first control voltage terminal V1, the first pole is electrically connected to the second voltage terminal V2, and the second pole is electrically connected to the gate and the first pole of the fourth N-type transistor N4.

On this basis, the differential input buffer circuit may further include a tenth P-type transistor P10, a gate of the tenth P-type transistor P10 being electrically connected to the P _ BIAS, a first electrode being electrically connected to the second voltage terminal, and a second electrode being electrically connected to the first electrode of the fifth P-type transistor P5 and the first electrode of the sixth P-type transistor P6, respectively.

It is assumed that the level of the first control voltage terminal IN _ N is low and the level of the second control voltage terminal IN _ P is high.

The sixth P-type transistor P6 is turned on under the control of the first control voltage terminal IN _ N; under the control of the second control voltage terminal IN _ P, the fifth P-type transistor P5 is turned off. The voltage at the second voltage terminal V2 (i.e., the tenth P-type transistor P10) is divided by the sixth P-type transistor P6, converted into a current by the sixth P-type transistor P6, and then converted into a voltage output by the fourth N-type transistor N4, so as to further increase the voltage value of the second level PRE _ OUT _ P, thereby further increasing the difference between the first level PRE _ OUT _ N and the second level PRE _ OUT _ P.

Similarly, when the level of the first control voltage terminal IN _ N is high and the level of the second control voltage terminal IN _ P is low, the voltage value of the first level PRE _ OUT _ N may be further increased, so as to further increase the difference between the first level PRE _ OUT _ N and the second level PRE _ OUT _ P.

Of course, the above circuit is also applicable when the level of the first control voltage terminal IN _ N and the level of the second control voltage terminal IN _ P are neither high level nor low level.

In some embodiments, the voltage inputted to the second voltage terminal V2 is a large voltage, so that the current divided by the fifth P-type transistor P5 or the sixth P-type transistor P6 is more, and the difference between the first level PRE _ OUT _ N and the second level PRE _ OUT _ P is more.

Optionally, the size of the first N-type transistor N1 is the same as the size of the second N-type transistor N2, the size of the first P-type transistor P1 is the same as the size of the third P-type transistor P3, the size of the second P-type transistor P2 is the same as the size of the fourth P-type transistor P4, and the size of the third N-type transistor N3 is the same as the size of the fourth N-type transistor N4.

Thus, the characteristics of the first N-type transistor N1 and the second N-type transistor N2 are the same, the characteristics of the first P-type transistor P1 and the third P-type transistor P3 are the same, the characteristics of the second P-type transistor P2 and the fourth P-type transistor P4 are the same, and the characteristics of the third N-type transistor N3 and the fourth N-type transistor N4 are the same, so that the differential input buffer circuit can be adjusted.

As shown in fig. 3, the present application further provides a differential signal buffer circuit, which includes a comparison circuit 30 and the differential input buffer circuit described in any one of the preceding paragraphs.

The comparison circuit 30 includes a first input terminal receiving the first level PRE _ OUT _ N input from the first sub differential output circuit 21, and a second input terminal receiving the second level PRE _ OUT _ P input from the second sub differential output circuit 22. The comparison circuit 30 is configured to output a comparison result according to the first level PRE _ OUT _ N and the second level PRE _ OUT _ P.

Specifically, as shown in fig. 4, the comparison circuit 30 includes a fifth N-type transistor N5, a sixth N-type transistor N6, a seventh N-type transistor N7, an eighth N-type transistor N8, a seventh P-type transistor P7, an eighth P-type transistor P8, a ninth P-type transistor P9, and a first inverter INV _ 1.

The gate of the fifth N-type transistor N5 is electrically connected to the gate and the first pole of the fourth N-type transistor N4, the first pole is electrically connected to the gate of the eighth P-type transistor P8, the gate of the seventh P-type transistor P7 and the second pole, and the second pole is grounded. The gate of the sixth N-type transistor N6 is electrically connected to the gate of the third N-type transistor N3 and the first pole, the first pole is electrically connected to the first node X, and the second pole is grounded. The gate of the seventh N-type transistor N7 is electrically connected to the gate of the fourth N-type transistor N4 and the first pole, the first pole is electrically connected to the second node Y, and the second pole is grounded. The gate of the eighth N-type transistor N8 is electrically connected to the third control voltage terminal, the first electrode is electrically connected to the first node X, and the second electrode is grounded. The first pole of the seventh P-type transistor P7 is electrically connected to the third voltage terminal V3. The eighth P-type transistor P8 has a first pole electrically connected to the third voltage terminal V3 and a second pole electrically connected to the first node X. The gate of the ninth P-type transistor P9 is electrically connected to the first node, the first pole is electrically connected to the third voltage terminal V3, and the second pole is electrically connected to the second node Y. An input end of the first inverter INV _1 is electrically connected to the second node Y, and the first inverter INV _1 is configured to output the comparison result of the comparison circuit 100.

Taking the first level PRE _ OUT _ N as a low level, the second level PRE _ OUT _ P as a high level, and the voltage of the third voltage terminal as a large voltage as an example, under the control of the second level PRE _ OUT _ P, the fifth N-type transistor N5 is turned on, since the second pole of the fifth N-type transistor N5 is grounded, the fifth N-type transistor N5 tends to be pulled down, further, the voltage of the first pole of the fifth N-type transistor N5 is decreased, when the voltage of the first pole of the fifth N-type transistor N5 is decreased to a low level, the seventh P-type transistor P7 and the eighth P-type transistor P8 are turned on, and the eighth P-type transistor P8 transmits the voltage of the third voltage terminal V3 to the first node X. Although the seventh N-type transistor N7 is turned on under the control of the second level PRE _ OUT _ P, since the sixth N-type transistor N6 is turned off under the control of the first level PRE _ OUT _ N, so that the voltage of the first node is all pumped away by the gate of the ninth P-type transistor P9, the ninth P-type transistor P9 is turned off, the voltage input to the second node Y by the ninth P-type transistor P9 is abruptly reduced, and the second node Y is rapidly pulled down, but since the voltage of the second node Y may not be absolutely low, but only the voltage value is small, the voltage of the second node Y may be shaped and inverted by the first inverter INV _1, and the voltage of the second node Y is shaped to be high and output.

Similarly, when the first level PRE _ OUT _ N is high and the second level PRE _ OUT _ P is low, the Y node is pulled high, and the voltage at the second node Y can be shaped to be low by the first inverter INV _1 and output.

The embodiment of the present application provides a differential signal buffer circuit, which includes a comparison circuit 30 and any one of the differential input buffer circuits described above. Before the comparator is used for comparing the two voltage values, the input signal can be pre-amplified through the differential input buffer circuit to expand the common mode input range and the differential mode input range. On the basis, the first level PRE _ OUT _ N and the second level PRE _ OUT _ P output by the differential input buffer circuit can also be used as a power supply circuit of the comparison circuit 30 to provide working voltage for a next stage circuit, so that the power consumption of the whole differential signal buffer circuit is reduced.

Optionally, as shown in fig. 5, the comparing circuit 30 further includes a hysteresis circuit, an input end of the hysteresis circuit is electrically connected to the output end of the first inverter INV _1, and the hysteresis circuit is configured to output the comparison result in a hysteresis manner.

Specifically, as shown in fig. 5, the hysteresis circuit includes a second inverter INV _2, a third inverter INV _3, a ninth N-type transistor N9, and a tenth N-type transistor N10. An input end L of the second inverter INV _2 is electrically connected to an output end of the first inverter INV _1 and a gate of the ninth N-type transistor N9, and an output end R is electrically connected to an input end of the third inverter INV _3 and a gate of the tenth N-type transistor N10. The third inverter INV _3 is configured to output the comparison result of the comparison circuit 30.

The ninth N-type transistor has a first electrode electrically connected to the first electrode (PD _1) of the second N-type transistor N2, and a second electrode grounded. A first pole of the tenth N-type transistor N10 is electrically connected to the first pole (PD _2) of the first N-type transistor N1, and a second pole is grounded.

Taking the example that the voltage of the first control voltage terminal IN _ N is greater than the voltage of the second control voltage terminal IN _ P, the second node is pulled high suddenly, the output end L of the first inverter INV _1 is low, and further after passing through the second inverter INV _2, the output end R of the second inverter INV _2 is high, and under the action of the output end R of the second inverter INV _2, the tenth N-type transistor N10 is turned on; the ninth N-type transistor N9 is turned off by the output terminal L of the first inverter INV _ 1. The second inverter INV _2 passes throughThe ten N transistor N10 holds a current, denoted Δ I, to the first pole of the first N transistor N1. As long as the voltage of the first control voltage terminal IN _ N is greater than the voltage of the second control voltage terminal IN _ P, the applied current Δ I always belongs to the first N-type transistor N1. When the voltage of the second control voltage terminal IN _ P increases to be equal to the voltage of the first control voltage terminal IN _ N, I_N4＝0.5I_P10+0.5I_N11And I is_N3＝0.5I_P10+0.5I_N11Therefore, the voltage of the second control voltage terminal IN _ P needs to be increased by Δ V corresponding to the current Δ I to enable the comparator circuit 30 to output the opposite result.

Wherein, Δ I ═ K_N9×[(V_{gs_N9}+VCC-V_THN9)²-(V_{gs_N9}-V_{TH_N9})²]Equation 1.

ΔI_P4＝K_P4×[(|V_{gs_P4}|+ΔV-|V_{TH_P4}|)²-(V_{gs_P4}-V_{TH_P4})²]Equation 2.

△I＝ΔI_P4From equation 1 and equation 2, we obtain:

wherein the content of the first and second substances,w denotes a channel width of the transistor, and L denotes a channel length of the transistor.

VCC is the sum of the voltage input to the first control voltage terminal IN _ N and the voltage of the second control voltage terminal IN _ P.

Thus, the user can adjust the ratio of the channel length to the channel width of the ninth N-type transistor N9 according to the actual design requirement to adjust the hysteresis amount.

Similarly, when the voltage of the first control voltage terminal IN _ N is less than the voltage of the second control voltage terminal IN _ P, the hysteresis amount may be adjusted by adjusting the ratio of the channel length to the channel width of the tenth N-type transistor N10.

In the embodiment of the application, the delay circuit is arranged, so that the comparison result can be output in a delayed mode, the noise tolerance is improved, and the anti-interference capability of the differential signal buffer circuit is enhanced. For example, a voltage of 10mV is generated by noise before hysteresis, and by setting a certain hysteresis amount, the noise margin can be increased to 70mV, and thus the noise margin of 70mV can neutralize the noise of 10 mV.

The embodiment of the application also provides an FPGA chip which comprises the differential signal buffer circuit in any one of the embodiments. For explanation and advantageous effects thereof, reference may be made to the foregoing embodiments.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.