阅读说明：本技术 制造降低缺陷密度的超晶格结构的方法和器件 (Method and device for manufacturing superlattice structure with reduced defect density ) 是由 K·D·威克斯 N·W·科迪 M·海塔 R·J·米尔斯 R·J·史蒂芬森 于 2019-08-27 设计创作，主要内容包括：一种用于制造半导体器件的方法,可以包括在包括多个堆叠的层组的基板上形成超晶格,其中每个层组包括限定基础半导体部分的多个堆叠的基体半导体单层,以及被限制在相邻基础半导体部分的晶格内的至少一个非半导体单层。此外,形成基础半导体部分中的至少一个基础半导体部分可以包括过度生长至少一个基础半导体部分以及回蚀过度生长的至少一个基础半导体部分。(A method for fabricating a semiconductor device may include forming a superlattice on a substrate including a plurality of stacked groups of layers, wherein each group of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.)

1. A method for manufacturing a semiconductor device, comprising:

forming a superlattice on a substrate including a plurality of stacked groups of layers, wherein each group of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

wherein forming at least one of the base semiconductor portions comprises overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

2. The method of claim 1, wherein forming each base semiconductor portion further comprises:

forming a first set of base semiconductor monolayers;

performing thermal annealing; and

after the thermal anneal, a second set of base semiconductor monolayers is formed on the first set of base semiconductor monolayers.

3. The method of claim 2 wherein the first set of base semiconductor monolayers has a thickness in the range ofWithin the range of (1).

4. The method of claim 2 wherein the second set of base semiconductor monolayers has a thickness in the range ofWithin the range of (1).

5. The method of claim 1, wherein etching back the overgrown at least one base semiconductor portion comprises: 2 to 2 of the at least one base semiconductor portionAnd etching.

6. The method of claim 1, wherein etching back the overgrown at least one base semiconductor portion comprises: the overgrown at least one base semiconductor portion is etched at a temperature in the range of 500 to 750 ℃.

7. The method of claim 1, further comprising: a semiconductor cap layer is formed on the superlattice by forming a first semiconductor cap portion on the substrate at a first temperature and forming a second semiconductor cap portion on the first semiconductor cap portion at a second temperature greater than or equal to the first temperature.

8. The method of claim 7, wherein the thickness of the first semiconductor cap portion is between 4 and 4aWithin the range of (1).

9. The method of claim 1, wherein the base semiconductor monolayer comprises a silicon monolayer.

10. The method of claim 1, wherein the non-semiconductor monolayer comprises oxygen.

11. A semiconductor device, comprising:

a substrate; and

a superlattice on the substrate including a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, wherein an upper portion of at least one of the base semiconductor portions adjacent to the respective at least one non-semiconductor monolayer has a thickness of less than or equal to 1 x 10⁵/cm²The defect density of (2).

12. The semiconductor device of claim 11 wherein said superlattice comprises at least four groups of layers.

13. The semiconductor device of claim 11, wherein each base semiconductor portion is at a thickness ofWithin the range of (1).

14. The semiconductor device of claim 11 wherein said superlattice further comprises a semiconductor cap layer on said plurality of groups of layers.

15. The semiconductor device of claim 14, wherein the thickness of said semiconductor cap layer is in the range of 70 to 90 nm.

16. The semiconductor device of claim 11 further comprising source and drain regions on the substrate at opposite ends of the superlattice and a gate overlying the superlattice.

17. The semiconductor device of claim 11, wherein said base semiconductor monolayer comprises silicon.

18. The semiconductor device of claim 11, wherein said base semiconductor monolayer comprises germanium.

19. The semiconductor device of claim 11, wherein said non-semiconductor monolayer comprises oxygen.

Technical Field

The present disclosure relates generally to semiconductor devices and, more particularly, to methods for fabricating semiconductor devices with enhanced semiconductor materials.

Background

Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of charge carriers. For example, U.S. patent application No.2003/0057416 to Currie et al discloses strained material layers of silicon, silicon germanium, and relaxed silicon, and also includes impurity-free regions (which would otherwise cause performance degradation). The resulting biaxial strain in the upper silicon layer modifies carrier mobility, thereby enabling higher speed and/or lower power devices. Published U.S. patent application No.2003/0034529 to Fitzgerald et al discloses a CMOS inverter that is also based on similar strained silicon technology.

U.S. patent No.6,472,685b2 to Takagi discloses a semiconductor device including silicon and a carbon layer sandwiched between silicon layers such that the conduction and valence bands of the second silicon layer receive a tensile strain. Electrons that are of smaller effective mass and that have been induced by an electric field applied to the gate electrode are confined in the second silicon layer, thus asserting that the n-channel MOSFET has higher mobility.

U.S. patent No.4,937,204 to Ishibashi et al discloses a superlattice in which a plurality of layers, less than eight monolayers therein and containing fractional or binary compound semiconductor layers, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.

U.S. patent No.5,357,119 to Wang et al discloses a Si-Ge short period superlattice with higher mobility obtained by reducing alloy scattering in the superlattice. Along these lines, U.S. patent No.5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising a silicon alloy alternating with a second material in a percentage that places the channel layer under tensile strain in a silicon lattice.

U.S. patent No.5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and an epitaxially grown thin semiconductor layer sandwiched between the barriers. Each barrier region is composed of alternating layers of SiO2/Si, typically ranging in thickness from two to six monolayers. A much thicker portion of silicon is sandwiched between barrier layers.

An article entitled "photomona in silicon nanostructured devices" published by Tsu on-line at Applied Physics and Materials Science & Processing at page 391-402 on 6.9.2000 by Tsu discloses a Semiconductor Atomic Superlattice (SAS) of silicon and oxygen. Si/O superlattices useful in silicon quantum and light emitting devices are disclosed. In particular, a green electroluminescent diode structure was constructed and tested. The current flow in the diode structure is vertical, i.e. perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms and CO molecules. Silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial growth with a fairly low defect density. One SAS structure included a 1.1nm thick silicon portion that was approximately an eight atomic layer of silicon, while the other structure had twice the thickness of silicon. An article entitled "Chemical Design of Direct-Gap Light-Emitting Silicon" by Luo et al, published in Physical Review Letters, Vol.89, No. 7 (8/12 2002), further discusses the Light-Emitting SAS structure of Tsu.

Published international application WO 02/103,767 a1 to Wang, Tsu and Lofgren discloses barrier layer building blocks formed of thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic or hydrogen, whereby more than four orders of magnitude further reduce current flow vertically through the lattice. The insulating layer/barrier layer allows low defect epitaxial silicon to be deposited alongside the insulating layer.

Published british patent application 2,347,520 to Mears et al discloses that the principles of Aperiodic Photonic Bandgap (APBG) structures can be applied to electronic bandgap engineering. In particular, this application discloses that material parameters (e.g., location of band minima, effective mass, etc.) can be tailored to produce novel aperiodic materials with desirable band structure characteristics. It is also disclosed that other parameters such as electrical conductivity, thermal conductivity and dielectric constant or magnetic permeability may also be designed into the material.

Further, U.S. patent No.6,376,337 to Wang et al discloses a method for producing an insulating or barrier layer for a semiconductor device, the method comprising depositing a layer of silicon and at least one additional element on a silicon substrate, whereby the deposited layer is substantially defect-free, such that epitaxial silicon substantially defect-free can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements (preferably including oxygen) is absorbed on the silicon substrate. A plurality of insulating layers sandwiched between the epitaxial silicon form a barrier composite.

Despite the existence of such approaches, in certain applications, further enhancements may be desirable to use advanced semiconductor processing techniques.

Disclosure of Invention

A method for fabricating a semiconductor device may include forming a superlattice on a substrate including a plurality of stacked groups of layers, wherein each group of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

More particularly, forming each base semiconductor portion may further include: forming a first set of base semiconductor monolayers; performing thermal annealing; and forming a second set of base semiconductor monolayers on the first set of base semiconductor monolayers after the thermal anneal. As an exampleThe first set of base semiconductor monolayers may be of a thicknessAnd the thickness of the second set of base semiconductor monolayers may be withinWithin the range of (1).

According to an example, etching back the overgrown at least one base semiconductor portion may be comprised between 2 and 2 of the at least one base semiconductor portionAnd etching. Also by way of example, etching back the overgrown at least one base semiconductor portion may include etching the overgrown at least one base semiconductor portion at a temperature in the range of 500 to 750 ℃.

Further, forming the superlattice may further include forming the semiconductor cap layer by forming a first semiconductor cap portion on the plurality of groups of layers at a first temperature and forming a second semiconductor cap portion on the first semiconductor cap portion at a second temperature higher than the first temperature. As an example, the thickness of the first semiconductor cover part may be in the range of 4 to 4aWithin the range of (1). Also by way of example, the base semiconductor monolayer may comprise a silicon monolayer, and the non-semiconductor monolayer may comprise oxygen.

According to another aspect, a semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, an upper portion of at least one of the base semiconductor portions adjacent to the respective at least one non-semiconductor monolayer has a thickness that may be less than or equal to 1 × 10⁵/cm²The defect density of (2).

As an example, the superlattice may comprise at least four groups of layers. Further, the thickness of each base semiconductor portion may be withinWithin the range of (1). The superlattice may further include a semiconductor cap layer on groups of layers, and the semiconductor cap layer may have a thickness in a range of 70 to 90nm, for example. The semiconductor device may further include source and drain regions on the substrate at opposite ends of the superlattice and a gate overlying the superlattice. As an example, the base semiconductor monolayer may include silicon and/or germanium, and the non-semiconductor monolayer may include oxygen.

Drawings

Fig. 1 is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with an example embodiment.

Fig. 2 is a perspective atomic schematic of a portion of the superlattice shown in fig. 1.

Fig. 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice in accordance with an example embodiment.

Fig. 4A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon in the prior art and for the 4/1Si/O superlattice as shown in fig. 1-2.

Fig. 4B is a graph of the calculated band structure from the Z point for both bulk silicon in the prior art and for the 4/1Si/O superlattice as shown in fig. 1-2.

Fig. 4C is a graph of the calculated band structure from the gamma and Z points for both bulk silicon in the prior art and for the 5/1/3/1Si/O superlattice as shown in fig. 3.

Fig. 5 is a flow chart illustrating a process for fabricating a superlattice having a reduced defect density in accordance with example embodiments.

Fig. 6-12 are a series of schematic cross-sectional views illustrating corresponding steps of the method of fig. 5.

Fig. 13 is a flow chart illustrating another process for fabricating a superlattice having a reduced defect density in accordance with example embodiments.

Fig. 14 is a schematic cross-sectional view of a semiconductor device incorporating a superlattice fabricated in accordance with the methods of fig. 5 or 13.

Detailed Description

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. Embodiments may, however, be embodied in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.

In general, the present disclosure relates to processes for fabricating enhanced semiconductor superlattices or films, which are also referred to in the present disclosure as "MST" films or layers, or "MST techniques". More particularly, MST technology relates to advanced semiconductor materials, such as the superlattice 25 as further described below. Applicants theorize without wishing to be bound thereto that certain superlattices as described herein reduce the effective mass of charge carriers and that this results in higher charge carrier mobility. Effective masses are defined variously in the literature. As a measure to improve the effective mass, applicants use the "conductivity reciprocal effective mass tensor", and for electrons and holesAndfor electrons are defined as:

and for a hole is defined as:

where f is the Fermi-Dirac distribution, E_FIs the fermi energy, T is the temperature, E (k, n) is the energy of an electron in a state corresponding to wave vector k and the nth band, the indices i and j refer to cartesian coordinates x, y and z, the integration is taken over the Brillouin region (B.Z.), and the sum is taken over bands of electrons and holes with energies above and below the fermi energy, respectively.

Applicants' definition of the reciprocal effective mass conductivity tensor is such that a tensor component of the electrical conductivity of the material is greater for greater values of the corresponding component of the reciprocal effective mass conductivity tensor. Without wishing to be bound by this, applicants theorize again that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, for characterizing the semiconductor material structure, the conductivity effective mass of electrons/holes as described above and calculated in the direction of expected carrier transport is used to distinguish improved materials.

Applicants have identified improved materials or structures for use in semiconductor devices. More specifically, applicants have identified materials or structures having band structures for which the appropriate conductivity effective mass for electrons and/or holes is substantially less than the corresponding value for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in a manner that provides piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

Referring now to fig. 1 and 2, the material or structure is in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as may be best understood with specific reference to the schematic cross-sectional view of fig. 1.

Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon. For clarity of illustration, the energy band-modifying layer 50 is indicated by a dot-dash line in fig. 1.

The energy band-modifying layer 50 illustratively comprises a non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By "constrained within the crystal lattice of adjacent base semiconductor portions" it is meant that at least some of the semiconductor atoms from the opposing base semiconductor portions 46a-46n are chemically bonded together by the non-semiconductor monolayer 50 therebetween, as seen in fig. 2. In general, this configuration is made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n by atomic layer deposition techniques such that not all (i.e., less than full or 100% coverage) of the available semiconductor bonding sites are filled with bonds to non-semiconductor atoms, as will be discussed further below. Thus, when an additional monolayer 46 of semiconductor material is deposited on or over the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will fill the remaining vacant bonding sites of semiconductor atoms under the non-semiconductor monolayer.

In other embodiments, it is possible that there may be more than one such non-semiconductor monolayer. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that if the material for the monolayer is formed in bulk, it will be non-semiconductor or semiconductor. That is, as one skilled in the art will recognize, a single monolayer of a material (such as silicon) does not necessarily exhibit the same characteristics as if formed in bulk or in a relatively thick layer.

Without wishing to be limited thereto, applicants theorize that the energy band-modifying layer 50 and the adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The energy band-modifying layers 50 may also cause the superlattice 25 to have a common energy band structure while also advantageously acting as an insulator between layers or regions vertically above and below the superlattice.

Moreover, such a superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice 25. These characteristics may thus advantageously allow the superlattice 25 to provide an interface for the high-K dielectric that not only reduces diffusion of the high-K material into the channel region, but may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

It is also theorized that semiconductor devices incorporating the superlattice 25 may enjoy higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present.

In some embodiments, and as a result of the band design achieved by the present invention, the superlattice 25 may also have a substantially direct energy bandgap, which may be particularly advantageous for optoelectronic devices, for example.

The superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45 n. The cap layer 52 may include a plurality of base semiconductor monolayers 46. The cap layer 52 may range from 2 monolayers to that of the base semiconductorOr a larger (e.g.,) And more preferably between 10 and 50 monolayers.

Each base semiconductor portion 46a-46n may include a base semiconductor selected from group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, as will be appreciated by those skilled in the art, the term "group IV semiconductor" also includes group IV-IV semiconductors. More particularly, for example, the base semiconductor may include at least one of silicon and germanium.

Each energy band-modifying layer 50 may comprise a non-semiconductor selected from oxygen, nitrogen, fluorine, and carbon-oxygen, for example. It is also desirable to thermally stabilize the non-semiconductor by depositing the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with a given semiconductor process, as will be appreciated by those skilled in the art. More particularly, for example, the base semiconductor may include at least one of silicon and germanium.

It should be noted that the term "monolayer" is meant to include a single atomic layer as well as a single molecular layer. It should also be noted that the energy band-modifying layer 50 provided by a single monolayer is also meant to include monolayers in which not all possible sites are occupied (i.e., less than full or 100% coverage). For example, referring specifically to the atomic diagram of FIG. 2, an 4/1 repeating structure is illustrated, with silicon as the base semiconductor material and oxygen as the energy band-modifying material. In the example shown, only half of the possible sites for oxygen are occupied.

In other embodiments and/or for different materials, as those skilled in the art will recognize, this half occupation would not necessarily be the case. Indeed, even in this schematic diagram it can be seen that the individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane, as will be appreciated by those skilled in the art of atomic deposition. For example, a preferred occupancy range is approximately one-eighth to one-half of the possible oxygen site fill, although other numbers may be used in certain embodiments.

Silicon and oxygen are currently widely used in conventional semiconductor processing, and thus manufacturers will be readily able to use these materials described herein. Atomic or monolayer deposition is also now widely used. Thus, semiconductor devices incorporating the superlattice 25 in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.

For example, in one example implementation of a Si/O superlattice, the number of silicon monolayers may be seven or less, such that the energy band of the superlattice is common or relatively uniform throughout the superlattice to achieve desired advantages. However, in other embodiments, different spacings may be used, for example, up to 5nm or more. For Si/O, the 4/1 repeat structure shown in fig. 1 and 2 has been modeled to indicate enhanced mobility of electrons and holes in the X direction. For example, the calculated conductivity effective mass is 0.26 for electrons (isotropy for bulk silicon) and 0.12 for the 4/1SiO superlattice in the X direction, resulting in a ratio of 0.46. Similarly, for bulk silicon, the calculated value for holes is 0.36 and for the 4/1Si/O superlattice the value is 0.16, resulting in a ratio of 0.44.

While such directionally preferential features may be desirable in some semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. As will be appreciated by those skilled in the art, it may also be beneficial to have increased mobility for both electrons and holes, or only one of these types of charge carriers.

The lower conductivity effective mass of the 4/1Si/O embodiment of the superlattice 25 may be less than two-thirds of that which would otherwise occur, and this applies to both electrons and holes. Of course, the superlattice 25 may further comprise at least one type of conductivity dopant therein as will also be appreciated by those skilled in the art.

Indeed, referring now additionally to fig. 3, another embodiment of a superlattice 25' in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of 3/1/5/1 is shown. More particularly, the lowermost base semiconductor portion 46a 'has three monolayers, and the second lowermost base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25'. The energy band-modifying layers 50' may each comprise a single monolayer. For such superlattices 25' including Si/O, the enhancement of charge carrier mobility is independent of the orientation of the layers in the plane. Those other elements not specifically mentioned in fig. 3 are similar to those discussed above with reference to fig. 1 and need no further discussion herein.

In some device embodiments, all of the base semiconductor portions of the superlattice may be as thick as the same number of monolayers. In other embodiments, at least some of the base semiconductor portions may be as thick as a different number of monolayers. In other embodiments, all of the base semiconductor portions may be as thick as a different number of monolayers.

In fig. 4A-4C, the band structure calculated using Density Functional Theory (DFT) is presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Thus, all bands above the gap can be shifted by appropriate "scissor correction". However, the shape of the energy bands is known to be much more reliable. The vertical energy axis should be interpreted in this angle.

Fig. 4A shows the calculated band structure from the gamma point (G) for both the bulk silicon (represented by continuous lines) and for the 4/1Si/O superlattice 25 shown in fig. 1 (represented by dotted lines). The direction refers to the unit cell of the 4/1Si/O structure, not the conventional unit cell of Si, but the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, thus showing the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will recognize that the energy bands of Si on the figure are folded to represent them in the appropriate reciprocal lattice direction for the 4/1Si/O structure.

It can be seen that the conduction band minimum for the 4/1Si/O structure is located at the gamma point compared to bulk silicon (Si), while the valence band minimum occurs at the edge of the Brillouin region in the (001) direction, which we refer to as the Z point. It may also be noted that the conduction band minimum for the 4/1Si/O structure has a greater curvature than the curvature of the conduction band minimum for Si due to band splitting caused by the perturbation introduced by the additional oxygen layer.

Fig. 4B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and the 4/1Si/O superlattice 25 (dotted lines). This figure illustrates the enhanced curvature of the valence band in the (100) direction.

Fig. 4C shows the calculated band structure from both the gamma and Z points for both the bulk silicon (continuous lines) and the 5/1/3/1Si/O structure for the superlattice 25' of fig. 3 (dotted lines). The calculated band structures in the (100) and (010) directions are equivalent due to the symmetry of the 5/1/3/1Si/O structure. Thus, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers (i.e., perpendicular to the (001) stacking direction). Note that in the 5/1/3/1Si/O example, both the conduction band minimum and the valence band maximum are at or near the Z-point.

Although an increase in curvature indicates a decrease in effective mass, appropriate comparisons and determinations can be made via the conductivity reciprocal effective mass tensor calculation. This has led applicants further to the theory that 5/1/3/1 the superlattice 25' should be substantially a direct bandgap. As will be understood by those skilled in the art, a suitable matrix element for optical transition is another indicator of the distinction between direct bandgap behavior and indirect bandgap behavior.

Having described an example MST film structure, a method of depositing the MST film 25 that provides reduced defect density is now described with reference to the flowchart 100 of fig. 5 and fig. 6-11. In particular, a method is provided for fabricating the above-described MST film 25 using a Cyclic Deposition and Etch (CDE) process to grow the base semiconductor portions 46a-46n of the superlattice stack, thereby advantageously reducing the amount of physical defects formed in the MST superlattice film. In example implementations, the defect level may be reduced by at least one to two orders of magnitude for a given amount of oxygen incorporated in the MST film stack. While the above-described method provides MST films having relatively low defect levels, as well as significant mobility improvements and leakage reduction in semiconductor devices, the present method advantageously provides further reduction in defect levels in MST film stacks for applications that may be particularly sensitive to such defects.

Generally, the present method forms the base semiconductor portions 46a-46n, also referred to herein as "spacer layers," using a CDE process using a single CDE cycle (meaning one cycle includes a non-semiconductor (e.g., oxygen) dopant amount, spacers, and etch-back). Using such an etch back reduces defects in the spacer layer by removing the initial starting point of the defect. The etching process etches defective silicon more aggressively than defect-free silicon. For epitaxially grown non-defective regions, the etchant gas can only etch from the surface down, but the etch can etch in multiple directions where defects are present.

Beginning at block 101, the method illustratively includes a wafer or substrate 21 preparation stepIn this example, the step is loading and baking (block 102). Baking is generally used as an epitaxial growth surface pretreatment, but other methods may be used to prepare the substrate 21 for epitaxial growth. More particularly, single crystal silicon surfaces typically require some type of surface preparation, such as hydrogen baking, prior to epitaxial growth. Another alternative is to use H₂The O-rinse is a hydrofluoric acid (HF) wet clean followed by loading and low temperature bake in a reduced pressure chemical vapor deposition reactor. For example, another method may utilize a low temperature chemical treatment similar to the AMAT Siconi or ASM Previum processes. Those skilled in the art of epitaxial growth will appreciate that other suitable surface pretreatment methods may also be used, and the foregoing examples are not intended to be an exhaustive list of pretreatment methods.

At block 103, an in-situ semiconductor (e.g., epitaxial silicon) buffer layer 47 may then be formed on the substrate 21 (fig. 6) by appropriate pre-processing. Then, at block 104, oxygen monolayer(s) 50 may be formed on buffer layer 47 (fig. 7). One use of N is described in U.S. Pat. No.9,558,939 to Stephenson et al₂An exemplary method of forming a non-semiconductor monolayer using O as an oxygen source is assigned to the present applicant and is incorporated herein by reference in its entirety. However, it should be noted that other methods and oxygen (or other non-semiconductor) delivery agents may be used in different embodiments.

In the example shown, at block 105, a first base silicon portion 46a is then formed by blanket (blanket) epitaxial silicon deposition of a first set of base silicon monolayers having a thickness in the range ofAnd more particularly withinLeft and right (fig. 8). Then, an intermediate anneal is performed (block 106), and then at block 107, a second set of base silicon monolayers is blanket epitaxially grown to a thicknessWithin a range of (1) (fig. 9). The height of the first set of base silicon monolayers is shown by dashed line 48 in fig. 9. More particularly, the second growth is an overgrowth that is thicker than the final desired thickness of the base silicon portion 46 a. The overgrowth may then be etched back (fig. 10, block 108) to the final desired thickness of the base silicon portion 46 a. As an example, in a typical implementation, the amount of silicon that is etched back may be atWithin the range of (1).

The overgrowth and etch-back operations can be achieved over a relatively wide range of temperatures and pressures. As an example, the etching temperature range may be between 300 ℃ to 1200 ℃. More particularly, the temperature may range between 400 ℃ and 800 ℃, and more particularly, between 500 ℃ and 750 ℃ for typical implementations. For a chemical vapor deposition process, an example pressure range may be between 1 torr and 760 torr, and more particularly between 10 torr and 600 torr. Generally speaking, in a low pressure state (P)<1 torr) and ultra high vacuum state (P)<10^-7Torr) lower pressures may be used. The etch-back temperature and pressure may be isostatic and isothermal during growth, for example, to help provide higher process yields.

Although the CDE process can be used over the entire pressure range described above, high pressure implementation in a depressurized process space may be desirable because the diffusion length of the adsorbed atoms is shorter at these pressures than at LP and UHV. In LP and UHV deposition, atoms tend to diffuse towards the step angle away from the deposition area. Thus, for example, reduced pressure deposition and etched superlattice deposition may have smoother surfaces than LP and UHV treated wafers.

An example etchant gas may include Cl₂And HCl. HCl and Cl₂Work well with superlattice structures deposited on patterned/structured wafers because these etchants etch little or no oxidation of silicon in the temperature and pressure ranges used for, for example, atmospheric and reduced pressure chemical vapor deposition processesA substance and/or a nitride. For example, other suitable etchants, such as NF, may also be used₃. Such as TMAH (C)₄H₁₃NO) can be etched at room temperature by cyclically removing the wafer and reintroducing it into the growth reactor.

Then, at block 109, the steps illustrated above with respect to block 104-108 may be repeated to create a desired number of groups of layers of the superlattice 25. In the example shown in fig. 11, there are four groups of groups, but in other embodiments, more or fewer groups may be used. Further, as described above, in different embodiments, each of the base silicon portions 46a-46d may have the same number of silicon monolayers, an alternating number of silicon monolayers, or a different number of silicon monolayers.

Once all of the base silicon portions 46a-46d and the oxygen monolayer 50 are formed, another epitaxial silicon layer 52 (fig. 12) may be grown to create a final cap layer for the superlattice 25 (block 110). As an example, selective epitaxial growth may be used to cover the MST film for typical applications, but in some cases, non-selective, pseudo-selective, or any combination of the three growth methods may be used. Pseudo-selective growth involves a cyclic approach, i.e., one deposition and one etch. The method of fig. 5 illustratively concludes at block 111, but further processing steps may be performed to create a different type of semiconductor device incorporating the superlattice 25, as will be discussed further below.

The above process may be considered as pseudo-selective epitaxial growth, wherein the amorphous and/or polysilicon etch rate is selected to be faster than the epitaxial etch rate. In other words, the poly and/or amorphous to epitaxial etch rate ratio is selected to be greater than 1. If this is not the case, the entire superlattice spacer will be lost during etching before the unwanted non-selective deposition is removed from the non-single crystalline structure of the wafer. More particularly, the etch rate may be adjusted based on how aggressive it is desired to reduce defects in the superlattice 25 for a given application. As an example, the ratio of polysilicon and/or amorphous silicon to epitaxial etch selectivity may be greater than 1.5, and more particularly in the range of 1.5 to 10. However, higher selectivity ratios may also be used in some embodiments.

Turning now to the flowchart 100' of fig. 13, another exemplary method is provided that is already selective without etch back. Here, the initial blanket growth and anneal steps shown at blocks 105-106 of FIG. 5 are omitted, and instead cooling and selective epitaxial growth (e.g., 8 to 106) are performed) (block 117') to define the base silicon portions 46a-46d of the superlattice 25. For example, the subsequent etch back may be in the range of 2 toWithin the range of (1). In this case, the etch rate can be chosen to be relatively high but still controllable at a given pressure and temperature of spacer growth so that defects are removed at the highest rate, thereby minimizing the impact on process yield.

Both the pseudo-selective process 100 and the selective process 100' have improved etch-back defectivity. The amount of etch-back can be adjusted by increasing the amount of initial epitaxial growth, so there is a relatively wide window of possibilities for improving defectivity. The ranges provided above may be used to select particular process values such that the amount of deposition and etching advantageously results in the desired spacer thickness and defect level for the final MST film 25. Here again, as will be appreciated by those skilled in the art, the number of layer sets and the thickness for the spacers will vary based on the desired application of the MST film 25.

As noted above, after completion of the process steps shown in fig. 5 or 13, additional processing steps may be performed to create various devices, such as planar MOSFET 20 now described with reference to fig. 14. However, those skilled in the art will recognize that the materials and techniques identified herein may be used in many different types of semiconductor devices, such as discrete devices and/or integrated circuits. The illustrated MOSFET 20 includes a substrate 21, source/drain regions 22, 23, source/drain extensions 26, 27, and a channel region therebetween provided by a superlattice 25. As will be appreciated by those skilled in the art, source/drain silicide layers 30, 31 and source/drain contacts 32, 33 overlie the source/drain regions. The regions shown by the dashed lines 34, 35 are optional remnants of the superlattice 25 initially but are thereafter heavily doped. In other embodiments, these remaining superlattice regions 34, 35 may not be present, as will also be appreciated by those skilled in the art. The gate 35 illustratively includes a gate insulating layer 37 adjacent the channel provided by the superlattice 25, and a gate electrode layer 36 on the gate insulating layer. Sidewall spacers 40, 41 are also provided in the illustrated MOSFET 20. Using the fabrication techniques described above, ≦ 1 × 10 may be achieved in one or more of the base semiconductor portions 46a-46n of the superlattice 25 adjacent to the interface with the non-semiconductor monolayer 50⁵/cm²The defect density of (2).

It should also be noted that in some embodiments of the methods shown in fig. 5 and 13, additional epitaxial growth may optionally be performed after defect elimination (i.e., after the steps shown in blocks 108, 108'). As noted above, the methods discussed herein are advantageously used to help optimize the initial deposition to etch ratio to eliminate crystal defects. In some cases, additional epitaxial growth may be desirable because the optimal final spacer thickness for device performance may be too thick for a given set of process conditions to exceed the optimal deposition to etch ratio. Thus, after defect annihilation, an additional amount of silicon spacer growth may be used to meet device spacer thickness targets. As will be appreciated by those skilled in the art, after the steps shown at blocks 108, 108' are completed, the defects have been removed and any additional epitaxial growth may be grown defect-free.

By way of example, it may be desirable to have intervening oxygen monolayersIn the application of spacers, epitaxial growth of siliconAnd etching backThe roots reaching the defect may not be etched enough and this may lead to an undesirable amount of overgrowth and etching for yield considerations. Growth in totalAnd etching back siliconThereby leaving behindMay be more efficient. Then, the remainder may be grown in this example

Another potential advantage of this approach is membrane morphology. If a relatively thick spacer layer is grown and etched sufficiently to completely remove all defects, this may result in etch pits (pits) in the areas where defects were present. The nature of the growth process is such that if the indentation is shallow and of sufficiently small diameter, it will, together with the surface migration, smooth out these pits. At some depths and diameters, even the enhanced growth kinetics and surface migration within and around the pits are not sufficient to allow the pits to flatten/smooth/fill before superlattice growth is completed.

Generally, decreasing oxygen at a higher rate will result in more defects, but will also result in higher oxidation throughput. One example of this is oxidation at higher than optimal dose temperatures, which may be close to higher silicon spacer growth temperatures for throughput considerations. At higher temperatures, some oxygen may bond with the silicon, forming defects in the silicon spacer deposition. However, the above approach advantageously allows some trade-offs in process temperature, pressure, or carrier gas environment that may not be optimal for oxidation, but still achieves a final low defect density epitaxial superlattice in addition to high throughput processes. A method aimed at higher throughput may be to make the initial silicon layer smaller than the thickness of the device target spacers. However, this is acceptable because additional defect-free silicon can be grown on top of the now defect-free silicon spacer seed to achieve the target spacer thickness, as described above.

Another example would be the introduction of defects due to the silicon growth process. Silicon grown at very low temperatures (e.g., matched to elevated oxidation temperatures) may have deposited silicon adatoms and no time to move to the correct lattice site. This type of silicon growth case can be generated, for example, by depositing an epitaxial layer at a high growth rate in the temperature range of 400 to 600 ℃. For example, silicon atoms located at interstitial sites can cause dislocations to form and propagate throughout the subsequent epitaxial stack. Also, based on the selected process conditions, the etch back will polish/remove the defects at the optimal deposition to etch ratio. Additional silicon may then be added after etching to help ensure that the final spacer thickness adheres to the desired device target. As will be appreciated by those skilled in the art, additional silicon may be grown according to process conditions that result in defect-free growth.

Many modifications and other embodiments will come to mind to one skilled in the art having the benefit of the teachings presented herein. Therefore, it is to be understood that the disclosure is not limited to the specific exemplary embodiments disclosed herein.