阅读说明：本技术 具有n型上拉晶体管和低电压输出摆幅的发送器电路 (Transmitter circuit with N-type pull-up transistor and low voltage output swing ) 是由 哈里尚卡尔·斯里德哈兰 卡尔蒂克·泰姆贡德鲁 于 2019-06-27 设计创作，主要内容包括：提供了一种装置,其中该装置包括：耦合在电源节点和输出节点之间的第一晶体管；串联耦合在输出节点和接地端子之间的电阻器和第二晶体管；电路,该电路用于接收数据,并且用于输出第一控制信号和第二控制信号以分别控制第一晶体管和第二晶体管,其中输出节点处的输出信号指示数据,并且其中第一晶体管是N型晶体管。(An apparatus is provided, wherein the apparatus comprises: a first transistor coupled between a power supply node and an output node; a resistor and a second transistor coupled in series between the output node and a ground terminal; a circuit to receive data and to output a first control signal and a second control signal to control the first transistor and the second transistor, respectively, wherein an output signal at the output node is indicative of the data, and wherein the first transistor is an N-type transistor.)

1. An apparatus, comprising:

a first transistor coupled between a first power supply node and an output node;

a resistive device and a second transistor coupled in series between the output node and a second supply node; and

a pre-driver circuit to receive data and to output first and second control signals to control the first and second transistors, respectively,

wherein the first transistor is an N-type transistor.

2. The apparatus of claim 1, further comprising:

a third transistor coupled between the first power supply node and the output node,

wherein the third transistor is a P-type transistor, and

wherein the circuit is to output a third control signal to control the third transistor.

3. The apparatus of claim 2, wherein:

the circuit is configured to: turning off the third transistor via the third control signal in response to the voltage at the first power supply node being less than a threshold voltage.

4. The apparatus of claim 2, further comprising:

a multiplexer to receive a first power supply and a second power supply and to output one of the first power supply or the second power supply to the first power supply node.

5. The apparatus of claim 4, wherein:

the multiplexer is to: in a first mode of operation, outputting the first power supply at a first voltage level to the first power supply node;

the first voltage level is lower than a second voltage level of the second power supply; and is

The circuit is configured to: in the first operation mode, the third transistor is turned off via the third control signal.

6. The apparatus of claim 5, wherein:

the circuit is configured to: in the first mode of operation, on and off states of the first and second transistors are controlled to selectively pull up or pull down the output node based on the data.

7. The apparatus of claim 5, wherein:

the multiplexer is to: in a second mode of operation, outputting the second power supply at the second voltage level to the first power supply node; and is

The circuit is configured to: in the second mode of operation, the first transistor operating is turned off via the first control signal.

8. The apparatus of claim 7, wherein:

the circuit is configured to: in the second operation mode, on-states and off-states of the second transistor and the third transistor are controlled to selectively pull up or pull down the output node based on the data.

9. The apparatus of claim 5, wherein:

the first voltage level is equal to or less than 0.7 volts (V); and is

The second voltage level is higher than 1.0V.

10. The apparatus of claim 1, wherein:

the apparatus is a transmitter circuit, the transmitter circuit being included in one of: a memory controller to send data to a memory interface, or the memory interface coupled to a memory.

11. The apparatus of any one of claims 1 to 10, wherein:

a voltage of the first power supply node is higher than a voltage of the second power supply node; and is

An output signal at the output node is indicative of the data.

12. A system, comprising:

a memory to store instructions;

a processor to execute the instructions;

a wireless interface to facilitate the processor to communicate with another system; and

a transmit circuit to transmit data to or from the memory over a channel, the transmit circuit comprising:

a first transistor and a second transistor for pulling up a voltage of the channel, wherein the first transistor is coupled in parallel with the second transistor, and wherein at least one of the first transistor or the second transistor is an N-type transistor; and

a third transistor to pull down a voltage of the channel, wherein the third transistor is an N-type transistor.

13. The system of claim 12, wherein the transmit circuit further comprises:

a resistive device coupled in series with the third transistor.

14. The system of claim 12, wherein at most one of the first transistor or the second transistor is turned on at a given time.

15. The system of any one of claims 12 to 14, wherein:

the first transistor comprises the N-type transistor; and is

The second transistor comprises a P-type transistor.

16. The system of claim 15, wherein the first transistor and the second transistor are coupled between a power supply node and the channel, and wherein the transmit circuit comprises:

a multiplexer to receive a first power supply and a second power supply and to output one of the first power supply or the second power supply to the power supply node.

17. A transmitter circuit, comprising:

a first pull-up (PU) transistor and a second pull-up (PU) transistor coupled in parallel between a power supply node and an output node, wherein the first PU transistor comprises a P-type transistor, and wherein the second PU transistor comprises an N-type transistor;

a pull-down (PD) transistor coupled between the output node and a ground terminal; and

a multiplexer to selectively output one of: a first voltage or a second voltage.

18. The transmitter circuit of claim 17, further comprising:

a resistor coupled in series with the PD transistor such that the resistor and the PD transistor are coupled between the output node and the ground terminal.

19. The transmitter circuit of claim 17, wherein a source of the first PU transistor is coupled to a gate of the first PU transistor.

20. The transmitter circuit of claim 17, wherein:

the first voltage is higher than the second voltage; and is

In response to the first voltage being output to the power supply node through the multiplexer:

the first PU transistor is to be selectively turned on or off based on data to be sent through the output node; and

the second PU transistor will be turned off.

21. The transmitter circuit of any of claims 17 to 20, wherein:

the first voltage is higher than the second voltage; and is

In response to the second voltage being output to the power supply node through the multiplexer:

the second PU transistor is to be selectively turned on or off based on data to be sent through the output node; and

the first PU transistor will be turned off.

22. A method, comprising:

coupling a first pull-up (PU) transistor and a second pull-up (PU) transistor in parallel between a power supply node and an output node, wherein the first PU transistor comprises a P-type transistor, and wherein the second PU transistor comprises an N-type transistor;

coupling a pull-down (PD) transistor between the output node and a ground terminal; and

selectively outputting one of: a first voltage or a second voltage.

23. The method of claim 22, comprising:

coupling a resistor in series with the PD transistor such that the resistor and the PD transistor are coupled between the output node and the ground terminal, wherein a source of the first PU transistor is coupled to a gate of the first PU transistor.

24. The method of claim 22, comprising:

in response to the first voltage being output to the power supply node through a multiplexer:

selectively turn on or off the first PU transistor based on data to be sent through the output node; and

turning off the second PU transistor, wherein the first voltage is higher than the second voltage.

25. The method of claim 22, comprising:

in response to the second voltage being output to the power supply node through a multiplexer:

selectively turn on or off the second PU transistor based on data to be sent through the output node; and

turning off the first PU transistor.

Background

Modern computing devices are becoming energy efficient. For example, input/output (I/O) supply voltages in current and previous generations of Double Data Rate (DDR) memories (e.g., DDR1, DDR2, DDR3, DDR4, etc.) are equal to or higher than about 1.2 volts (V). However, the new generation of DDR memories (e.g., DDR5, low power DDRs such as LP4x, LP5, etc.) have much lower I/O supply voltages, e.g., in the range of 0.3-0.6V. It may be desirable to take advantage of such low I/O supply voltages, for example, for designing more efficient and power and area optimized I/O designs for new generation memory systems.

Drawings

In the drawings, the materials described herein are illustrated by way of example and not by way of limitation. For simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements. In the drawings:

fig. 1 schematically illustrates a transmitter circuit in accordance with some embodiments, wherein a driver of the circuit includes one or more pull-up (PU) transistors and one or more pull-down (PD) transistors, and wherein at least one of the one or more PU transistors is an N-type transistor.

Fig. 2 illustrates an example implementation of the transmitter circuit of fig. 1 in further detail, in accordance with some embodiments.

Fig. 3 schematically illustrates a transmitter circuit in accordance with some embodiments, wherein a driver of the circuit includes N-type PU transistors and P-type PU transistors.

Fig. 4 schematically illustrates the transmitter circuit of fig. 3, in which a level shifter is used to generate PU drive signals for the P-type PU transistors, in accordance with some embodiments.

Fig. 5 schematically illustrates the transmitter circuit of fig. 3, and also illustrates an example implementation of a predriver circuit, in accordance with some embodiments.

Fig. 6 illustrates an example eye diagram generated by any of the transmitter circuits of fig. 1-5, in accordance with some embodiments.

Fig. 7 illustrates a system in which any of the transmitter circuits of fig. 1-5 may be used, according to some embodiments.

Fig. 8 illustrates a flow diagram depicting a method for operating the transmitter circuit of any of fig. 3-5, in accordance with some embodiments.

Fig. 9 illustrates a computer system, computing device, or SoC (system on a chip) in accordance with some embodiments, wherein the computing device includes one or more of the transmitter circuits of fig. 1-8, wherein the transmitter circuits include at least one N-type transmitter in a pull-up path.

Detailed Description

Current and older generation memory devices (e.g., DDR1, DDR2, DDR3, DDR4, etc.) have higher supply voltages (e.g., above 1V) to drive the driver circuits of the transmitters. Thus, as discussed in further detail herein, the P-type transistor serves as a pull-up transistor in the driver circuit.

However, new generation memory devices (e.g., LP4x, LP5, etc.) have significantly reduced supply voltages (e.g., below 0.7V) to drive the driver circuits of the transmitters. Thus, as discussed in further detail herein, an N-type transistor may be used as a pull-up transistor in a driver circuit. Thus, in some embodiments, a transmitter for a new generation memory device has an N-type transistor for pulling up an output node of the transmitter circuit.

Further, to make the transmitter circuit universally compatible (e.g., to enable the transmitter circuit to work with current and older generation memory devices as well as new generation memory devices), parallel coupled P-type transistors and N-type transistors may be used in the pull-up driver circuit. When the transmitter circuit is used with current and older generation memory devices (e.g., where the driver supply voltage is greater than 1V), the P-type transistor is used for pull-up, while the N-type transistor is disabled. On the other hand, when the transmitter circuit is used with a new generation of memory devices (e.g., where the driver supply voltage is less than 0.7V), the N-type transistor is used for pull-up, while the P-type transistor is disabled. Thus, the transmitter circuit can be used for current and old generation memory devices, as well as new generation memory devices.

Furthermore, the use of N-type devices makes it possible to: the pre-driver circuit is operated at a relatively low voltage (e.g., less than 0.7V). This eliminates many high voltage components in the pre-driver circuit (e.g., components operating at more than 1V). For example, a conventional transmitter circuit has one or more P-type transistors for pull-up and one or more N-type transistors for pull-down, a pre-driver circuit has multiple level shifters, a Vss-Hi power supply (e.g., where the Vss-Hi power supply is slightly higher than ground, but lower than the power supply voltage of the driver circuit), and so on. In contrast, since the transmitter circuits discussed in this disclosure use N-type transistors for both pull-up and pull-down, these components are not required by the pre-driver of the transmitter circuit (e.g., multiple level shifters, Vss-Hi power supplies, etc. are not required). For the transmitter circuits discussed in this disclosure, this results in savings in area, performance, and/or power (compared to conventional transmitter circuits). Other technical effects will be apparent from the various embodiments and drawings.

One or more embodiments are described with reference to the accompanying drawings. Although specific configurations and arrangements are described and discussed in detail, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to one skilled in the relevant art that the techniques and/or arrangements described herein may be used in a variety of other systems and applications beyond those detailed herein.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which illustrate exemplary embodiments. Moreover, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references, such as upper, lower, top, bottom, etc., may be used merely to facilitate describing the features in the drawings. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and equivalents thereof.

In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known methods and apparatus are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in an embodiment" or "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment wherever particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to any and all possible combinations of one or more of the associated listed items and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "coupled" may be used to indicate that two or more elements are in direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that two or more elements are in cooperation or interaction with each other (e.g., as in a cause and effect relationship).

The terms "substantially", "close", "approximately", "adjacent" and "approximately" generally mean within +/-10% of a target value. For example, the terms "substantially equal," "about equal," and "approximately equal" mean that there is only incidental variation between the described things, unless otherwise indicated in the explicit context of their use. In the art, this variation is typically no greater than +/-10% of the predetermined target value.

The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another, and then shrinking in the layout area. The term "scaling" also generally refers to shrinking the layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up-e.g., respectively scaling down or amplifying) the signal frequency relative to another parameter (e.g., the power supply level).

As used throughout the specification and in the claims, a list of items joined by the term "at least one" or "one or more" may refer to any combination of the listed items. For example, the phrase "A, B or at least one of C" may represent a; b; c; a and B; a and C; b and C; or A, B and C.

The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. For example, the terms "above," below, "" front side, "" back side, "" top, "" bottom, "" above …, "" below …, "and" on. These terms are used herein for descriptive purposes only and are used primarily in the context of the z-axis of the device and thus may relate to the orientation of the device. Thus, a first material "above" a second material in the context of the figures provided herein may also be "below" the second material if the apparatus is oriented upside down with respect to the context of the figures provided. In the context of materials, a material disposed above or below another material may be in direct contact or may have one or more intervening materials. Also, a material disposed between two materials may be in direct contact with both layers, or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with the second material. Similar distinctions will be made in the context of assembly of components.

The term "between" may be used in the context of the z-axis, x-axis, or y-axis of the device. The material between the two other materials may be in contact with one or both of these materials, or may be separated from both of these other materials by one or more intermediate materials. Thus a material between two other materials may be in contact with either of the two other materials or may be coupled to the two other materials through an intermediate material. A device between two other devices may be directly connected to one or both of the devices or may be separated from both of the other devices by one or more intermediate devices.

It is pointed out that those elements of the drawings having the same reference numbers (or names) as the elements of any other drawing can operate or function in any manner similar to that described, but are not limited to such.

Fig. 1 schematically illustrates a transmitter circuit 100 (also referred to as circuit 100) in accordance with some embodiments, wherein a driver 130 of the circuit 100 includes one or more pull-up (PU) transistors 134 and one or more pull-down (PD) transistors 138, and wherein at least one of the one or more PU transistors 134 is an N-type transistor.

In some embodiments, the circuit 100 includes a pre-driver circuit 118 (also referred to as circuit 118). The circuit 118 receives the data input 102 via a Time To Clock Out (TCO)/delay circuit 110. The circuit 118 also receives the driver input 104 via the TCO/delay circuit 112. The circuit 118 also receives the equalizer input 106 via the TCO/delay circuit 114. In some embodiments, and as will be discussed in further detail herein, the pre-driver circuitry 118 may include a decoder, pre-driver logic, etc., e.g., to generate a pull-up (PU) drive signal 122 and a pull-down (PD) drive signal 126, e.g., based at least in part on the data 102. For example, the pre-driver circuit 118 includes decoders, multiplexers, level shifters, etc., that convert the data 102 into the PU drive signal 122 and the PD drive signal 126.

Driver 130 includes one or more PU transistors 134 and one or more PD transistors 138. The PU transistor 134 and the PD transistor 138 control an output signal 142 (also referred to as output 142) at an output node 147 based on the data 102. For example, a high logic value of data 102 produces a relatively high voltage at output node 147 (e.g., PU transistor 134 pulls output node 142 up to a relatively high voltage), and a low logic value of data 102 produces a relatively low voltage at output node 147 (e.g., PD transistor 138 pulls output node 142 down to a relatively low voltage). In some embodiments, the driver 130 is driven by the driving voltage Vdrv 151 from the driving power supply node 145. In some embodiments, the swing in the output signal 142 at the output node 147 (e.g., where the swing is the difference between the high and low voltages at the output node 147) may be based on the drive voltage Vdrv 151. Output 142 is sent to a receiver (not shown in fig. 1) via communication channel 143.

In an example, the circuit 100 may be used in a transmitter of a memory controller and/or a transmitter of a memory interface (e.g., as discussed later herein with respect to fig. 7). In an example, during current and previous generation DDR technology, driver 130 may be driven using relatively high voltages. As an example, if the memory controller is used with a DDR1 memory, the drive voltage Vdrv is about 2.5V. For DDR2, DDR3, and DDR4, the drive voltage Vdrv is about 1.8V, 1.5V, and 1.2V, respectively. Newer generation DDR memories, such as LP4x DDR, LP5 DDR, etc., may use lower voltages, such as voltages in the range of 0.7V to 0.3V (e.g., at least less than 1.0V). Accordingly, the driving voltage Vdrv may be in the range of 1.2V to 2.5V (e.g., if DDR1, DDR2, DDR3, or DDR4 are used), or may be in the range of 0.3V to 0.7V (e.g., if a new generation memory such as LP4x DDR, LP5 DDR, DDR5, etc.) based on the memory in which the circuit 100 is to be used.

Conventionally (e.g., for relatively high values of the drive voltage Vdrv, such as the drive voltage Vdrv is at least up to 1.0V), a P-type transistor is used for pull-up. This is because the N-type pull-up transistor may not be fully turned on for relatively low driving voltages. The use of an N-type pull-up transistor can result in a swing at the output node in the millivolt range, which is generally insufficient for conventional transmitters.

However, when the driving voltage Vdrv in the circuit 100 can be relatively low (e.g., at 0.7V or even lower), the N-type PU transistor may be turned on during the pull-up state of the circuit 100. As will be discussed in detail herein, the N-type PU transistor may enable a voltage swing in the range of hundreds of millivolts (mV), such as in the range of about 150mV to about 300 mV. Such low voltage swings may be sufficient for modern transmitters and receivers, such as those used for new generation memories (e.g., LP4x DDR, LP5 DDR, DDR5, etc.).

Fig. 2 illustrates an example implementation of the transmitter circuit 100 of fig. 1 in further detail, in accordance with some embodiments. Specifically, the driver 130 is shown in further detail.

In some embodiments, the driver 130 includes a PU transistor 234, the PU transistor 234 being coupled between the drive supply node 145 and the output node 147. Driver 130 also includes a resistor 249 and a PD transistor 238, the resistor 249 and PD transistor 238 being coupled between output node 147 and a ground terminal.

Although a resistor 249 is shown in fig. 2, in an example, the resistor 249 (or any other resistor discussed with respect to any other figure) may be replaced by any suitable resistive device, such as: transistors operating in the active region, passive resistors provided by process nodes (e.g., polysilicon resistors), thin film resistors, devices fabricated at the front end of the die (e.g., the active region up to the lower Metal layers, such as Metal 3), devices fabricated at the back end of the die (at upper Metal layers, such as M4 and higher), off-chip resistive devices, on-chip resistive devices, resistive devices formed in the substrate of the package, and the like.

In some embodiments, transistor 234 is an N-type transistor, for example, an N-type metal oxide semiconductor field effect transistor (nMOS FET, NFET or nMOS transistor). In some embodiments, transistor 238 is an N-type transistor, e.g., an nMOS FET, NFET, or nMOS transistor.

When a low or logic 0 bit of data 102 is to be transmitted (also referred to as a pull-down state of circuit 100), PU drive signal 122 turns off PU transistor 234 and PD drive signal 126 turns on PD transistor 238. When the drive voltage Vdrv 151 is disconnected from the output node 147 (e.g., when the PU transistor 234 is off), and when the output node 147 is coupled to a ground terminal (e.g., via the PD transistor 238 and the resistor 249), the output 142 is pulled down and has a relatively low voltage (e.g., is zero or near zero).

When a high or logic 1 bit of data 102 is to be transmitted (also referred to as a pull-up state of circuit 100), PU drive signal 122 turns on PU transistor 234 and PD drive signal 126 turns off PD transistor 238. When the drive voltage Vdrv 151 is coupled to the output node 147 (e.g., via the PU transmitter 234), and when the output node 147 is disconnected from the ground terminal (e.g., when the PD transistor 238 is turned off), the output 142 is pulled up and has a relatively high voltage.

In the example of fig. 2, the drive voltage Vdrv is in the range of 0.3V-0.7V. The swing in output node 147 (e.g., the voltage difference between output node 147 at a relatively high voltage corresponding to a logic 1 of data 102 and a relatively low voltage corresponding to a logic 0 of data 102) may be in the range of about 150mV to about 300mV, depending on drive voltage Vdrv 151, for example.

As discussed above, for relatively high values of the drive voltage Vdrv 151 (e.g., the drive voltage Vdrv is at least as high as 1.2V), a P-type transistor is used for pull-up. This is because the N-type pull-up transistor may not be fully turned on for relatively low driving voltages. Furthermore, the use of an N-type pull-up transistor can result in a swing at the output node in the millivolt range, which is generally insufficient for conventional transmitters. However, when the driving voltage Vdrv in the circuit 100 of fig. 2 is relatively low (e.g., at 0.7V or even lower), the N-type PU transistor 234 may be fully turned on during the pull-up state of the circuit 100. The N-type transistors 234, 238 may enable a voltage swing of the output 142 in a range of several hundred millivolts, such as in a range of about 150mV to about 300 mV. Such low voltage swings may be sufficient for modern transmitters and receivers, such as those used for new generation memories (e.g., LP4x DDR, LP5 DDR, DDR5, etc.).

In an example, an N-type transistor has a relatively high non-linearity when used as a pull-up transistor (e.g., an N-type transistor passes 0 better than 1 due to its inherent properties). However, for lower output swings (e.g., output swings of about 300mV or less, such as swings in the storage interface of new generation memories (e.g., LP4x, LP5, etc.)), N-type transistors are a good choice (e.g., because P-type transistors cannot typically be used for such low output voltage swings). Because the operation is at a V of 300mV or less_DSOr output voltage swing, the overall impact on linearity using N-type transistors is relatively small.

Enabling the driver 130 with the PU N-type transistor 234 is linear because the swing in the output 142 and the drive voltage Vdrv 151 are relatively low. The PU N-type transistor 234 may cause nonlinearity at a higher value of the driving voltage Vdrv 151, but, for the example of fig. 2, since the upper limit of the driving voltage Vdrv 151 is about 0.7V, such nonlinearity does not occur in the driver 130.

In conventional drive circuits, no resistor is coupled in series with the pull-down transistor, instead, the resistor is typically coupled at the output node 142, e.g., in series with a communication channel (e.g., communication channel 143). However, in circuit 100, driver 130 has a resistor 249 in series with PD transistor 238. For example, since the N-type transistor 234 is used as a PU transistor, the resistor between the PU transistor 234 and the channel 143 may effectively lower the drive voltage Vdrv 151, making it difficult for the N-type PU transistor to be fully turned on during the pull-up phase. Therefore, it is desirable not to insert a resistor in series with the PU transistor 234 during the pull-up phase (e.g., when the PU transistor 234 is to be turned on and the PD transistor 238 is to be turned off). Thus, circuit 100 lacks a resistor in series with channel 143. If such a resistor is present in series with the channel, the turn-on process of the N-type PU transistor 234, and thus the linearity of the driver 130, may be adversely affected. However, resistor 249 in series with PD transistor 238 dominates the linearity of driver 130, thereby helping driver 130 achieve linearity.

Fig. 3 schematically illustrates a transmitter circuit 300 (also referred to as circuit 300) in accordance with some embodiments, wherein a driver 330 of circuit 300 includes N-type PU transistors 334a and P-type PU transistors 334 b.

The circuit 300 is at least partially similar to the circuit 100 of fig. 1 and 2. For example, similar to the circuit 100, the circuit 300 includes a pre-driver circuit 318 (also referred to as circuit 318), the pre-driver circuit 318 receiving the data input 302 (e.g., via the TCO/delay circuit 310), the driver input 304 (e.g., via the TCO/delay circuit 312), and the equalizer input 306 (e.g., via the TCO/delay circuit 314).

In some embodiments, the pre-driver circuit 318 may include a decoder, pre-drive logic, etc., for example, to generate the PU drive signals 322a and 322b that control the PU transistors 334a and 334b, respectively. The pre-driver circuit 318 also generates a PD drive signal 326 to control the N-type PD transistor 338.

Driver 330 includes PU transistors 334a, 334b and PD transistor 338. The PU transistors 334a, 334b are coupled in parallel between the drive supply node 345 and the output node 347. Transistor 334b is a compensated P-type transistor with the source of transistor 334b coupled to the gate of transistor 334 b. Resistor 349 and PD transistor 338 are coupled in series between output node 347 and a ground terminal (e.g., similar to fig. 2).

The circuit 300 also includes a multiplexer 350 for receiving the high drive voltage VdrvH 355 and the low drive voltage VdrvL 356. The high drive voltage VdrvH 355 may be higher than the low drive voltage VdrvL 356. Mode select signal 301 controls multiplexer 350. The multiplexer 350 outputs one of the high drive voltage VdrvH 355 or the low drive voltage VdrvL 356 as the drive voltage Vdrv 351 as an output at the drive power supply node 345 based on the mode select signal 301.

For example only, while the circuit 100 of fig. 1 and 2 may be used for low voltage operation (e.g., where the drive voltage Vdrv 151 may have a value of 0.7V or lower), the circuit 300 may be suitable for both low voltage and high voltage operation.

For example, when the circuit 300 is to be used with a memory having a relatively high voltage rating (e.g., DDR1, DDR2, DDR3, DDR4, etc.), the multiplexer 350 may output a high drive voltage VdrvH 355, this mode of operation of the circuit 300 also being referred to as a high voltage mode of the circuit 300. For the high voltage mode of the circuit 300, the high drive voltage VdrvH 355 may be in the range of about 1.2V to about 2.5V, e.g., may be higher than at least 1.0V.

In addition, when the circuit 300 is to be used with a memory having a relatively low voltage rating (e.g., LP4x DDR, LP5 DDR, DDR5, etc.), the multiplexer 350 may output a low drive voltage VdrvL 356, this mode of operation of the circuit 300 also being referred to as a low voltage mode of the circuit 300. For the low voltage mode of the circuit 300, the low drive voltage VdrvL 356 may be in the range of about 0.3V to about 0.7V, or at least less than 1V. Thus, the mode select signal 301 may be set based on memory used with the circuit 300.

For the reasons discussed with respect to fig. 1 and 2, when circuit 300 is operating in a low voltage mode (e.g., drive voltage Vdrv 351 at node 345 is voltage VdrvL 356), N-type PU transistor 334a may be sufficient to pull up output node 347, e.g., for generating a sufficient swing (e.g., a swing in the range of approximately 150mV-300mV as discussed with respect to fig. 1-2) at output node 347. Thus, when the circuit 300 operates in the low voltage mode, the P-type PU transistor 334b is always turned off, and the N-type PU transistor 334a is selectively turned on (e.g., when the output node 347 is to be pulled up to a relatively high voltage) and off (e.g., when the output node 347 is to be pulled down to a relatively low voltage). Thus, when the circuit 300 operates in the low voltage mode, the N-type PU transistor 334a and the N-type PD transistor 338 are used to control the output node 347.

The pre-driver circuit 318 also receives the mode select signal 301. In some embodiments, when the circuit 300 operates in the low voltage mode, the pre-driver circuit 318 generates the PU drive signals 322a, 322b such that the P-type PU transistor 334b is turned off during the pull-up and pull-down of the output node 247, and the N-type PU transistor 334a is turned on or off to pull-up or pull-down the output node 247, respectively.

On the other hand, in some embodiments, when the circuit 300 operates in the high voltage mode, the pre-driver circuit 318 generates the PU drive signals 322a, 322b such that the N-type PU transistor 334a is turned off during the pull-up and pull-down of the output node 347, and the P-type PU transistor 334b is turned on or off to pull-up or pull-down the output node 347, respectively.

Fig. 4 schematically illustrates the transmitter circuit 300 of fig. 3 in which a level shifter 411 is used to generate the PU drive signal 322b for the P-type PU transistor 334b, in accordance with some embodiments. For example, as discussed above, the N-type PU transistor 334a is used during the low voltage mode of the circuit 300 and the P-type PU transistor 334b is used during the high voltage mode of the circuit 300. For example, PU drive signal 322a (and one or more other components of pre-driver circuit 318) may operate at a relatively low voltage compared to the voltage level of PU drive signal 322 b. Thus, in some embodiments, such as when the circuit 300 is operating in a high voltage mode, the level shifter 411 is used to generate the PU drive signal 322b at a relatively high voltage. The level shifter 411 is used to change the voltage level of the PU drive signal 322b from a relatively low voltage (e.g., at which the pre-driver circuit 318 operates) to a relatively high voltage (e.g., at which the gate of the PU transistor 334b operates).

Fig. 5 schematically illustrates the transmitter circuit 300 of fig. 3, and also illustrates an example implementation of the predriver circuit 318, in accordance with some embodiments. In some embodiments, the pre-driver circuit 318 receives the PU-PFET code 572 and/or the PU-NFET code 574. For example, the PU-PFET code 572 is used to generate the PU drive signal 322b, e.g., when the circuit 300 is operating in a high voltage mode. The PU-NFET code 574 is used to generate the PU drive signal 322a, for example, when the circuit 300 is operating in a low voltage mode. Thus, in essence, PU-PFET code 572 is used to control the P-type PU transistor 334b and PU-NFET code 574 is used to control the N-type PU transistor 334 a. The PU-PFET code 572 and/or the PU-NFET code 574 are generated based on the data 102. For example, a high logic value of data 102 means that output node 347 is to be pulled up by drive voltage Vdrv 351 and one of PU transistors 334a, 334b is to be turned on (e.g., depending on the operating mode of circuit 300). On the other hand, a low logic value of the data 102 means that the output node 347 is to be pulled down and the PU transistors 334a, 334b are to be turned off. The PU-PFET code 572 and/or the PU-NFET code 574 are generated accordingly, e.g., based on the data 102.

As discussed with respect to fig. 3, the mode select signal 301 indicates whether the circuit 300 is operating in a high voltage mode or a low voltage mode. The pre-driver circuit 318 in fig. 5 receives a mode signal 501, the mode signal 501 also indicating whether the circuit 300 is operating in a high voltage mode or a low voltage mode. For example, the mode selection signal 301 and the mode signal 501 may be the same signal, may be derived from a signal source, are correlated, and so on.

As discussed with respect to fig. 4, the PU drive signal 322b may be at a higher voltage level than, for example, one or more components of the pre-driver circuit 318. Thus, in fig. 5, level shifter 411 receives PU-PFET code 572 and generates PU drive signal 322 b. The PU drive signal 322b may have a higher voltage level than the PU-PFET code 572.

In some embodiments, the mode signal 501 controls the level shifter 411. For example, if the mode signal 501 indicates a low voltage mode, the level shifter 411 may generate the PU drive signal 322b such that the P-type PU transistor 334b turns off during the pull-up and pull-down phases. For example, if the mode signal 501 indicates a high voltage mode, the level shifter 411 may generate the PU drive signal 322b based on the PU-PFET code 572.

In some embodiments, multiplexer 570 of pre-driver circuit 318 receives PU-NFET code 574 and voltage Vss, where voltage Vss may be a ground voltage (e.g., substantially zero). Multiplexer 570 outputs PU drive signal 322a and is controlled by mode signal 501. For example, if mode signal 501 indicates a high voltage mode, multiplexer 570 may output voltage Vss such that N-type PU transistor 334a turns off during the pull-up and pull-down phases. For example, if the mode signal 501 indicates a low voltage mode, the multiplexer may output the PU-NFET code 574 such that the N-type PU transistor 334a is turned on and off based on the PU-NFET code 574 (e.g., which is based on the data 102).

In some embodiments, pre-driver circuit 318 receives PD code 582. During operation of circuit 300, pre-driver circuit 318 outputs PD code 582 as PD drive signal 326. PD code 582 is derived from data 102 and is used to operate PD transistor 338. For example, PD code 582 is used to turn PD transistor 338 on or off, respectively, based on whether output node 347 is to be pulled down or pulled up, for example.

Referring to fig. 1-5, the use of N-type transistors in the circuits 100, 300 makes it possible to: the pre-driver circuit is operated at a relatively low voltage (e.g., less than 0.7V). This eliminates many high voltage components in the pre-driver circuit (e.g., components operating at more than 1V). For example, a conventional transmitter circuit has one or more P-type transistors for pull-up and one or more N-type transistors for pull-down, a pre-driver circuit has multiple level shifters, a Vss-Hi power supply (e.g., where the Vss-Hi power supply is slightly higher than ground, but lower than the power supply voltage of the driver circuit), and so on. In contrast, since the transmitter circuit 100, 300 uses N-type transistors for both pull-up and pull-down, the predriver 118, 318 of the transmitter circuit 100, 300 does not require these components (e.g., does not require multiple level shifters, Vss-Hi power supplies, etc.). This results in savings in area, performance and/or power for the transmitter circuit 100, 300 (compared to conventional transmitter circuits).

Fig. 6 illustrates an example eye diagram (eye diagram)600 generated by the circuit 100 of fig. 1-2 or the circuit 300 of fig. 3-5 (e.g., when the circuit 300 operates in a low voltage mode), in accordance with some embodiments. Eye diagram 600 may be generated by an output of circuit 100 or 300, for example at a receiver (e.g., coupled to communication channel 143 or 343).

For example only, arrow A in eye diagram 600 represents approximately 100 mV. The total swing of the voltage in eye diagram 600 may be in the range of about 150mV to 300 mV. As previously discussed herein, this may correspond to a drive voltage Vdrv of the circuit 100, 300 in the range of about 0.3V-0.7V. Arrows B and C are associated with eye width (eye width). In an example, arrow B represents about 72.9 picoseconds (ps), and arrow C represents about 37.5 ps. Even for such low values of the drive voltage Vdrv of the circuit 100, 300 (e.g., in the range of about 0.3V-0.7V), the eye diagram 600 provides significant eye opening, thereby providing accurate detection of the output of the circuit 100, 300.

Fig. 7 illustrates a system 700 in which the transmitter circuits 100, 300 of fig. 1-5 may be used, according to some embodiments. System 700 includes a memory controller 705 in communication with a memory interface 740 (e.g., where memory interface 740 is coupled to a memory, which is not shown in fig. 7). The processor 702 may be communicatively coupled to a memory controller 705. In an example, memory controller 705 may be combined with processor 702, thus, memory controller 705 and processor 702 are shown within dashed box 703.

The memory controller 705 includes a transmitter module 717, the transmitter module 717 including: a Phase Locked Loop (PLL) and clock distribution circuit 712; a Transmitter (TX) clock circuit 714, the Transmitter (TX) clock circuit 714 including a Delay Locked Loop (DLL) and a Phase Integrator (PI) TX; and a transmitter circuit 710.

The memory controller 705 also includes a matched receiver 719, the matched receiver 719 including a matched filter 720, an Rx clock recovery circuit 718, and an Rx receiver circuit 716. The Rx clock recovery circuit 718 extracts a clock signal from the received data stream through a data output strobe DQS 764 and includes a Voltage Controlled Delay Line (VCDL) and a Phase Integrator (PI). The matched filter 720 operates such that the delay on the data output DQ 762 matches at least the minimum delay of the data output strobe DQs 764. Receiver RX 716 extracts the data from the data stream output by matched filter 720.

Memory interface 740 includes an RX receiver 742. Memory interface 740 also includes transmitter circuits 744 and 748 that transmit data output DQ 762 and data output strobe DQs 764, respectively, to memory controller 705.

In some embodiments, any one or more of the transmitters 710, 744, 748 may be implemented using any of the transmitter circuits 100, 300 of fig. 1-5. In an example, if circuit 300 is used, depending on the type of memory coupled to memory interface 740, the high voltage mode or the low voltage mode of circuit 300 may be used for a transmitter of system 700, as discussed with respect to fig. 3-5.

Fig. 8 shows a flow diagram depicting a method 800 for operating the transmitter circuit 300 of any of fig. 3-5, in accordance with some embodiments. Although the blocks in the flow chart with reference to fig. 8 are shown in a particular order, the order of the actions may be modified. Thus, the illustrated embodiments may be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in fig. 8 may be optional in accordance with certain embodiments. The numbering of the blocks is given for clarity and is not intended to specify the order in which the various blocks must be performed.

At 804, a mode of the transmitter circuit 300 is detected. For example, mode select signal 301 and/or mode signal 501 indicate a mode of circuit 300. As discussed with respect to fig. 3-5, the mode of the circuit 300 may be one of a high voltage mode or a low voltage mode.

At 808, in response to detecting the high voltage pattern, a P-type transistor (e.g., P-type PU transistor 334b) is activated for pull-up and an N-type transistor (e.g., N-type PD transistor 338) is activated for pull-down. As also discussed with respect to fig. 3-5, for the high voltage mode, drive supply node 345 receives a high drive voltage VdrvH 355 and multiplexer 570 outputs Vss to turn PU transistor 334a off.

Additionally, at 808, in response to detecting the low voltage mode, on the other hand, an N-type transistor (e.g., N-type PU transistor 334a) is activated for pull-up and another N-type transistor (e.g., N-type PD transistor 338) is activated for pull-down. As also discussed with respect to fig. 3-5, for the low voltage mode, drive supply node 345 receives a low drive voltage VdrvL 356 and multiplexer 570 outputs PU-NFET code 574, e.g., to cause PU transistor 334a to be turned on and/or off based on data 102. During the low voltage mode of operation, the P-type PU transistor 334b is turned off.

At 812, in accordance with the received data 102, a pull-up transistor (e.g., either of PU transistors 334a or 334b based on the mode) and a pull-down transistor (e.g., PD transistor 338) are operated to pull up and/or pull down the output node 347, e.g., as discussed with respect to fig. 3-5.

Fig. 9 illustrates a computer system, computing device, or SoC (system on a chip) 2100, in accordance with some embodiments, wherein the computing device includes one or both of the transmitter circuits 100 or 300 of fig. 1-8, wherein the transmitter circuits 100, 300 include at least one N-type transmitter in a pull-up path. It is pointed out that those elements of fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, computing device 2100 represents a suitable computing device, such as a computing tablet, mobile phone or smart phone, laptop computer, desktop computer, IOT device, server, set-top box, wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, but not all components of such devices are shown in computing device 2100.

In some embodiments, the computing device 2100 includes a first processor 2110. Various embodiments of the present disclosure may also include a network interface, such as a wireless interface, within 2170 so that system embodiments may be incorporated into a wireless device, such as a cellular telephone or personal digital assistant.

In one embodiment, processor 2110 may include one or more physical devices such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. The processing operations performed by processor 2110 include the execution of an operating platform or operating system on which applications and/or device functions are executed. Processing operations include operations related to a human user or to I/O of other devices, operations related to power management, and/or operations related to connecting the computing device 2100 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device 2100 includes an audio subsystem 2120 that represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. The audio functions may include speaker and/or headphone output, and microphone input. Devices for such functions can be integrated into computing device 2100 or connected to computing device 2100. In one embodiment, a user interacts with the computing device 2100 by providing audio commands that are received and processed by the processor 2110.

Display subsystem 2130 represents hardware (e.g., display device) and software (e.g., driver) components that provide a visual and/or tactile display for a user to interact with computing device 2100. Display subsystem 2130 includes a display interface 2132, which includes a particular screen or hardware device for providing a display to a user. In one embodiment, the display interface 2132 includes logic separate from the processor 2110 to perform at least some processing related to display. In one embodiment, display subsystem 2130 includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller 2140 represents hardware devices and software components related to interaction with a user. I/O controller 2140 is operative to manage hardware that is part of audio subsystem 2120 and/or display subsystem 2130. In addition, I/O controller 2140 illustrates a connection point for additional devices that connect to computing device 2100 through which a user may interact with the system. For example, devices that may be attached to the computing device 2100 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I/O devices for use with particular applications such as card readers or other devices.

As described above, the I/O controller 2140 may interact with the audio subsystem 2120 and/or the display subsystem 2130. For example, input through a microphone or other audio device may provide input or commands for one or more applications or functions of the computing device 2100. Additionally, audio output may be provided instead of or in addition to display output. In another example, if display subsystem 2130 includes a touch screen, the display device also acts as an input device, which may be managed, at least in part, by I/O controller 2140. There may also be other buttons or switches on the computing device 2100 to provide I/O functions managed by the I/O controller 2140.

In one embodiment, I/O controller 2140 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in computing device 2100. The input may be part of direct user interaction, or environmental input may be provided to the system to affect its operation (such as filtering noise, adjusting a display for brightness detection, applying a flash for a camera, or other functions).

In one embodiment, computing device 2100 includes power management 2150 that manages battery power usage, charging of the battery, and features related to power saving operations. Memory subsystem 2160 includes memory devices for storing information in computing device 2100. Memory may include non-volatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 2160 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of computing device 2100. In one embodiment, computing device 2100 includes a clock generation subsystem 2152 that generates clock signals.

Elements of embodiments are also provided as a machine-readable medium (e.g., memory 2160) for storing computer-executable instructions (e.g., instructions for implementing any other processes discussed herein). The machine-readable medium (e.g., memory 2160) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, Phase Change Memory (PCM), or other type of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

Connection 2170 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable computing device 2100 to communicate with external devices. The computing device 2100 may be a stand-alone device, such as other computing devices, wireless access points, or base stations, and a peripheral device, such as a headset, printer, or other device.

Connection 2170 can include a number of different types of connections. In general, computing device 2100 is illustrated with a cellular connection 2172 and a wireless connection 2174. Cellular connection 2172 generally refers to a cellular network connection provided by a wireless carrier, such as via GSM (global system for mobile communications) or variants or derivatives, CDMA (code division multiple access) or variants or derivatives, TDM (time division multiplexing) or variants or derivatives, or other cellular service standards. Wireless connection (or wireless interface) 2174 refers to a non-cellular wireless connection and may include a personal area network (such as bluetooth, near field, etc.), a local area network (such as Wi-Fi), and/or a wide area network (such as WiMax), or other wireless communication.

Peripheral connections 2180 include hardware interfaces and connectors, and software components (e.g., drivers, protocol stacks) for making peripheral connections. It will be understood that computing device 2100 may be both a peripheral device ("to" 2182) to other computing devices, and may have a peripheral device ("from" 2184) connected thereto. Computing device 2100 typically has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 2100. In addition, a docking connector may allow the computing device 2100 to connect to certain peripherals that allow the computing device 2100 to control the output of content to, for example, an audiovisual system or other system.

In addition to proprietary docking connectors or other proprietary connection hardware, the computing device 2100 may also make peripheral connections 2180 via common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of a number of different hardware interfaces), displayports including mini-displayport (MDP), high-definition multimedia interface (HDMI), firewire, or other types.

In some embodiments, computing device 2100 includes transmitter circuit 100 and/or transmitter circuit 300 of fig. 1-8. For example only, transmitter circuits 100 and/or 300 may be in memory subsystem 2160, e.g., to transmit data to or from memory (e.g., as discussed with respect to fig. 7). In another example, transmitter circuits 100 and/or 300 may be in any suitable component of computing device 2100. As discussed herein with respect to fig. 1-8, transmitter circuits 100 and/or 300 include at least one N-type transistor for pulling up an output node.

Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may", "might", or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claims refer to "a" or "an" element, that does not mean there is only one of the element. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment wherever particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the present disclosure are intended to embrace all such alternatives, modifications and variances that fall within the broad scope of the appended claims.

In addition, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the following facts: the details regarding the implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such details should be well within the capabilities of those skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

The following examples relate to further embodiments. The details of the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

Example 1. an apparatus, comprising: a first transistor coupled between a first power supply node and an output node; a resistive device and a second transistor coupled in series between the output node and a second supply node; and a pre-driver circuit for receiving data and for outputting a first control signal and a second control signal to control the first transistor and the second transistor, respectively, wherein the first transistor is an N-type transistor.

Example 2. the apparatus of example 1 or any other example, further comprising: a third transistor coupled between the first power supply node and the output node, wherein the third transistor is a P-type transistor, and wherein the circuit is to output a third control signal to control the third transistor.

Example 3. the apparatus of example 2 or any other example, wherein: the circuit is configured to: turning off the third transistor via the third control signal in response to the voltage at the first power supply node being less than a threshold voltage.

Example 4. the apparatus of example 2 or any other example, further comprising: a multiplexer to receive a first power supply and a second power supply and to output one of the first power supply or the second power supply to the first power supply node.

Example 5. the apparatus of example 4 or any other example, wherein: the multiplexer is to: in a first mode of operation, outputting the first power supply at a first voltage level to the first power supply node; the first voltage level is lower than a second voltage level of the second power supply; and the circuitry is to: in the first operation mode, the third transistor is turned off via the third control signal.

Example 6. the apparatus of example 5 or any other example, wherein: the circuit is configured to: in the first mode of operation, on and off states of the first and second transistors are controlled to selectively pull up or pull down the output node based on the data.

Example 7. the apparatus of example 5 or any other example, wherein: the multiplexer is to: in a second mode of operation, outputting the second power supply at the second voltage level to the first power supply node; and the circuitry is to: in the second mode of operation, the first transistor operating is turned off via the first control signal.

Example 8. the apparatus of example 7 or any other example, wherein: the circuit is configured to: in the second operation mode, on-states and off-states of the second transistor and the third transistor are controlled to selectively pull up or pull down the output node based on the data.

Example 9. the apparatus of example 5 or any other example, wherein: the first voltage level is equal to or less than 0.7 volts (V); and the second voltage level is higher than 1.0V.

Example 10. the apparatus of example 1 or any other example, wherein: the apparatus is a transmitter circuit, the transmitter circuit being included in one of: a memory controller to send data to a memory interface, or the memory interface coupled to a memory.

Example 11. the apparatus of example 1 or any other example, wherein: a voltage of the first power supply node is higher than a voltage of a second power supply node; and an output signal at the output node is indicative of the data.

Example 12. a system, comprising: a memory to store instructions; a processor to execute the instructions; a wireless interface to facilitate the processor to communicate with another system; and a transmission circuit for transmitting data to or from the memory through a channel, the transmission circuit including: a first transistor and a second transistor for pulling up a voltage of the channel, wherein the first transistor is coupled in parallel with the second transistor, wherein at least one of the first transistor or the second transistor is an N-type transistor; and a third transistor for pulling down a voltage of the channel, wherein the third transistor is an N-type transistor.

Example 13. the system of example 12 or any other example, wherein the transmit circuit further comprises: a resistive device coupled in series with the third transistor.

Example 14. the system of example 12 or any other example, wherein at most one of the first transistor or the second transistor is turned on at a given time.

Example 15. the system of example 12 or any other example, wherein: the first transistor comprises the N-type transistor; and the second transistor comprises a P-type transistor.

Example 16. the system of example 15 or any other example, wherein the first transistor and the second transistor are coupled between a power supply node and the channel, and wherein the transmit circuit comprises: a multiplexer to receive a first power supply and a second power supply and to output one of the first power supply or the second power supply to the power supply node.

Example 17 a transmitter circuit, comprising: a first pull-up (PU) transistor and a second pull-up (PU) transistor coupled in parallel between a power supply node and an output node, wherein the first PU transistor comprises a P-type transistor, and wherein the second PU transistor comprises an N-type transistor; a pull-down (PD) transistor coupled between the output node and a ground terminal; and a multiplexer for selectively outputting to the power supply node one of: a first voltage or a second voltage.

Example 18. the transmitter circuit of example 17 or any other example, further comprising: a resistor coupled in series with the PD transistor such that the resistor and the PD transistor are coupled between the output node and the ground terminal.

Example 19. the transmitter circuit of example 17 or any other example, wherein a source of the first PU transistor is coupled to a gate of the first PU transistor.

Example 20. the transmitter circuit of example 17 or any other example, wherein: the first voltage is higher than the second voltage; and in response to the first voltage being output to the power supply node through the multiplexer: the first PU transistor is to be selectively turned on or off based on data to be sent through the output node, and the second PU transistor is to be turned off.

Example 21. the transmitter circuit of example 17 or any other example, wherein: the first voltage is higher than the second voltage; and in response to the second voltage being output to the power supply node through the multiplexer: the second PU transistor is to be selectively turned on or off based on data to be sent through the output node, and the first PU transistor is to be turned off.

The abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the following understanding: this Abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.