阅读说明：本技术 存储器的行译码器 (Row decoder for memory ) 是由 何伟伟 戴瑾 于 2019-10-10 设计创作，主要内容包括：本申请提供一种存储器的行译码器,其主要结构在于,选择译码器、前置译码器与主译码器为多对多译码器结构,选择译码器与前置译码器受控于放电信号控制线以进行选址信号的输出或清除,驱动模块设置于选择译码器的输出端以调节所有字线驱动电路的选址与读/写控制电位,其各个输出连接对应字线驱动电路。通过选择译码器、前置译码器与主译码器依据输出选址信号,结合驱动模块转换读/写操作电位,及时序模块协调多个三态门传输电路的信号延迟,在缩减组件架构的行译码器结构下,实现字线驱动电路对字线数据的选择和控制。此行译码器具有结构简单、制造成本低、可靠性高等优点。(The application provides a row decoder of a memory, which mainly comprises a selection decoder, a preposed decoder and a main decoder in a many-to-many decoder structure, wherein the selection decoder and the preposed decoder are controlled by a discharge signal control line to output or clear an address selection signal, a driving module is arranged at the output end of the selection decoder to adjust the address selection and read/write control potential of all word line driving circuits, and each output is connected with a corresponding word line driving circuit. The selection and control of the word line driving circuit to the word line data are realized under the row decoder structure of a reduced component architecture by the selection decoder, the pre-decoder and the main decoder according to the output address selection signal, the conversion of the read/write operation potential by the driving module and the coordination of the signal delay of the tri-state gate transmission circuits by the time sequence module. The row decoder has the advantages of simple structure, low manufacturing cost, high reliability and the like.)

1. A row decoder of a memory, which is suitable for a magnetic random access memory chip architecture, is connected with a selected word line and a selected bit line through the control of the row decoder and a column decoder, and is characterized in that the row decoder comprises:

the input end of the selection decoder is connected with a first group of bit address lines;

the input end of the pre-decoder is connected with a second group of bit address lines;

the discharge signal control line is electrically connected with the control ends of the selection decoder and the pre-decoder;

the input end of the main decoder is connected with the output end of the pre-decoder;

the selection decoder, the pre-decoder and the main decoder are of a many-to-many decoder structure;

a plurality of word line driver circuits, each word line driver circuit comprising:

a potential converter connected to an output terminal of the main decoder for converting a low logic level signal suitable for the core device output by the main decoder into a high logic level signal suitable for the peripheral device;

the input ends of the tri-state gate transmission circuits are correspondingly and electrically connected with the output end of the selection decoder, and the address selection control ends of the tri-state gate transmission circuits are connected with the output end of the potential converter;

the input end of the time sequence module is electrically connected with the address selection control ends of the tri-state gate transmission circuits, and the output end of the time sequence module is connected with the word line selection control ends of the tri-state gate transmission circuits;

the driving module is arranged between the plurality of selection output ends and the plurality of word line driving circuits and switches each output voltage of the selection decoder to be at different electric potentials according to control information;

the pre-decoder and the selection decoder output address signals or clear address signals according to the potential of the discharge signal control line, the main decoder drives a selected word line driving circuit according to the address signals output by the pre-decoder, and the selected word line driving circuit enables a tri-state gate transmission circuit of the selected word line driving circuit to read or write bit word line data through the output information of the selection decoder and the driving module; the timing module coordinates the signal timing delay of the address selection control end and the word line selection control end of the tri-state gate transmission circuits to be within a delay value.

2. The row decoder of claim 1, wherein the output terminals of the pre-decoder all output a low voltage when the discharge signal control line outputs an active control signal, and the main decoder is controlled to make all output terminals output a high voltage to pull all word lines low.

3. The row decoder of claim 1, wherein said pre-decoder controls said main decoder to drive a corresponding word line driver circuit in response to a bit address line signal provided by said second set of bit address lines when said discharge signal control line outputs an inactive control signal, said potential shifter of said corresponding word line driver circuit outputting a high potential.

4. The row decoder of claim 1, wherein said select decoder outputs a bit address signal to said plurality of word line driver circuits in response to a bit address line signal provided by said first set of bit address lines when said discharge signal control line outputs an inactive control signal, said driver module selectively adjusting a potential of said bit address signal to be either a read word line potential or a write word line potential.

5. The row decoder of claim 1, wherein said write word line potential is higher than said read word line potential.

6. The row decoder of claim 1, wherein each tri-state gate transmission circuit comprises a signal transmission gate and a word line control transistor, a control terminal of the signal transmission gate is electrically connected to one of the output terminals of the driving module, a control terminal of the signal transmission gate is connected to the input terminal of the timing module, a control terminal of the word line control transistor is connected to the output terminal of the timing module, a drain of the word line control transistor is connected to a corresponding word line, and an output terminal of the signal transmission gate is connected to a drain of the word line control transistor.

7. The row decoder of claim 6, wherein said signal transmission gate comprises a P-type field effect transistor and an N-type field effect transistor, and said word line control transistor is an N-type field effect transistor, wherein the signals received by the P-type field effect transistor and the gate of the N-type field effect transistor of said signal transmission gate are in anti-phase.

8. The row decoder of claim 1, wherein said timing module comprises a nand logic gate and an inverter, two inputs of said nand logic gate are connected to an output of said level shifter, one of said two inputs is provided with a delay unit, an output of said nand logic gate is connected to an input of said inverter, and an output of said inverter is connected to a word line selection control terminal of said plurality of tri-state gate transmission circuits; the time sequence module has an inverting function so as to complete the discharging capability of the corresponding word line and the voltage signal transmission capability.

9. The row decoder of claim 8 wherein said delay elements are comprised of an even number of inverters.

10. A method of timing control of a row decoder of a memory as claimed in claim 1, comprising:

when address information reaches the row decoder, the selective decoder controls all the output of the potential conversion module to be pulled down to a low potential according to the discharge signal, and simultaneously the pre-decoder and the main decoder control all the output of the driver to be pulled down to the low potential, so that the transmission gate controlled by the control signal is gradually turned off;

after passing through the delay value, charging the delay signals corresponding to all the address information to high-potential signals, thereby discharging all the word lines;

when all the word lines are discharged, the discharge signal is pulled down, the selective decoder controls the corresponding potential conversion module to output a high potential according to the address signal, and meanwhile, the pre-decoder and the main decoder control the corresponding driver to output a high potential so as to gradually open a transmission gate controlled by the control signal and transmit the output signal of the corresponding potential conversion module to the corresponding word line, so that the potential of the selected word line is raised to the high potential;

and the selected unit in the memory array realizes the potential correct configuration of the word line according to the read/write operation.

Technical Field

The present invention relates to the field of memory technologies, and in particular, to a row decoder of a memory.

Background

The row decoder circuit converts a multi-bit input signal to a multi-bit output signal to select a word line of the memory array cell. In the case of a nonvolatile memory of a Magnetoresistive Random Access Memory (MRAM), in order to achieve reliable operation, in a write operation, since a large drive current capability is required for a Magnetic Tunneling Junction (MTJ) to be switched from a high resistance to a low resistance (or from a low resistance to a high resistance), a word line is generally subjected to an over-voltage process in the write operation, that is, a selected unit word line has a high potential; when reading, only an external circuit is needed to read the resistance value of the selected unit MTJ, so that data is not rewritten, and power consumption is reduced. Therefore, special processing is required to design the MRAM memory row decoder circuit.

The memory device uses high voltage devices to reliably transmit high voltage signals, and is matched with Level Shift (LEVEL SHIFT) and transmission using the high voltage devices. As the process progresses, the size of the high voltage device is not proportionally reduced compared to the size of the low voltage device, and the current practice is to first combine the 512 corresponding potential converting circuits and transmission gates through two stages of decoders, so the row decoder circuit in the array word line direction may occupy a large area, increasing the cost of manufacturing the memory chip. Second, the pull-down transistors are controlled by the discharge signal (DISCAHRGE) because of the higher driving capability of the circuit. Secondly, the delay of the discharge signal to the input end of the word line driving circuit and the delay of the relevant pull-down tube are difficult to be consistent, the time required for selecting the word line is easily prolonged, the charge and discharge time of the selected word line and the turn-on and turn-off time of the relevant transistor are unstable, and more power consumption waste is caused.

U.S. Pat. No. 5719818 discloses a DECODER which controls address segments to a part of address lines to a PRE-DECODER (PRE-DECODER) and a MAIN DECODER (MAIN-DECODER) and controls input signals (F0-Fi) of a wordline driver circuit by read/write potential selection signals of VCC/VHH; the other part of the address lines control a selection DECODER (SELECT-DECODER) to drive selection signals (S0-Sj) of the three-state gate transmission circuit, and finally the word lines (WL 0-WLj) are driven together by input signals Fi and selection signals Sj.

Disclosure of Invention

In order to solve the above technical problem, an object of the present invention is to provide a row decoder of a memory, which selects and controls word line data by a word line driving circuit under a row decoder structure with a reduced component architecture by adjusting decoders with different functions. The row decoder has the advantages of simple structure, low manufacturing cost, high reliability and the like.

The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme.

According to the row decoder of the memory provided by the application, the row decoder is suitable for a magnetic random access memory chip architecture, and is connected with a selected word line and a selected bit line through the control of the row decoder and a column decoder, and the row decoder comprises: the input end of the selection decoder is connected with a first group of bit address lines; the input end of the pre-decoder is connected with a second group of bit address lines; the discharge signal control line is electrically connected with the control ends of the selection decoder and the pre-decoder; the input end of the main decoder is connected with the output end of the pre-decoder; the selection decoder, the pre-decoder and the main decoder are of a many-to-many decoder structure; a plurality of word line driver circuits, each word line driver circuit comprising: a potential converter connected to an output terminal of the main decoder for converting a low logic level signal suitable for the core device output by the main decoder into a high logic level signal suitable for the peripheral device; the input ends of the tri-state gate transmission circuits are correspondingly and electrically connected with the output end of the selection decoder, and the address selection control ends of the tri-state gate transmission circuits are connected with the output end of the potential converter; the input end of the time sequence module is electrically connected with the address selection control ends of the tri-state gate transmission circuits, and the output end of the time sequence module is connected with the word line selection control ends of the tri-state gate transmission circuits; the driving module is arranged between the plurality of selection output ends and the plurality of word line driving circuits and switches each output voltage of the selection decoder to be at different electric potentials according to control information; the pre-decoder and the selection decoder output address signals or clear address signals according to the potential of the discharge signal control line, the main decoder drives a selected word line driving circuit according to the address signals output by the pre-decoder, and the selected word line driving circuit enables a tri-state gate transmission circuit of the selected word line driving circuit to read or write bit word line data through the output information of the selection decoder and the driving module; the timing module coordinates the signal timing delay of the address selection control end and the word line selection control end of the tri-state gate transmission circuits to be within a delay value.

The technical problem solved by the application can be further realized by adopting the following technical measures.

In an embodiment of the application, when the discharge signal control line outputs an active control signal, the output terminals of the pre-decoder all output a low potential, and the main decoder is controlled to make all the output terminals output a high potential, so as to pull down all the word lines to a low potential.

In an embodiment of the present application, when the discharge signal control line outputs an inactive control signal, the pre-decoder controls the main decoder according to a bit address line signal provided by the second set of bit address lines to drive a corresponding word line driving circuit, and a potential converter of the corresponding word line driving circuit outputs a high potential.

In an embodiment of the present application, when the discharge signal control line outputs an inactive control signal, the select decoder outputs a bit address signal to the plurality of word line driving circuits according to a bit address line signal provided by the first set of bit address lines, and the driving module selectively adjusts a potential of the bit address signal to be a read operation word line potential or a write operation word line potential.

In an embodiment of the present application, the write word line potential is higher than the read word line potential.

In an embodiment of the present application, each tri-state gate transmission circuit includes a signal transmission gate and a word line control transistor, a control end of the signal transmission gate is electrically connected to one of output ends of the driving module, a control end of the signal transmission gate is connected to an input end of the timing module, a control end of the word line control transistor is connected to an output end of the timing module, a drain of the word line control transistor is connected to a corresponding word line, and an output end of the signal transmission gate is connected to a drain of the word line control transistor.

In an embodiment of the present application, the signal transmission gate is formed by a P-type field effect transistor and an N-type field effect transistor, and the word line control transistor is an N-type field effect transistor, wherein signals received by the P-type field effect transistor and the N-type field effect transistor of the signal transmission gate are in opposite phases.

In an embodiment of the present application, the timing module includes a nand logic gate and an inverter, two input terminals of the nand logic gate are connected to one output terminal of the potential converter, one of the two input terminals is provided with a delay unit, an output terminal of the nand logic gate is connected to an input terminal of the inverter, and an output terminal of the inverter is connected to word line selection control terminals of the plurality of tri-state gate transmission circuits; the time sequence module has an inverting function so as to complete the discharging capability of the corresponding word line and the voltage signal transmission capability.

In an embodiment of the present application, the delay unit is composed of an even number of inverters.

Another object of the present invention is to provide a timing control method for a row decoder of a memory as described above, including: when address information reaches the row decoder, the selective decoder controls all the output of the potential conversion module to be pulled down to a low potential according to the discharge signal, and simultaneously the pre-decoder and the main decoder control all the output of the driver to be pulled down to the low potential, so that the transmission gate controlled by the control signal is gradually turned off; after passing through the delay value, charging the delay signals corresponding to all the address information to high-potential signals, thereby discharging all the word lines; when all the word lines are discharged, the discharge signal is pulled down, the selective decoder controls the corresponding potential conversion module to output a high potential according to the address signal, and meanwhile, the pre-decoder and the main decoder control the corresponding driver to output a high potential so as to gradually open a transmission gate controlled by the control signal and transmit the output signal of the corresponding potential conversion module to the corresponding word line, so that the potential of the selected word line is raised to the high potential; and the selected unit in the memory array realizes the potential correct configuration of the word line according to the read/write operation.

According to the method, through the change of the component connection structure, all the word line driving circuits are controlled by a single main decoder instead, the discharge signal control line is only used for controlling the address selection and signal clearing of the selective decoder and the pre-decoder, the word line control end of each word line driving circuit is controlled by the respective time sequence module, and the discharge signal control line is connected to the word line control ends of all the word line driving circuits, so that the circuit scale can be selectively reduced, the information driving capability is reduced on the premise of keeping the address selection information, and the chip cost can be reduced. And secondly, through the delay module, word line selection signals of all the tri-state gate transmission circuits are obtained by delaying output signals of the potential converter, the time sequence of the two signals is relatively fixed, the situation of mutual delay of the signals cannot occur, the situation of discharging and simultaneously charging the previously selected word line is avoided, and the dynamic power consumption of the row decoding circuit can be reduced. Moreover, the unselected word lines greatly reduce the influence of the falling edge of the delay signal on the word lines due to the strong discharging capacity of the N-type field effect transistor, and the reliability of word line selection and operation is improved. The row decoder disclosed by the application has the advantages of simplicity in operation, low chip cost, high reliability and the like, and is suitable for a memory circuit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a block diagram of an exemplary column decoder of a memory;

FIG. 2 is a schematic diagram of a row decoder of a memory according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a timing module of a row decoder according to an embodiment of the present disclosure;

FIG. 4 is a timing diagram illustrating operation of a row decoder of a memory according to an embodiment of the present application;

fig. 5a to 5d are schematic diagrams of a memory row decoder according to an embodiment of the present application.

Detailed Description

Refer to the drawings wherein like reference numbers refer to like elements throughout. The following description is based on illustrated embodiments of the application and should not be taken as limiting the application with respect to other embodiments that are not detailed herein.

The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. In the present application, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", and the like are merely referring to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting.

The terms "first," "second," "third," and the like in the description and in the claims of the present application and in the above-described drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as variations thereof, such as, for example, are intended to cover non-exclusive inclusions.

The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts of the present application. Unless the context clearly dictates otherwise, expressions used in the singular form encompass expressions in the plural form. In the present specification, it will be understood that terms such as "including," "having," and "containing" are intended to specify the presence of the features, integers, steps, acts, or combinations thereof disclosed in the specification, and are not intended to preclude the presence or addition of one or more other features, integers, steps, acts, or combinations thereof. Like reference symbols in the various drawings indicate like elements.

The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present application is not limited thereto.

In the drawings, the range of configurations of devices, systems, components, circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of a column decoder of a memory according to the present invention with reference to the accompanying drawings and embodiments shows the following detailed descriptions.

FIG. 1 is a block diagram of an exemplary column decoder of a memory. As shown in fig. 1, the row Decoder includes a Select-Decoder (Select-Decoder)110, a Pre-Decoder (Pre-Decoder)120, a Main-Decoder (Main-Decoder)130, a plurality of Word Line Driver circuits (Word Line drivers) 140, and a plurality of Driver modules (Drive modules) 150. The select decoder 110 and the pre-decoder 120 are many-to-many decoders, and the main decoder 130 is a many-to-one decoder. The input terminal of the selection decoder 110 is connected to the first bit address line 210 to receive the first bit address signal, and the output terminal of the selection decoder 110 outputs the bit address signal (S0 Sj). The inputs of the pre-decoder 120 are connected to the second set of bit address lines 220 for receiving the second set of bit address signals, and the outputs of the pre-decoder 120 are connected to the inputs of all the main decoders 130 for selecting and controlling the main decoders 130. The output terminal of each main decoder 130 is connected to the driving module 150 for adjusting the control signals (F0-Fj) transmitted to the corresponding word line driving circuit 140, wherein the main decoder 130, the driving module 150 and the word line driving circuit 140 are correspondingly configured, and have i +1 groups. Each word line driving circuit 140 has j tri-state gate transmission circuits, signal input terminals of the j tri-state gate transmission circuits are respectively connected to the output terminal of the selection decoder 110 to obtain bit selection address signals (S0-Sj), address selection control terminals of the j tri-state gate transmission circuits are all connected to the output terminal of the driving module 150 to receive the control signal (Fi) of the word line driving circuit 140, and the word line selection control terminals of all the word line driving circuits 140 and the control terminal of the pre-decoder 120 are all connected to a Discharge signal control line (Discharge). In some embodiments, the word lines (WL 0-WLj-WL (i-1) × j-WLi) × j) are driven by the control signal (Fi) and the bit address signal (Sj), and the charge/Discharge time of the word lines is controlled in cooperation with the Discharge signal (Discharge).

However, the Discharge signal (Discharge) controls the pre-decoder 120 and the pull-down transistors that drive all the word line select control terminals. With respect to the memory array structure shown in fig. 1, j is generally 256/512, which means that each word line can mount 256/512 cells or even more, so that the pull-down transistors corresponding to the word line are required to have larger size, and all the pull-down transistors are controlled by the Discharge signal (Discharge). Therefore, the signal driving capability of the Discharge signal (Discharge) circuit is required to be high.

Further, it is difficult to match the delay from the Discharge signal (Discharge) to the control signal (Fi) with the delay from the Discharge signal (Discharge) to the pull-down tube at the word line selection control end. Assuming that the rising edge of the control signal (Fi) is reached later than before, the word line selected by the previous address is charged while being discharged, causing the word line selection result to depend on the magnitude of the charge and discharge currents, i.e.: when the discharge current is small, the potential of the word line is kept unchanged, otherwise, the potential is reduced. Similarly, assuming that the falling edge of the control signal (Fi) is reached first, it may cause the word line potential to drop. Therefore, the time of arrival of the control signal (Fi) and the Discharge signal (Discharge) is not consistent, which results in a longer time required for the selected word line and additional waste of power consumption.

In addition, after the bit address selection signal (Sj) is reached and the potential of the control signal (Fi) is reduced, the potential of the selected word line is discharged, and the PMOS tube is used for charging, so that the time is possibly long; in addition, at the moment, the unselected word lines have finished discharging, because the control signal (Fi) is high potential at the moment, the PMOS tube is already closed, when the Discharge signal (Discharge) changes from high to low, the NMOS tube controlled by the control signal (Fi) is gradually closed and the PMOS tube is slowly opened, because parasitic capacitance exists at the drain end and the grid electrode of the pull-down tube at the word line selection control end, the charges on the word lines are reduced and changed into negative potential because the charges cannot be supplemented in time; the magnitude of the negative potential value depends on the gate-drain parasitic capacitance and the gate capacitance and gate potential abrupt change value. If the word line potential is sufficiently negative, then a large transient current is generated. Even if the PMOS transistor is slowly turned on and the on-resistance is large, it still takes a long time to pull the unselected word line potential back to zero-level. Therefore, the conventional segmented decoder has the problems of power consumption waste and long word line opening time caused by difficult word line driving and different transmission delays.

Fig. 2 is a schematic structural diagram of a row decoder of a memory according to an embodiment of the present disclosure. Referring to fig. 2, a row decoder of a memory, which is suitable for a magnetic random access memory chip architecture, is connected to a selected word line and a selected bit line through the control of the row decoder and a column decoder, and includes: a Select-Decoder (Select-Decoder)110, an input terminal of the Select-Decoder 110 being connected to a first set of bit address lines 210; a Pre-Decoder (Pre-Decoder)120, an input of the Pre-Decoder 120 being connected to a second set of bit address lines 220; a Discharge signal control line (Discharge) electrically connected to the control terminals of the select decoder 110 and the pre-decoder 120; a Main-Decoder (Main-Decoder)130 having an input terminal connected to an output terminal of the pre-Decoder 120; the select decoder 110, the pre-decoder 120, and the main decoder 130 are in a many-to-many decoder configuration; a plurality of word line driver circuits 140, each word line driver circuit 140 comprising: a Level Shift (Level Shift)160 connected to an output terminal of the main decoder 130, for converting a low logic Level signal suitable for a core device output by the main decoder 130 into a high logic Level signal suitable for a peripheral device; the input ends of the tri-state gate transmission circuits are correspondingly and electrically connected with the output end of the selection decoder 110, and the address selection control ends 141 of the tri-state gate transmission circuits are connected with the output end of the potential converter 160; a timing module 143, an input end of the timing module 143 being electrically connected to the address selection control end 141 of the plurality of tri-state gate transmission circuits, and an output end of the timing module 143 being connected to the word line selection control end 142 of the plurality of tri-state gate transmission circuits; a driving module 150, disposed between the plurality of selection output terminals and the plurality of word line driving circuits 140, for switching each output voltage of the selection decoder 110 to different potentials according to control information; wherein, the pre-decoder 120 and the select decoder 110 output an address selection signal or clear an address selection signal according to the potential of the Discharge signal control line (Discharge), the main decoder 130 drives the selected word line driving circuit 140 according to the address selection signal output by the pre-decoder 120, and the selected word line driving circuit 140 makes the tri-state gate transmission circuit of the selected word line driving circuit 140 perform a reading or writing operation of bit word line data through the output information of the select decoder 110 and the driving module 150; the timing module 143 coordinates the timing delay of the signals at the address selection control terminal and the word line selection control terminal of the tri-state gate transmission circuits to be within a delay value.

In some embodiments, the level shifter 160 mainly includes a signal driving unit and a level shifting circuit (driving of transmission of a control signal (Fi) and driving of the timing module 143).

In one embodiment of the present application, the input signals of the pre-decoder 120 mainly come from the Discharge signal control line (Discharge) and the second set of bit address lines 220. The output signal of the pre-decoder 120 is directly used as the address input of the main decoder 130. The multi-bit output signal of the main decoder 130 is potential-converted and signal-driven by the potential converter 160 to output a control signal (Fi).

In some embodiments, when the Discharge signal control line (Discharge) outputs an active control signal, the output terminals of the pre-decoder 120 all output a low voltage, and the main decoder 130 is controlled to make all the output terminals output a high voltage, so as to effectively pull down all the word lines to a low voltage.

In some embodiments, when the Discharge signal control line (Discharge) outputs an inactive control signal, the pre-decoder 120 controls the main decoder 130 according to the bit address line signal provided by the second set of bit address lines 220 to drive the corresponding word line driving circuit 140, and the potential converter 160 of the corresponding word line driving circuit 140 outputs a high potential, i.e. only one high potential of the i control signals (F) has a voltage value of VHH.

In one embodiment of the present application, the input signals of the selection decoder 110 mainly come from the Discharge signal control line (Discharge) and the first set of bit address lines 210. The multi-bit signal decoded by the selection decoder 110 is converted by the driving module 150 and used as the input signal of the word line driving circuit 140.

In an embodiment of the present application, when the Discharge signal control line (Discharge) outputs an active control signal, the output terminals of the selection decoder 110 all output a low voltage, and the driving module 150 is controlled to output a low voltage, that is, all the bit address signals (V0-Vj) are all low voltage.

In an embodiment of the present application, when the Discharge signal control line (Discharge) outputs an inactive control signal, the select decoder 110 outputs a bit address signal to the word line driving circuits 140 according to a bit address line signal provided by the first set of bit address lines 210, and the driving module 150 selectively adjusts a potential of the bit address signal to a high potential, that is, only one high potential of the j bit address signals (V) exists, and a specific potential of the high potential is configured according to a Write Enable (WEN) signal, that is, the read word line potential or the write word line potential is adjusted according to a level of the WEN signal.

In one embodiment of the present application, the entire row decoder includes i +1 word line driver circuits 140. Each word line driver circuit 140 includes 1 timing module 143 and j +1 tri-state gate transmission circuits. Whether j +1 bit address signals (V) are connected to their corresponding bit word lines WLi x j is controlled by i control signals (F) and delay signals (D).

In some embodiments, the tri-state gate transmission circuit is used to control the effective conduction or non-conduction of the bit address signal (Vj) and the corresponding word line. Each tristate gate transmission circuit comprises a signal transmission gate (a component corresponding to the address selection control terminal 141) and a word line control transistor (a component corresponding to the word line selection control terminal 142), wherein the control terminal of the signal transmission gate is electrically connected with one of the output terminals of the driving module 150, the control terminal of the signal transmission gate is connected with the input terminal of the timing module 143, the control terminal of the word line control transistor is connected with the output terminal of the timing module 143, the drain electrode of the word line control transistor is connected with a word line, and the output terminal of the signal transmission gate is connected with the source electrode of the word line control transistor.

In some embodiments, the signal transmission gate is composed of a P-type field effect transistor and an N-type field effect transistor, wherein the P-type field effect transistor and the N-type field effect transistor of the signal transmission gate receive signals in opposite phases; for example: in transmission, the gate of the PMOS is controlled by the control signal Fi, but the gate of the NMOS is controlled by the inverse of the control signal Fi.

In some embodiments, the word line control transistor is an N-type field effect transistor.

Fig. 3 is a schematic structural diagram of the timing module 143 of the row decoder according to the embodiment of the present application. In an embodiment of the present application, the timing module 143 is formed by a logic Gate (Logical Gate), the timing module 143 includes a NAND Gate (NAND Gate)145 and an inverter 146, two input terminals of the NAND Gate 145 are connected to an output terminal of the potential converter 160, one of the two input terminals is provided with a delay unit 144, an output terminal of the NAND Gate 145 is connected to an input terminal of the inverter 146, and an output terminal of the inverter 146 is connected to a word line selection control terminal of the plurality of tri-state Gate transmission circuits; the timing module 143 has an inverting function to complete the discharging capability of the corresponding word line and the voltage signal transmitting capability.

In some embodiments, the delay unit 144 is composed of an even number of inverters.

In some embodiments, the timing module 143 logically nand the control signal (Fi) with the control signal (Fi) passing through the delay unit 144, and outputs the delayed signal (Di) through the inverter 146 to drive the word line.

It is worth noting that the delay unit 144 cannot be set too large or too small. If the delay is small, the transient large current cannot be effectively reduced; on the contrary, if the delay value is larger, the word line cannot be effectively driven, even the word line cannot be opened, so that it is reasonable to set a smaller delay value. The delay unit 144 may be formed simply by an inverter chain, or may be formed by a resistor and a capacitor, which are selected mainly according to the delay value. If the delay value is small, it is easier to construct with an inverter chain to save chip area.

In some embodiments, in the case of an MRAM, the selected middle bit word line needs to have a different potential for a write operation or a read operation. Generally, since the write word line potential is higher than the read word line potential, after the selection decoder 110 finishes decoding, the potential is converted into the read word line potential VCC or the write word line potential VHH by the driving module 150 according to the WEN signal. In some embodiments, the write word line potential VHH is passed as a bit addressing signal (Vj) to the tri-state gate transmission circuit in the selection during a write operation, and the read word line potential VCC is passed as a bit addressing signal (Vj) to the tri-state gate transmission circuit in the selection during a read operation. In the level shifter 160, since the word line level VHH is written to complete the functions of transmitting the bit address signal (Vj) to the corresponding word line and discharging the word line, it is only necessary to convert the level to VHH, thereby saving the chip cost.

Fig. 4 is a timing diagram of operation of a memory row decoder according to an embodiment of the present application, please refer to fig. 1 to fig. 3 in combination with fig. 5a to fig. 5d for understanding. FIG. 4 illustrates the process of converting the address of the memory from ADD0 to ADD1, but not limited thereto, and other address selection methods are within the scope of the concept.

In some embodiments, when ADD1 address information arrives at the row decoder (whether via the first set 210 and second set 220 of bit address lines), all control signals (Fi) (including the F signal selected by the last address) are first pulled up to VHH potential based on the Discharge signal (Discharge); all bit address signals (Vj), including the V signal selected by the last address, are pulled down to 0. The transmission gate controlled by the control signal (Fi) is gradually turned off, and after a delay value, the corresponding delay signal (Di) is charged to the VHH signal, thereby effectively discharging the selected word line (WLi is taken as an example in fig. 4). After all the word lines are discharged, the Discharge signal (Discharge) starts to be pulled down, at this time, the selected bit address signal (Vj) is charged to a high potential (i.e., the read operation potential VCC or the write operation word line potential VHH described earlier), and simultaneously the selected control signal (Fi) and the delay signal (Di) are pulled down to a 0 potential, so that the selected word line potential is raised to a high potential (WLj is taken as an example in fig. 4, and the potential is VCC or VHH). The selected bit word line unit in the memory array performs corresponding read/write operation according to the electric potential of the word line and the bit line. So far, the above entire timing is one complete operation when the row decoder circuit is switched from the address ADD0 to the ADD 1. From the above, the row decoder disclosed in the present application has the advantages of simple timing operation, low chip cost, and the like, and is suitable for being applied to a memory circuit.

Fig. 5a to 5d are schematic diagrams of a memory row decoder according to an embodiment of the present application. In one embodiment of the present application, the addressing of 256 address lines of the MRAM circuit is described in detail. As shown in fig. 5a to 5d, the schematic diagram of the present application mainly includes 1 read/write operation selector (controlled by a WEN signal), 2 4-16 decoders (the selection decoder 110, the pre-decoder 120 and the main decoder 130 are combined), 33 driving modules 150 (16 output ends of the selection decoder 110, 16 output ends of the main decoder 130, 1 or 33 read/write operation selectors) and 16 word line driving circuits 140. The use of an op-amp in combination with a bandgap reference signal to generate VCC (preferably VCC potential is the same as the low voltage device supply potential) and VHH circuits (i.e., one implementation of the driver module 150) is also shown. The voltage VCC and VHH are obtained by converting a reference voltage VREF in a memory circuit by Operational amplifiers (OPAs) of different specifications.

In some embodiments, the low bit word lines ADD 0-ADD 3 (the first group of bit address lines 210) decode VSELs 0-VSELs 15, and a part of 16 VSEL signal lines raise a certain high voltage VCC to VHH through a voltage level conversion circuit to control whether the bit selection address signals (Vj) and VHH are conducted or not; the other part 16 VSELs transmit a certain high potential (VCC) to a bit selection address signal (Vj) through the driving circuit and the PMOS tube, and the specific potential of the selected bit selection address signal (Vj) is VHH or VCC depends on WEN signals. When the WEN signal is at a high potential (writing operation is carried out on the selected unit), the corresponding bit address signal (Vj) is VHH, and when the WEN signal is at a low level (reading operation is carried out on the selected unit), the potential of the corresponding bit address signal (Vj) is VCC (only one signal is at a high potential in normal operation, and the potential value is VHH or VCC).

In some embodiments, the upper bit lines ADD 4-ADD 7 (the second set of bit address lines 220) decode XSEL 0-XSEL 15, and perform level shifting and signal conditioning through the level shifter 160 to form control signals F0-F15 (only one signal is low in normal operation), obtain delay signals D0-D15 through the timing module 143, and finally charge the selected cell bit line electric potential to the level of the bit selection signal (Vj). Furthermore, the selected unit word line is in a VHH potential value during the writing operation; during reading operation, the word line of the selected unit is VCC potential value.

According to the method, through the change of the component connection structure, all the word line driving circuits are controlled by a single main decoder instead, the discharge signal control line is only used for controlling the address selection and signal clearing of the selective decoder and the pre-decoder, the word line control end of each word line driving circuit is controlled by the respective time sequence module, and the discharge signal control line is connected to the word line control ends of all the word line driving circuits, so that the circuit scale can be selectively reduced, the information driving capability is reduced on the premise of keeping the address selection information, and the chip cost can be reduced. And secondly, through the delay module, word line selection signals of all the tri-state gate transmission circuits are obtained by delaying output signals of the potential converter, the time sequence of the two signals is relatively fixed, the situation of mutual delay of the signals cannot occur, the situation of discharging and simultaneously charging the previously selected word line is avoided, and the dynamic power consumption of the row decoding circuit can be reduced. Moreover, the unselected word lines greatly reduce the influence of the falling edge of the delay signal on the word lines due to the strong discharging capacity of the N-type field effect transistor, and the reliability of word line selection and operation is improved. The row decoder disclosed by the application has the advantages of simplicity in operation, low chip cost, high reliability and the like, and is suitable for a memory circuit. .

The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This phrase generally does not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.

Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.