阅读说明：本技术 用于基于鳍状物的电子设备的固体源扩散结 (Solid source diffusion junctions for fin-based electronics ) 是由 W·M·哈菲兹 C-H·简 于 2014-07-14 设计创作，主要内容包括：描述了用于基于鳍状物的电子设备的固体源扩散的结。在一个示例中,在衬底上形成鳍状物。在衬底之上并且在鳍状物的下部部分之上沉积第一掺杂剂类型的玻璃。在衬底和鳍状物之上沉积第二掺杂剂类型的玻璃。对玻璃进行退火以将掺杂剂驱动到鳍状物和衬底中。去除玻璃并且在鳍状物之上形成不接触鳍状物的下部部分的第一接触部和第二接触部。(Solid source diffused junctions for fin-based electronic devices are described. In one example, fins are formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive dopants into the fin and substrate. The glass is removed and first and second contacts are formed over the fin that do not contact the lower portion of the fin.)

1. An integrated circuit structure, comprising:

a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;

a dielectric layer comprising a P-type dopant directly on first and second sidewalls of the lower fin portion of the fin, the dielectric layer having a first upper end portion laterally adjacent the first sidewall of the lower fin portion of the fin and a second upper end portion laterally adjacent the second sidewall of the lower fin portion of the fin;

an isolation material comprising oxygen laterally adjacent the dielectric layer directly on the first and second sidewalls of the lower fin portion of the fin, the isolation material having a first upper surface portion and a second upper surface portion, wherein the first upper surface portion of the isolation material is located below the first upper end portion of the dielectric layer, and wherein the second upper surface portion of the isolation material is located below the second upper end portion of the dielectric layer; and

a gate electrode over a top of the upper fin portion of the fin and laterally adjacent sidewalls of the upper fin portion of the fin, and over the first and second upper end portions of the dielectric layer, and over the first and second upper surface portions of the isolation material.

2. The integrated circuit structure of claim 1, wherein the P-type dopant is boron.

3. The integrated circuit structure of claim 1 wherein the first upper surface portion of the isolation material is laterally adjacent to the dielectric layer on the first sidewall of the lower fin portion of the fin.

4. The integrated circuit structure of claim 3, wherein the second upper surface portion of the isolation material is laterally adjacent to the dielectric layer on the second sidewall of the lower fin portion of the fin.

5. The integrated circuit structure of claim 1, further comprising:

an insulating layer directly laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin portion of the fin, wherein the isolation material is directly laterally adjacent to the insulating layer.

6. The integrated circuit structure of claim 5, wherein the insulating layer has a first upper end portion laterally adjacent to the first upper end portion of the dielectric layer, and wherein the insulating layer has a second upper end portion laterally adjacent to the second upper end portion of the dielectric layer.

7. The integrated circuit structure of claim 6, wherein the first upper end portion of the insulating layer is substantially coplanar with the first upper end portion of the dielectric layer, and wherein the second upper end portion of the insulating layer is substantially coplanar with the second upper end portion of the dielectric layer.

8. The integrated circuit structure of claim 6, wherein the first upper surface portion of the isolation material is located below the first upper end portion of the insulating layer, and wherein the second upper surface portion of the isolation material is located below the second upper end portion of the insulating layer.

9. The integrated circuit structure of claim 6, wherein the gate electrode is located over the first and second upper end portions of the insulating layer.

10. The integrated circuit structure of claim 1, wherein the first upper end portion of the dielectric layer is substantially coplanar with the second upper end portion of the dielectric layer.

11. The integrated circuit structure of claim 10, wherein the first upper surface portion of the isolation material is substantially coplanar with the second upper surface portion of the isolation material.

12. A method of fabricating an integrated circuit structure, the method comprising:

forming a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;

forming a layer comprising a phosphosilicate glass (PSG), the layer comprising the phosphosilicate glass being located directly on a first sidewall and a second sidewall of the lower fin portion of the fin, the layer comprising the phosphosilicate glass having a first upper end portion laterally adjacent to the first sidewall of the lower fin portion of the fin and the layer comprising the phosphosilicate glass having a second upper end portion laterally adjacent to the second sidewall of the lower fin portion of the fin;

forming an isolation material comprising oxygen laterally adjacent the layer comprising the phosphosilicate glass directly on the first and second sidewalls of the lower fin portion of the fin, the isolation material having a first upper surface portion and a second upper surface portion, wherein the first upper surface portion of the isolation material is located below the first upper end portion of the layer comprising the phosphosilicate glass, and wherein the second upper surface portion of the isolation material is located below the second upper end portion of the layer comprising the phosphosilicate glass; and

forming a gate electrode over a top of the upper fin portion of the fin and laterally adjacent sidewalls of the upper fin portion of the fin, and over the first and second upper end portions of the layer comprising the phosphosilicate glass, and over the first and second upper surface portions of the isolation material.

13. The method of claim 12 wherein the first upper surface portion of the isolation material is laterally adjacent the layer comprising the phosphosilicate glass on the first sidewalls of the lower fin portion of the fin.

14. The method of claim 13 wherein the second upper surface portion of the isolation material is laterally adjacent the layer comprising the phosphosilicate glass on the second sidewall of the lower fin portion of the fin.

15. The method of claim 12, further comprising:

forming an insulating layer directly laterally adjacent to the layer comprising the phosphosilicate glass directly on the first and second sidewalls of the lower fin portion of the fin, wherein the isolation material is directly laterally adjacent to the insulating layer.

16. The method of claim 15, wherein the insulating layer comprises borosilicate glass (BSG).

17. The method of claim 15, wherein the insulating layer has a first upper end portion laterally adjacent to the first upper end portion of the layer comprising the phosphosilicate glass, and wherein the insulating layer has a second upper end portion laterally adjacent to the second upper end portion of the layer comprising the phosphosilicate glass.

18. A method of fabricating an integrated circuit structure, the method comprising:

forming a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;

forming a dielectric layer comprising a P-type dopant, the dielectric layer located directly on a first sidewall and a second sidewall of the lower fin portion of the fin, the dielectric layer having a first upper end portion laterally adjacent to the first sidewall of the lower fin portion of the fin and the dielectric layer having a second upper end portion laterally adjacent to the second sidewall of the lower fin portion of the fin;

forming an isolation material comprising oxygen laterally adjacent the dielectric layer directly on the first and second sidewalls of the lower fin portion of the fin, the isolation material having a first upper surface portion and a second upper surface portion, wherein the first upper surface portion of the isolation material is located below the first upper end portion of the dielectric layer, and wherein the second upper surface portion of the isolation material is located below the second upper end portion of the dielectric layer; and

forming a gate electrode over a top of the upper fin portion of the fin and laterally adjacent sidewalls of the upper fin portion of the fin, and over the first and second upper end portions of the dielectric layer, and over the first and second upper surface portions of the isolation material.

19. The method of claim 18, wherein the P-type dopant is boron.

20. The method of claim 18 wherein the first upper surface portion of the isolation material is laterally adjacent the dielectric layer on the first sidewalls of the lower fin portion of the fin.

21. The method of claim 20 wherein the second upper surface portion of the isolation material is laterally adjacent the dielectric layer on the second sidewall of the lower fin portion of the fin.

22. The method of claim 18, further comprising:

forming an insulating layer directly laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin portion of the fin, wherein the isolation material is directly laterally adjacent to the insulating layer.

23. The method of claim 22, wherein the insulating layer has a first upper end portion laterally adjacent to the first upper end portion of the dielectric layer, and wherein the insulating layer has a second upper end portion laterally adjacent to the second upper end portion of the dielectric layer.

24. A computing device, comprising:

a plate; and

a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising:

a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;

a layer comprising a phosphosilicate glass (PSG), the layer comprising the phosphosilicate glass being located directly on a first sidewall and a second sidewall of the lower fin portion of the fin, the layer comprising the phosphosilicate glass having a first upper end portion laterally adjacent to the first sidewall of the lower fin portion of the fin and the layer comprising the phosphosilicate glass having a second upper end portion laterally adjacent to the second sidewall of the lower fin portion of the fin;

an isolation material comprising oxygen laterally adjacent the layer comprising the phosphosilicate glass directly on the first and second sidewalls of the lower fin portion of the fin, the isolation material having a first upper surface portion and a second upper surface portion, wherein the first upper surface portion of the isolation material is located below the first upper end portion of the layer comprising the phosphosilicate glass, and wherein the second upper surface portion of the isolation material is located below the second upper end portion of the layer comprising the phosphosilicate glass; and

a gate electrode over a top of the upper fin portion of the fin and laterally adjacent sidewalls of the upper fin portion of the fin, and over the first and second upper end portions of the layer comprising the phosphosilicate glass, and over the first and second upper surface portions of the isolation material.

25. The computing device of claim 24, further comprising:

a memory coupled to the board.

26. The computing device of claim 24, further comprising:

a communication chip coupled to the board.

27. The computing device of claim 24, further comprising:

a camera coupled to the board.

28. The computing device of claim 24, further comprising:

a battery coupled to the plate.

29. The computing device of claim 24, further comprising:

an antenna coupled to the board.

30. The computing device of claim 24, wherein the component is a packaged integrated circuit die.

31. A computing device, comprising:

a plate; and

a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising:

a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;

a dielectric layer comprising an N-type dopant directly on first and second sidewalls of the lower fin portion of the fin, the dielectric layer having a first upper end portion laterally adjacent the first sidewall of the lower fin portion of the fin and a second upper end portion laterally adjacent the second sidewall of the lower fin portion of the fin;

an isolation material comprising oxygen laterally adjacent the dielectric layer directly on the first and second sidewalls of the lower fin portion of the fin, the isolation material having a first upper surface portion and a second upper surface portion, wherein the first upper surface portion of the isolation material is located below the first upper end portion of the dielectric layer, and wherein the second upper surface portion of the isolation material is located below the second upper end portion of the dielectric layer; and

a gate electrode over a top of the upper fin portion of the fin and laterally adjacent sidewalls of the upper fin portion of the fin, and over the first and second upper end portions of the dielectric layer, and over the first and second upper surface portions of the isolation material.

32. The computing device of claim 31, further comprising:

a memory coupled to the board.

33. The computing device of claim 31, further comprising:

a communication chip coupled to the board.

34. The computing device of claim 31, further comprising:

a camera coupled to the board.

35. The computing device of claim 31, further comprising:

a battery coupled to the plate.

36. The computing device of claim 31, further comprising:

an antenna coupled to the board.

37. The computing device of claim 31, wherein the component is a packaged integrated circuit die.

38. A computing device, comprising:

a plate; and

a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising:

a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;

a dielectric layer comprising a P-type dopant directly on first and second sidewalls of the lower fin portion of the fin, the dielectric layer having a first upper end portion laterally adjacent the first sidewall of the lower fin portion of the fin and a second upper end portion laterally adjacent the second sidewall of the lower fin portion of the fin;

an isolation material comprising oxygen laterally adjacent the dielectric layer directly on the first and second sidewalls of the lower fin portion of the fin, the isolation material having a first upper surface portion and a second upper surface portion, wherein the first upper surface portion of the isolation material is located below the first upper end portion of the dielectric layer, and wherein the second upper surface portion of the isolation material is located below the second upper end portion of the dielectric layer; and

a gate electrode over a top of the upper fin portion of the fin and laterally adjacent sidewalls of the upper fin portion of the fin, and over the first and second upper end portions of the dielectric layer, and over the first and second upper surface portions of the isolation material.

39. The computing device of claim 38, further comprising:

a memory coupled to the board.

40. The computing device of claim 38, further comprising:

a communication chip coupled to the board.

41. The computing device of claim 38, further comprising:

a camera coupled to the board.

42. The computing device of claim 38, further comprising:

a battery coupled to the plate.

43. The computing device of claim 38, wherein the component is a packaged integrated circuit die.

Technical Field

The present disclosure relates to fin-based electronic devices, and in particular, to junctions using solid source diffusion.

Background

Monolithic integrated circuits typically have a large number of transistors, such as metal-oxide semiconductor field effect transistors (MOSFETs) fabricated above a planar substrate, such as a silicon wafer. System-on-chip (SoC) architectures use such transistors in both analog and digital integrated circuits. When high-speed analog circuits are integrated on a single monolithic structure with digital circuits, the digital switches may introduce substrate noise, which limits the accuracy and linearity of the analog circuits.

Junction gate field effect transistors (JFETs) are used primarily in analog applications due to their superior low noise performance compared to standard MOSFET (metal oxide semiconductor FET) devices. JFETs are useful in radio frequency devices (e.g., filters and balancers), and are also useful in power circuits for power supplies, power regulators, and the like.

JFET transistors are fabricated in blocks of planar process technology using implanted junctions to establish back gate, channel, and top gate electrodes. JFETs are fabricated using implanted n-type and p-type wells to form top and back gates, and source and drain contacts. The body plane process may use fins formed on the substrate instead of MOSFET devices. The formation of FET devices on fins has been referred to as FinFET architectures.

Drawings

Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

Figures 1-4 are cross-sectional side views and corresponding front views of a p-channel current flow control gate on a fin architecture, according to embodiments of the invention.

Figure 5 is a cross-sectional side view of an n-channel current flow control gate on a fin architecture according to an embodiment of the present invention.

Figure 6 is a cross-sectional side view of a p-channel current flow control device having multiple gates on a fin architecture, in accordance with an embodiment of the present invention.

Fig. 7-22 are cross-sectional side views and corresponding front views of stages of manufacture of the device of fig. 1, in accordance with embodiments of the present invention.

Fig. 23-28 are cross-sectional side views and corresponding front views of alternative stages of manufacture of fig. 13-22, in accordance with embodiments of the present invention.

Figure 29 is a cross-sectional side view of a transistor on a finFET architecture, in accordance with an embodiment of the invention.

Fig. 30 is a circuit diagram of the transistor of fig. 29 according to an embodiment of the invention.

Fig. 31-55 are cross-sectional side views and corresponding front views of alternative stages of fabrication of the transistor of fig. 29, in accordance with embodiments of the present invention.

Fig. 56 is a block diagram of a computing device incorporating an integrated circuit built with a FinFET architecture and including solid state source diffusion junctions, according to an embodiment.

Detailed Description

High performance JFETs may be fabricated on the fins of a FinFET process architecture. JFET devices built on the fin in the same manner as MOSFET devices lose their ability to bulk transfer and high current since the electrical characteristics of the JFET device depend on its structure as a bulk transfer device. However, JFETs can be built using solid source diffusion on fin architectures to achieve high performance, scalable devices for system-on-chip process technology.

Similar techniques may be used to form the variable resistor. A P-channel or n-channel may be formed in the fin with contacts on either side of the fin. A control gate may be formed over the channel in the fin between the two contacts. The control gate provides excellent electrostatic control of carrier density inside the fin due to the nature of the current conduction inside the fin and the narrow width of the fin. By using this control gate, the carrier density can be increased (by channel accumulation) or decreased (by channel depletion) depending on the applied bias.

The same control gate technology can also be used on one or both sides of the gate of the JFET in the fin. The control gate functions as a variable resistor built into the fin-based JFET architecture. Since JFETs are typically longer channel devices to sustain high voltage operation, these control gates do not have an increased layout area penalty and can increase the pinch-off voltage required to completely close the channel.

Fig. 1 is a cross-sectional side view of a current flow control gate in a FinFET architecture. Which shows a portion of a fin on a substrate in a FinFET architecture. The fins 106, 108 protrude from the substrate 102 overlying the isolation oxide 104. The device 101 is built on a substrate 102 and fins. An n-well 106 is formed on the fin and may extend partially into the substrate, and a p-type channel 108 has been formed over the n-well on the fin. The fin as shown consists of these two parts, however, the fin may extend beyond the device and beyond the n-well and p-channel on either side of the device. A pair of contacts 110, 112 are formed in the p-channel, one on each side of the channel. A control gate 114 is formed over the fin between the two contacts. The flow of current from one channel contact 110 through the p-channel 108 to the other channel contact 112 is controlled by the control gate 114.

A portion of the device 101 of fig. 1 is shown in the front cross-sectional view of fig. 2. This view is a cross-section taken through line 2-2 of fig. 1, through control gate 114. As shown, the isolation oxide 102 and the n-well 106 are located directly above the substrate 102. A p-channel 108 is formed over the n-well 106.

A control gate 114 is formed over and around the P-channel, surrounding the P-channel on three sides. This allows the control gate electrode to pinch off the flow of carriers through the p-channel between the two contacts 110, 112. The p-channel is surrounded by a barrier layer 118 between the p-channel and the control gate to prevent diffusion between the p-channel and the gate.

The n-well extends through the isolation oxide. The n-well also extends above and below the top of the isolation oxide 104. This allows the control gate to extend all the way around the p-channel to more effectively control the flow of carriers through the p-channel. As shown, the control gate extends deeper on the fin than in the p-channel. This ensures that the p-channel is not only completely closed on three sides. Alternatively, the gate may be made smaller to allow leakage current through the p-channel even when the maximum voltage has been applied to the control gate.

Figure 3 is a cross-sectional front view of the fin and device 101 of figure 1 taken through either of the two contacts 110, 112 and in this example through line 3-3 of figure 1. As shown, the n-well is deep through the isolation oxide 104 to the substrate 102. A contact is formed over p-channel 108 to provide a suitable connection to the p-channel from an external source. The contact does not extend over the n-well and is not as deep as the control gate 114. Electrodes 120 and 122 are formed on both contacts 110, 112 so that an electric current can be applied to one or the other of the two contacts. The current flow between the two contacts is then controlled by the control gate.

Fig. 4 is a cross-sectional front view of an alternative contact 110-1. Fig. 4 presents the same view as fig. 3, but for an alternative embodiment. The contact of fig. 4 may be formed by adding an isolation oxide 124 to the contact of fig. 3. The same isolation oxide 104 and n-well 106 are formed over a substrate 102 (e.g., a silicon substrate). The P-channel 108 is built over the n-well 106 and is covered on top with contacts 110, 126 (similar to the contact 110 of fig. 3). In the example of fig. 4, additional fin spacers 124 are applied between the isolation oxide and the contacts 126 to prevent diffusion between the n-well and the p-type contacts. In practice, the fin is formed first and the fin is subsequently doped to form the n-well and the p-channel. Fin spacers 124 are then built around the fins with doped contacts 126 over fin spacers 124.

Fig. 5 is a cross-sectional side view of an n-channel variable current flow device in a FinFET architecture. An alternative variable resistor device 200 using an n-channel instead of a p-channel is shown. In this example, the substrate is not shown for simplicity, however, the device is formed using a FinFET architecture similar to that of fig. 1. The fin is constructed over a substrate. The fin is doped to form a deep p-well 206. The fin is surrounded by isolation oxide 204. The upper portion of the fin is doped to form an n-channel 208 over the p-well 206.

A pair of contacts (in this case, n-type contacts 210, 222) forms one contact on either side of the n-channel. The electrodes 220, 224 are attached to the contacts to allow current to be applied to one of the contacts. The flow through the n-channel 208 is controlled by a control gate 214, the control gate 214 having an electrode 230, and a variable voltage may be applied to the electrode 230. The variable resistor 200 of fig. 2 operates similarly to the variable resistor 101 of fig. 1. The increased voltage applied to terminal 230 allows more current to flow through the n-channel through control gate 214. In this case, the current takes the form of electrons rather than holes, however, the basic operation is the same.

Fig. 6 is a cross-sectional side view of a p-channel device with variable current flow controlled by multiple gates in a FinFET architecture. P-type contacts 310, 312 and n-type contact 318 as in figure 2 are combined to fabricate a dual gate p-type device 300. The device has a fin with a deep n-well 306. The upper portion of the fin is doped as a p-channel 308 and the fin is surrounded by isolation oxide 304. p-type contacts 310, 312 are formed at either end of the p-channel. An n-type contact 318 is formed between the two p-type channels. The first control gate 314 is placed between the left p-type contact 310 and the middle n-type contact 318. The second control gate 316 is placed between the n-type contact 318 and the right side p-type contact 312. The three contacts 310, 312, 318 each have terminals 320, 324, 322 to which an electrical current can be applied. The two control gates 314, 316 also have terminals 326, 328 to which voltages can be applied. By controlling the voltage in one or both of the control gates, the current flow through the p-channel can be regulated. In addition, the n-type contact 318 may also be used to regulate current flow through the device 300. These three contact devices allow very precise control of the current flow, which can be used for any of a number of different purposes.

As shown in fig. 1-6, a plurality of different devices may be formed using a fin architecture and solid surface annealing. The simplest devices have contacts at each end of the current channel. The contact may be coupled to an electrode or another device. This provides an isolated electrical conduit between the two points. The structure may be augmented by one or more control gates as shown in fig. 1 and 6. The structure may be augmented with transistor gates as shown in fig. 29 or the device may have a combination of different types of gates. Various different types of transistors, resistors, and other current control devices may be formed using the techniques described herein.

Fig. 7-28 are cross-sectional side views and corresponding front views of stages of manufacture of a variable resistor such as that depicted in fig. 1 and 5. In fig. 7 and 8, a substrate 402, such as a silicon substrate, has been processed to have fins 404, but only one fin is shown, and typically the substrate will have hundreds or thousands of fins, depending on the intended application.

In fig. 9 and 10, n-doped glass is deposited over the substrate. The n-type glass 406 comprises a doped oxide and may take the form of, for example, a phosphosilicate. The glass may be applied by chemical vapor deposition or a variety of other processes.

Fig. 11 and 12 show that spin-on hard mask 408 has been applied as a thick blanket coating over the substrate and glass. The mask covers the substrate and a lower portion of the fin. The masking layer leaves only the upper portion of the fin exposed. The glass on the rest of the structure is covered. Such an overlay coating of barrier material allows for the selective application of additional layers by protecting some areas but not others.

In this case, a spin-on hard mask has been used to protect the n-doped glass and the substrate on the lower portion of the fin from the etching process, as shown in fig. 13 and 14. Thus, the n-doped glass applied to the top of the fin has been removed. As shown in fig. 13 and 14, the exposed top of the fin sets the depth of the p-type channel to be formed, and also sets the back gate depth. In fig. 13 and 14, the glass over the upper portion of the fin has been removed, and the carbon hard mask has been removed, and a low-doped p-type glass has been deposited over the entire structure.

In fig. 15 and 16, the structure of fig. 13 and 14 has been annealed and all glass has been removed. Annealing drives dopants from the glass into the silicon or other thin material. The glass may then be removed using a standard oxide etch process or any of a variety of other processes. The structure of figures 15 and 16 has a lower silicon portion 402, an n-type substrate region 412, and an n-type lower portion of fin 414 due to glass deposition and annealing. Note that the upper portion of the substrate closest to the fin is also doped due to the n-type glass deposited over the substrate. This allows a very deep n-well to be formed under the p-channel at the top portion of the fin. The top of fin 416 is doped p-type to later form a p-channel over the deep n-well.

In this example, the doped glass forms a solid source of dopant. When the structure is annealed, dopants diffuse from the solid source into the fin. The specific process parameters of the solid source diffusion may be adjusted to suit the particular material, desired doping level, and overall process flow for fabricating the device. While doped glasses are described, other solid source diffusion methods and techniques may be used depending on the particular application and process parameters.

In fig. 17 and 18, an isolation oxide 418 is applied, which isolation oxide 418 may be any of a variety of oxides, including silicon dioxide. In fig. 19 and 20, the oxide is then planarized and patterned to allow a polysilicon control gate 420 structure to be applied over the fin. The polysilicon material may then be removed and backfilled with metal to form a metal control gate.

In fig. 21 and 22, contacts 420, 422 are applied over the fins, and spacers 426 are applied to separate the control gate 420 from the two contacts 422, 422. The spacers may be formed by deposition and may be left in place to control epitaxial growth, which may be applied to the structure in a later process.

As shown in fig. 19 and 20, the control gate surrounds the fin on three sides (the top side of the fin and two vertical sides of the fin. similarly, contacts 420, 422 also surround the fin on the top side and two sides.

Fig. 23-28 are side cross-sections and corresponding front views of stages of manufacture to illustrate an alternative manufacturing process. In the example of fig. 23 and 24, a deposited oxide has been applied over the structure of fig. 14. The structure of fig. 14 has been formed and the structure has subsequently been annealed. However, instead of subsequently removing the doped glass from the structure, an oxide isolation layer 518 is applied over the fin, substrate, and glass. Due to the anneal, a portion 512 of silicon substrate 502 is n-doped, a portion of fin 514 and substrate 512 form a deep n-well, with a higher doped p-type channel 516 on the upper portion of the fin. Due to the oxide isolation structure, p-doped glass 510 covers the fins and n-type glass 506 covers the fins and the substrate.

In fig. 25 and 26, deposited oxide 518 has been planarized and removed down to under the n-well region or the beginning of the n-type portion of fin 514. This exposes a large portion of the fins. All deposited glass over oxide layer 518 is then removed and a polysilicon structure 520 is formed over and around the fin to begin fabrication of the control gate.

In fig. 27 and 28, the control gate has been formed, the extra oxide has been removed, and the device is in a preliminary stage in preparation for application of the contacts as shown in fig. 21 and 22. By applying the isolation oxide before removing the deposited glass layer, several steps in the manufacturing process can be avoided, thereby reducing costs.

Fig. 29 is a cross-sectional side view of a transistor device formed on a fin of a FinFET architecture. As described above, solid source diffusion may be used in conjunction with implantation to form contacts for the resistor. The same techniques can be used for the source 612, drain 614, and top-gate back-gate contacts 626, 628 of the JFET. In JFET 600 as shown in fig. 29, when gate 620 between the source and drain is off, current flows in this case from p-type source 612 to p-type drain 614 through p-type channel 616. The p-channel, source, gate, and drain are all formed in fin 622 of the FinFET device architecture. The n-type gate has a contact 624 that is also coupled to an n-type top gate 626 and a back gate 628 that is also formed on the fin that is electrically coupled to the p-channel but spaced apart from the source, gate, and drain.

The n-type back 626 and top 620 gates deplete carriers of the narrow p-channel between the source and drain due to the increased gate voltage. This pinches off the channel and reduces the current that can flow from the source to the drain. Similar designs may be applied to an n-type channel in a fin having n-type sources and drains and a p-type gate.

Using a fin-based architecture, additional control gates 630, 632, similar to the control gates of the variable resistors described herein, may be used to further enhance or slow the current flow through the p-channel. The control gate may be formed inside the JFET on one or both sides of the gate. Similar to the variable resistor of fig. 1, the control gate of fig. 29 is fabricated over a fin, which covers the fin on the top and on both sides to substantially surround the p-channel.

The surrounding of the three sides of the gate enables excellent electrostatic control of the carrier density inside the fin due to the nature of the current conduction inside the fin and the narrow width of the fin. Depending on the applied bias, the control gate can instead increase carrier density by channel accumulation and decrease carrier density by channel depletion. As described above, in this way, the control gate functions as a variable resistor built into the fin-based JFET architecture. Since JFETs are typically longer channel devices to maintain high voltage operation, these control gates typically do not have increased layout area penalty and increase the pinch-off voltage required to completely turn off the channel.

Fig. 30 shows a corresponding circuit representation of a FinFET transistor showing a gate 620 to control current flow from the source 612 to the drain 614 and connections for two control gates 630, 632.

An exemplary process sequence over a 14 nm-like technology is shown below. Standard processing is used to define the fins and n-type glass is then conformally deposited on the tops of the fins. The glass is patterned using, for example, a spin-on hard mask that is recessed to expose the top of the fin. Followed by deposition of a conformal p-type glass. An anneal is performed to drive dopants from the glass into the silicon fins, and the glass is subsequently removed. A standard isolation oxide is deposited, planarized, and recessed to set the active fin height. An intermediate portion of the gate spacer is then deposited.

In some embodiments, the spacers are left entirely or partially on the fin to enable downstream epitaxial patterning of the JFET device. Epitaxial silicon undercut etching and growth may then be performed using conventional techniques, and a gate isolation oxide may then be deposited to enable formation of the contacts. Contacts for the source, drain, and gate are then constructed.

Fig. 31-55 are cross-sectional side and front views of stages in the fabrication of a JFET in a FinFET architecture. In fig. 31 and 32, a substrate 702 has one or more fins 704 formed thereon. The fins may be formed in any of a variety of different ways, depending on the particular implementation. In fig. 33 and 34, n-type glass 706 is deposited over the fin and substrate. Such glasses can be formed by a variety of different deposition processes and contain moderate dopant concentrations of n-type dopants. As mentioned above, the borosilicate or phosphosilicate may be applied by chemical vapor deposition, or any other technique may be used.

In fig. 35 and 36, a barrier material 708, such as a planarizing spin-on hard mask, is applied and patterned over the substrate. In the example shown, a thick cap is used, exposing the top of the fin while coating the bottom of the fin and the top of the substrate. The height of the mask layer determines the depth of the p-channel.

In fig. 37 and 38, the exposed n-type glass (i.e., where it is not covered by the spin-on hard mask) has been removed, and after the glass has been etched away, the blocking material is also removed. A high concentration of p-type doped glass is then applied over the entire fin and substrate. The p-type glass 710 will allow the fins to be doped as p-type material to build up a p-channel.

In fig. 39 and 40, the substrate, fins, and glass have been annealed. This drives the dopants from the glass into the silicon material. The glass is then removed using, for example, an oxide etch to leave the structure shown in fig. 39 and 40. The structure has a silicon substrate at its base and an n-doped well at the top of the substrate 712. In addition, the fin has a lower portion 714 that is also n-doped to form a back gate. The fin has an upper portion 716 that is p-doped to form a current flow channel.

In fig. 41 and 42, the entire structure is covered with an oxide layer 718 (e.g., silicon dioxide or another oxide). The oxide forms an isolation oxide that is subsequently planarized to a certain level as shown in figures 43 and 44 to expose some portion of the fin. The oxide is removed to expose a portion of the n-doped portion 714 of the fin. As shown in fig. 43 and 44, the fin is exposed, so that the entire p-channel is exposed because it is part of the N-doped back gate 714. The control gate 720 may then be formed around the entire exposed area of the fin down to the oxide level. The height or level of the oxide determines the size of the control gate accordingly. The control gate is deeper than the p-channel and covers the entire active fin height.

The control gate is typically metallic and may be formed in any of a variety of different ways. In the example shown, the control gate is first formed by polysilicon patterning to build up a structure corresponding to the desired shape 720 of the control gate. Patterning is done at this level and the polysilicon is subsequently removed, leaving voids in the shape of the desired control gate. The voids are then backfilled with metal to form the control gate. Electrodes and other connectors may then be attached to the metal. In the example shown, there are two control gates, however, there may be one control gate or no control gate depending on the intended final form of the JFET.

In fig. 45 and 46, the remaining spacers have been applied to the fin to control subsequent epitaxial growth. Spacers 722 are applied around the base of the fin over the oxide layer that remains in place.

Fig. 47-55 are cross-sectional side and front views of a further stage in the manufacture of the device of fig. 29. In these figures, a source, a gate, and a drain are added. The cross-sectional front views of fig. 48, 51, and 54 are taken at the location of the source similar to the view at the drain. The cross-sectional front views of fig. 49, 52, and 55 are taken at the location of the gate, rather than at the location of the control gate as in fig. 31-46. This is because the control gate, at least in the form of polysilicon, is already formed and is not affected by other stages.

In fig. 47, fig. 48, and fig. 49, the source gate and the drain of the JFET have been formed. Source 730 and drain 732 are formed by epitaxial growth of p-type elements, and gate 734 is formed by n-type epitaxial growth. A source and a drain are formed over the fin and the spacer using patterning and epitaxial growth. Spacers 722 prevent the source and drain from coming into contact with or coming too close to the deep n-well or back gate 714 of the fin. Thus, each contact node is in contact with only the p-channel. The source and drain may be formed by applying a doping material over the p-channel or by doping the actual p-channel. Similarly, an n-type gate is formed in or over the fin and is blocked by fin spacers 722 from being too close to the n-type back gate. On the other hand, as shown in fig. 22, for example, the control gate surrounds the p-channel all the way around and physically contacts the n-type back gate.

As shown, a first control gate is located between and in contact with the source and the gate, and a second control gate is located between and in contact with the gate and the drain. As shown, an isolation barrier is applied over and surrounding the control gate to prevent conduction and electrical contact between the control gate and the source, gate, and drain. The control gate may be isolated using any of a variety of dielectric barriers, and may also be physically spaced apart from any other structure.

In fig. 50, 51, and 52, the entire structure is covered in a deep layer of isolation oxide 738, which isolates the source, gate, and drain and control gates from each other. The top layer of isolation oxide may be planarized using any of a variety of different processes, for example, at the level of the top of control gates, electrodes, and other structures. In this example, the fin is well below the isolation oxide along with the source, gate, and drain.

In fig. 53, 54, and 55, contacts are formed over the gate, these contacts 740, 742, and 744 allowing connections to be made to the source, gate, and drain of the transistor device. Additionally, the polysilicon control gate may be dissolved and backfilled with metal, depending on the embodiment of the control gate. In the case where additional features are to be formed over the JFET structure, the top layer of dielectric 738 may be used as an interlayer dielectric. Depending on the fabrication technique, the electrodes may be formed from any of a variety of different materials, including tungsten.

As described, very common and widely used transistor types (JFETs) may be used in socs, power applications, or other types of ICs fabricated using non-planar transistor process technologies. In addition, the resistor or JFET device provides unique FinFET transfer characteristics not seen in planar fabrication techniques.

FIG. 55 illustrates a computing device 100 according to an embodiment of the invention. The computing device 100 houses a system board 2. The board 2 may include a number of components including, but not limited to, a processor 4 and at least one communication assembly 6. The communication assembly program is coupled to one or more antennas 16. The processor 4 is physically and electrically coupled to the board 2. In some embodiments of the invention, any one or more of the components, controllers, hubs, or interfaces are constructed using a FinFET architecture that includes solid-state source diffusion junctions.

Depending on its application, computing device 100 may include other components that may or may not be physically and electrically coupled to board 2. These other components include, but are not limited to, volatile memory (e.g., DRAM)8, non-volatile memory (e.g., ROM)9, flash memory (not shown), graphics processor 12, digital signal processor (not shown), cryptographic co-processor (not shown), chipset 14, antenna 16, display 18 (e.g., touchscreen display), touchscreen controller 20, battery 22, audio codec (not shown), video codec (not shown), power amplifier 24, Global Positioning System (GPS) device 26, compass 28, accelerometer (not shown), gyroscope (not shown), speaker 30, camera 32, and mass storage device (e.g., hard disk drive) 10, Compact Disc (CD) (not shown), Digital Versatile Disc (DVD) (not shown), and so forth. These components may be connected to the system board 2, mounted to the system board, or combined with any of the other components.

The communication assembly program 6 enables wireless and/or wired communication for data transfer to and from the computing device 100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communications combiner 6 may implement any of a number of wireless standards or protocols including, but not limited to, Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, bluetooth, ethernet, derivatives thereof, and any other wireless and wired protocols designated as 3G, 4G, 5G, and higher generation. The computing device 100 may include a plurality of communication assembly programs 6. For example, a first communication assembly procedure 6 may be dedicated to shorter range wireless communications (e.g., Wi-Fi and bluetooth), and a second communication assembly procedure 6 may be dedicated to longer range wireless communications (e.g., GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.).

Processor 4 of computing device 100 includes an integrated circuit die packaged within processor 4. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In various implementations, the computing device 100 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. The computing device may be fixed, portable, or wearable. In further implementations, the computing device 100 may be any other electronic device that processes data.

Embodiments may be implemented as part of one or more memory chips, controllers, CPUs (central processing units), microchips or integrated circuits interconnected using a motherboard, Application Specific Integrated Circuits (ASICs), and/or Field Programmable Gate Arrays (FPGAs).

References to "one embodiment," "an example embodiment," "various embodiments" indicate that the embodiment(s) of the invention so described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. In addition, some embodiments may have some, all, or none of the features described for other embodiments.

In the following description and claims, the term "coupled" along with its derivatives may be used. "coupled" is used to indicate that two or more elements co-operate or interact with each other, but the elements may or may not have intervening physical or electrical components between them.

As used in the claims, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common element, merely indicate that different instances of like elements are being referred to, and are not intended to imply that the elements so described must be in a given sequence, either spatially, temporally, in ranking, or in any other manner.

The figures and the foregoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be divided into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the order of the processes described herein may be changed and is not limited to the manner described herein. Further, the actions of any flow diagram need not be implemented in the order shown; nor is all actions necessarily performed. Additionally, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is in no way limited by these specific examples. Many variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the embodiments is at least as broad as given by the following claims.

The following examples relate to further embodiments. Various features of different embodiments may be combined in various ways with some features included and others excluded to suit various applications. Some embodiments relate to a method comprising forming a fin on a substrate; depositing a glass of a first dopant type over the substrate and over a lower portion of the fin; depositing a glass of a second dopant type over the substrate and the fin; annealing the glass to drive dopants into the fin and the substrate; removing the glass; and forming first and second contacts over the fin that do not contact a lower portion of the fin.

Further embodiments include forming a control gate over the fin, the control gate being a conductive material located over the top and on the sides of the fin to control current flow through the fin between the first contact and the second contact.

In further embodiments, forming the control gate includes patterning polysilicon over the fin, removing the polysilicon and backfilling a void in the polysilicon with a metal. Forming the control gate includes forming the control gate over the fin after removing the glass and before forming the first contact and the second contact. The first contact includes a source and the second contact includes a drain, the method further comprising forming a gate over the fin between the source and the drain that does not contact a lower portion of the fin.

Additional embodiments include depositing an oxide over the silicon substrate after removing the glass, the oxide having a depth that covers a lower portion of the fin, the oxide isolating the lower portion of the fin prior to forming the doped source, gate, and drain.

Additional embodiments include forming isolation spacers over the lower portion of the fin prior to forming the source, gate, and drain to prevent the source, gate, and drain from contacting the lower portion of the fin.

In further embodiments, the substrate and the fins are silicon.

In further embodiments, depositing the glass of the first dopant type includes: depositing a glass of a first dopant type over the substrate and the fin; depositing a barrier material (carbon hard mask) over portions of the fin and the substrate; removing the deposited glass not covered in the barrier material; and removing the barrier material.

In further embodiments, the blocking material is a carbon hard mask. Depositing a second dopant type of glass comprises: the method further includes removing the glass of the first dopant type from the portion of the fin and depositing the glass of the second dopant type over the portion of the fin and over the glass of the first dopant type. Removing the glass includes removing the glass using an oxide etchant.

Additional embodiments include forming a control gate over the fin, the control gate being a conductive material located over the top and on the sides of the fin for controlling current flow through the fin between the source and the drain.

In further embodiments, forming the control gate includes: patterning the polysilicon over the fin; the polysilicon is removed and the voids of the polysilicon are backfilled with metal. Forming the control gate includes forming the control gate over the fin after removing the glass and before forming the source, gate, and drain.

Some embodiments relate to an apparatus, comprising: a substrate; a fin over a substrate, the fin having a channel of a first dopant type and at least a portion of a well of a second dopant type; and a first contact and a second contact of the fin formed not to contact the well of the fin.

Further embodiments include a control gate located between and formed over and around the fin between the first contact and the second contact to control an electrical resistance between the first contact and the second contact.

In further embodiments, the control gate is a metal. The control gate is formed of polysilicon, which is subsequently removed, and the void created by the removal of the polysilicon is filled with metal. The first contact and the second contact are formed of a first dopant type. First and second contacts are formed over the epitaxially grown fin. The first contact and the second contact are formed in a fin having dopants therein. The channel of the first dopant type is a current channel between the first contact and the second contact. A control gate extends over and around the channel of the fin on both sides.

In further embodiments, the first contact includes a source and the second contact includes a drain, the apparatus further comprising a gate of the second dopant type formed by the fin between the source and the drain formed to not contact the well of the fin.

In further embodiments, a gate is formed over the epitaxially grown fin. A gate is formed in the fin with dopants in the fin. A gate is formed in the fin by depositing a doped glass over the fin, annealing the glass, and removing the glass. The channel of the first dopant type is a current channel between the source and the drain, and wherein a voltage applied to the gate determines whether current flows in the channel.

Further embodiments include a control gate located between the source and the drain, the control gate extending over and around the channel of the fin on both sides and configured to restrict current flow through the channel.

In further embodiments, the control gate is located between the source and the gate, and the transistor further comprises a second control gate located between the gate and the drain. The control gate is a metal. The control gate is formed of polysilicon which is subsequently removed and the void created by the removal of the polysilicon is filled with metal.

Some embodiments relate to a computing system including a communication chip, a power supply, and a processor having a plurality of transistors, at least one transistor being a junction gate field effect transistor having a substrate, a fin located above the substrate, the fin having a channel of a first dopant type and at least a portion of a well of a second dopant type, a source and a drain of the first dopant type of the fin formed as a well that does not contact the fin, and a gate of the second dopant type formed by the fin between the source and the drain formed as a well that does not contact the fin.

In further embodiments, a gate is formed in the fin by depositing a doped glass over the fin, annealing the glass, and removing the glass. The junction gate field effect transistor also includes a control gate between the source and the gate, the control gate being formed over and around the fin to control a resistance between the source and the drain. The control gate is formed by patterning polysilicon over the fin, removing the polysilicon, and backfilling the void in the polysilicon with a metal.

Some embodiments relate to a junction gate field effect transistor that includes a substrate, a fin located over the substrate, the fin having a channel of a first dopant type and at least a portion of a well of a second dopant type, a source and a drain of the first dopant type of the fin formed to not contact the well of the fin, and a gate of the second dopant type formed from the fin between the source and the drain formed to not contact the well of the fin.

Some embodiments relate to a variable resistor including a substrate, a fin over the substrate, the fin having a channel of a first dopant type and at least a portion of a well of a second dopant type, a first contact and a second contact of the fin formed without contacting the well of the fin, and a control gate between the first contact and the second contact formed over and around the fin to control a resistance between the first contact and the second contact.