阅读说明：本技术 一种时钟相位选择电路 (Clock phase selection circuit ) 是由 黄金煌 于 2021-03-17 设计创作，主要内容包括：本发明提供一种时钟相位选择电路,包括相位选择译码电路和时钟选择模块。相位选择译码电路包括M个脉冲发生单元、M个与门、M个触发单元和第一非门。在使能信号为高电平时,与M路相位依次延迟的候选时钟中相位在通讯场时钟的相位之前且与通讯场时钟的相位最接近的候选时钟对应的触发单元输出高电平,其它触发单元均输出低电平。时钟选择模块将与输出高电平的触发单元对应的1路候选时钟作为输出时钟输出。本发明提供的时钟相位选择电路,选出相位相近的候选时钟的时间仅需要通讯场时钟的几个周期,相比仅使用数字锁相环电路的方法,提高了根据通讯场时钟的相位变化锁定相位相近的候选时钟输出的响应时间。(The invention provides a clock phase selection circuit, which comprises a phase selection decoding circuit and a clock selection module. The phase selection decoding circuit comprises M pulse generating units, M AND gates, M trigger units and a first NOT gate. When the enable signal is at a high level, the trigger unit corresponding to the candidate clock, which is prior to the phase of the communication field clock and closest to the phase of the communication field clock, among the candidate clocks sequentially delayed from the M-way phase outputs the high level, and the other trigger units all output the low levels. The clock selection module outputs the 1-path candidate clock corresponding to the trigger unit outputting the high level as an output clock. The clock phase selection circuit provided by the invention has the advantages that the time for selecting the candidate clocks with similar phases only needs a few cycles of the communication field clock, and compared with the method only using the digital phase-locked loop circuit, the response time for locking the candidate clocks with similar phases according to the phase change of the communication field clock to output is improved.)

1. A clock phase selection circuit, comprising: the phase selection decoding circuit and the clock selection module;

the phase selection decoding circuit comprises M pulse generating units, M AND gates, M trigger units and a first NOT gate;

the input end of the ith pulse generation unit is used for inputting an ith candidate clock, the output end of the ith pulse generation unit is connected with one input end of an ith AND gate, the other input end of the ith AND gate is connected with the output end of the first NOT gate, the output end of the ith AND gate is connected with a first trigger end of an ith trigger unit, an enable end of the ith trigger unit is used for inputting an enable signal, a second trigger end of the ith trigger unit is connected with the output end of an i +1 th AND gate, the input end of the first NOT gate is used for inputting a communication field clock, the frequency of each candidate clock is N times of the frequency of the communication field clock, N is a positive integer, the phase of the i +1 th candidate clock lags behind the phase of the ith candidate clock by T/M, i =1, 2, … …, M and T is the period of the candidate clock;

the clock selection module is used for outputting 1 path of candidate clocks corresponding to the trigger unit with the data of 1 in the output end as an output clock;

the pulse generating unit is used for outputting a pulse signal under the triggering of the rising edge of the input signal;

the trigger unit is used for outputting a low level when the input enable signal is a low level; when the input enable signal is at a high level, if only the first trigger end generates a pulse signal, the high level is output and maintained, if only the second trigger end generates a pulse signal, the low level is output and maintained, and if neither the first trigger end nor the second trigger end generates a pulse signal, the output is maintained.

2. The clock phase selection circuit of claim 1, wherein the clock selection module comprises:

the clock selection submodule comprises a first delayer, a first OR gate, a second NOT gate, a first AND gate and M clock selection submodules;

the input end of the first delayer is used for inputting the communication field clock, the output end of the first delayer is connected with one input end of the first AND gate, and the other input end of the first AND gate is used for inputting the enable signal;

each clock selection submodule comprises a first-stage register, a second-stage register, a latch and an AND gate;

the first OR gate comprises M input ends, and the output end of the first OR gate outputs an output clock;

the data input end of the first-stage register of the ith clock selection submodule is connected with the output end of the ith trigger unit, the input clock end of the first-stage register of the ith clock selection submodule is connected with the output end of the first AND gate, and the data output end of the first-stage register of the ith clock selection submodule is connected with the data input end of the second-stage register of the ith clock selection submodule;

the data input end of the latch of the ith clock selection submodule is connected with the data output port of the second-stage register of the ith clock selection submodule, and the input clock end of the latch of the ith clock selection submodule is used for inputting the ith candidate clock;

one input end of the AND gate of the ith clock selection submodule is connected with the data output end of the latch of the ith clock selection submodule, the other input end of the AND gate of the ith clock selection submodule is used for inputting an ith candidate clock, and the output end of the AND gate of the ith clock selection submodule is connected with the ith input end of the first OR gate;

and the output end of the first OR gate is connected with the input clock end of the second-stage register of each clock selection submodule through the second NOT gate.

3. The clock phase selection circuit of claim 2, wherein the first delay is configured to delay the incoming communication field clock by 8 ns and transmit the delayed communication field clock to the first and gate.

4. The clock phase selection circuit of claim 1, wherein the pulse generation unit comprises:

the first delayer, the second NOT gate and the second AND gate;

the input end of the second delayer is connected with one input end of the second AND gate and serves as the input end of the pulse generation unit;

the output end of the second delayer is connected with the input end of the third not gate, the output end of the third not gate is connected with the other input end of the second and gate, and the output end of the second and gate is used as the output end of the pulse generation unit.

5. The clock phase selection circuit according to claim 1, wherein the pulse width of the pulse signal output from the pulse generation unit is 300 picoseconds.

6. The clock phase selection circuit of claim 1, wherein the trigger unit comprises:

a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a third AND gate, a second OR gate, a third OR gate and a fourth OR gate;

one input end of the third and gate is used as a first trigger end of the trigger unit;

the other input end of the third AND gate is connected with the input end of the fourth NOT gate and is used as an enabling end of the trigger unit;

one input end of the second OR gate is used as a second trigger end of the trigger unit;

the other input end of the second OR gate is connected with the output end of the fourth NOT gate, the output end of the second OR gate is connected with one input end of the third OR gate, the other input end of the third OR gate is connected with the output end of the fifth NOT gate, and the input end of the fifth NOT gate is connected with the output end of the fourth OR gate;

the output end of the third and gate is connected with one input end of the fourth or gate, the other input end of the fourth or gate is connected with the output end of the sixth not gate, the input end of the sixth not gate is connected with the output end of the third or gate, and the output end of the sixth not gate is used as the output end of the trigger unit.

7. The clock phase selection circuit of claim 1, wherein N is 2.

8. The clock phase selection circuit of claim 1, wherein the clock phase selection circuit is applied to an NFC card.

Technical Field

The present invention relates to the Field of NFC (Near Field Communication) technology, and more particularly, to a clock phase selection circuit.

Background

In the NFC scheme, the reader generates a communication field with a frequency of 13.56 MHz. The NFC card realizes communication with the card reader by reading the strength of a communication field sent by the card reader, and the speed of data sending is synchronous with the frequency of the communication field. This requires that the clock in the NFC card be identical in frequency and phase to the clock of the communication field sent by the reader.

The current common method is to use a digital phase-locked loop to achieve the required clock frequency to be consistent with the clock frequency of the communication field. However, the phase adjustment of the digital phase-locked loop is a very slow process, and if the phase of the communication field clock changes, the digital phase-locked loop cannot be locked to the same phase as the communication field clock in a short time. When the phase of the communication field changes suddenly, the phase of the digital phase-locked loop will deviate for a long time.

Disclosure of Invention

In view of the above, the present invention provides a clock phase selection circuit for quickly responding to a change of a clock phase of a communication field.

In order to achieve the above object, the following solutions are proposed:

a clock phase selection circuit, comprising: the phase selection decoding circuit and the clock selection module;

the phase selection decoding circuit comprises M pulse generating units, M AND gates, M trigger units and a first NOT gate;

the input end of the ith pulse generation unit is used for inputting an ith candidate clock, the output end of the ith pulse generation unit is connected with one input end of an ith AND gate, the other input end of the ith AND gate is connected with the output end of the first NOT gate, the output end of the ith AND gate is connected with a first trigger end of an ith trigger unit, an enable end of the ith trigger unit is used for inputting an enable signal, a second trigger end of the ith trigger unit is connected with the output end of an i +1 th AND gate, the input end of the first NOT gate is used for inputting a communication field clock, the frequency of each candidate clock is N times of the frequency of the communication field clock, N is a positive integer, the phase of the i +1 th candidate clock lags behind the phase of the ith candidate clock by T/M, i =1, 2, … …, M and T is the period of the candidate clock;

the clock selection module is used for outputting 1 path of candidate clocks corresponding to the trigger unit with the data of 1 in the output end as an output clock;

the pulse generating unit is used for outputting a pulse signal under the triggering of the rising edge of the input signal;

the trigger unit is used for outputting a low level when the input enable signal is a low level; when the input enable signal is at a high level, if only the first trigger end generates a pulse signal, the high level is output and maintained, if only the second trigger end generates a pulse signal, the low level is output and maintained, and if neither the first trigger end nor the second trigger end generates a pulse signal, the output is maintained.

Preferably, the clock selection module includes:

the clock selection submodule comprises a first delayer, a first OR gate, a second NOT gate, a first AND gate and M clock selection submodules;

the input end of the first delayer is used for inputting the communication field clock, the output end of the first delayer is connected with one input end of the first AND gate, and the other input end of the first AND gate is used for inputting the enable signal;

each clock selection submodule comprises a first-stage register, a second-stage register, a latch and an AND gate;

the first OR gate comprises M input ends, and the output end of the first OR gate outputs an output clock;

the data input end of the first-stage register of the ith clock selection submodule is connected with the output end of the ith trigger unit, the input clock end of the first-stage register of the ith clock selection submodule is connected with the output end of the first AND gate, and the data output end of the first-stage register of the ith clock selection submodule is connected with the data input end of the second-stage register of the ith clock selection submodule;

the data input end of the latch of the ith clock selection submodule is connected with the data output port of the second-stage register of the ith clock selection submodule, and the input clock end of the latch of the ith clock selection submodule is used for inputting the ith candidate clock;

one input end of the AND gate of the ith clock selection submodule is connected with the data output end of the latch of the ith clock selection submodule, the other input end of the AND gate of the ith clock selection submodule is used for inputting an ith candidate clock, and the output end of the AND gate of the ith clock selection submodule is connected with the ith input end of the first OR gate;

and the output end of the first OR gate is connected with the input clock end of the second-stage register of each clock selection submodule through the second NOT gate.

Preferably, the first delayer is configured to delay the input communication field clock by 8 nanoseconds and transmit the delayed communication field clock to the first and gate.

Preferably, the pulse generating unit includes:

the first delayer, the second NOT gate and the second AND gate;

the input end of the second delayer is connected with one input end of the second AND gate and serves as the input end of the pulse generation unit;

the output end of the second delayer is connected with the input end of the third not gate, the output end of the third not gate is connected with the other input end of the second and gate, and the output end of the second and gate is used as the output end of the pulse generation unit.

Preferably, the pulse width of the pulse signal output by the pulse generating unit is 300 picoseconds.

Preferably, the trigger unit includes:

a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a third AND gate, a second OR gate, a third OR gate and a fourth OR gate;

one input end of the third and gate is used as a first trigger end of the trigger unit;

the other input end of the third AND gate is connected with the input end of the fourth NOT gate and is used as an enabling end of the trigger unit;

one input end of the second OR gate is used as a second trigger end of the trigger unit;

the other input end of the second OR gate is connected with the output end of the fourth NOT gate, the output end of the second OR gate is connected with one input end of the third OR gate, the other input end of the third OR gate is connected with the output end of the fifth NOT gate, and the input end of the fifth NOT gate is connected with the output end of the fourth OR gate;

the output end of the third and gate is connected with one input end of the fourth or gate, the other input end of the fourth or gate is connected with the output end of the sixth not gate, the input end of the sixth not gate is connected with the output end of the third or gate, and the output end of the sixth not gate is used as the output end of the trigger unit.

Preferably, N is 2.

Preferably, the clock phase selection circuit is applied to an NFC card.

Compared with the prior art, the technical scheme of the invention has the following advantages:

the clock phase selection circuit provided by the technical scheme comprises a phase selection decoding circuit and a clock selection module. The phase selection decoding circuit comprises M pulse generating units, M AND gates, M trigger units and a first NOT gate. When the enable signal is at a high level, the trigger unit corresponding to the candidate clock, which is prior to the phase of the communication field clock and closest to the phase of the communication field clock, among the candidate clocks sequentially delayed from the M-way phase outputs the high level, and the other trigger units all output the low levels. The clock selection module outputs the 1-path candidate clock corresponding to the trigger unit outputting the high level as an output clock. The clock phase selection circuit provided by the invention has the advantages that the time for selecting the candidate clocks with similar phases only needs a few cycles of the communication field clock, and compared with the method only using the digital phase-locked loop circuit, the response time for locking the candidate clocks with similar phases according to the phase change of the communication field clock to output is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic diagram of a clock phase selection circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a clock selection module according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a pulse generating unit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a trigger unit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of input signals and output signals of a clock phase selection circuit according to an embodiment of the present invention;

fig. 6 is a schematic timing diagram of internal signals of the clock phase selection circuit according to the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, a clock phase selection circuit provided in this embodiment includes: a phase selection decoding circuit 11 and a clock selection block 12. The phase selection decoding circuit 11 includes M pulse generating units, M and gates, M trigger units, and a first not gate. Clk_iI =1, 2, … …, M, representing the ith candidate clock; in the technical scheme shown in fig. 1, M is 36, it should be noted that the numerical value of M is not limited in the present invention, and can be selected by a person skilled in the art according to the actual precision requirement. CR denotes a communication field clock. The frequency of each candidate clock is N times of the frequency of the communication field clock CR, and N is a positive integer. The phase of the (i + 1) th candidate clock lags behind the phase of the (i) th candidate clock by T/M, wherein T is the period of the candidate clock. p is a radical of_iRepresenting the pulse signal generated by the ith pulse generating unit.Representing the logical negation of the communication field clock. pa is a_iTo representAnd p_iAnd performing logical AND operation to obtain a signal. DEC (decamethylene tetra fluoro ethylene)_iOutput terminal of the ith flip-flopThe output signal.

The input end of the ith pulse generating unit is used for inputting the ith candidate clock. The output end of the ith pulse generating unit is connected with one input end of the ith AND gate. The other input end of the ith AND gate is connected with the output end of the first NOT gate. The output end of the ith AND gate is connected with the first trigger end R of the ith trigger unit. The enable terminal EN of the ith flip-flop is used for inputting an enable signal EN. And the second trigger end S of the ith trigger unit is connected with the output end of the (i + 1) th AND gate. The input of the first not-gate is used for inputting the communication field clock CR. When i = M, the second trigger end S of the ith trigger unit is connected to the output end of the i +1 th and gate, which means that the second trigger end S of the mth trigger unit is connected to the output end of the 1 st and gate.

And a clock selection module 12, configured to output, as an output clock CO, the 1-channel candidate clock corresponding to the trigger unit whose data in the output end is set to 1. It should be noted that the ith trigger unit corresponds to the ith candidate clock, that is, the 1 st candidate clock corresponding to the ith trigger unit is the ith candidate clock.

The pulse generating unit is used for outputting a pulse signal under the trigger of the rising edge (when the input signal jumps from the low level to the high level) of the input signal, wherein the pulse signal is changed from the low level to the high level and is changed back to the low level. Due to the delay and implementation of the circuit components of the trigger unit, the trigger signals of the first trigger terminal R and the second trigger terminal S of the trigger unit need to be maintained for at least 150 picoseconds to effectively trigger the trigger unit. In one embodiment, the pulse width of the pulse signal is 300 picoseconds to ensure that the trigger unit can be triggered normally.

The trigger unit is used for outputting a low level when the input enable signal EN is at a low level; when the input enable signal EN is at high level, if only the first trigger terminal R generates a pulse signal, the high level is output and kept, if only the second trigger terminal S generates a pulse signal, the low level is output and kept, and if the first trigger terminal R and the second trigger terminal R generate pulse signals, the low level is output and keptAnd keeping the low level when the pulse signal does not appear in S. That is, the trigger unit outputs the enable signal "0Will always output a "0"; when the enable signal EN is "1", if a pulse signal appears at the first trigger terminal R, the output terminalOutputting and keeping the output of '1'; if a pulse signal appears at the second trigger terminal S, the output terminalWill output "0" and hold; if the first trigger terminal R and the second trigger terminal S are both kept at low level, the output terminalWill keep the output unchanged; if the first trigger end and the second trigger end simultaneously generate pulse signals, the output endIt will become unstable.

The phase selection decoder circuit 11 functions to select 36 clock candidates Clk when the enable signal EN is "1" (high level)_i(i is more than or equal to 1 and less than or equal to 36) finding the k-th candidate clock with the phase which is before the phase of the communication field clock CR and is closest to the phase of the communication field clock CR; the output data of the kth flip-flop cell corresponding to the kth candidate clock is set to "1", and the output data of the remaining flip-flops are all "0" (low level). When the enable signal EN is "0", the output data of each flip-flop cell will remain unchanged from the previous value, i.e., the data value before the time when EN changes from "1" to "0".

After the 36 paths of candidate clocks are respectively accessed into the pulse generating unit, 36 paths of pulse signals p are obtained_i(i is more than or equal to 1 and less than or equal to 36). Pulse signal p_iAnd corresponding candidate clock Clk_iAre aligned; pulse signal p_iPulse period and Clk_iThe clock periods T are the same; the pulse period refers to the time from one pulse to the next. After the candidate clock passes through the pulse generating unit, a very short high-level pulse is generated at the original rising edge, and the other moments are all low levels, which is equivalent to shortening the high-level width of the candidate clock and keeping the period unchanged.

36 paths of pulse signals p_i(i is more than or equal to 1 and less than or equal to 36) and the input communication field clock CR respectivelyAfter logical AND operation, 36 paths of signals pa are obtained_i(ii) a I.e. all those paths which generate pulses at a low level of the communication field clock CR_iWill be retained to pa_iAnd all those paths generating pulses at the high level of the communication field clock CR_iCorresponding pa_iWill be low with no pulse generated. If p is_k-1Is generated before the rising edge of the communication field clock CR, and p_kIs generated after the rising edge of the communication field clock CR, then p_k-1With the previous signal (p)_k-2Etc.) will hold the pulse signal, and p_kAnd a subsequent signal (p)_k+1Etc.) will not be pulsed.

First trigger terminal input pa of ith trigger unit_iSecond trigger input pa_i+1. When the enable signal EN is '0', the output end of each trigger unitAll data of (1) are kept to "0". When the enable signal EN is "1", if only pa_iGenerating a pulse to cause the output of the ith trigger unitBecomes "1" and remains; when the enable signal EN is "1", if only pa_i+1Generating a pulse to cause the output of the ith trigger unitBecomes "0" and remains; when the enable signal EN is "1", if pa_iAnd pa_i+1All generate pulses due to pa_i+1Will be compared pa_iThe delay T/36 is generated, so that the output end of the ith trigger unitThe data of (1) will soon change back to "0" and remain at "0"; when the enable signal EN is "1", if pa_iAnd pa_i+1No pulse is generated, then the output end of the ith trigger unitThe data of (1) will remain unchanged for "0" all the time; therefore, only when pa_iGenerate pulses toOutput of the pulse-free, i-th trigger unitWill continue to remain "1" unchanged after becoming "1"; thus, there is only one output of the trigger unitWill always be "1", the output of the other trigger unitsThe data of (a) is mostly "0" or always remains "0".

Referring to fig. 2, a preferred implementation of the clock selection module 12 is shown, in this embodiment, the clock selection module includes a first delayer, a first or gate, a second not gate, a first and gate, and 36 clock selection submodules. 36-way candidate clock Clk_i(i =1, … …, 36), the period of each candidate clock is T, and the phase of each candidate clock is TThe phase of the candidate clock is delayed by T/36 compared with the previous path.

The input end of the first delayer is used for inputting a communication field clock CR; the output end of the first delayer is connected with one input end of the first AND gate; the other input end of the first AND gate is used for inputting an enable signal EN. The first or gate includes 36 inputs. The output of the first or gate is an output clock CO. The delay is also a standard circuit device, comprising a data input and a data output. The function of the delayer is to delay the data of the data input end for a certain time and then output the data output end. In a specific embodiment, the first delayer is configured to delay the input communication field clock CR by 8 nanoseconds, transmit the delayed communication field clock CRD to the first and gate, and perform a logical and operation with the enable signal EN to obtain the delayed reference clock CRG. The delayed reference clock CRG is an 8-nanosecond delayed clock of CR when the enable signal EN is "1", and the delayed reference clock CRG is always maintained at "0" when the enable signal EN is "0". Delaying CR by 8 ns enables first-stage registers to acquire DEC_iThen, DEC_iHas stabilized.

Each clock selection submodule comprises a first-stage register, a second-stage register, a latch and an AND gate. The register is a standard circuit device and comprises a data input end D, an input clock end and a data output end Q. The registers adopted in the invention are all rising edge trigger registers; the function of the rising edge triggered register is: and when the rising edge of the input clock occurs, storing the data of the data input end D to the data output end Q, namely acquiring and maintaining the data of the data input end D to the data output end Q.

The data input end D of the first-stage register of the ith clock selection submodule is connected with the output end of the ith trigger unit. And the input clock end of the first-stage register of the ith clock selection submodule is connected with the output end of the first AND gate. The data output end Q of the first-stage register of the ith clock selection submodule is connected with the number of the second-stage registers of the ith clock selection submoduleAccording to the input terminal D. en is a radical of_iData representing the data output port of the first stage register of the ith clock select submodule.

And the data input end E of the latch of the ith clock selection submodule is connected with the data output end of the second-stage register of the ith clock selection submodule. And the input clock end of the latch of the ith clock selection submodule is used for inputting the ith candidate clock. A latch is a standard circuit device comprising a data input E, an input clock terminal and a data output Q. The function of the latch is: when the input clock is at a low level, the data of the data input end E is directly output to the data output end Q; when the input clock is high, the data at the data output terminal Q remains unchanged. den (r)_iRepresenting the data at the data output Q of the second stage register of the ith clock selection submodule.

And one input end of the AND gate of the ith clock selection submodule is connected with the data output end Q of the latch of the ith clock selection submodule. The other input end of the AND gate of the ith clock selection submodule is used for inputting the ith candidate clock Clk_i. And the output end of the AND gate of the ith clock selection submodule is connected with the ith input end of the first OR gate. The output port of the first OR gate is connected with the input clock end of the second-stage register of each clock selection submodule through a second NOT gate; the output port of the first or gate is connected with the input end of the second not gate, and the output end of the second not gate is respectively connected with the input clock end of each second-stage register. Gate (gate)_iData representing the data output Q of the latch of the ith clock selection submodule; gclk_iData representing the output of the and gate of the ith clock selection submodule;which represents the inverted clock obtained after the output clock CO is subjected to a logical negation operation.

The ith clock selection submodule uses the delay reference clock CRG of the output end of the first AND gate as the input clock of the first-stage register to collect DEC output by the trigger unit_iEn obtained_i(ii) a Backward clock using output clock COAs input clock for the second stage register, pair en_iCollecting to obtain the collected resultApproximately synchronized with the candidate clock to be selected. Clk_iAs the input clock of the latch, the latch is obtained. Due to the fact that in the den_i(i =1, 2, … … 36), only one value is "1", and the rest are all "0"; and dec_iApproximately synchronous with the candidate clock to be selected, so that the latch result is also only "1" all the way. Latching the result gate with each way_iClk respectively corresponding to local path_iPerforming an AND operation; then the result gclk obtained from each path_iThen the result of the OR operation is output as CO; since only one way has a "1" latch result, only the candidate clock for that way is selected for output as CO.

Because the phase selection decoding circuit is composed of a series of circuits, each circuit and the connecting line have time delay, and after passing through the phase selection decoding circuit, the output value DEC of the phase selection decoding circuit₁~DEC₃₆There may be delays of different degrees, making it difficult to obtain stable results simultaneously; possible occurrence of DEC₁Has been changed from "0" to "1", and DEC₂A case where "1" has not changed to "0". Therefore if latches are used directly to latch DEC₁~~DEC₃₆Since each latch uses a different candidate clock as the input clock, and DEC₁~DEC₃₆Cannot guarantee simultaneous change, so there is a possibility that the acquisition value gate is generated₁~gate₃₆There are multiple disallowed cases where "1" is simultaneously or all are "0". Aiming at the technical problem, the ith clock selection submodule acquires DEC by utilizing a first-stage register₁~DEC₃₆At the input of an enabling messageDEC is acquired on the rising edge of CRG with number EN being "1₁~DEC₃₆To yield en₁~en₃₆While when the enable signal EN is "0", CRG will always be kept low, so EN₁~en₃₆Will remain there; next, en₁~en₃₆The phase is synchronous with the rising edge of the CRG, and if the rising edge of the candidate clock is directly used for acquisition, the problem of unstable state can be caused as the phase cannot be ensured; the invention uses a second stage register, and the input clock of the second stage register uses a reverse clockUsing the falling edge of the output clock CO as a trigger for the second stage register, en₁~en₃₆And (5) collecting. Since the frequency of the candidate clock isIntegral multiple of the first, so that the candidate clock selected at each rising edge of CR does not change much from the previous one, and is likely to be unchanged, or is adjacent to the previous one; i.e. the phase difference between the selected candidate clock and the output clock CO is small, so that the clock is usedCollecting en falling edge₁~en₃₆On the one hand, the unstable change can be avoided, and en is collected₁~en₃₆On the other hand, the obtained en₁~en₃₆The location of the output change is not near the rising edge of the candidate clock to be selected.

Referring to fig. 3, a pulse generating unit provided in this embodiment includes a second delay, a third not gate, and a second and gate. The input end of the second time delay device is connected with one input end of the second AND gate and serves as the input end of the pulse generation unit. The output end of the second time delay is connected with the input end of the third NOT gate. The output end of the third NOT gate is connected with the other input end of the second AND gate. The output end of the second AND gate is used as the pulseAn output of the generating unit. Processing an input signal I of the pulse generation unit by a second delayer to obtain a signal d; performing logical negation operation on the signal d to obtain a signal(ii) a Will signalAnd performing logical AND operation with the input signal I of the pulse generating unit to obtain an output signal O of the pulse generating unit. The delay time of the second delayer determines the pulse width of the pulse signal output by the pulse generating unit.

Referring to fig. 4, a trigger unit provided for this embodiment includes a fourth not gate, a fifth not gate, a sixth not gate, a third and gate, a second or gate, a third or gate, and a fourth or gate. One input end of the third and gate is used as a first trigger end R of the trigger unit. The other input end of the third AND gate is connected with the input end of the fourth NOT gate and is used as an enabling end EN of the trigger unit. One input terminal of the second or gate serves as the second trigger terminal S of the trigger unit. The other input of the second or gate is connected to the output of the fourth not gate. The output of the second or gate is connected to an input of a third or gate. The other input end of the third OR gate is connected with the output end of the fifth NOT gate. And the input end of the fifth NOT gate is connected with the output end of the fourth OR gate. The output end of the third AND gate is connected with one input end of the fourth OR gate. The other input end of the fourth OR gate is connected with the output end of the sixth NOT gate. And the input end of the sixth NOT gate is connected with the output end of the third OR gate. The output end of the sixth NOT gate is used as the output end of the trigger unit。

Performing logical AND operation on a signal input by a first trigger end R of the trigger unit and an enable signal EN to obtain a signal d 1; performing logical negation operation on the enable signal EN of the trigger unit to obtain a signal d 0; performing logical or operation on the signal d0 and a signal input by the second trigger terminal S to obtain a signal d 2; will signald1 and output terminalThe signal d3 is obtained by logical or operation; performing logical negation on the signal d3 to obtain a signal Q; performing logical OR operation on the signal d2 and the signal Q to obtain a signal d 4; performing logical negation operation on the signal d4 to obtain an output endOf the signal of (1). When the enable signal EN is "0", the inverted d0 is "1", and d1 is always "0" regardless of the value of the signal of the first flip-flop R, and d2 is always "1" regardless of the value of the signal of the second flip-flop S, which will make the output terminal outputThe signal of (1) is always "0"; when EN is "1", d0 is "0", d1 will be consistent with the signal of the first trigger terminal R, and d2 will be consistent with the signal of the second trigger terminal S; if the signals of the first trigger terminal R and the second trigger terminal S are kept at low level all the time, the output terminalThe signal of (1) always keeps the value of "0" when EN is "0"; if the first trigger terminal R generates a pulse, the output terminal is connected to the output terminalBecomes "1"; if the second trigger terminal S generates a pulse, the output terminal is connected to the first trigger terminal SBecomes "0"; if the first trigger terminal R and the second trigger terminal S generate pulses simultaneously, the output terminalThe signal of (2) will become unstable value, but the present invention does not actually generate pulses at the same time at the first trigger terminal R and the second trigger terminal S; due to the trigger unit circuitFor the reason of realizing the characteristics, it is required that the high level pulse widths of the first trigger terminal R and the second trigger terminal S need to be maintained for more than 150 picoseconds.

The clock phase selection circuit provided by the invention can be applied to an NFC card. In some embodiments, N is 2, i.e., each candidate clock is generated at twice the frequency of the communication field clock.

Referring to fig. 5, a schematic diagram of an input signal and an output signal of the clock phase selection circuit provided in this embodiment is shown. The input clock of the clock phase selection circuit is as follows: 36-way candidate clock Clk₁~Clk₃₆The clock periods are all T. Clk₂Phase ratio Clk of₁Time of T/36, Clk₃Phase ratio Clk of₂Push back T/36 time, and so on, Clk₁Phase ratio Clk of₃₆And the time of T/36 is pushed back. The period of the communication field clock is 2T. This clock phase selection circuit selects, as the output clock CO, a candidate clock whose rising edge (phase) precedes the rising edge of CR and is closest to the rising edge of CR. Referring to FIG. 5, if the rising edge of CR is at Clk₃₆Rising edge of and Clk₁Between rising edges, Clk is then set₃₆As an output clock CO.

Referring to fig. 6, a timing diagram of internal signals of the clock phase selection circuit provided in this embodiment is shown. Candidate clock Clk₁~Clk₃₆A periodic pulse signal p is obtained after passing through the pulse generating unit₁~p₃₆. Pulse signal p₁~p₃₆Respectively with corresponding Clk₁~Clk₃₆Are aligned. p is a radical of₁~p₃₆Are respectively connected withCarrying out logical AND operation to obtain pa₁~pa₃₆This corresponds to the pulse signal P occurring at the time of CR low level_iIs transmitted to corresponding pa_iAnd when CR is high level, pa₁~pa₃₆Is always kept low. Pulse signal pa₃₅Let DEC₃₅Goes high and then pulse signal pa is generated₃₆Will soon DEC₃₅Change back to low level, thus DEC₃₅Maintained for only brief periods of high level, also DEC₀The same brief high time will occur. While signal DEC₃₆Is being pulsed with signal pa₃₆After the trigger goes high, due to the subsequent p₁No pulse signal is generated, resulting in pa₃₆Keeps high level for a long time until next pulse signal p₁And then becomes low. The reference delay signal CRG is a signal obtained by delaying CR for 8 ns, and is also "0" when the enable signal EN is "0"; at the rising edge of the reference delay signal CRG, pa₃₆Is a value of "1", hence en₃₆Will become "1" and hold; but due to other DECs_iAll values are "0", so the corresponding en_iWill remain at "0".

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The embodiments in the present description are mainly described as different from other embodiments, the same and similar parts in the embodiments may be referred to each other, and the features described in the embodiments in the present description may be replaced with each other or combined with each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.