阅读说明：本技术 脉冲信号产生器 (Pulse signal generator ) 是由 刘温良 陈淑娟 于 2020-05-12 设计创作，主要内容包括：本公开提出一种脉冲信号产生器,包含触发电路、处理电路及脉冲产生电路。触发电路检测交流电源的一过零点,交流电源是供应电子装置操作于运行功率,触发电路在检测到过零点时产生触发信号。处理电路在触发电路产生触发信号后输出对应运行功率的脉冲宽度初始值,且输出宽度初始值与宽度目标值之间的宽度中间值,并在宽度中间值变化一变化量后达到宽度目标值时输出宽度目标值。脉冲产生电路根据处理电路输出的宽度初始值、宽度中间值及宽度目标值在不同时间点产生脉冲宽度不相同的脉冲信号。(The present disclosure provides a pulse signal generator, which includes a trigger circuit, a processing circuit and a pulse generating circuit. The trigger circuit detects a zero crossing point of an alternating current power supply, the alternating current power supply supplies the electronic device with operating power, and the trigger circuit generates a trigger signal when the zero crossing point is detected. The processing circuit outputs a pulse width initial value corresponding to the operation power after the trigger circuit generates the trigger signal, outputs a width intermediate value between the pulse width initial value and the width target value, and outputs the width target value when the width intermediate value changes by a change amount and reaches the width target value. The pulse generating circuit generates pulse signals with different pulse widths at different time points according to the width initial value, the width intermediate value and the width target value output by the processing circuit.)

1. A pulse signal generator for providing a pulse signal required by an electronic device operating at a running power, comprising:

the trigger circuit is used for detecting a zero crossing point of an alternating current power supply, the alternating current power supply supplies the electronic device with the running power, and the trigger circuit generates a trigger signal when the zero crossing point is detected;

a processing circuit coupled to the trigger circuit for outputting a first width initial value corresponding to the operating power after the trigger circuit generates the trigger signal, and outputting a first width intermediate value after a first preset time, the first intermediate width value is a value obtained by changing the first initial width value by a first variation to approach a first target width value, and determining whether the first width intermediate value reaches the first width target value after changing toward the first width target value by a second variation amount, the processing circuit outputs a second width intermediate value after a second preset time elapses after outputting the first width intermediate value, the second width intermediate value is the first width intermediate value and changes the second variation to approach the first width target value, when the judgment is yes, the processing circuit outputs the first width target value after the second preset time passes after outputting the first width intermediate value; and

a pulse generating circuit, coupled to the processing circuit, for generating a first pulse signal having a pulse width of the first initial value when the processing circuit outputs the first initial value, generating a second pulse signal having a pulse width of the first intermediate value when the processing circuit outputs the first intermediate value, generating a third pulse signal having a pulse width of the second intermediate value when the processing circuit outputs the second intermediate value, and generating a fourth pulse signal having a pulse width of the first target value when the processing circuit outputs the first target value.

2. The pulse signal generator according to claim 1, wherein when the first width target value is greater than the first width initial value, the first width intermediate value is greater than the first width initial value and the second width intermediate value is greater than or equal to the first width intermediate value, and when the first width target value is less than the first width initial value, the first width intermediate value is less than the first width initial value and the second width intermediate value is less than or equal to the first width intermediate value.

3. The pulse signal generator according to claim 1, further comprising a timing circuit coupled to the trigger circuit, the timing circuit being triggered by the trigger signal to time a first time interval and a second time interval, the pulse generating circuit generating a plurality of pulse signals with fixed pulse widths in the first time interval, the pulse generating circuit generating the first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal according to the first width initial value, the first width intermediate value, the second width intermediate value and the first width target value output by the processing circuit in the second time interval.

4. The pulse signal generator according to claim 3, wherein the timing circuit further clocks a third time interval, the processing circuit outputs the first width target value or a third width intermediate value between the first width initial value and the first width target value and changing towards a second width target value by a third change amount in the third time interval, and determining whether the third width intermediate value reaches the second width target value after changing toward the second width target value by a fourth variation amount, the processing circuit outputs a fourth width intermediate value after a third preset time elapses after outputting the third width intermediate value, the fourth width intermediate value is the third width intermediate value and changes the fourth variation to approach the second width target value, when the judgment is yes, the processing circuit outputs the second width target value after the third preset time passes after outputting the third width intermediate value;

the pulse generating circuit further generates a fifth pulse signal having a pulse width equal to the third intermediate width value when the processing circuit outputs the third intermediate width value, generates a sixth pulse signal having a pulse width equal to the fourth intermediate width value when the processing circuit outputs the fourth intermediate width value, and generates a seventh pulse signal having a pulse width equal to the second target width value when the processing circuit outputs the second target width value.

5. The pulse signal generator according to claim 4, wherein the processing circuit determines whether the first predetermined time, the second predetermined time and the third predetermined time are equal or unequal according to the operating power.

6. The pulse signal generator according to claim 4, wherein the processing circuit determines the first variation is equal to or not equal to the second variation and the third variation is equal to or not equal to the fourth variation according to the operating power.

7. The pulse signal generator according to claim 4, wherein a difference between the third variation and the fourth variation is smaller than zero when a difference between the first variation and the second variation is larger than zero, and a difference between the third variation and the fourth variation is larger than zero when the difference between the first variation and the second variation is smaller than zero.

8. The pulse signal generator according to claim 7, wherein an absolute value of a difference between the first variation and the second variation is equal to an absolute value of a difference between the third variation and the fourth variation.

9. The pulse signal generator according to claim 4, wherein after the timing circuit times the third time interval, the timing circuit times a fourth time interval before the AC power source passes through a next zero-crossing point, and the pulse generating circuit generates a plurality of pulse signals with fixed pulse widths in the fourth time interval.

10. The pulse signal generator according to claim 1, wherein the electronic device comprises a switch circuit implemented by an insulated gate bipolar transistor, the pulse generating circuit coupled to the switch circuit for outputting the first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal to the switch circuit.

Technical Field

The present disclosure relates to a pulse signal generator, and more particularly, to a pulse signal generator generating a variable pulse width.

Background

The conventional electromagnetic heating apparatus includes a pulse generator for driving a resonant circuit on a wire coil in the electromagnetic heating apparatus, and the pulse generator can generate a pulse signal with a fixed width under the same operating power, thereby causing severe electromagnetic interference (EMI) when the electromagnetic heating apparatus is operated at the maximum power (e.g., 2100W). In recent years, the health and environmental protection concept is rising, and various countries in the world successively require that various electronic products must limit EMI emission and consider the problem of electromagnetic interference (EMC) resistance and electromagnetic compatibility (EMS), and various standards and implementation routes such as electromagnetic interference EMI/EMC/EMS are made according to the requirements of the countries.

Therefore, if the EMI problem is not emphasized in the product development stage, the EMI problem cannot be solved only by a limited reduction of EMI only by adding the EMI-resistant element to the external printed circuit board in the later stage of the product development, and the product may need to be redesigned to delay the time to market. Therefore, from the viewpoint of the main generation source of EMI, EMI problems occur in that an Insulated Gate Bipolar Transistor (IGBT) of the electromagnetic heating device has a problem of hard turn-on when it operates at low power, and the operating voltage of the IGBT is excessively high when the electromagnetic heating device operates at high power. In order to effectively reduce the hard conduction problem of the IGBT, the distance between the coil panel and the furnace surface is increased in the existing electromagnetic heating device, but the IGBT generates too high back pressure, so that the electromagnetic heating device cannot operate at the maximum power, and meanwhile, the more serious EMI problem is caused.

Disclosure of Invention

In one embodiment, a pulse signal generator includes a trigger circuit, a processing circuit, and a pulse generating circuit. The trigger circuit detects a zero crossing point of an alternating current power supply, the alternating current power supply supplies the electronic device with running power, and the trigger circuit generates a trigger signal when the zero crossing point is detected. The processing circuit outputs a first width initial value corresponding to the running power after the trigger circuit generates the trigger signal, and outputs a first width intermediate value when a first preset time passes, wherein the first width intermediate value is the first width initial value and changes a first variation to approach a first width target value, and judges whether the first width intermediate value reaches the first width target value after changing a second variation towards the first width target value. The pulse generating circuit generates a first pulse signal with a pulse width of the first width initial value when the processing circuit outputs the first width initial value, generates a second pulse signal with a pulse width of the first width intermediate value when the processing circuit outputs the first width intermediate value, generates a third pulse signal with a pulse width of the second width intermediate value when the processing circuit outputs the second width intermediate value, and generates a fourth pulse signal with a pulse width of the first width target value when the processing circuit outputs the first width target value.

Drawings

Fig. 1 is a block diagram of an embodiment of a pulse signal generator suitable for an electronic device according to the present disclosure.

FIG. 2 is a waveform diagram of an embodiment of the pulse generating circuit of FIG. 1 generating different pulse signals with different pulse widths.

FIG. 3 is a diagram illustrating an embodiment of a time interval clocked by the timing circuit of FIG. 1.

FIG. 4 is a waveform diagram of another embodiment of the pulse generating circuit of FIG. 1 generating different pulse signals with different pulse widths.

FIG. 5 is a diagram illustrating an embodiment of a variation trend of different pulse widths output by the processing circuit of FIG. 1 at different time points.

Description of reference numerals:

1: pulse signal generator

11: trigger circuit

12: processing circuit

13: pulse generating circuit

14: timing circuit

S1: trigger signal

S2: timing signal

S3: pulse width signal

S4: pulse signal

T1: a first time interval

T2: second time interval

T3: third time interval

T4: a fourth time interval

Detailed Description

Fig. 1 is a block schematic diagram of an embodiment of a pulse signal generator 1 suitable for an electronic device according to the present disclosure. Referring to fig. 1, the pulse signal generator 1 may generate a pulse signal S4 required by the electronic device to operate at an operating power set by a user, where the electronic device may be an Induction cooker, a microwave oven, or an Induction Heating (IH) electric cooker, and the operating power may be 1600 watts, 1800 watts, or 2000 watts. If the electronic device operates at 2000 watts, the pulse signal generator 1 may generate the pulse signal S4 with different pulse widths corresponding to the operating power of 2000 watts, so that the pulse signal S4 with different pulse widths may generate the operating power with an average power of 2000 watts within a predetermined time period; if the electronic device operates at 1600 w, the pulse signal generator 1 can generate the pulse signal S4 with different pulse widths corresponding to the operating power of 1600 w, so that the pulse signal S4 with different pulse widths can generate the operating power with an average power of 1600 w within a predetermined time period, and so on, and thus, the description thereof is omitted.

As shown in fig. 1, the pulse signal generator 1 includes a trigger circuit 11, a processing circuit 12, and a pulse generating circuit 13. The processing circuit 12 is coupled between the trigger circuit 11 and the pulse generating circuit 13. When the electronic device receives the ac power and operates at the operating power set by the user, the trigger circuit 11 detects a zero-crossing point of the ac power, and the trigger circuit 11 generates a trigger signal S1 when the zero-crossing point is detected. After the trigger circuit 11 generates the trigger signal S1, according to the operating power of the electronic device, the processing circuit 12 outputs a corresponding initial width value (hereinafter referred to as a first initial width value for convenience of description) as the pulse width signal S3 at a first time point, and outputs an intermediate width value (hereinafter referred to as a first intermediate width value) as the pulse width signal S3 at a second time point when a predetermined time (hereinafter referred to as a first predetermined time) elapses, the first intermediate width value is between the first initial width value and a first target width value, and the first intermediate width value is changed by a first change amount from the first initial width value to approach a target width value (hereinafter referred to as a first target width value), and the processing circuit 12 determines whether the first intermediate width value reaches the first target width value after changing by a second change amount toward the first target width value.

If the determination is "no", it indicates that the changed first intermediate width value does not reach the first target width value, and therefore, after a predetermined time (hereinafter referred to as a second predetermined time) has elapsed from the second time point, the processing circuit 12 outputs another intermediate width value (hereinafter referred to as a second intermediate width value) as the pulse width signal S3 at a third time point, the second intermediate width value being between the first intermediate width value and the first target width value, and the second intermediate width value being the first intermediate width value and changing by the aforementioned second change amount to approach the first target width value. Accordingly, the processing circuit 12 may continuously output the pulse width signal S3 as the middle value of the width that does not reach the first width target value until the processing circuit 12 determines (i.e., determines yes) that the middle value of the width changes by a change amount to reach the first width target value, and the processing circuit 12 outputs the pulse width signal S3 as the first width target value at a time point after a predetermined time point after the middle value of the width is output last time.

Point in time	Pulse width	Remarks for note
			First point in time	25μs	First width initial value
Second point in time	24.5μs	Middle value of first width
			Third time point	24μs	Second width middle value
A fourth point in time	23.5μs	Other width intermediate values
			N time point	20.5μs	Other width intermediate values
Time point n +1	20μs	First width target value
			Time point n +2	20μs	First width target value

Watch 1

For example, as shown in the table (one), taking the first width initial value as 25 μ s, the first width target value as 20 μ s, the first variation as 0.5 μ s and the second variation as 0.5 μ s as an example, the processing circuit 12 outputs the first width initial value of 25 μ s at the first time point and outputs the first width intermediate value of 24.5 μ s at the second time point, and the processing circuit 12 determines that the first width intermediate value does not reach the first width target value, so the processing circuit 12 outputs the second width intermediate value of 24 μ s at the third time point, and when the processing circuit 12 determines that the width intermediate values do not reach the first width target value of 20 μ s, the processing circuit 12 changes the first width intermediate value output at the previous time point by 0.5 μ s at different time points and outputs the same, and gradually decreases the width intermediate values toward 20 μ s until the processing circuit 12 determines that the width intermediate value output at the nth time point and which is 20.5 μ s changes by 0.5 μ s is approximately 0.5 μ s By the first width target value, the processing circuit 12 outputs the first width target value of 20 μ s at the n +1 th time point, and may output the first width target value of 20 μ s at the n +2 th time point.

It should be noted that, in the foregoing embodiment, the first width target value is smaller than the first width initial value, so that the intermediate width values are in a decreasing relationship, but the disclosure is not limited thereto, and the first width target value may also be larger than the first width initial value according to different electronic devices or different operating powers of the electronic devices, so that the intermediate width values are in an increasing relationship.

According to each pulse width signal S3 output by the processing circuit 12, the pulse generating circuit 13 can generate a pulse signal S4 with a corresponding pulse width according to the output of the processing circuit 12 to generate a pulse signal S4 with different pulse widths. For example, the processing circuit 12 outputs the aforementioned first initial value of the width as the pulse width signal S3, the pulse generating circuit 13 generates a first pulse signal with a pulse width of 25 μ S, the processing circuit 12 outputs the aforementioned first intermediate value of the width as the pulse width signal S3, the pulse generating circuit 13 generates a second pulse signal with a pulse width of 24.5 μ S, the processing circuit 12 outputs the aforementioned second intermediate value of the width as the pulse width signal S3, the pulse generating circuit 13 generates a third pulse signal with a pulse width of 24 μ S, and so on until the processing circuit 12 outputs the aforementioned first target value of the width as the pulse width signal S3, and the pulse generating circuit 13 generates a fourth pulse signal with a pulse width of 20 μ S.

Accordingly, as shown in fig. 2, the pulse generating circuit 13 can generate the pulse signal S4 with decreasing or increasing pulse width, so that the electronic device can provide the operating power set by the user, and at the same time, the intensity of the single frequency emitted by the electronic device can be reduced, and the EMI effect can be reduced to meet the EMI standard specification. Furthermore, the pulse generating circuit 13 sends the pulse signal S4 with a variable width to a switching circuit implemented by an insulated gate bipolar transistor in the electronic device, so as to reduce the back voltage generated by the insulated gate bipolar transistor, so that the electronic device can operate at the maximum power.

In an embodiment, the pulse signal generator 1 further includes a timing circuit 14, and the timing circuit 14 is coupled between the trigger circuit 11 and the processing circuit 12. The timing circuit 14 receives the trigger signal S1 generated by the trigger circuit 11 to know that the ac power source passes through the zero crossing point, and the timing circuit 14 starts timing when receiving the trigger signal S1. Referring to fig. 3, the timing circuit 14 clocks two time intervals T1 and T2 (hereinafter referred to as a first time interval T1 and a second time interval T2, respectively) according to a preset design, in the first time interval T1, the processing circuit 12 outputs a pulse width signal S3 with a fixed pulse width value, for example, the processing circuit 12 continuously outputs the aforementioned first width initial value, so that the pulse generating circuit 13 generates a pulse signal S4 with a fixed pulse width of 25 μ S in the first time interval T1; in the second time interval T2, the processing circuit 12 starts outputting the pulse width signal S3 as the middle value of the width gradually changing from the first width initial value to the first width target value, so that the pulse generating circuit 13 generates the pulse signal S4 (i.e., the first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal) with variable width in the second time interval T2.

Accordingly, the timing circuit 14 sends the timing signal S2 to the processing circuit 12, so that the processing circuit 12 knows whether the ac power enters the second time interval T2 after passing through the zero crossing point, and the processing circuit 12 can know whether the first preset time and the second preset time have passed since the previous time point according to the timing signal S2, and the processing circuit 12 can output the initial width value, the intermediate width values, and the target width value at the corresponding time points (for example, the first time point to the n +2 time point) in the second time interval T2, as illustrated in the table (a). It should be noted that, according to the duration of the second time interval T2, the processing circuit 12 may output the first width target value at the last time point in the second time interval T2, or output any width intermediate value between the first width initial value and the first width target value that has not changed to the first width target value, and the pulse width output by the processing circuit 12 at the last time point in the second time interval T2 is hereinafter referred to as a first width end value.

Further, as shown in fig. 3, the timing circuit 14 further clocks a third time interval T3, the processing circuit 12 outputs a pulse width signal S3 according to the first width end value and a second width target value in the third time interval T3, that is, the processing circuit 12 can output width intermediate values gradually changing from the first width end value to the second width target value, and the second width target value is different from the first width target value. Specifically, the processing circuit 12 outputs a middle width value (hereinafter referred to as a third middle width value) of the first middle width value after the first end width value changes toward the second target width value by a third change amount at one time point (hereinafter referred to as a first time point) in the third time interval T3 according to the timing signal S2 as the pulse width signal S3, and the processing circuit 12 determines whether the middle width value changes toward the second target width value by a fourth change amount and reaches the second target width value. When the determination is "no", it indicates that the changed third intermediate width value does not reach the second target width value, and then, after a preset time (hereinafter referred to as a third preset time) has elapsed from the first time point in the third time interval T3 according to the timing signal S2, the processing circuit 12 outputs another intermediate width value (hereinafter referred to as a fourth intermediate width value) as the pulse width signal S3 at the second time point, the fourth intermediate width value is between the third intermediate width value and the second target width value, and the fourth intermediate width value is changed by the aforementioned fourth change amount for the third intermediate width value to approach the second target width value.

Accordingly, the processing circuit 12 may continuously output the pulse width signal S3 as the middle value of the width not reaching the second width target value until the processing circuit 12 determines (i.e., determines yes) that the middle value of the width changes by a change amount to reach the second width target value, and the processing circuit 12 outputs the pulse width signal S3 as the second width target value at a time point after a predetermined time has elapsed since the previous output of the middle value of the width.

Watch 2

For example, as shown in table (two), taking the third variation amount and the fourth variation amount as 0.5 μ s and the second width target value as 22.5 μ s as an example, the third width intermediate value output by the processing circuit 12 at the first time point is changed from the first width target value (i.e., 20 μ s) to 22.5 μ s by 0.5 μ s, the third width intermediate value is made to be 20.5 μ s, and the processing circuit 12 determines that the third width intermediate value has not reached the second width target value after changing to 22.5 μ s, so that the processing circuit 12 outputs the fourth width intermediate value of 21 μ s at the second time point, and when the processing circuit 12 determines that each width intermediate value has not reached the second width target value of 22.5 μ s, the processing circuit 12 changes the width intermediate value output at the previous time point by 0.5 μ s at each different time point and outputs the same, and gradually increases each width intermediate value toward 22.5 μ s, until the processing circuit 12 determines that the width median value output at the nth time point is changed by 0.5 μ s and reaches the second width target value, the processing circuit 12 outputs the second width target value at the nth +1 time point as 22.5 μ s and may output the second width target value at the nth +2 time point as 22.5 μ s.

It should be noted that, according to the duration of the third time interval T3, the processing circuit 12 may output the second width target value at the last time point in the third time interval T3, or output any width intermediate value between the first width end point value and the second width target value that has not changed to the second width target value, and the pulse width output by the processing circuit 12 at the last time point in the third time interval T3 is hereinafter referred to as the second width end point value.

Accordingly, the pulse generating circuit 13 may generate the pulse signal S4 having the corresponding pulse width signal S3 according to the pulse width signal S3 outputted by the processing circuit 12 in the third time interval T3. For example, the processing circuit 12 outputs the aforementioned third intermediate value of width as the pulse width signal S3, the pulse generating circuit 13 generates a fifth pulse signal with a pulse width of 20.5 μ S, the processing circuit 12 outputs the aforementioned fourth intermediate value of width as the pulse width signal S3, the pulse generating circuit 13 generates a sixth pulse signal with a pulse width of 21 μ S, and so on until the processing circuit 12 outputs the aforementioned second target value of width as the pulse width signal S3, and the pulse generating circuit 13 generates a seventh pulse signal with a pulse width of 22.5 μ S. It should be noted that, in the foregoing embodiment, the second width target value is greater than the first width target value, so that the intermediate width values are in an increasing relationship, but the disclosure is not limited thereto, and the second width target value may also be smaller than the first width target value according to different electronic devices or different operating powers of the electronic devices, so that the intermediate width values are in a decreasing relationship. As shown in fig. 4, the pulse generating circuit 13 may output the pulse signal S4 whose pulse width changes from decreasing to increasing, or output the pulse signal S4 whose pulse width changes from increasing to decreasing.

In one embodiment, the timing circuit 14 can perform the timing process for three time intervals T1, T2, and T3 by using three registers.

In an embodiment, the first preset time, the second preset time and the third preset time may be the same or different, and the processing circuit 12 may determine each preset time according to the operating power of the electronic device. For example, the first preset time, the second preset time and the third preset time may be three clock cycle times, or the first preset time and the first preset time are three clock cycle times and five clock cycle times, respectively, and the third preset time is two clock cycle times. Moreover, the first variation, the second variation, the third variation and the fourth variation may be the same or different, and the processing circuit 12 may determine each variation according to the operating power of the electronic device. For example, the first variation, the second variation, the third variation and the fourth variation are all 0.5 μ s, or the first variation and the second variation are respectively 0.5 μ s and 1.5 μ s, and the third variation and the fourth variation are respectively 1.5 μ s and 1 μ s.

In one embodiment, when the variation amounts of the pulse width signals S3 output by the processing circuit 12 at different time points are different, the difference between the variation amounts of the pulse width signals S3 output by the processing circuit 12 in the second time interval T2 and the difference between the variation amounts of the pulse width signals S3 output by the processing circuit 12 in the third time interval T3 are one of greater than zero and the other of less than zero. Taking the first variation, the second variation, the third variation and the fourth variation as an example, when the first variation, the second variation, the third variation and the fourth variation are different, a difference between the first variation and the second variation (hereinafter referred to as a first difference) and a difference between the third variation and the fourth variation (hereinafter referred to as a second difference) are one of the first variation and the second variation being greater than zero and the other being less than zero, for example, the first variation is greater than zero and the second variation is less than zero, or the first variation is less than zero and the second variation is greater than zero, and an absolute value of the first difference is equal to an absolute value of the second difference.

Watch (III)

For example, as shown in table (three), taking the first width target value and the second width target value as 102 μ S and 128 μ S, respectively, in the second time interval T2, the processing circuit 12 may output the pulse width signals S3 to the pulse generating circuit 13 in increments according to the variation amounts of 4 μ S, 5 μ S, 6 μ S, 7 μ S and 8 μ S, respectively, that is, the difference between the variation amounts in the second time interval T2 is +1 μ S; in the third time interval T3, the processing circuit 12 may output the pulse width signals S3 to the pulse generating circuit 13 in increments according to the variation amounts of 7 μ S, 6 μ S, 5 μ S and 4 μ S respectively, that is, the difference between the variation amounts in the third time interval T3 is-1 μ S and the absolute values of the difference values are equal to each other. Thus, as shown in fig. 5, the variation trend of each variation in the second time interval T2 (hereinafter referred to as a first variation trend) and the variation trend of each variation in the third time interval T3 (hereinafter referred to as a second variation trend) may present various curves, such as parabolas, and the first and second variation trends are one of increasing and the other of decreasing.

In one embodiment, as shown in fig. 3, the timing circuit 14 further clocks a fourth time interval T4 before the ac power source passes through the zero-crossing point, so as to generate the timing signal S2 to the processing circuit 12. The processing circuit 12 outputs the pulse width signal S3 with a fixed pulse width value in the fourth time interval T4, for example, the processing circuit 12 continuously outputs the second width target value of 22.5 μ S in the fourth time interval T4, or continuously outputs the second width end value of 21.5 μ S, for example, so that the pulse generating circuit 13 generates the pulse signal S4 with a fixed pulse width of 22.5 μ S or 21.5 μ S in the fourth time interval T4.

In one embodiment, the pulse signal generator 1 may be implemented by a Microcontroller (MCU), or the pulse signal generator 1 may be an Application Specific Integrated Circuit (ASIC), that is, the pulse signal generator 1 is designed and implemented as an integrated circuit chip in a hardware description language such as verilog language, so as to avoid the problem that dynamically adjusting the pulse width by software operation is limited by the priority of software processing, and avoid the problem that dynamically adjusting the pulse width under the limited resource condition of the microcontroller occupies most of the processing resources of the microcontroller, so that other requirements cannot be processed in time. Furthermore, the variation, the width initial value and the width target value can be stored in a storage circuit coupled to the processing circuit 12, and the processing circuit 12 can read the corresponding variation, width initial value and width target value from the storage circuit in real time according to the operating power of the electronic device, and send the variation, width initial value and width target value to the pulse generating circuit 13 to generate the corresponding pulse signal S4, so that the electronic device can provide the operating power set by the user.

In summary, according to an embodiment of the pulse signal generator of the present disclosure, the pulse generating circuit can generate a pulse signal with a decreasing or increasing pulse width to reduce the intensity of the single frequency emitted by the electronic device, so that the EMI influence is reduced to meet the EMI standard specification, and at the same time, the electronic device provides the operating power set by the user to heat the object. And the pulse generating circuit sends a pulse signal with variable width to a switching circuit which is realized by an insulated gate bipolar transistor in the electronic device, so that the back pressure generated by the insulated gate bipolar transistor can be reduced, and the electronic device can operate at the maximum power. Furthermore, the implementation with hardware circuits avoids the problem of being limited by software processing scheduling priority, thereby avoiding occupying most of the processing resources of the microcontroller.

Although the present disclosure has been described with reference to exemplary embodiments, it should be understood that various changes and modifications can be made without departing from the spirit and scope of the disclosure, and therefore the scope of the disclosure should be limited only by the appended claims.