阅读说明：本技术 振荡电路和锁相回路 (Oscillator circuit and phase-locked loop ) 是由 石田宇一 中村誉 于 2019-09-04 设计创作，主要内容包括：根据本公开的该振荡电路包括：电流源,其连接到连接节点并且能够使具有根据输入电压的电流值的电流从第一电源节点流到连接节点；振荡部,其设置在连接节点与第二电源节点之间的电流路径上,并且能够以根据流过电流路径的电流的振荡频率振荡；第一电容器,其设置在连接节点与第二电源节点之间,并且根据连接节点的电压改变电容值；以及设置部,其能够基于连接节点的电压执行用于改变连接节点与第二电源节点之间的阻抗的改变操作。(The oscillation circuit according to the present disclosure includes: a current source connected to the connection node and capable of causing a current having a current value according to the input voltage to flow from the first power supply node to the connection node; an oscillating portion that is provided on a current path between the connection node and the second power supply node, and is capable of oscillating at an oscillation frequency according to a current flowing through the current path; a first capacitor that is provided between the connection node and the second power supply node and changes a capacitance value according to a voltage of the connection node; and a setting section capable of performing a changing operation for changing an impedance between the connection node and the second power supply node based on a voltage of the connection node.)

1. An oscillating circuit comprising:

a current source coupled to a connection node, the current source configured to cause a current having a current value based on an input voltage to flow from a first power supply node to the connection node;

an oscillating section provided on a current path between the connection node and a second power supply node, the oscillating section configured to oscillate at an oscillation frequency based on a current flowing through the current path;

a first capacitor provided between the connection node and the second power supply node, the first capacitor having a capacitance that changes in accordance with a voltage at the connection node; and

a setting section configured to perform a changing operation based on a voltage at the connection node, the changing operation being an operation of changing an impedance between the connection node and the second power supply node.

2. The oscillation circuit of claim 1, further comprising:

a variable capacitance section provided between the connection node and the second power supply node, the variable capacitance section having a variable capacitance,

the setting section is configured to change the capacitance of the variable capacitance section to perform the changing operation.

3. The oscillation circuit according to claim 2, wherein the setting section is configured to make the capacitance of the variable capacitance section in a case where the voltage at the connection node is lower than a predetermined threshold value larger than the capacitance in a case where the voltage at the connection node is higher than the predetermined threshold value.

4. The oscillation circuit of claim 2, wherein,

the variable capacitance part includes two or more sub-circuits coupled in parallel with each other, each sub-circuit having one end coupled to the connection node and the other end coupled to the second power supply node,

the two or more sub-circuits each include a second capacitor and a switch coupled in series with each other, and

the setting section is configured to change the number of switches to be turned on among the switches in the two or more sub-circuits and thereby change the capacitance of the variable capacitance section.

5. The oscillation circuit of claim 1, further comprising:

a variable resistance section provided on the current path, the variable resistance section having a variable resistance, wherein,

the setting section is configured to change the resistance of the variable resistance section and thereby perform the changing operation.

6. The oscillation circuit according to claim 5, wherein the setting section changes the resistance of the variable resistance section, thereby changing a voltage at the connection node and changing a capacitance of the first capacitor.

7. The oscillation circuit according to claim 5, wherein the setting section is configured to make the resistance of the variable resistance section in a case where the voltage at the connection node is lower than a predetermined threshold value larger than the resistance in a case where the voltage at the connection node is higher than the predetermined threshold value.

8. The oscillation circuit according to claim 1, wherein the setting section is configured to perform the changing operation based on the voltage at the connection node in a first operation mode, and is configured not to perform the changing operation in a second operation mode.

9. The oscillation circuit of claim 1, wherein a capacitance of the first capacitor when the voltage at the connection node is a first voltage is greater than a capacitance of the first capacitor when the voltage at the connection node is a second voltage, the second voltage being lower than the first voltage.

10. The oscillation circuit according to claim 1, wherein the first capacitor has a MOS structure.

11. A phase locked loop comprising:

a phase comparison circuit configured to compare a phase of the first signal with a phase of the second signal based on the clock signal;

a loop filter configured to generate a control voltage based on a phase comparison result in the phase comparison circuit; and

an oscillation circuit configured to generate the clock signal based on the control voltage;

the oscillation circuit includes:

a current source coupled to a connection node, the current source configured to cause a current having a current value based on the control voltage to flow from a first power supply node to the connection node,

an oscillating section provided on a current path between the connection node and a second power supply node, the oscillating section configured to oscillate at an oscillation frequency based on a current flowing through the current path and thereby generate the clock signal;

a first capacitor provided between the connection node and the second power supply node, the first capacitor having a capacitance that changes in accordance with a voltage at the connection node; and

a setting section configured to perform a changing operation based on a voltage at the connection node, the changing operation being an operation of changing an impedance between the connection node and the second power supply node.

Technical Field

The present disclosure relates to an oscillation circuit and a phase locked loop including the same.

Background

The phase locked loop includes a phase comparison circuit, a loop filter, a voltage controlled oscillation circuit (VCO: voltage controlled oscillator), and the like. For example, patent document 1 discloses a PLL (phase locked loop) that changes the capacitance of a VCO decoupling capacitor provided in accordance with an operating frequency.

Reference list

Patent document

Patent document 1: japanese unexamined patent application publication (translation of PCT application) No. 2012-525105.

Disclosure of Invention

Incidentally, with respect to the electronic circuit, a high Power Supply Rejection Ratio (PSRR: Power Supply Rejection Ratio) is desired. It is also desirable for the oscillating circuit to have a high power supply rejection ratio.

It is desirable to provide an oscillation circuit and a phase-locked loop that make it possible to improve the power supply rejection ratio.

An oscillation circuit according to one embodiment of the present disclosure includes a current source, an oscillation section, a first capacitor, and a setting section. The current source is coupled to the connection node. The current source is configured to cause a current having a current value based on the input voltage to flow from the first power supply node to the connection node. The oscillating portion is provided on a current path between the connection node and the second power supply node. The oscillating portion is configured to oscillate at an oscillation frequency based on a current flowing through the current path. The first capacitor is disposed between the connection node and the second power supply node. The first capacitor has a capacitance that changes in accordance with a voltage at the connection node. The setting section is configured to perform a changing operation based on a voltage at the connection node. The changing operation is an operation of changing an impedance between the connection node and the second power supply node.

A phase-locked loop according to one embodiment of the present disclosure includes a phase comparison circuit, a loop filter, and an oscillation circuit. The phase comparison circuit is configured to compare a phase of the first signal with a phase of the second signal based on the clock signal. The loop filter is configured to generate a control voltage based on a phase comparison result in the phase comparison circuit. The oscillation circuit is configured to generate a clock signal based on the control voltage. The oscillation circuit includes a current source, an oscillation section, a first capacitor, and a setting section. The current source is coupled to the connection node. The current source is configured to cause a current having a current value based on the control voltage to flow from the first power supply node to the connection node. The oscillating portion is provided on a current path between the connection node and the second power supply node. The oscillating section is configured to oscillate at an oscillation frequency based on a current flowing through the current path and thereby generate a clock signal. The first capacitor is disposed between the connection node and the second power supply node. The first capacitor has a capacitance that changes in accordance with a voltage at the connection node. The setting section is configured to perform a changing operation based on a voltage at the connection node. The changing operation is an operation of changing an impedance between the connection node and the second power supply node.

In an oscillation circuit and a phase locked loop according to an embodiment of the present disclosure, a current having a current value based on an input voltage flows from a first power supply node to a connection node. The oscillating portion is provided on a current path between the connection node and the second power supply node. The oscillating portion oscillates at an oscillation frequency based on a current flowing through the current path. Further, the first capacitor is disposed between the connection node and the second power supply node. The first capacitor has a capacitance that changes in accordance with a voltage at the connection node. Further, the setting section performs a changing operation based on the voltage at the connection node. The changing operation is an operation of changing an impedance between the connection node and the second power supply node.

Drawings

Fig. 1 is a block diagram showing a configuration example of a phase locked loop according to an embodiment of the present disclosure.

Fig. 2 is a circuit diagram showing a configuration example of an oscillation circuit according to the first embodiment.

Fig. 3 is a circuit diagram showing a configuration example of the oscillating section shown in fig. 2.

Fig. 4 is a characteristic diagram showing a characteristic example of the capacitance of the capacitor shown in fig. 2.

Fig. 5 is a flowchart showing an operation example of the oscillation circuit shown in fig. 2.

Fig. 6 is a table describing an operation example of the oscillation circuit shown in fig. 2.

Fig. 7 is a circuit diagram showing a configuration example of an oscillation circuit of a modification of the first embodiment.

Fig. 8 is a circuit diagram showing a configuration example of an oscillation circuit of another modification of the first embodiment.

Fig. 9 is a circuit diagram showing a configuration example of an oscillation circuit of another modification of the first embodiment.

Fig. 10 is a table describing an operation example of the oscillation circuit shown in fig. 9.

Fig. 11 is a circuit diagram showing a configuration example of an oscillation circuit according to another modification of the first embodiment.

Fig. 12 is a block diagram showing a configuration example of a phase locked loop according to another modification of the first embodiment.

Fig. 13 is a circuit diagram showing a configuration example of the oscillation circuit shown in fig. 12.

Fig. 14 is a circuit diagram showing a configuration example of an oscillation circuit according to the second embodiment.

Fig. 15 is a flowchart showing an operation example of the oscillation circuit shown in fig. 14.

Fig. 16 is a table describing an operation example of the oscillation circuit shown in fig. 14.

Fig. 17 is a table describing an operation example of an oscillation circuit according to another modification of the second embodiment.

Detailed Description

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Note that the description is given in the following order.

1. First embodiment

2. Second embodiment

<1. first embodiment >

[ configuration example ]

Fig. 1 shows a configuration example of a phase locked loop (phase locked loop 1) including an oscillation circuit according to an embodiment. The phase locked loop 1 is configured to generate a clock signal CLK having a frequency higher than that of the clock signal CLK1, for example, based on the clock signal CLK 1. The phase locked loop 1 is provided on a single semiconductor chip, for example.

The phase locked loop 1 includes a phase comparison circuit 11, a charge pump 12, a loop filter 13, an oscillation circuit 20, a frequency dividing circuit 14, and a lock detection circuit 15. Each signal in the phase locked loop 1 may be a single-ended signal or a differential signal.

The phase comparison circuit 11 is configured to compare the phase of the clock signal CLKl with the phase of the clock signal CLK2 supplied from the frequency division circuit 14 to generate signals UP and DN based on the comparison result. The Phase comparison circuit 11 includes, for example, a so-called Phase Frequency Detector (PFD; Phase Frequency Detector).

The charge pump 12 is configured to flow current into the loop filter 13 or sink current from the loop filter 13 based on the signals UP and DN.

The loop filter 13 is configured to generate the control voltage Vctrl based on the current supplied from the charge pump 12.

The oscillation circuit 20 is a voltage-controlled oscillator (VCO; voltage-controlled oscillator) and is configured to generate a clock signal CLK having a frequency based on a control voltage Vctrl based on the control voltage Vctrl.

The frequency dividing circuit 14 is configured to divide the frequency of the clock signal CLK based on the clock signal CLK to generate the clock signal CLK 2. The division ratio in the division circuit 14 may be an integer or a non-integer.

The lock detection circuit 15 is configured to detect whether phase synchronization is established in the phase locked loop 1 based on the signals UP and DN. Specifically, in the case where the phase of the clock signal CLK1 and the phase of the clock signal CLK2 are synchronized with each other, the lock detection circuit 15 detects the establishment of phase synchronization. Further, the lock detection circuit 15 supplies a signal DET indicating the detection result to the oscillation circuit 20. Note that, in this example, the lock detection circuit 15 is configured to operate based on the signals UP and DN. However, this is not limiting. Alternatively, for example, the lock detection circuit 15 may operate based on the clock signals CLK1 and CLK 2.

(oscillation circuit 20)

Fig. 2 shows a configuration example of the oscillation circuit 20. The oscillation circuit 20 includes a transistor 21, an oscillation section 30, a capacitor 22, a variable capacitance section 23, and a capacitance setting section 24.

The transistor 21 is a P-type MOS (metal oxide semiconductor) transistor. The transistor 21 has a source receiving the power supply voltage VDD, a gate receiving the control voltage Vctrl, and a drain coupled to the connection node ND. The transistor 21 functions as a current source that generates a current Iosc having a current value based on the control voltage Vctrl. The current Iosc flows into the oscillating unit 30 via the connection node ND. Therefore, the voltage Vtail is generated at the connection node ND.

The oscillating section 30 is provided on a path between the connection node ND and the ground. The oscillating section 30 is configured to oscillate at an oscillation frequency fosc based on the current Iosc flowing through the path, and thereby generate the clock signal CLK. In this example, the clock signal CLK is a differential signal.

Fig. 3 shows a configuration example of the oscillating portion 30. The oscillating section 30 is a differential ring oscillator. The clock signal CLK includes clock signals CLKP and CLKN that constitute a differential signal. The oscillation section 30 outputs a clock signal CLKP from a terminal TP, and outputs a clock signal CLKN from a terminal TN. The oscillating section 30 includes inverters 31P, 32P, 33P, 31N, 32N, 33N, and 41 to 46. These inverters are each a so-called CMOS (complementary metal oxide semiconductor) inverter including a P-type MOS transistor and an N-type MOS transistor.

The input terminal of inverter 31P is coupled to terminal TP and to the output terminal of inverter 33P. The output terminal of the inverter 31P is coupled to the input terminal of the inverter 32P. An input terminal of the inverter 32P is coupled to an output terminal of the inverter 31P, and an output terminal of the inverter 32P is coupled to an input terminal of the inverter 33P. An input terminal of inverter 33P is coupled to an output terminal of inverter 32P, and an output terminal of inverter 33P is coupled to terminal TP and to an input terminal of inverter 31P.

The input terminal of the inverter 31N is coupled to the terminal TN and to the output terminal of the inverter 33N. The output terminal of the inverter 31N is coupled to the input terminal of the inverter 32N. An input terminal of the inverter 32N is coupled to an output terminal of the inverter 31N, and an output terminal of the inverter 32N is coupled to an input terminal of the inverter 33N. An input terminal of the inverter 33N is coupled to an output terminal of the inverter 32N, and an output terminal of the inverter 33N is coupled to the TN terminal and to an input terminal of the inverter 31N.

An input terminal of the inverter 41 is coupled to the output terminal of the inverter 31P and the input terminal of the inverter 32P, and an output terminal of the inverter 41 is coupled to the output terminal of the inverter 31N and the input terminal of the inverter 32N. An input terminal of the inverter 42 is coupled to the output terminal of the inverter 31N and the input terminal of the inverter 32N, and an output terminal of the inverter 42 is coupled to the output terminal of the inverter 31P and the input terminal of the inverter 32P. An input terminal of the inverter 43 is coupled to the output terminal of the inverter 32P and the input terminal of the inverter 33P, and an output terminal of the inverter 43 is coupled to the output terminal of the inverter 32N and the input terminal of the inverter 33N. An input terminal of the inverter 44 is coupled to the output terminal of the inverter 32N and the input terminal of the inverter 33N, and an output terminal of the inverter 44 is coupled to the output terminal of the inverter 32P and the input terminal of the inverter 33P. An input terminal of the inverter 45 is coupled to the output terminal of the inverter 33P and the input terminal of the inverter 31P, and an output terminal of the inverter 45 is coupled to the output terminal of the inverter 33N and the input terminal of the inverter 31N. An input terminal of the inverter 46 is coupled to the output terminal of the inverter 33N and the input terminal of the inverter 31N, and an output terminal of the inverter 46 is coupled to the output terminal of the inverter 33P and the input terminal of the inverter 31P.

In this example, a ring oscillator is configured using three-stage inverters (inverters 31P and 31N, inverters 32P and 32N, and inverters 33P and 33N). However, this is not limiting. Alternatively, for example, a five-stage inverter or a seven-stage inverter may be used.

The power supply terminals of the inverters 31P, 32P, 33P, 31N, 32N, 33N, and 41 to 46 are coupled to each other and to the connection node ND (fig. 2). Therefore, a current Iosc generated by the transistor 21 flows as a power supply current of these inverters. Therefore, for example, the delay times of the inverters 31P, 32P, 33P, 31N, 32N, and 33N are changed according to the current Iosc. Specifically, when the current Iosc is small, the delay time becomes long, and when the current Iosc is large, the delay time becomes short. Therefore, when the current Iosc is small, the oscillation frequency fosc becomes low, and when the current Iosc is large, the oscillation frequency fosc becomes high. Therefore, the oscillating section 30 functions as a so-called current-controlled oscillating circuit having an oscillating frequency fosc that changes based on the current Iosc.

The capacitor 22 (fig. 2) serves as a decoupling capacitor of the oscillating portion 30. One end of the capacitor 22 is coupled to the connection node ND, and the other end is grounded. The capacitor 22 includes a so-called MOS capacitor having a MOS structure. The capacitance per unit area of the MOS capacitor is larger than that of a capacitor having an MIM (metal insulator metal) structure, for example. In the oscillation circuit 20, such use of the MOS capacitor makes it possible to suppress the circuit area.

The variable capacitance section 23 (fig. 2) is configured to have a capacitance that is variable based on the control signals S1 to S3. The variable capacitance section 23 includes switches SW1 to SW3 and capacitors CAP1 to CAP 3. The switches SW1 to SW3 include MOS transistors, for example. The capacitors CAP1 to CAP3 include, for example, MOS capacitors. The capacitors CAP1 to CAP3 have the same capacitance, for example.

One terminal of the switch SW1 is coupled to the connection node ND, and the other terminal is coupled to one terminal of the capacitor CAP 1. The switch SW1 is turned on and off based on the control signal S1. One terminal of the capacitor CAP1 is coupled to the other terminal of the switch SWl, and the other terminal is grounded. One terminal of the switch SW2 is coupled to the connection node ND, and the other terminal is coupled to one terminal of the capacitor CAP 2. The switch SW2 is turned on and off based on the control signal S2. One terminal of the capacitor CAP2 is coupled to the other terminal of the switch SW2, and the other terminal is grounded. One terminal of the switch SW3 is coupled to the connection node ND, and the other terminal is coupled to one terminal of the capacitor CAP 3. The switch SW3 is turned on and off based on the control signal S3. One terminal of the capacitor CAP3 is coupled to the other terminal of the switch SW3, and the other terminal is grounded.

With this configuration, in the variable capacitance section 23, the number of switches turned on in the switches SW1 to SW3 is changed based on the control signals S1 to S3. Accordingly, the variable capacitance section 23 is configured to change the capacitance based on the control signals S1 to S3. Note that, in this example, three switches SW1 to SW3 are provided. However, this is not limiting. Alternatively, two switches may be provided, or four or more switches may be provided.

Capacitance setting section 24 is configured to set the capacitance of variable capacitance section 23 based on voltage Vtail. The capacitance setting section 24 includes an AD (analog-to-digital) converter 25 and a switch controller 26. The AD converter 25 is configured to convert the voltage Vtail into an N-bit digital code. The switch controller 26 is configured to generate the control signals S1 to S3 based on the digital code supplied from the AD converter 25 and the signal DET supplied from the lock detection circuit 15. Specifically, the switch controller 26 generates the control signals S1 to S3 such that the lower the voltage Vtail, the greater the number of switches SW1 to SW3 that are turned on. Accordingly, as voltage Vtail is lower, capacitance providing unit 24 increases the capacitance of variable capacitance unit 23. The switch controller 26 holds, for example, table information indicating the correspondence between the digital codes and the control signals S1 to S3. The switch controller 26 generates the control signals S1 to S3 based on the voltage Vtail using the table information.

With this configuration, in the oscillation circuit 20, in the case where the voltage Vtail is low, the capacitance of the variable capacitance section 23 increases. By increasing the capacitance of the variable capacitance section 23 in this way, the impedance between the connection node ND and the ground in the oscillation circuit 20 can be reduced. Therefore, in the oscillation circuit 20, the power supply rejection ratio can be improved as described below.

Here, the transistor 21 corresponds to one specific example of the "current source" of the present disclosure. The oscillating portion 30 corresponds to one specific example of "oscillating portion" of the present disclosure. The capacitor 22 corresponds to one specific example of "first capacitor" of the present disclosure. The capacitance setting section 24 corresponds to one specific example of "setting section" of the present disclosure. The connection node ND corresponds to one specific example of "connection node" of the present disclosure. The node receiving the power supply voltage VDD corresponds to one specific example of the "first power supply node" of the present disclosure. The ground node corresponds to one specific example of the "second power supply node" of the present disclosure. The variable capacitance section 23 corresponds to one specific example of "variable capacitance section" of the present disclosure.

[ operation and working ]

Subsequently, the operation and working of the phase locked loop 1 according to the present embodiment are described.

(overview of the Integrated operation)

First, referring to fig. 1, an overview of the overall operation of the phase locked loop 1 is described. The phase comparison circuit 11 compares the phase of the clock signal CLK1 with the phase of the clock signal CLK2 supplied from the frequency division circuit 14, and generates signals UP and DN according to the comparison result. The charge pump 12 flows current into the loop filter 13 or sinks current from the loop filter 13 based on the signals UP and DN. The loop filter 13 generates a control voltage Vctrl based on the current supplied from the charge pump 12. The oscillation circuit 20 generates a clock signal CLK having a frequency based on the control voltage Vctrl. The frequency dividing circuit 14 divides the frequency of the clock signal CLK based on the clock signal CLK to generate the clock signal CLK 2. The lock detection circuit 15 detects whether phase synchronization is established in the phase locked loop 1 based on the signals UP and DN.

(detailed operation)

The oscillation circuit 20 generates a clock signal CLK having a frequency based on the control voltage Vctrl. As shown in fig. 2, the oscillation circuit 20 is provided with a capacitor 22 as a decoupling capacitor, and thereby the power supply rejection ratio is improved.

Incidentally, in the oscillation circuit 20, the capacitor 22 includes a MOS capacitor. The capacitance of the MOS capacitor is voltage dependent.

Fig. 4 shows an example of the capacitance of the capacitor 22. In fig. 4, the horizontal axis indicates the voltage Vtail, and the vertical axis indicates the capacitance of the capacitor 22. Since the capacitor 22 is a MOS capacitor, the capacitance may be changed according to a voltage difference between the two terminals. Therefore, the capacitance of the capacitor 22 can be changed according to the voltage Vtail. As shown in fig. 4, in this example, in the case where the voltage Vtail is high, the capacitance is high, and in the case where the voltage Vtail is low, the capacitance is low.

As described above, the current Iosc generated by the transistor 21 flows into the oscillating unit 30. Therefore, the voltage Vtail is generated at the connection node ND. For example, when the current Iosc is small, the voltage Vtail is low, and when the current Iosc is large, the voltage Vtail is high. In other words, in case the oscillation frequency fosc is low, the voltage Vtail is low, whereas in case the oscillation frequency fosc is high, the voltage Vtail is high. Therefore, the capacitance of the capacitor 22 can be changed according to the oscillation frequency fosc.

Further, the voltage Vtail may change due to, for example, process variations in a semiconductor manufacturing process. Further, the voltage Vtail may be changed due to a power supply voltage variation and a temperature variation when the phase locked loop 1 is operated. Accordingly, the capacitance of the capacitor 22 may change due to process variations, power supply voltage variations, temperature variations, and the like.

Therefore, the voltage Vtail varies depending on various factors. Therefore, the capacitance of the capacitor 22 also changes depending on various factors. For example, in the case where the capacitance of the capacitor 22 decreases, the impedance between the connection node ND and the ground increases. Therefore, the power supply rejection rate can be reduced. For example, in the case where the power supply rejection rate is low, the power supply voltage fluctuates. Therefore, there is a possibility that the phase noise of the clock signal CLK generated by the oscillation section 30 is deteriorated.

Therefore, in the oscillation circuit 20, when the voltage Vtail is low, the capacitance of the variable capacitance section 23 increases. By increasing the capacitance of variable capacitance section 23 in this way, the impedance between connection node ND and ground in oscillation circuit 20 is reduced. Therefore, in the oscillation circuit 20, the power supply rejection ratio can be improved.

Next, the setting of the capacitance of the variable capacitance section 23 is described in detail.

Fig. 5 shows an example of an operation of setting the capacitance of the variable capacitance section 23. The capacitance setting section 24 changes the capacitance of the variable capacitance section 23 based on the voltage Vtail at the connection node ND. In this example, in the initial state, all of the switches SW1 to SW3 are in the off state. This operation is described in detail below.

First, the switch controller 26 confirms whether phase synchronization is established in the phase-locked loop 1 based on the signal DET supplied from the lock detection circuit 15 (step S101). In the case where phase synchronization is not established (no in step S101), step S101 is repeated until phase synchronization is established. The phase locked loop 1 performs a closed loop operation. Thus, phase synchronization is established after a period of time has elapsed.

In the case where phase synchronization is established in step S101 (yes in step S101), the switch controller 26 confirms whether the voltage Vtail is lower than the predetermined voltage Vth based on the digital code supplied from the AD converter 25 (step S102). In the case where voltage Vtail is not lower than predetermined voltage Vth (no in step 102), the flow ends.

In the case where the voltage Vtail is lower than the predetermined voltage Vth in step S102 (yes in step S102), the switch controller 26 sets the on-off states of the switches SW1 to SW3 according to the voltage Vtail (step S103).

Fig. 6 shows an example of the setting operation in the switch controller 26. In the case where the voltage Vtail is equal to or higher than the predetermined voltage V1 and lower than the predetermined voltage Vth, the switch controller 26 turns on the switch SW1 and turns off the switches SW2 and SW 3. Further, in the case where the voltage Vtail is equal to or higher than the predetermined voltage V2 and lower than the predetermined voltage V1, the switch controller 26 turns on the switches SW1 and SW2 and turns off the switch SW 3. Further, in the case where the voltage Vtail is lower than the predetermined voltage V2, the switch controller 26 turns on the switches SW1 to SW 3. Therefore, the lower the voltage Vtail, the more the switch controller 26 increases the number of switches to be turned on among the switches SW1 to SW 3. Therefore, the switch controller 26 increases the capacitance of the variable capacitance section 23 as the voltage Vtail is lower. Therefore, in the oscillation circuit 20, even if the voltage Vtail is reduced, the capacitance between the connection node ND and the ground can be prevented from being excessively small. In other words, even if the voltage Vtail changes, the capacitance between the connection node ND and the ground can be prevented from changing greatly.

Next, the switch controller 26 confirms whether or not phase synchronization is maintained based on the signal DET supplied from the lock detection circuit 15 (step S104). If the phase synchronization is maintained (yes in step S104), the flow ends.

In the case where the phase synchronization is not maintained in step S104 (no in step S104), the switch controller 26 confirms whether the phase synchronization is established based on the signal DET supplied from the lock detection circuit 15 (step S105). In the case where phase synchronization is not established (no in step S105), this step S105 is repeated until phase synchronization is established. That is, in the case where the phase synchronization is not maintained in step S104, the phase synchronization is not established. Thus, waiting until phase synchronization is established. Since the phase locked loop 1 performs a closed loop operation, phase synchronization is established after a period of time has elapsed. Further, in the case where the phase synchronization is established (yes in step S105), the flow ends.

As described above, in the phase locked loop 1, the impedance between the connection node ND and the ground changes based on the voltage Vtail at the connection node ND. Specifically, in the phase locked loop 1, the capacitance of the variable capacitance section 23 changes in accordance with the voltage Vtail. Therefore, in the phase locked loop 1, even if the voltage Vtail is reduced, the capacitance between the connection node ND and the ground can be prevented from being excessively small. Therefore, with the phase locked loop 1, the power supply rejection ratio can be improved.

In the phase locked loop 1, the capacitance of the variable capacitance section 23 changes according to the voltage Vtail. In the case where the capacitance of the variable capacitance section 23 is thus changed, the DC operating point before the change is substantially the same as the DC operating point after the change. Therefore, by changing the capacitance of the variable capacitance section 23, the possibility of the phase synchronization entering an unstable state can be reduced. Therefore, in the phase locked loop 1, when the power supply rejection ratio is increased, the possibility that the phase synchronization enters an unstable state can be reduced.

Further, in the phase locked loop 1, the capacitance of the variable capacitance section 23 is thus changed according to the voltage Vtail. Therefore, even if the voltage Vtail changes, the capacitance between the connection node ND and the ground can be prevented from changing greatly. Therefore, even if the decoupling capacitor affects the loop transfer function of the phase locked loop 1, the possibility that the influence on the loop transfer function is largely changed can be reduced. Therefore, in the phase locked loop 1, the possibility of changing the loop response characteristic of the phase locked loop 1 can be reduced.

[ Effect ]

As described above, according to the present embodiment, the impedance between the connection node and the ground is changed based on the voltage at the connection node. Therefore, the power supply rejection ratio can be improved.

According to the present embodiment, the capacitance of the variable capacitance section changes according to the voltage Vtail. Thus, the DC operating point is allowed to be maintained. Therefore, when the power supply rejection ratio is increased, the possibility that the phase synchronization enters an unstable state can be reduced.

According to the present embodiment, the capacitance of the variable capacitance section changes according to the voltage Vtail. Therefore, the range of possible values of the capacitance between the connection node and the ground is allowed to be narrowed. Therefore, the possibility of a change in the loop response characteristic of the phase locked loop can be reduced.

[ modification 1-1]

In the above-described embodiment, as shown in fig. 2, for example, the capacitor CAP1 is provided between the switch SW1 and the ground. However, this is not limiting. Alternatively, for example, as in the oscillation circuit 20A shown in fig. 7, the setting position of the capacitor CAP1 and the setting position of the switch SW1 may be interchanged. The oscillation circuit 20A includes a variable capacitance section 23A. In the variable capacitance section 23A, one end of the capacitor CAP1 is coupled to the connection node ND, and the other end is coupled to one end of the switch SW 1. One terminal of the switch SW1 is coupled to the other terminal of the capacitor CAP1, and the other terminal is grounded. This similarly applies to capacitor CAP2 and switch SW 2. This similarly applies to capacitor CAP3 and switch SW 3.

In the configuration shown in fig. 7, for example, with the switch SW1 open, the other end of the capacitor CAP1 is in a floating state. Therefore, there is a possibility that an unexpected malfunction occurs. Therefore, as in the oscillation circuit 20B shown in fig. 8, it can be configured to avoid such a floating state. The oscillation circuit 20B includes a variable capacitance section 23B. The variable capacitance section 23B includes inverters IV1 to IV3, switches SW11 to SW13, and an Operational Amplifier (OPA). The inverter IV1 inverts the control signal S1 to generate the control signal S11. The inverter IV2 inverts the control signal S2 to generate the control signal S12. The inverter IV3 inverts the control signal S3 to generate the control signal S13. One terminal of the switch SW1l is coupled to the other terminal of the capacitor CAP1 and one terminal of the switch SW 1. The other end of the switch SW11 is coupled to the negative input terminal and the output terminal of the operational amplifier OPA. The switch SW11 is turned on and off based on the control signal S11. One terminal of the switch SW12 is coupled to the other terminal of the capacitor CAP2 and one terminal of the switch SW 2. The other end of the switch SW12 is coupled to the negative input terminal and the output terminal of the operational amplifier OPA. The switch SW12 is turned on and off based on the control signal S12. One terminal of the switch SW13 is coupled to the other terminal of the capacitor CAP3 and one terminal of the switch SW 3. The other end of the switch SW13 is coupled to the negative input terminal and the output terminal of the operational amplifier OPA. The switch SW13 is turned on and off based on the control signal S13. The positive input terminal of the operational amplifier OPA is coupled to the connection node ND, the negative input terminal of the operational amplifier OPA is coupled to the output terminal of the operational amplifier OPA and the other ends of the switches SW11 to SW13, and the output terminal of the operational amplifier OPA is coupled to the negative input terminal of the operational amplifier OPA and the other ends of the switches SW11 to SW 13. The operational amplifier OPA functions as a so-called voltage follower, thereby setting the voltage at the other ends of the switches SW11 to SW13 to substantially the same voltage as the voltage Vtail. For example, in the case where the switch SW1 is off, the switch SW11 is on. Therefore, the other end of the capacitor CAP1 receives substantially the same voltage as the voltage Vtail. In this way, for example, in the oscillation circuit 20B, even in the case where the switch SW1 is turned off, the other end of the capacitor CAP1 can be prevented from being in a floating state.

[ modifications 1-2]

According to the above-described embodiment, as shown in fig. 2, the variable capacitance section 23 includes the plurality of capacitors CAP1 to CAP3 having the same capacitance as each other. However, this is not limiting. Alternatively, as in the oscillation circuit 20C shown in fig. 9, the variable capacitance section may include a plurality of capacitors having different capacitances from each other. The oscillation circuit 20C includes a variable capacitance section 23C and a capacitance setting section 24C.

The variable capacitance section 23C includes switches SW1 and SW2 and capacitors CAP1 and CAP 2. In this example, the capacitance of the capacitor CAP2 is twice the capacitance of the capacitor CAP 1. That is, the capacitances of the capacitors CAP1 and CAP2 are weighted. One terminal of the switch SW1 is coupled to the connection node ND, and the other terminal is coupled to one terminal of the capacitor CAP 1. One terminal of the capacitor CAP1 is coupled to the other terminal of the switch SW1, and the other terminal is grounded. One terminal of the switch SW2 is coupled to the connection node ND, and the other terminal is coupled to one terminal of the capacitor CAP 2. One terminal of the capacitor CAP2 is coupled to the other terminal of the switch SW2, and the other terminal is grounded.

Capacitance setting section 24C includes a switch controller 26C. The switch controller 26C is configured to generate the control signals S1 and S2 based on the digital code supplied from the AD converter 25 and the signal DET supplied from the lock detection circuit 15. Specifically, as shown in fig. 10, in the case where the voltage Vtail is equal to or higher than the predetermined voltage Vl and lower than the predetermined voltage Vth, the switch controller 26C turns on the switch SW1 and turns off the switch SW 2. Further, in the case where the voltage Vtail is equal to or higher than the predetermined voltage V2 and lower than the predetermined voltage V1, the switch controller 26C turns off the switch SW1 and turns on the switch SW 2. Further, in the case where the voltage Vtail is lower than the predetermined voltage V2, the switch controller 26C turns on the switches SW1 and SW 2. Thus, the switch controller 26C is allowed to increase the capacitance of the variable capacitance section 23C as the voltage Vtail is lower.

[ modifications 1 to 3]

According to the above-described embodiment, as shown in fig. 2, the transistor 21 is configured to generate the current Iosc based on the control voltage Vctrl. However, this is not limiting. Alternatively, for example, as in the oscillation circuit 20D shown in fig. 11, the current Iosc may be generated based on the control voltage Vctrl using a circuit configuration different from the above-described embodiment. The oscillation circuit 20D includes an operational amplifier 51D, a transistor 52D, and a resistor 53D. The negative input terminal of the operational amplifier 51D receives the control voltage Vctrl. The positive input terminal of the operational amplifier 51D is coupled to the drain of the transistor 52D and one end of the resistor 53D. The output terminal of the operational amplifier 51D is coupled to the gates of the transistors 21 and 52D. The transistor 52D is a P-type MOS transistor. A source of transistor 52D receives the supply voltage VDD. A gate of the transistor 52D is coupled to the output terminal of the operational amplifier 51D and the gate of the transistor 21. The drain of the transistor 52D is coupled to the positive input terminal of the operational amplifier 51D and one end of the resistor 53D. One end of the resistor 53D is coupled to the positive input terminal of the operational amplifier 51D and the drain of the transistor 52D. The other end of the resistor 53D is grounded. A gate of the transistor 21 is coupled to the output terminal of the operational amplifier 51D and the gate of the transistor 52D. In this example, the gate length of the transistor 52D is the same as the gate length of the transistor 21. The gate width of the transistor 52D is the same as the gate width of the transistor 21. Thus, the transistors 52D and 21 provide a so-called current mirror circuit. Here, the operational amplifier 51D, the transistor 52D, the resistor 53D, and the transistor 21 correspond to one specific example of the "current source" of the present disclosure. With this configuration, the voltage of one end of the resistor 53D becomes substantially the same voltage as the control voltage Vctrl. Therefore, a current having substantially the same current value as a value obtained by dividing the control voltage Vctrl by the resistance of the resistor 53D flows into the transistor 52D. Therefore, a current Iosc having a current value substantially equal to the current value flowing through the transistor 52D flows into the transistor 21. In this way, the oscillation circuit 20D generates the current Iosc based on the control voltage Vctrl.

[ modifications 1 to 4]

According to the above-described embodiment, the impedance between the connection node ND and the ground changes based on the voltage at the connection node ND. For example, in the case of the first operation mode, the impedance between the connection node ND and the ground may be changed based on the voltage at the connection node ND, and in the case of the second operation mode, the impedance may not be changed based on the voltage at the connection node ND. Hereinafter, the present modification is described in detail.

Fig. 12 shows a configuration example of a phase locked loop 1E according to the present modification. The phase locked loop 1E includes an operating frequency setting section 19E, a frequency dividing circuit 14E, and an oscillation circuit 20E.

The operating frequency setting section 19E is configured to set the frequency of the clock signal CLK. The frequency of the clock signal CLK is set according to the application to which the phase locked loop 1E is applied. Further, the operation frequency setting section 19E generates control signals SET1, SET2 based on the SET frequency. The operating frequency setting section 19E supplies the control signal SET1 to the frequency dividing circuit 14E, and supplies the control signal SET2 to the oscillation circuit 20E.

The frequency dividing circuit 14E SETs the frequency dividing ratio based on the control signal SET 1. The frequency dividing circuit 14E is configured to divide the frequency of the clock signal CLK at the set frequency division ratio, and thereby generate the clock signal CLK 2. For example, in the case where the frequency of the clock signal CLK is to be increased, the frequency dividing ratio is set to a large value, and in the case where the frequency of the clock signal CLK is to be decreased, the frequency dividing ratio is set to a small value.

Fig. 13 shows a configuration example of the oscillation circuit 20E. The oscillation circuit 20E includes an oscillation frequency setting section 59E, a variable resistor 53E, a current mirror circuit 54E, and a capacitance setting section 24E.

The oscillation frequency setting section 59E is configured to supply a control signal to the variable resistor 53E, the current mirror circuit 54E, and the capacitance setting section 24E based on the control signal SET 2.

The variable resistor 53E is configured to have a resistance that is variable based on a control signal supplied from the oscillation frequency setting section 59E. One end of the variable resistor 53E is coupled to the positive input terminal of the operational amplifier 51D and the drain of the transistor 52D in the current mirror circuit 54E. The other end of the variable resistor 53E is grounded. The resistance is set to a small value in the case where the frequency of the clock signal CLK is to be increased, and is set to a small value in the case where the frequency of the clock signal CLK is to be decreased.

The current mirror circuit 54E includes a plurality of transistors 52D and a plurality of transistors 21. Based on the control signal supplied from the oscillation frequency setting section 59E, while maintaining the current mirror ratio, the current mirror circuit 54E is configured to change the number of transistors 52D used in the plurality of transistors 52D and change the number of transistors 21 used in the plurality of transistors 21. For example, in the case where the frequency of the clock signal CLK is to be increased, the number of transistors 52D used and the number of transistors 21 used are increased, and in the case where the frequency of the clock signal CLK is to be decreased, the number of transistors 52D used and the number of transistors 21 used are decreased.

Capacitance setting section 24E includes a switch controller 26E. The switch controller 26E determines whether to change the capacitance of the variable capacitance section 23 based on the control signal supplied from the oscillation frequency setting section 59E. For example, in the case where the frequency of the clock signal CLK is to be made higher than the predetermined threshold frequency fth, as in the case of the first embodiment described above, the switch controller 26E generates the control signals S1 to S3 based on the digital code supplied from the AD converter 25 and the signal DET supplied from the lock detection circuit 15. Further, for example, in the case where the frequency of the clock signal CLK is to be made lower than the predetermined threshold frequency fth, the capacitance of the variable capacitance section 23 is not changed, and the off-states of the switches SW1 to SW3 are maintained.

Here, the operation mode in which the frequency of the clock signal CLK is made higher than the predetermined threshold frequency fth corresponds to one specific example of the "first operation mode" of the present disclosure. The operation mode in which the frequency of the clock signal CLK is made lower than the predetermined threshold frequency fth corresponds to one specific example of the "second operation mode" of the present disclosure.

Therefore, in the phase-locked loop 1E, as in the above-described embodiment, in the case where the frequency of the clock signal CLK is to be made higher than the predetermined threshold frequency fth, the capacitance of the variable capacitance section 23 is changed based on the voltage at the connection node ND. Therefore, for example, also in the case where the capacitance of the capacitor 22 is changed due to setting of the frequency of the clock signal CLK, process variation, power supply voltage variation, temperature variation, or the like, it is allowed to keep the impedance between the connection node ND and the ground at a low value. Therefore, the power supply rejection ratio can be improved.

Further, in the phase-locked loop 1E, in the case where the frequency of the clock signal CLK is to be made lower than the predetermined threshold frequency fth, the loop response characteristic of the phase-locked loop 1E can be stabilized. That is, in the case where the frequency of the clock signal CLK is to be lowered, since the resistance of the variable resistor 53E is increased, the current Iosc is lowered. Therefore, the oscillation frequency fosc in the oscillation section 30 can be reduced. However, in the case where the current Iosc is small in this way, the voltage Vtail at the connection node ND is low. Therefore, as in the case of the above-described embodiment, in the case where the capacitance of the variable capacitance section 23 is increased in accordance with the voltage Vtail, there is a possibility that the capacitance between the connection node ND and the ground becomes excessively large. In this case, the capacitance greatly affects the loop response characteristic of the phase locked loop 1, and there is a possibility that the stability of the loop response characteristic is lowered. Therefore, in the phase locked loop 1E, in the case where the frequency of the clock signal CLK is to be made lower than the predetermined threshold frequency fth, the capacitance of the variable capacitance section 23 is not changed. This makes the capacitance between the connection node ND and ground low. This reduces the influence on the loop response characteristic of the phase locked loop 1. Therefore, the loop response characteristic of the phase locked loop 1 can be stabilized.

[ other modifications ]

Furthermore, two or more of these modifications may be combined.

<2 > second embodiment

Next, a description is given of the phase locked loop 2 having the oscillation circuit according to the second embodiment. The oscillation circuit according to the present embodiment is different from the oscillation circuit in the case of the above-described first embodiment in a method of changing the impedance between the connection node ND and the ground. Note that substantially the same components as those of the phase locked loop 1 according to the above-described first embodiment are denoted by the same reference numerals, and description thereof is appropriately omitted.

As shown in fig. 1, the phase locked loop 2 includes an oscillation circuit 60.

Fig. 14 shows a configuration example of the oscillation circuit 60. The oscillation circuit 60 includes a transistor 21, a variable resistance portion 63, an oscillation portion 30, a capacitor 22, and a resistance setting portion 64.

The variable resistance section 63 is configured to have a resistance variable based on the control signals S1 to S3. The variable resistance section 63 includes switches SW1 to SW3 and resistors RES1 to RES 3. The resistors RESl to RES3 have, for example, the same resistance.

One end of the resistor RES1 is coupled to the connection node ND, and the other end is coupled to one end of the resistor RES 2. One end of the resistor RES2 is coupled to the other end of the resistor RES1, and the other end is coupled to one end of the resistor RES 3. One end of the resistor RES3 is coupled to the other end of the resistor RES2, and the other end is coupled to the oscillation section 30.

One end of the switch SW1 is coupled to one end of the resistor RES1, and the other end of the switch SW1 is coupled to the other end of the resistor RES 1. One end of the switch SW2 is coupled to one end of the resistor RES2, and the other end of the switch SW2 is coupled to the other end of the resistor RES 2. One end of the switch SW3 is coupled to one end of the resistor RES3, and the other end of the switch SW3 is coupled to the other end of the resistor RES 3.

With this configuration, the variable resistance section 63 is allowed to change the resistance based on the control signals S1 to S3.

The resistance setting section 64 is configured to set the resistance of the variable resistance section 63 based on the voltage Vtail. The resistance setting section 64 includes the AD converter 25 and the switch controller 66. The switch controller 66 is configured to generate the control signals S1 to S3 based on the digital code supplied from the AD converter 25 and the signal DET supplied from the lock detection circuit 15. Specifically, the switch controller 66 generates the control signals S1 to S3 such that the lower the voltage Vtail, the more the number of switches to be turned on of the switches SW1 to SW3 is reduced. Therefore, as voltage Vtai1 decreases, resistance setting unit 64 increases the resistance of variable resistance unit 63.

With this configuration, in the oscillation circuit 60, in the case where the voltage Vtail is low, the resistance of the variable resistance section 63 increases. In the oscillation circuit 60, an increase in the resistance of the variable resistance section 63 increases the voltage drop at the variable resistance section 63. Therefore, the voltage Vtail at the connection node ND increases. In this example, the capacitor 22 has the voltage dependence shown in fig. 4. Therefore, in the oscillation circuit 60, an increase in the voltage Vtail increases the capacitance of the capacitor 22. Therefore, in the oscillation circuit 60, increasing the resistance of the variable resistance portion 63 when the voltage Vtail is low allows increasing the capacitance of the capacitor 22. This makes it possible to reduce the impedance between the connection node ND and the ground. Therefore, in the oscillation circuit 60, the power supply rejection ratio can be improved.

Here, the resistance setting portion 64 corresponds to one specific example of "setting portion" of the present disclosure. The variable resistance portion 63 corresponds to one specific example of "variable resistance portion" of the present disclosure.

Fig. 15 shows an example of an operation of setting the resistance of the variable resistance portion 63. In this example, in the initial state, all of the switches SW1 to SW3 are in the on state.

First, the switch controller 66 confirms whether phase synchronization is established in the phase-locked loop 2 based on the signal DET supplied from the lock detection circuit 15 (step S201). In the case where phase synchronization is not established (no in step S201), the switch controller 66 repeats step S201 until phase synchronization is established.

In the case where phase synchronization is established in step S201 (yes in step S201), the switch controller 66 confirms whether the voltage Vtail is lower than the predetermined voltage Vth based on the digital code supplied from the AD converter 25 (step S202). In the case where the voltage Vtail is not lower than the predetermined voltage Vth (no in step 202), the flow ends.

In the case where the voltage Vtail is lower than the predetermined voltage Vth in step S202 (yes in step S202), the switch controller 66 sets the on-off states of the switches SW1 to SW3 according to the voltage Vtail (step S203).

Fig. 16 shows an example of the setting operation of the switch controller 66. In the case where the voltage Vtail is equal to or higher than the predetermined voltage Vl and lower than the predetermined voltage Vth, the switch controller 66 turns on the switches SW1 and SW2 and turns off the switch SW 3. Further, in the case where the voltage Vtail is equal to or higher than the predetermined voltage V2 and lower than the predetermined voltage V1, the switch controller 26 turns on the switch SW1 and turns off the switches SW2 and SW 3. Further, in the case where the voltage Vtail is lower than the predetermined voltage V2, the switch controller 26 turns off the switches SW1 to SW 3. As described above, the lower the voltage Vtail, the more the switch controller 66 increases the number of switches to be turned off of the switches SW1 to SW 3. Therefore, the switch controller 66 increases the resistance of the variable resistance portion 63 as the voltage Vtail is lower. The increase in the resistance of the variable resistance portion 63 increases the voltage drop of the variable resistance portion 63. Therefore, the voltage Vtail at the connection node ND increases and the capacitance of the capacitor 22 increases. Therefore, in the oscillation circuit 60, the capacitance between the connection node ND and the ground can be prevented from being excessively small. In other words, the capacitance between the connection node ND and the ground can be prevented from largely changing.

Next, the switch controller 66 confirms whether or not phase synchronization is maintained based on the signal DET supplied from the lock detection circuit 15 (step S204). If the phase synchronization is not maintained (no in step S204), the process returns to step S201. Further, the operations in steps S201 to S204 are repeated until the voltage Vtail becomes equal to or higher than the predetermined voltage Vth. In contrast, in the case where the phase synchronization is maintained in step S204 (yes in step S204), the flow ends.

As described above, in the phase locked loop 2, the impedance between the connection node ND and the ground changes based on the voltage Vtail at the connection node ND. Specifically, in the phase locked loop 2, the resistance of the variable resistance section 63 changes according to the voltage Vtail. This changes the voltage Vtail at the connection node ND. Thus, the capacitance of the capacitor 22 is changed. Therefore, in the phase locked loop 2, as in the case of the first embodiment described above, the power supply rejection ratio can be improved.

Further, the phase locked loop 2 changes the resistance of the variable resistance portion 63, thereby changing the impedance between the connection node ND and the ground. The area of the allowable variable resistance portion 63 in the semiconductor chip is allowed to be smaller than the area of the variable capacitance portion 23 according to the above-described first embodiment (fig. 2). Therefore, in the phase locked loop 2, the circuit area in the semiconductor chip can be reduced.

As described above, in the present embodiment, the resistance of the variable resistance portion is changed, thereby changing the impedance between the connection node ND and the ground. Therefore, the circuit area in the semiconductor chip can be reduced. Other effects are similar to those in the case of the first embodiment described above.

[ modification 2-1]

In the above-described embodiment, as shown in fig. 15, it is confirmed in step S204 whether or not phase synchronization is maintained; however, this is not limiting. Alternatively, for example, as shown in fig. 17, step S204 may be omitted, and after the switches SW1 to SW3 are set in step S203, it may be returned to step S201. That is, in the phase locked loop 2, in the case where the resistance of the variable resistance portion 63 is changed in step S203, the DC operating point may be changed. Therefore, there is a high possibility that the phase synchronization enters an unstable state. Therefore, in the phase locked loop 2, step S204 is omissible.

[ other modifications ]

The modification of the first embodiment can be applied to the phase locked loop 2 according to the above-described embodiment. Specifically, for example, in the oscillation circuit 60, as in the case of the oscillation circuit 20C according to modification 1-2 of the first embodiment, the resistances of the resistors RES1 to RES3 may be weighted. Further, for example, in the oscillation circuit 60, as in the case of the oscillation circuit 20D (fig. 11) according to modifications 1 to 3 of the first embodiment, an operational amplifier 51D, a transistor 52D, and a resistor 53D may be provided. Further, for example, in the phase locked loop 2, as in the case of the phase locked loop 1E according to modifications 1 to 4 of the first embodiment (fig. 12 and 13), in the case of the first operation mode, the impedance between the connection node ND and the ground may be changed based on the voltage at the connection node ND, and in the case of the second operation mode, the impedance may not be changed based on the voltage at the connection node ND.

Although the present technology has been described with reference to some of the above embodiments and modifications, the present technology is not limited to these embodiments and the like, and various modifications may be made.

For example, although the frequency dividing circuit 14 is provided in each of the above embodiments, this is not limitative. Alternatively, for example, the frequency dividing circuit 14 may be omitted. In this case, the phase comparison circuit 11 may be configured to compare the phase of the clock signal CLK1 with the phase of the clock signal CLK supplied from the oscillation circuit 20, and generate the signals UP and DN according to the comparison result.

It should be noted that the effects described herein are merely illustrative and not restrictive, and any other effects may be provided.

Note that the present technology can be configured as follows. According to the present technology having any of the following configurations, the power supply rejection ratio can be improved.

(1) An oscillating circuit comprising:

a current source coupled to the connection node, the current source configured to cause a current having a current value based on the input voltage to flow from the first power supply node to the connection node;

an oscillating section provided on a current path between the connection node and the second power supply node, the oscillating section configured to oscillate at an oscillation frequency based on a current flowing through the current path;

a first capacitor disposed between the connection node and the second power supply node, the first capacitor having a capacitance that changes according to a voltage at the connection node; and

a setting section configured to perform a changing operation based on the voltage at the connection node, the changing operation being an operation of changing an impedance between the connection node and the second power supply node.

(2) The oscillation circuit according to the above (1), further comprising:

a variable capacitance section provided between the connection node and the second power supply node, the variable capacitance section having a variable capacitor, wherein,

the setting section is configured to change the capacitance of the variable capacitance section to perform a changing operation.

(3) The oscillation circuit according to the above (2), wherein the setting section is configured to make the capacitance of the variable capacitance section in a case where the voltage at the connection node is lower than a predetermined threshold larger than the capacitance in a case where the voltage at the connection node is higher than the predetermined threshold.

(4) The oscillation circuit according to claim 2 or 3,

the variable capacitance part includes two or more sub-circuits coupled in parallel with each other, each sub-circuit having one end coupled to the connection node and the other end coupled to the second power supply node,

two or more sub-circuits each include a second capacitor and a switch coupled in series with each other, and

the setting section is configured to change the number of switches to be turned on among the switches in the two or more sub-circuits and thereby change the capacitance of the variable capacitance section.

(5) The oscillation circuit according to the above (2) or (3), further comprising:

a variable resistance section provided on the current path, the variable resistance section having a variable resistance, wherein,

the setting section is configured to change the resistance of the variable resistance section and thereby perform a changing operation.

(6) The oscillation circuit according to the above (5), wherein the setting section changes the resistance of the variable resistance section, thereby changing the voltage at the connection node and changing the capacitance of the first capacitor.

(7) The oscillation circuit according to the above (5) or (6), wherein the setting section is configured to make a resistance of the variable resistance section in a case where the voltage at the connection node is lower than a predetermined threshold value larger than a resistance in a case where the voltage at the connection node is higher than the predetermined threshold value.

(8) The oscillation circuit according to any one of the above (1) to (7), wherein the setting section is configured to perform the changing operation based on the voltage at the connection node in the first operation mode, and is configured not to perform the changing operation in the second operation mode.

(9) The oscillation circuit according to any one of the above (1) to (8), wherein a capacitance of the first capacitor when the voltage at the connection node is the first voltage is larger than a capacitance of the first capacitor when the voltage at the connection node is the second voltage, and the second voltage is lower than the first voltage.

(10) The oscillation circuit according to any one of the above (1) to (9), wherein the first capacitor has a MOS structure.

(11) A phase locked loop comprising:

a phase comparison circuit configured to compare a phase of the first signal with a phase of the second signal based on the clock signal;

a loop filter configured to generate a control voltage based on a phase comparison result in the phase comparison circuit; and

an oscillation circuit configured to generate a clock signal based on a control voltage;

the oscillation circuit includes:

a current source coupled to the connection node, the current source configured to cause a current having a current value based on the control voltage to flow from the first power supply node to the connection node,

an oscillating section provided on a current path between the connection node and the second power supply node, the oscillating section configured to oscillate at an oscillation frequency based on a current flowing through the current path and thereby generate a clock signal;

a first capacitor provided between the connection node and the second power supply node, the first capacitor having a capacitance that changes according to a voltage at the connection node; and

a setting section configured to perform a changing operation based on the voltage at the connection node, the changing operation being an operation of changing an impedance between the connection node and the second power supply node.

This application claims priority based on japanese patent application No. 2018-174087, filed in 2018, 9, 18 to the present patent office, the entire contents of which are incorporated herein by reference.

It should be understood that various modifications, combinations, sub-combinations and alterations may occur to those skilled in the art, depending on design requirements and other factors, and they are within the scope of the appended claims or their equivalents.