阅读说明：本技术 半导体元件 (Semiconductor device with a plurality of semiconductor chips ) 是由 苏圣凯 于 2020-05-11 设计创作，主要内容包括：一种半导体元件包括基板、栅极结构、半金属源/漏极结构,以及源/漏极接触。栅极结构位于基板上方。半金属源/漏极结构位于栅极结构的相对两侧,其中半金属源/漏极结构的能带结构具有位于不对称K点上的价带和传导带。源/漏极接触分别位于半金属源/漏极结构的上表面上方。(A semiconductor device includes a substrate, a gate structure, a semi-metal source/drain structure, and source/drain contacts. The gate structure is located above the substrate. The semi-metal source/drain electrode structure is positioned on two opposite sides of the grid electrode structure, wherein the energy band structure of the semi-metal source/drain electrode structure is provided with a valence band and a conduction band which are positioned on an asymmetric K point. Source/drain contacts are respectively located over the upper surface of the semi-metal source/drain structure.)

1. A semiconductor device, comprising:

a gate structure on a substrate;

a plurality of semi-metal source/drain structures located on opposite sides of the gate structure, wherein an energy band structure of the plurality of semi-metal source/drain structures has a valence band and a conduction band located at asymmetric K points; and

a plurality of source/drain contacts respectively located over upper surfaces of the plurality of semi-metal source/drain structures.

Technical Field

The present disclosure relates to a semiconductor device.

Background

The semiconductor integrated circuit industry has experienced rapid growth. Technological growth in integrated circuit materials and designs has created several generations of integrated circuits. Each generation has a smaller size and more complex circuitry than the previous generation. However, such advances also increase the complexity of manufacturing bulk integrated circuits.

In the subject of the evolution of bulk integrated circuits, the functional density (e.g., the number of interconnected devices per unit area of a chip) is gradually increasing, while the geometric size (e.g., the smallest device or line that can be fabricated in a manufacturing process) is gradually decreasing. The advantage of this size reduction process is increased manufacturing efficiency and reduced associated costs.

However, as feature sizes are scaled down, the manufacturing process becomes more difficult. Therefore, in an era of smaller and smaller size, it is a challenge to form a reliable semiconductor element.

Disclosure of Invention

According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a gate structure, a semi-metal source/drain structure, and source/drain contacts. The gate structure is located above the substrate. The semi-metal source/drain electrode structure is positioned on two opposite sides of the grid electrode structure, wherein the energy band structure of the semi-metal source/drain electrode structure is provided with a valence band and a conduction band which are positioned on an asymmetric K point. Source/drain contacts are respectively located over the upper surface of the semi-metal source/drain structure.

Drawings

Various aspects of the disclosure can be understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A to 11B are schematic diagrams of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure at different steps;

fig. 12A and 12B are band diagrams of semiconductor devices according to some embodiments of the present disclosure;

FIG. 13 shows PtSe according to some embodiments of the disclosure₂The energy band structure of (1);

fig. 14 is a simulation result of sub-threshold slope of a semiconductor device with the introduction of a semi-metal source/drain structure according to some embodiments of the present disclosure;

FIG. 15 illustrates a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 16A to 27B are schematic diagrams of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure at different steps;

fig. 28 illustrates a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

[ notation ] to show

100 substrate

102 semiconductor fin

105 isolation structure

110 two-dimensional material layer

120 dummy gate structure

122 gate dielectric layer

123 gate dielectric

124 dummy gate layer

125 dummy gate

130 two-dimensional material layer

130A first part

130B second part

135 gate spacer

140 interlayer dielectric layer

150 two-dimensional material layer

160 interlayer dielectric layer

170 metal gate structure

172 gate dielectric layer

174 workfunction metal layer

176 gate electrode

180 source/drain contact

190 two-dimensional material layer/source/drain structure

S is source electrode

D is drain electrode

CH channel

C_S、C_CH、C_DConduction band

V_S、V_CH、V_DValence band

TIC-Heat injection Current

SDT Source to drain tunneling

O1, O2, O3 openings

T1, T2, T3, T4, T5 thickness

C1, C2 Condition

S101-S111, S201-212, Block

B-B: line

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter presented herein. A specific example of components and arrangements are described below to simplify the present disclosure. Of course, this example is merely illustrative and not intended to be limiting. For example, the following description of a first feature formed over or on a second feature may, in embodiments, include the first feature being in direct contact with the second feature, and may also include forming additional features between the first and second features such that the first and second features are not in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below", "lower", "above", "upper", and the like, are used herein to simplify description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms also encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The fins on the semiconductor substrate may be patterned by any method. For example, the fins may be patterned by one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes, which allow the pattern to have, for example, a smaller pitch than fins produced using other current single and direct photolithography processes. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are grown in a self-aligned manner along both sides of the patterned sacrificial layer. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins.

Fig. 1A to 11B are schematic diagrams of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure at different steps.

Referring to fig. 1A and 1B, fig. 1B is a cross-sectional view taken along line B-B of fig. 1A. A semiconductor fin 102 is formed over the substrate 100, and a plurality of isolation structures 105 are formed over the substrate 100 and adjacent to the semiconductor fin 102. In some embodiments, the substrate 100 may be a semiconductor substrate and may include a layered or buried oxide. In some embodiments, the substrate 100 comprises bulk silicon, which may be undoped or doped (e.g., P-type, N-type, or a combination thereof). Other materials suitable for semiconductor devices may also be used. Other materials such as germanium, quartz, sapphire, or glass may be substituted for the material of the substrate 100. Alternatively, the silicon substrate 100 may be an active layer of a semiconductor-on-insulator substrate, or a multi-layer structure formed over a bulk silicon layer, such as a silicon germanium layer. In some embodiments, the substrate 100 includes silicon, germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide and/or indium antimonide, and alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP.

The semiconductor fin 102 may be formed by, for example, patterning and etching the substrate 100 using photolithography techniques. In some embodiments, a photoresist layer is deposited over the substrate 100. The photoresist layer is irradiated (exposed) according to a desired pattern, which is divided into the pattern of the semiconductor fins 102, and developed to remove a portion of the photoresist layer. The remaining photoresist protects the underlying material from damage from subsequent processes such as etching. It should be appreciated that other masks, such as oxide or silicon nitride masks, may also be used for the etching process.

The isolation structure 105 serves as a shallow trench isolation Structure (STI) around the semiconductor fin 102. In some embodiments, the isolation structure 105 is formed of silicon oxide, silicon nitride, silicon oxynitride, fluoride doped silicate glass (FSG), or other low-K dielectric material. In some embodiments, the isolation structure 105 may be formed by a High Density Plasma (HDP) Chemical Vapor Deposition (CVD) process using Silane (SiH)₄) And oxygen (O)₂) As a reaction precursor. In some other embodiments, the isolation structure 105 may be formed using a sub-atmospheric chemical vapor deposition (SACVD) process or a High Aspect Ratio Process (HARP), wherein the process gases may include Tetraethylorthosilicate (TEOS) and ozone (O3). In yet other embodiments, the isolation structure 105 may be formed by, for example, a spin-on dielectric process, such as Hydrogen Silsesquioxane (HSQ) or Methyl Silsesquioxane (MSQ). It can also be usedOther processes or materials. In some embodiments, the isolation structure 105 may have a multi-layer structure, such as a thermal oxide liner and silicon nitride on the liner. Then, a thermal annealing process may be optionally performed on the isolation structure 105.

Referring to fig. 2A and 2B, fig. 2B is a cross-sectional view taken along line B-B of fig. 2A. A first two-dimensional material layer 110, a gate dielectric layer 122, and a dummy gate layer 124 are sequentially formed over the substrate 100. In some embodiments, the first two-dimensional material layer 110 extends along the surface of the semiconductor fin 102 and the isolation structure 105. According to a widely accepted definition in solid state materials science, "two-dimensional material" refers to a lattice material composed of a single layer of atoms. In a widely accepted definition in the art, a "two-dimensional material" may also be referred to as a "monolayer" material. In the present disclosure, "two-dimensional material" and "single layer" may be used interchangeably and have the same meaning unless otherwise specified.

The first two-dimensional material layer 110 may be a two-dimensional material and have an appropriate thickness. In some embodiments, a monolayer of atoms is included in each monolayer structure of the two-dimensional material, and thus the thickness of the layer of two-dimensional material also represents the number of monolayers of the two-dimensional material, which may be a single monolayer or multiple monolayers. The coupling of two adjacent monolayers of a two-dimensional material is by van der Waals force (van der Waals force), which is weak compared to the chemical bonding between atoms in a single monolayer.

The first two-dimensional material layer 110 may be formed by a suitable method according to the materials of the first two-dimensional material layer 110 and the substrate 100. In some embodiments, the first two-dimensional material layer 110 includes a Transition Metal Dichalcogenide (TMD) single layer material. In some embodiments, the transition metal dichalcogenide monolayer includes a layer of transition metal atoms sandwiched between two layers of chalcogen atoms. The semiconductor fin 102 of the substrate 100 may comprise a material suitable for forming a transition metal dichalcogenide monolayer thereover. For example, the semiconductor fin 102 of the substrate 100 may be of a material, such as silicon, that is capable of withstanding the potentially high temperatures of growing transition metal dichalcogenides.

In some embodiments, if the first two-dimensional materialThe material layer 110 is a transition metal dichalcogenide monolayer comprising platinum diselenide (PtSe)₂) Each layer of the lattice comprises a two-dimensional array of closely arranged platinum atoms sandwiched between selenium atoms in a 1T structure. The electrical property of the first two-dimensional material layer 110, such as platinum diselenide, may have different states of semi-metal (semi-metal) and semiconductor depending on the thickness of the layer (i.e., a single layer of the first two-dimensional material layer 110).

In some embodiments, platinum diselenide has semiconductor properties (e.g., band gap) if it is a single layer structure or a double layer structure. For example, a single layer of platinum diselenide has a thickness of aboutTo about(e.g. in) And has an energy gap of about 1.2eV to about 1.4eV (e.g., 1.3 eV). In another aspect, the bilayer platinum diselenide monolayer has a thickness of about 1.4nm to about 1.6nm (e.g., 1.5nm) and an energy gap of about 0.2eV to about 0.4eV (e.g., 0.3 eV). Some experimental results show that the platinum diselenide layer has semiconductor properties if the thickness of the platinum diselenide is less than about 2.5 nm. As discussed herein, the semiconductor property of a material or the semiconductor state of a material refers to the material or the state of the material being its Fermi level (E)_F) Is the gap (i.e., energy gap) between the filled valence band (valence band) and the empty conduction band (conduction band), wherein the energy gap is greater than 0 and less than about 4 electron-ford (eV).

However, if platinum diselenide becomes increasingly thicker, e.g., three or more layers, the platinum diselenide will lose the energy gap and become a semi-metal. For example, a three-layer platinum diselenide monolayer has a thickness of about 2nm to about 3nm (e.g., 2.5nm) and no energy gap. Thus, platinum diselenide has a semi-metallic character if its thickness is greater than about 2.5nm or has a three-layer structure (or more). Herein, theAs discussed, semimetal electrical (semimetal characteristics) refers to the Fermi level (E) with no bandgap and its Fermi level_F) Have negligible density of states (diversity of states). The semi-metallic material or semi-metallic state of the material has holes and electrons that make electrical conduction, so it is conductive.

In some embodiments, since the first two-dimensional material layer 110 of platinum diselenide will serve as a semiconductor channel layer in the semiconductor device, the thickness of the first two-dimensional material layer 110 will be less than about 2nm to about 3nm (e.g., 2.5nm), i.e., equal to or less than two monolayers of platinum diselenide. In some embodiments, forming the first two-dimensional material layer 110 also includes processing the first two-dimensional material layer 110 to obtain a desired electrical property (e.g., a semiconductor electrical property). The processing process includes thinning (i.e., reducing the thickness of the first two-dimensional material layer 110), doping, or applying stress to make the first two-dimensional material layer 110 exhibit specific semiconductor characteristics, such as having an energy gap. For example, if the thickness of the initial platinum diselenide first two-dimensional material layer 110 is greater than about 2nm to about 3nm (e.g., 2.5nm), i.e., equal to or greater than three platinum diselenide monolayers, the initial platinum diselenide first two-dimensional material layer 110 may exhibit semi-metallic characteristics, and may not be suitable for use as a transistor channel region. Thus, the first two-dimensional material layer 110 may be thinned such that the thickness of the platinum diselenide first two-dimensional material layer 110 provides semiconductor characteristics such that it is less than about 2.5nm thick (or less than three monolayers of platinum diselenide). In some embodiments, a plasma dry etch, such as a reactive ion etch, may be used to reduce the number of monolayers in the first two-dimensional material layer 110.

In some embodiments, the step of forming the first two-dimensional material layer 110 with semiconductor characteristics may be referred to as "bandgap opening". Since a two-dimensional material may undergo a transition between a semiconductor state or a semi-metal state, the term "bandgap opened" as used herein refers to a state of the two-dimensional material in which a direct or indirect energy gap exists in an electrical state of the two-dimensional material, such that the two-dimensional material has semiconductor properties. As discussed herein, the semiconductor state of the first two-dimensional material layer 110 may be obtained by one or more of selective growth, thinning/reducing the number of monolayers, or using other energy level opening techniques such as doping or stressing.

The first two-dimensional material layer 110 of platinum diselenide may be formed on the semiconductor fin 102 of the substrate 100 by a suitable method. For example, platinum diselenide may be formed on the substrate 100 by a deposition technique or by a micro mechanical lift-off (micro mechanical lift-off) and coupled to the semiconductor fin 102 of the substrate 100.

In some embodiments, the first two-dimensional material layer 110 may be formed by Molecular Beam Epitaxy (MBE), Chemical Vapor Transport (CVT), Chemical Vapor Deposition (CVD), or other suitable processes. In chemical vapor deposition, PtCl₂(or PtO) and selenide can be evaporated to produce Pt ions and Se ions, which react with Se ions to form PtSe deposited on the semiconductor fin 102 of the substrate 100₂。

In other embodiments, if the platinum diselenide is formed by a micro-mechanical lift-off process, the first two-dimensional material layer 110 is formed on another substrate and transferred to the substrate 100. For example, a two-dimensional material thin film is formed on the first substrate by CVD, sputtering, ALD. A polymer film, such as Polymethylmethacrylate (PMMA), is then formed on the two-dimensional material film. After the polymer film is formed, the sample is heated, for example, by placing the sample on a high temperature tray. After heating, the two-dimensional material film is peeled from the first substrate 100 from the corners thereof, for example, using tweezers, and the sample may be immersed in a solution to facilitate separation of the two-dimensional material film and the first substrate. The two-dimensional material film and the polymer film are transferred to the substrate 100. The polymer film is then removed from the two-dimensional material film using a suitable solvent.

The gate dielectric layer 122 may be, for example, silicon oxide, silicon nitride, combinations thereof, and the like, and may be grown by suitable techniques such as deposition or thermal growth. The gate dielectric layer 122 may be formed by a suitable process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any suitable process.

Dummy gate layer 124 may be deposited over gate dielectric layer 122 and then planarized, for example by CMP. Dummy gate layer 124 may include polysilicon (poly-Si) or polycrystalline silicon germanium (poly-SiGe). In addition, the dummy gate layer 124 may be polysilicon doped with uniform or non-uniform doping. Dummy gate layer 124 may be formed by a suitable process, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any suitable process.

Referring to fig. 3A and 3B, fig. 3B is a cross-sectional view taken along line B-B of fig. 3A. The first two-dimensional material layer 110, the gate dielectric layer 122, and the dummy gate layer 124 are patterned to form a patterned first two-dimensional material layer 110, a gate dielectric 123, and a dummy gate 125, such that portions of the semiconductor fin 102 and the isolation structure 105 are exposed. The gate dielectric layer 122 and the dummy gate layer 124 may be collectively referred to as a dummy gate structure 120 or a dummy gate stack. After patterning, portions of the semiconductor fin 102 and the isolation structure 105 are exposed through the dummy gate structure 120. In some embodiments, opposing sidewalls of the patterned first two-dimensional material layer 110 are exposed.

In some embodiments, the first two-dimensional material layer 110, the gate dielectric layer 122, and the dummy gate layer 124 may be patterned by photolithography. In some embodiments, a photoresist layer may be deposited over dummy gate layer 124. The photoresist layer may be irradiated (exposed) according to a desired pattern, here dummy gate structure 120, and developed to remove a portion of the photoresist material. The remaining photoresist protects the underlying material from damage by subsequent processes, such as etching.

Referring to fig. 4A and 4B, fig. 4B is a cross-sectional view taken along line B-B of fig. 4A. A second two-dimensional material layer 130 is formed on the exposed portions of the semiconductor fin 102 and the isolation structure 105. In some embodiments, the second two-dimensional material layer 130 is grown from the first two-dimensional material layer 110 along the exposed surfaces of the semiconductor fin 102 and the isolation structure 105. Thus, the bottom surfaces of the first two-dimensional material layer 110 and the second two-dimensional material layer 130 are collinear. In some embodiments, the first two-dimensional material layer 110 and the second two-dimensional material layer 130 have the same material, such as platinum diselenide. Since the first two-dimensional material layer 110 is formed along the surface of the semiconductor fin 102 and the isolation structure 105, the chemical bonds between the atoms within the monolayer in the first two-dimensional material layer 110 are substantially parallel to the surface of the semiconductor fin 102 and the isolation structure 105. In addition, since the sidewalls of the first two-dimensional material layer 110 are exposed to the dummy gate structure 120, atoms of the second two-dimensional material layer 130 tend to bond with chemical bonds on the sidewalls of the first two-dimensional material layer 110, so that the second two-dimensional material layer 130 can grow laterally from the sidewalls of the first two-dimensional material layer 110. In other words, the second two-dimensional material layer 130 takes the exposed sidewall of the first two-dimensional material layer 110 as a base layer and grows horizontally from the exposed sidewall of the first two-dimensional material layer 110. In some embodiments, the second two-dimensional material layer 130 may be formed by molecular beam epitaxy, chemical vapor transport, chemical vapor deposition, or a suitable method.

As mentioned above, since the second two-dimensional material layer 130 uses the first two-dimensional material layer 110 as a base layer, the second two-dimensional material layer 130 and the first two-dimensional material layer 110 have substantially the same thickness. For example, if the first two-dimensional material layer 110 is a single monolayer, the second two-dimensional material layer 130 is also a single monolayer, and may have a thickness from aboutTo about(e.g. in). On the other hand, if the first two-dimensional material layer 110 is a double-layer monolayer, the second two-dimensional material layer 130 is also a double-layer monolayer, and may have a thickness from about 1.4nm to about 1.6nm (e.g., 1.5 nm). Generally, the thickness of the second two-dimensional material layer 130 is less than about 2.5 nm. Such that the second two-dimensional material layer 130 (e.g., platinum diselenide) has semiconductor properties. In some embodiments, if the first two-dimensional material layer 110 and the second two-dimensional material layer 130 are made of the same material (e.g., platinum diselenide), there may not be a distinguishable interface between the two. In some embodiments, if the second two-dimensional material layer 130 is a different material than the first two-dimensional material layer 110, there may be a distinguishable interface between the two.

Referring to fig. 5A and 5B, fig. 5B is a cross-sectional view taken along line B-B of fig. 5A. Gate spacers 135 are formed on opposing sidewalls of dummy gate structure 120. In some embodiments, the gate spacers 135 cover the first portion 130A of the second two-dimensional material layer 130 and expose the second portion 130B of the second two-dimensional material layer 130. The gate spacers 135 may be formed, for example, by blanket depositing a spacer layer over the dummy gate structure 120 and the second two-dimensional material layer 130, followed by performing an etch process to remove horizontal portions of the spacer layer such that vertical portions of the spacer layer remain on the sidewalls of the dummy gate structure 120 and on the second two-dimensional material layer 130. In some embodiments, gate spacers 135 may comprise SiO₂、Si₃N₄、SiO_xN_ySiC, SiCN, SiOC, SiOCN and/or combinations thereof. In some embodiments, each gate spacer 135 may comprise multiple layers, such as a main spacer, a liner, and the like. In some embodiments, the gate spacers 135 may be formed by CVD, SACVD, FCVD, ALD, PVD, or other suitable processes.

Referring to fig. 6A and 6B, fig. 6B is a cross-sectional view taken along line B-B of fig. 6A. An interlayer dielectric layer 140 is formed next to the gate spacers 135. The interlayer dielectric layer 140 extends over the second portion 130B of the second two-dimensional material layer 130. In some embodiments, a dielectric layer is blanket deposited over the substrate 100 and fills the space around the gate spacers 135, followed by a CMP process to remove excess dielectric layer until the upper surface of the dummy gate structure 120 is exposed. In some embodiments, the dielectric material includes silicon oxide, silicon nitride, silicon oxynitride, Tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric material. Examples of low-k dielectric materials include, but are not limited to, fluorinated quartz glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), or polyimide. The interlayer dielectric layer 140 may be formed using, for example, CVD, ALD, Spin On Glass (SOG), or other suitable techniques.

Referring to fig. 7A and 7B, fig. 7B is a cross-sectional view taken along line B-B of fig. 7A. The interlayer dielectric layer 140 is patterned to form a plurality of first openings O1 and expose the second two-dimensional material layer 130. In detail, the first opening O1 exposes a second portion of the second two-dimensional material layer 130. In some embodiments, a photoresist layer is formed over the substrate 100, the photoresist layer is irradiated (exposed) according to a desired pattern, and developed to remove a portion of the photoresist layer. The remaining photoresist protects the underlying material from damage from subsequent processes such as etching. It should be appreciated that other masks, such as oxide or silicon nitride masks, may also be used for the etching process.

Referring to fig. 8A and 8B, fig. 8B is a cross-sectional view taken along line B-B of fig. 8A. A plurality of third two-dimensional material layers 150 are respectively formed in the first openings O1. In some embodiments, the third two-dimensional material layer 150 may be formed by molecular beam epitaxy, chemical vapor transport, chemical vapor deposition, or a suitable method. In some embodiments, the two-dimensional material layer tends to form on the surface of the two-dimensional material rather than on the surface of the three-dimensional crystal. Therefore, the third two-dimensional material layer 150 is more likely to be formed on the exposed surface of the second portion 130B of the second two-dimensional material layer 130 than the three-dimensional crystalline structure, such as the interlayer dielectric layer 140, the gate spacer 135 and the dummy gate structure 120. In other words, the second two-dimensional material layer 130 has a higher growth rate (e.g., deposition rate) on the exposed surface of the second portion 130B of the second two-dimensional material layer 130 than a structure having a three-dimensional crystal, such as the interlayer dielectric layer 140, the gate spacer 135 and the dummy gate structure 120. Here, the "three-dimensional crystal structure" refers to a regular arrangement of atoms in a three-dimensional manner, and may be represented by a repetitive three-dimensional unit (unit cell) arrangement, in which a unit refers to a minimum repetitive unit that can exhibit complete symmetry of a three-dimensional structure. In some embodiments, the first two-dimensional material layer 110, the second two-dimensional material layer 130, and the third two-dimensional material layer 150 are the same material, such as platinum diselenide.

In fig. 8B, if the first two-dimensional material layer 110, the second two-dimensional material layer 130, and the third two-dimensional material layer 150 are platinum diselenide in some embodiments, the first two-dimensional material layer 110 has a thickness T1, the second two-dimensional material layer 130 has a thickness T2, and the third two-dimensional material layer 150 has a thickness T3. As mentioned above, the thickness T1 of the first two-dimensional material layer 110 is less than about 2.5nm, i.e., equal to or less than two monolayers of platinum diselenide, so that the first two-dimensional material layer 110 has semiconductor characteristics. Likewise, the thickness T2 of the second two-dimensional material layer 130 is less than about 2.5 nm. However, the third two-dimensional material layer 150 having the thickness T3 is formed on the second portion 130B of the second two-dimensional material layer 130 such that the total thickness T4 of the second two-dimensional material layer 130 and the third two-dimensional material layer 150 is greater than about 2.5nm, which makes the combination of the third two-dimensional material layer 150 and the second portion 130B of the second two-dimensional material layer 130 have a semi-metallic characteristic. Accordingly, the combination of the third two-dimensional material layer 150 and the second portion 130B of the second two-dimensional material layer 130 may be made as a source/drain structure of a transistor. As such, the undoped half-metal source/drain structure can be used to replace the conventional N-doped or P-doped semiconductor source/drain structure. In other words, the first portion 130A of the second two-dimensional material layer 130 below the gate spacer 135 still maintains the semiconductor characteristics because the first portion 130A of the second two-dimensional material layer 130 still maintains the thickness T2 less than about 2.5 nm.

In some embodiments, the third two-dimensional material layer 150 should be formed with a sufficient thickness T3 such that the combination of the third two-dimensional material layer 150 and the second portion 130B of the second two-dimensional material layer 130 has semi-metallic properties. In other words, the third two-dimensional material layer 150 should be formed to have a thickness T3 such that the sum of the thickness T2 and the thickness T3 is greater than about 2.5 nm. Since the second two-dimensional material layer 130 and the third two-dimensional material layer 150 are made of the same material (platinum diselenide), there may not be a discernible interface therebetween.

Referring to fig. 9A and 9B, fig. 9B is a sectional view taken along line B-B of fig. 9A. An interlayer dielectric layer 160 is formed in the first opening O1. An interlayer dielectric layer 160 extends over the third two-dimensional material layer 150. In some embodiments, a dielectric layer is blanket deposited over the substrate 100 and fills the first opening O1, and a CMP process is then performed to remove excess dielectric layer until the upper surface of the dummy gate structure 120 is exposed. In some embodiments, the dielectric material includes silicon oxide, silicon nitride, silicon oxynitride, Tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric material. Examples of low-k dielectric materials include, but are not limited to, fluorinated quartz glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), or polyimide. The interlayer dielectric layer 160 may be formed using, for example, CVD, ALD, Spin On Glass (SOG), or other suitable techniques.

Referring to fig. 10A and 10B, fig. 10B is a sectional view taken along line B-B of fig. 10A. Dummy gate structure 120 is replaced with metal gate structure 170. In some embodiments, metal gate structure 170 includes a gate dielectric layer 172, a work function metal layer 174 over gate dielectric layer 172, and a gate electrode 176 over work function metal layer 174. In some embodiments, the metal gate structure 170 may be formed by, for example, removing the dummy gate structure 120 to form a gate trench between the gate spacers 135, sequentially depositing a gate dielectric material, a work function metal material, and a gate electrode material in the gate trench, and then performing a CMP process to remove excess gate dielectric material, work function metal material, and gate electrode material until the upper surface of the interlayer dielectric 160 is exposed to form the metal gate structure 170.

In some embodiments, gate dielectric layer 172 may comprise a high-k dielectric, such as TiO₂、HfZrO、Ta₂O₃、HfSiO₄、ZrO₂，ZrSiO₂、LaO、AlO、ZrO、TiO、Ta₂O₅、Y₂O₃、SrTiO₃(STO)、BaTiO₃(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba，Sr)TiO₃(BST)、Al₂O₃、Si₃N₄Oxynitride (SiON), combinations thereof, or other suitable materials. In some embodiments, the work function metal layer 174 may be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi₂、MoSi₂、TaSi₂、NiSi₂WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type workfunction metals include Ti,Ag. TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include a plurality of layers. In some embodiments, the gate electrode 176 may include tungsten (W). In some other embodiments, gate electrode 176 includes aluminum (Al), copper (Cu), or other suitable conductive material.

Referring to fig. 11A and 11B, fig. 11B is a sectional view taken along line B-B of fig. 11A. A plurality of source/drain contacts 180 are formed in the interlayer dielectric layer 160. In some embodiments, the source/drain contact 180 includes a liner and a plug. The liner is located between the plug and the underlying source/drain structure (e.g., the third two-dimensional material layer 150 and the second portion 130B of the second two-dimensional material layer 130). In some embodiments, the liner layer facilitates deposition of the plug and facilitates reducing out-diffusion of the metal material of the plug. In some embodiments, the liner comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another suitable material. The plug includes a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or other suitable conductive material. The source/drain contacts 180 may be formed, for example, by patterning the interlayer dielectric 160 to form a plurality of openings defining the locations of the source/drain contacts 180, filling the openings with a conductive material, and performing a CMP process to remove excess conductive material. In some embodiments, the source/drain contacts 180 may be formed by PVD, CVD, ALD, or other suitable process.

Fig. 12A and 12B are band diagrams of the semiconductor device of fig. 11A and 11B in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor elements of fig. 11A and 11B operate as switches, have an Off State (Off State) with no conductivity (or low conductivity) between elements, and have an On State (On State) with elements having a higher conductivity than the Off State. The band diagram of fig. 12A is in an open state, and the band diagram of fig. 12B is in a closed state.

Fig. 12A and 12B are schematic diagrams of relative positions of a conduction band and a valence band having a band offset (band offset) in a length direction along the semiconductor fin 102 (refer to fig. 11A and 11B). The band diagram plots the lower edge of the conduction band and the upper edge of the valence band. The conduction band includes a source S, a drain D, and a channel CH between the source S and the drain D. In some embodiments, the source S and the drain D correspond to the source/drain structure of fig. 11A and 11B (e.g., the combination of the third two-dimensional material layer 150 and the second portion 130B of the second two-dimensional material layer 130 thereunder), and the channel CH corresponds to the channel region of fig. 11A and 11B (e.g., the first two-dimensional material layer 110).

As mentioned above, the source S and drain D are not semiconductors, but rather have a semi-metallic character, and thus the source valence band V_SUpper edge of and source conduction band C_SOverlap or overlap with the lower edge of the drain, and a drain valence band V_DUpper edge and drain conduction band C of_DThe lower edges of which coincide or overlap. The electrons occupy the valence band, as indicated by the shading. In this case, the fermi levels of the source S and drain D are respectively the same as the source conduction band C_SAnd drain conduction band C_D. On the other hand, in the channel region CH having semiconductor characteristics, the channel valence band V is set_CHAnd channel conduction band C_CHThere is a bandgap (bandgap) between them.

Referring to fig. 11A, 11B and 12A, in the on state, a first voltage is applied to the metal gate structure 170 and the channel conduction band C is shifted_CHThe lower edge of (a) is made to be at the same height or slightly higher than the occupied energy level (e.g., fermi level) of the source S. In the on state of fig. 12A, the current transfer mechanism is a combination of heat injection current TIC (thermal injection current) and source-to-drain tunneling SDT (source-to-drain tunneling). The heat injection current TIC is a current self-source electrode conduction band C_STransmission cross channel conduction band C_CHTo the drain conduction band C_DThe current of (2). Source-to-drain tunneling SDT as current self-source conduction band C_STunneling through the barrier formed by the bandgap in the channel CH to the drain conduction band C_DThe current of (2). Current conduction band C_S、C_CHAnd C_DThe heat injection current TIC of (a) is significantly larger than the source-to-drain tunneling SDT and is therefore the dominant transport mechanism in the on state. Thus, in the ON state, the source to drain punch-throughThe tunneling SDT may be ignored. The first voltage may be equal to or higher than a threshold voltage of the semiconductor element of fig. 11A and 11B to convert it to an on state. Threshold voltage of current-carrying conduction band C_S、C_CHAnd C_DThe minimum voltage at which the hot injection current TIC starts to occur. Here, the term "heat injected current" means that carriers flow through the conduction band C by thermal kinetic energy_S、C_CHAnd C_DThe current of (2).

Referring to fig. 11A, 11B and 12B, in the off state, a second voltage is applied across the metal gate structure 170. In the closed state of FIG. 12B, the channel conduction band C_CHIs shifted beyond the source S (e.g. the conduction band C of the source S)_S) Occupied energy level (e.g., fermi energy level). The channel valence band V is due to the constant energy gap of the channel CH_CHAlso offset upwardly. In the off state, the hot injection current TIC is suppressed due to the large valence offset between the source S and channel CH, so the source-to-drain tunneling SDT becomes the dominant transport mechanism responsible for the current generation in the off state. In embodiments of the present disclosure, because the source/drain structure has a half-metal characteristic, source-to-drain tunneling SDT may be suppressed, as will be discussed in detail below.

Referring to fig. 13, fig. 13 is an energy band structure of bulk platinum diselenide, wherein "bulk platinum diselenide" refers to platinum diselenide having three or more monolayers (e.g., greater than about 2.5nm as described above) with semi-metallic properties. As shown by the band structure, the conduction band and the valence band of bulk platinum diselenide are located at different symmetric K-points (differential symmetry K-points). For example, the conduction band of bulk platinum diselenide is at the K Valley (Valley), while the valence band of bulk platinum diselenide is at the Γ Valley. For this case where the conduction and valence bands are at different symmetric K points, tunneling between the conduction and valence bands needs to be through phonon's assist. The additional mechanism (phonon assist) is required to drive tunneling, which reduces the probability of tunneling. Since the conduction band and the valence band are located at different symmetric K points in the embodiments of the present disclosure, the tunneling probability between the source S and the drain D is reduced, and the source-to-drain tunneling SDT is suppressed, which also results in an improvement in the sub-threshold slope (SS) performance, as will be discussed in more detail below. If the source/drain structure is a half-metal with conduction and valence bands at the same K-point, the tunneling probability between the source S and the drain D will not be significantly reduced, since such tunneling does not require phonon assist and thus increases the probability of tunneling.

Refer to FIGS. 11A, 11B, 12A, 12B and 14. FIG. 14 plots the current (I) flowing from the source S through the channel CH to the drain S at a fixed source/drain voltage, scaled by semi-log, and at room temperature_DS) To gate voltage (V)_GS) The figure (a). The I-V curve is calculated from the semiconductor element plotted in fig. 11A and 11B. Ideally, the source/drain current is low in the off state and high in the on state, and the step difference generated at the threshold voltage represents the transition of the device from off to on. There is no significant step change in the actual device, and the sub-threshold slope (SS) is used to evaluate how close a device is to the ideal device. Here, the "subthreshold slope" is the slope of the curve in fig. 14. As the subthreshold slope SS increases, the element is farther from the ideal direction.

In fig. 14, condition C1 is a simulation result of the semiconductor device having an N-doped or P-doped epitaxial source/drain structure according to some embodiments of the present disclosure. On the other hand, condition C2 is a simulation result of a semiconductor device having an undoped semi-metal source/drain structure according to some embodiments of the present disclosure, such as the semiconductor device of fig. 11A and 11B. Comparing condition C1 with condition C2, the sub-threshold slope of condition C2 is lower than that of condition C1 because the use of a half-metal source/drain structure with conduction and valence bands at different symmetric K points suppresses the unwanted source-to-drain tunneling SDT (as in fig. 12B), as discussed in fig. 13. Therefore, based on such a configuration, the sub-threshold slope of condition C2 for the semiconductor device having the semi-metal source/drain structure is improved compared to condition C1.

On the other hand, since the source/drain structure has a semi-metal characteristic, the resistance value of the source/drain structure may be reduced. Therefore, the contact resistance between the semi-metal source/drain structure and the source/drain contact can also be reduced, which can also facilitate the performance of the device.

Fig. 15 illustrates a method of fabricating a semiconductor device according to some embodiments of the present disclosure. Although method M1 is described as a series of acts or steps, it should be understood that the method is not limited by the acts or the order of acts. Thus, in some embodiments, these operations or steps may be performed in a different order, and/or simultaneously. In addition, in some embodiments, a described operation or step may be divided into multiple operations or steps, which may be performed at different times or at the same time with other operations or sub-operations. In some embodiments, described operations or steps may be omitted, or other operations or steps not described may be included.

In block S101, a semiconductor fin is formed over a substrate, and an isolation structure is formed over the substrate and adjacent to the semiconductor fin. Fig. 1A and 1B depict some embodiments of block S101.

In block S102, a first two-dimensional material layer, a gate dielectric, and a dummy gate layer are sequentially formed over a substrate. Fig. 2A and 2B depict some embodiments of block S102.

In block S103, the first two-dimensional material layer, the gate dielectric, and the dummy gate layer are patterned to form a patterned first two-dimensional material layer and a dummy gate structure. Fig. 3A and 3B depict some embodiments of block S103.

In block S104, a second two-dimensional material layer is laterally grown from sidewalls of the first two-dimensional material layer along exposed portions of the semiconductor fin and the isolation structure. Fig. 4A and 4B depict some embodiments of block S104.

In block S105, gate spacers are formed on opposing sidewalls of the dummy gate structure. Fig. 5A and 5B depict some embodiments of block S105.

At block S106, a first interlayer dielectric layer is formed next to the gate spacers. Fig. 6A and 6B depict some embodiments of block S106.

In block S107, a plurality of openings are formed in the first interlayer dielectric layer to expose the second two-dimensional material layer. Fig. 7A and 7B depict some embodiments of block S107.

In block S108, a plurality of third two-dimensional material layers are formed in the openings, respectively. Fig. 8A and 8B depict some embodiments of block S108.

In block S109, a second interlayer dielectric layer is formed in the opening. Fig. 9A and 9B depict some embodiments of block S109.

In block S110, the dummy gate structure is replaced with a metal gate structure. Fig. 10A and 10B depict some embodiments of block S110.

At block S111, a plurality of source/drain contacts are formed in the second interlayer dielectric layer. Fig. 11A and 11B depict some embodiments of block S111.

Fig. 16A to 27B are schematic diagrams of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure at different steps. Some elements of fig. 16A to 27B are the same as or similar to those discussed in fig. 1A to 11B, and thus the related details will not be repeated.

Referring to fig. 16A and 16B, fig. 16B is a sectional view taken along line B-B of fig. 16A. A semiconductor fin 102 is formed over the substrate 100, and a plurality of isolation structures 105 are formed over the substrate 100 and adjacent to the semiconductor fin 102. The substrate 100, the semiconductor fin 102, and the isolation structure 105 are similar to those discussed with respect to fig. 1A and 1B, and thus the formation methods and materials will not be described again.

Referring to fig. 17A and 17B, fig. 17B is a sectional view taken along line B-B of fig. 17A. A gate dielectric layer 122 and a dummy gate layer 124 are sequentially formed over the substrate 100. The gate dielectric layer 122 and the dummy gate layer 124 are similar to those discussed with reference to fig. 2A and 2B, and thus the formation method and materials will not be described again.

Referring to fig. 18A and 18B, fig. 18B is a sectional view taken along line B-B of fig. 18A. The gate dielectric layer 122 and the dummy gate layer 124 are patterned to form a gate dielectric 123 and a dummy gate 125 such that portions of the semiconductor fin 102 and the isolation structure 105 are exposed. The patterned gate dielectric layer 122 and the dummy gate layer 124 are similar to those discussed in fig. 3A and 3B, and thus, the related details will not be repeated.

Referring to fig. 19A and 19B, fig. 19B is a sectional view taken along line B-B of fig. 19A. Gate spacers 135 are formed on opposing sidewalls of dummy gate structure 120. Gate spacers 135 are similar to those discussed with respect to fig. 5A and 5B, and thus the formation methods and materials will not be described again.

Referring to fig. 20A and 20B, fig. 20B is a sectional view taken along line B-B of fig. 20A. An interlayer dielectric layer 140 is formed next to the gate spacers 135. The interlayer dielectric layer 140 is similar to that discussed with respect to fig. 6A and 6B, and thus the formation methods and materials will not be described again.

Referring to fig. 21A and 21B, fig. 21B is a sectional view taken along line B-B of fig. 21A. The interlayer dielectric layer 140 is patterned to form a plurality of first openings O2 and expose the semiconductor fin 102 and the isolation structure. The patterned interlayer dielectric layer 140 is similar to that discussed with reference to fig. 7A and 7B, and thus, the details thereof will not be repeated.

Referring to fig. 22A and 22B, fig. 22B is a sectional view taken along line B-B of fig. 22A. The semiconductor fin 102 is etched to form a plurality of recesses R1 in the isolation structure 105. In detail, the etching process removes portions of the semiconductor fin 102 exposed outside of the dummy gate structure 120 and the gate spacers 135. In some embodiments, the etching process includes dry etching, wet etching, or a combination thereof.

Referring to fig. 23A and 23B, fig. 23B is a sectional view taken along line B-B of fig. 23A. A plurality of two-dimensional material layers 190 are formed within the first opening O2 and the recess R1. In some embodiments, the two-dimensional material layer 190 may be formed by, for example, depositing a two-dimensional material in the first opening O2 and the recess R1, and then performing a CMP process to remove excess two-dimensional material until the upper surface of the dummy gate structure 120 is exposed. In some embodiments, the thickness of the two-dimensional material layer 190 is greater than about 2.5nm, i.e., equal to or greater than three single layers of platinum diselenide, such that the platinum diselenide has a semi-metallic characteristic, as discussed above with reference to fig. 1A to 15, and further details thereof will not be repeated.

Referring to fig. 24A and 24B, fig. 24B is a sectional view taken along line B-B of fig. 24A. The two-dimensional material layer 190 is etched back to form a second opening O3 in the interlayer dielectric layer 140. Etching back the two-dimensional material layer 190 includes dry etching, wet etching, or a combination thereof. In some embodiments, the etchant has a faster etch rate for the two-dimensional material layer 190 than the interlayer dielectric layer 140, the gate spacers 135, and the dummy gate structure 120. In some embodiments, an additional mask (e.g., photoresist) may be used to protect the interlayer dielectric layer 140, the gate spacers 135, and the dummy gate structures 120 during the etch back of the two-dimensional material layer 190, and may be removed after etching, for example, by plasma ashing.

In fig. 24B, each remaining two-dimensional material layer 190 has a thickness T5. As discussed above in fig. 1A-15, the two-dimensional material layer 190 is comprised of undoped platinum diselenide, wherein the thickness T5 of the two-dimensional material layer 190 is greater than about 2.5nm, i.e., equal to or greater than three monolayers of platinum diselenide, such that the two-dimensional material layer 190 has semi-metallic properties. Accordingly, the remaining two-dimensional material layer 190 may be referred to as a source/drain structure 190. If the two-dimensional material layer 190 is etched back to a thickness of less than about 2.5nm, the remaining two-dimensional material layer 190 may become a semiconductor feature, and may not be used as a source/drain structure in a final product. In other words, the performing of the etch-back process thins the two-dimensional material layer 190, but stops before the thickness T5 of the two-dimensional material layer 190 is less than about 2.5nm (e.g., the two-dimensional material layer 190 is less than three monolayers). The stopping point of the etch-back can be determined by, for example, a time module.

In fig. 24A, each remaining two-dimensional material layer 190 has a portion 190A embedded in the isolation structure 105, wherein the portion 190A extends along sidewalls of the isolation structure 105. In some embodiments, the bottom surface of portion 190A, i.e., the bottom-most surface of two-dimensional material layer 190, is lower than the bottom surfaces of dummy gate structure 120, gate spacer 135, and interlayer dielectric layer 140. On the other hand, in fig. 24B, a portion of the semiconductor fin 102 remains under the dummy gate structure 120 and the gate spacers 135 and will be the channel region of the final product, while the two-dimensional material layer 190 (or source/drain structures 190) extends along the sidewalls of the semiconductor fin 102.

Referring to fig. 25A and 25B, fig. 25B is a sectional view taken along line B-B of fig. 25A. The interlayer dielectric layer 160 is formed within the second opening O3. The interlayer dielectric layer 160 is similar to that discussed in fig. 9A and 9B, and thus the formation methods and materials will not be described again.

Referring to fig. 26A and 26B, fig. 26B is a sectional view taken along line B-B of fig. 26A. Dummy gate structure 120 is replaced with metal gate structure 170. In some embodiments, metal gate structure 170 includes a gate dielectric layer 172, a work function metal layer 174 over gate dielectric layer 172, and a gate electrode 176 over work function metal layer 174. The metal gate structure 170 is similar to that discussed with respect to fig. 10A and 10B, and thus the formation methods and materials will not be described again.

Referring to fig. 27A and 27B, fig. 27B is a sectional view taken along line B-B of fig. 27A. A plurality of source/drain contacts 180 are formed in the interlayer dielectric layer 160. The source/drain contacts 180 are similar to those discussed with respect to fig. 11A and 11B, and thus the formation methods and materials will not be described again.

Fig. 28 illustrates a method M2 for fabricating a semiconductor device according to some embodiments of the present disclosure. Although method M2 is described as a series of acts or steps, it should be understood that the method is not limited by the acts or the order of acts. Thus, in some embodiments, these operations or steps may be performed in a different order, and/or simultaneously. In addition, in some embodiments, a described operation or step may be divided into multiple operations or steps, which may be performed at different times or at the same time with other operations or sub-operations. In some embodiments, described operations or steps may be omitted, or other operations or steps not described may be included.

In block S201, a semiconductor fin is formed over a substrate, and an isolation structure is formed over the substrate and adjacent to the semiconductor fin. Fig. 16A and 16B depict some embodiments of block S201.

In block S202, a gate dielectric and a dummy gate layer are sequentially formed over a substrate. Fig. 17A and 17B depict some embodiments of block S202.

In block S203, the gate dielectric and the dummy gate layer are patterned to form a dummy gate structure. Fig. 18A and 18B depict some embodiments of block S103.

In block S204, gate spacers are formed on opposing sidewalls of the dummy gate structure. Fig. 19A and 19B depict some embodiments of block S204.

At block S205, a first interlayer dielectric layer is formed next to the gate spacers. Fig. 20A and 20B depict some embodiments of block S206.

At block S206, a plurality of openings are formed in the first interlayer dielectric layer to expose the semiconductor fins and the isolation structures. Fig. 21A and 21B depict some embodiments of block S206.

In block S207, the semiconductor fin is etched to form a plurality of recesses in the isolation structure. Fig. 22A and 22B depict some embodiments of block S207.

In block S208, a plurality of two-dimensional material layers are formed in the openings and the recesses, respectively. Fig. 23A and 23B depict some embodiments of block S208.

In block S209, the two-dimensional material layer is etched back to form a plurality of second openings in the first interlayer dielectric layer. Fig. 24A and 24B depict some embodiments of block S209.

In block S210, a second interlayer dielectric layer is formed in the second opening. Fig. 25A and 25B depict some embodiments of block S210.

In block S211, the dummy gate structure is replaced with a metal gate structure. Fig. 26A and 26B depict some embodiments of block S211.

In block S212, a plurality of source/drain contacts are formed in the second interlayer dielectric layer. Fig. 27A and 27B depict some embodiments of block S212.

From the above discussion, it can be seen that some embodiments of the present disclosure provide advantages. It is to be understood, however, that these embodiments may provide additional advantages, and that not all advantages need be discussed herein, and that not all embodiments have a particular advantage. One advantage is that the source/drain structure of the semiconductor device is formed of a two-dimensional material having half-metallic characteristics with conduction and valence bands at asymmetric K-points. Since the tunneling effect between the semi-metal source/drain structures is less likely to occur than that of the epitaxial source/drain structures, the short channel effect of the semiconductor device of the present disclosure can be suppressed, and thus the sub-threshold slope can be reduced. Another advantage is that the resistance of the semi-metal source/drain structure is lower than that of the epitaxial source/drain structure, and the contact resistance between the semi-metal source/drain structure and the source/drain contact is also reduced, so that the device performance can be improved.

According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a gate structure, a semi-metal source/drain structure, and source/drain contacts. The gate structure is located above the substrate. The semi-metal source/drain electrode structure is positioned on two opposite sides of the grid electrode structure, wherein the energy band structure of the semi-metal source/drain electrode structure is provided with a valence band and a conduction band which are positioned on an asymmetric K point. Source/drain contacts are respectively located over the upper surface of the semi-metal source/drain structure.

According to some embodiments, the semiconductor component further comprises a layer of a semi-metallic two-dimensional material between the gate structure and the substrate.

According to some embodiments, wherein the semi-metallic source/drain structure and the semi-metallic two-dimensional material layer are comprised of the same material.

According to some embodiments, the thickness of the layer of semi-metallic two-dimensional material is less than the thickness of one of the semi-metallic source/drain structures.

According to some embodiments, wherein the bottom surface of the semi-metal source/drain structure and the bottom surface of the semi-metal two-dimensional material layer are collinear.

According to some embodiments, wherein the metallic two-dimensional material layer comprises less than three monolayers of platinum diselenide.

According to some embodiments, each of the semi-metal source/drain structures includes no less than three monolayers of platinum diselenide.

According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a gate structure, a gate spacer, a first two-dimensional material layer, a second two-dimensional material layer, a third two-dimensional material layer, and a metal contact. The gate structure is located above the substrate. The gate spacers are located on two opposite sidewalls of the gate structure. The first two-dimensional material layer extends between the gate structure and the substrate. The second two-dimensional material layer has a first portion extending laterally from the first two-dimensional material layer to below the gate spacer and a second portion extending laterally from the first portion to beyond the gate spacer. The third two-dimensional material layer is over a second portion of the second two-dimensional material layer, wherein a total thickness of the third two-dimensional material layer and the second portion of the second two-dimensional material layer is greater than a thickness of the first two-dimensional material layer. A metal contact is over the third two-dimensional material layer.

According to some embodiments, the thickness of the second two-dimensional material layer is the same as the thickness of the first two-dimensional material layer.

According to some embodiments, the thickness of the third two-dimensional material layer is greater than the thickness of the first two-dimensional material layer.

According to some embodiments, the first, second and third two-dimensional material layers are comprised of platinum diselenide.

According to some embodiments, the first two-dimensional material layer has a larger energy gap than a combination of the third two-dimensional material layer and the second portion of the second two-dimensional material layer.

According to some embodiments, a total thickness of the third two-dimensional material layer and the second portion of the second two-dimensional material layer is equal to or greater than about 2.5 nm.

According to some embodiments, wherein the third two-dimensional material layer extends along sidewalls of the gate spacers.

According to some embodiments, a topmost surface of the gate spacer is higher than a top surface of the third two-dimensional material layer.

According to some embodiments of the present disclosure, a method includes forming a semiconductor fin protruding above a substrate. A first two-dimensional material layer is formed across the semiconductor fin. Depositing a gate material layer over the first two-dimensional material layer. The gate material layer and the first two-dimensional material layer are etched to form a gate structure and a patterned first two-dimensional material layer located below the gate structure. And laterally growing a second two-dimensional material layer from the patterned first two-dimensional material layer. After laterally growing the second two-dimensional material layer, gate spacers are formed on opposing sidewalls of the gate structure. After forming the gate spacers, a layer of a third two-dimensional material is formed over the layer of the second two-dimensional material at least until the combination of the layer of the third two-dimensional material and the layer of the second two-dimensional material comprises more than three or more monolayers of platinum diselenide.

According to some embodiments, wherein laterally growing the layer of the second two-dimensional material is performed such that the second two-dimensional material surrounds a region of the semiconductor fin exposed outside of the gate structure.

According to some embodiments, wherein laterally growing the second two-dimensional material is performed such that the second two-dimensional material extends along a top surface of the shallow trench isolation structure surrounding the semiconductor fin.

According to some embodiments, removing the gate structure from over the patterned first two-dimensional material layer is also included. After removing the gate structure, a metal gate structure is formed over the patterned first two-dimensional material layer.

According to some embodiments, forming source/drain contacts over the third two-dimensional layer of material is also included.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.