阅读说明：本技术 平面型碳化硅逆阻mosfet器件及其制备方法 (Planar silicon carbide reverse-resistance MOSFET device and preparation method thereof ) 是由 张金平 王鹏蛟 陈伟 刘竞秀 张波 于 2020-12-29 设计创作，主要内容包括：本发明属于功率半导体器件技术领域,具体涉及一种平面型碳化硅逆阻MOSFET器件及其制备方法。本发明相对于传统的平面型碳化硅MOSFET,去掉了其N型碳化硅衬底,在器件源区一侧引入了第一N型碳化硅缓冲层,在器件漏区一侧引入了第二N型碳化硅缓冲层,并且在器件漏区一侧引入了结型肖特基势垒二极管结构。所述器件结构可以使平面型碳化硅MOSFET在获得大的正反向对称耐压的同时,具有较小的正向导通压降。此外,为了进一步提升器件耐压以及导通特性,给出了几种相应的衍生结构。(The invention belongs to the technical field of power semiconductor devices, and particularly relates to a planar silicon carbide reverse-resistance MOSFET device and a preparation method thereof. Compared with the traditional planar silicon carbide MOSFET, the N-type silicon carbide substrate of the planar silicon carbide MOSFET is removed, the first N-type silicon carbide buffer layer is introduced to one side of the source region of the device, the second N-type silicon carbide buffer layer is introduced to one side of the drain region of the device, and the junction Schottky barrier diode structure is introduced to one side of the drain region of the device. The device structure can enable the planar silicon carbide MOSFET to obtain large forward and reverse symmetrical voltage resistance and simultaneously have small forward conduction voltage drop. In addition, in order to further improve the voltage resistance and the conduction characteristic of the device, a plurality of corresponding derivative structures are provided.)

1. A planar silicon carbide reverse-resistance MOSFET device, the cellular structure of which comprises: the back drain metal (1), the second N-type silicon carbide buffer layer (21), the N-type silicon carbide epitaxial layer (3) and the first N-type silicon carbide buffer layer (11) are sequentially stacked from bottom to top; the first N-type silicon carbide buffer layer (11) is provided with a first P-type silicon carbide base region (4) and a second P-type silicon carbide base region (41); the lower part of the first N-type silicon carbide buffer layer (11) is connected with the N-type silicon carbide epitaxial layer (3), and the upper part of the first N-type silicon carbide buffer layer (11) separates the first P-type silicon carbide base region (4) from the second P-type silicon carbide base region (41); the first P-type silicon carbide base region (4) is provided with a first P-type silicon carbide source region (5) and a first N-type silicon carbide source region (7); the first P-type silicon carbide source region (5) is connected with the first N-type silicon carbide source region (7) left and right; the second P-type silicon carbide base region (41) is provided with a second P-type silicon carbide source region (51) and a second N-type silicon carbide source region (71); the second P-type silicon carbide source region (51) is connected with the second N-type silicon carbide source region (71) left and right; a gate dielectric layer (10) is arranged above the first P-type silicon carbide base region (4), the second P-type silicon carbide base region (41) and the first N-type silicon carbide buffer layer (11); a grid electrode (9) is arranged above the grid dielectric layer (10); the first source metal (6) is vertically connected with the first P-type silicon carbide source region (5) and part of the first N-type silicon carbide source region (7) and forms ohmic contact; the second source metal (61) is connected with the second P-type silicon carbide source region (51) and part of the second N-type silicon carbide source region (71) up and down and forms ohmic contact;

the method is characterized in that: the second N-type silicon carbide buffer layer (21) is provided with non-adjacent P-type regions (12); ohmic contact (13) is formed between the lower part of the P-type region (12) and the back drain metal (1); a Schottky contact (14) is formed between the second N-type silicon carbide buffer layer (21) and the back drain metal (1).

2. A planar silicon carbide reverse-resistance MOSFET device, the cellular structure of which comprises: the back drain metal (1), the second N-type silicon carbide buffer layer (21), the N-type silicon carbide epitaxial layer (3) and the first N-type silicon carbide buffer layer (11) are sequentially stacked from bottom to top; the first N-type silicon carbide buffer layer (11) is provided with a first P-type silicon carbide base region (4) and a second P-type silicon carbide base region (41); the lower part of the first N-type silicon carbide buffer layer (11) is connected with the N-type silicon carbide epitaxial layer (3), and the upper part of the first N-type silicon carbide buffer layer (11) separates the first P-type silicon carbide base region (4) from the second P-type silicon carbide base region (41); the first P-type silicon carbide base region (4) is provided with a first P-type silicon carbide source region (5) and a first N-type silicon carbide source region (7); the first P-type silicon carbide source region (5) is connected with the first N-type silicon carbide source region (7) left and right; the second P-type silicon carbide base region (41) is provided with a second P-type silicon carbide source region (51) and a second N-type silicon carbide source region (71); the second P-type silicon carbide source region (51) is connected with the second N-type silicon carbide source region (71) left and right; a gate dielectric layer (10) is arranged above the first P-type silicon carbide base region (4), the second P-type silicon carbide base region (41) and the first N-type silicon carbide buffer layer (11); a grid electrode (9) is arranged above the grid dielectric layer (10); the first source metal (6) is vertically connected with the first P-type silicon carbide source region (5) and part of the first N-type silicon carbide source region (7) and forms ohmic contact; the second source metal (61) is connected with the second P-type silicon carbide source region (51) and part of the second N-type silicon carbide source region (71) up and down and forms ohmic contact;

the method is characterized in that: the second N-type silicon carbide buffer layer (21) is provided with unconnected P-type floating zones (17); the lower part of the P-type floating empty area (17) is not in contact with the back drain metal (1), and the P-type floating empty area completely floats in the second N-type silicon carbide buffer layer (21); a Schottky contact is formed between the second N-type silicon carbide buffer layer (21) and the back drain metal (1).

3. A planar silicon carbide reverse-resistance MOSFET device according to claim 1 or 2, wherein: the N-type silicon carbide epitaxial layer (3) is replaced by a P column (31) and an N column (32).

4. A planar silicon carbide reverse-resistance MOSFET device according to claim 1 or 2, wherein: and first P-type buried layers (15) are arranged right below, at the left lower side and at the right lower side of the first N-type silicon carbide buffer layer (11).

5. The planar silicon carbide reverse-resistance MOSFET device of claim 4, wherein: and a second P-type buried layer (18) is arranged in the first N-type silicon carbide buffer layer (11).

6. A planar silicon carbide reverse-resistance MOSFET device according to claim 1, 2 or 3, wherein: all silicon carbide materials are replaced by gallium nitride, gallium oxide, boron nitride, silicon materials.

7. The method of manufacturing a planar silicon carbide reverse-resistance MOSFET device according to claim 1, comprising the steps of:

step 1: preparing a second N-type silicon carbide buffer layer (21) on the surface of the N-type silicon carbide substrate (2) by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer (3) on the surface of the second N-type silicon carbide buffer layer (21) by adopting an epitaxial process;

and step 3: preparing a first N-type silicon carbide buffer layer (11) on the surface of the N-type silicon carbide epitaxial layer (3) by adopting an epitaxial process;

and 4, step 4: injecting a P-type semiconductor impurity into one end of the first N-type silicon carbide buffer layer (11) to form a first P-type silicon carbide base region (4) by adopting photoetching and ion injection processes, and injecting a P-type semiconductor impurity into the other end of the first N-type silicon carbide buffer layer (11) to form a second P-type silicon carbide base region (41);

and 5: injecting P-type semiconductor impurities into the first P-type silicon carbide base region (4) to form a first P-type source region (5), injecting N-type semiconductor impurities to form a first N-type source region (7), injecting P-type semiconductor impurities into the second P-type base region (41) to form a second P-type source region (51), and injecting N-type semiconductor impurities to form a second N-type source region (71) by adopting photoetching and ion injection processes;

step 6: preparing a gate dielectric layer (10) on the surfaces of the first P-type silicon carbide base region (4), the second P-type silicon carbide base region (41) and the first N-type silicon carbide buffer layer (11) by adopting a thermal oxidation process;

and 7: preparing a grid (9) on the surface of the grid dielectric layer (10) by adopting a deposition and etching process;

and 8: turning over the silicon wafer, and removing the N-type silicon carbide substrate (2) by adopting a grinding process;

and step 9: manufacturing nonadjacent P-type regions (12) in the second N-type silicon carbide buffer layer (21) by adopting photoetching and ion implantation processes;

step 10: preparing a first source metal (6) and a second source metal (61) by adopting an evaporation or sputtering process and an etching process;

step 11: and preparing the back drain metal (1) by adopting an evaporation or sputtering process and an etching process, forming Schottky contact between the back drain metal (1) and the second N-type silicon carbide buffer layer (21), and forming ohmic contact between the back drain metal (1) and the P-type region (12).

8. The method of manufacturing a planar silicon carbide reverse-resistance MOSFET device according to claim 2, comprising the steps of:

step 1: preparing a second N-type silicon carbide buffer layer (21) on the surface of the N-type silicon carbide substrate (2) by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer (3) on the surface of the second N-type silicon carbide buffer layer (21) by adopting an epitaxial process;

and step 3: preparing a first N-type silicon carbide buffer layer (11) on the surface of the N-type silicon carbide epitaxial layer (3) by adopting an epitaxial process;

and 4, step 4: injecting a P-type semiconductor impurity into one end of the first N-type silicon carbide buffer layer (11) to form a first P-type silicon carbide base region (4) by adopting photoetching and ion injection processes, and injecting a P-type semiconductor impurity into the other end of the first N-type silicon carbide buffer layer (11) to form a second P-type silicon carbide base region (41);

and 5: injecting P-type semiconductor impurities into the first P-type silicon carbide base region (4) to form a first P-type source region (5) and injecting N-type semiconductor impurities to form a first N-type source region (7) by adopting photoetching and ion injection processes; injecting P-type semiconductor impurities into the second P-type base region (41) to form a second P-type source region (51), and injecting N-type semiconductor impurities to form a second N-type source region (71);

step 6: preparing a gate dielectric layer (10) on the surfaces of the first P-type silicon carbide base region (4), the second P-type silicon carbide base region (41) and the first N-type silicon carbide buffer layer (11) by adopting a thermal oxidation process;

and 7: preparing a grid (9) on the surface of the grid dielectric layer (10) by adopting a deposition and etching process;

and 8: turning over the silicon wafer, and removing the N-type silicon carbide substrate (2) by adopting a grinding process;

and step 9: manufacturing nonadjacent P-type floating empty regions (17) in the second N-type silicon carbide buffer layer (21) by adopting photoetching and ion implantation processes;

step 10: preparing a first source metal (6) and a second source metal (61) by adopting an evaporation or sputtering process and an etching process;

step 11: and preparing the back drain metal (1) by adopting an evaporation or sputtering process and an etching process, and forming Schottky contact between the back drain metal (1) and the second N-type silicon carbide buffer layer (21).

Technical Field

The invention belongs to the technical field of power semiconductor devices, and particularly relates to a planar silicon carbide reverse-resistance MOSFET device and a preparation method thereof.

Background

The inverter is a device for converting direct current into alternating current, and has a wide application range, such as a photovoltaic inverter, an uninterruptible power supply, a rail transit and trolley bus, a frequency converter and the like. The multi-level inverter has the excellent characteristics of low loss, low noise, output waveform close to a sine wave and the like, so that the application scene of the multi-level inverter is wider. The matrix inverter is a novel power converter, and can directly realize alternating current-alternating current conversion. Compared with the traditional alternating current-direct current-alternating current frequency conversion mode, the matrix inverter does not need a direct current capacitor for intermediate energy storage, the reliability of the whole system is improved, and the cost is reduced.

Bidirectional switches with forward and reverse conduction capability and blocking capability are core devices of multilevel inverters and matrix inverters. A reverse-blocking type insulated gate bipolar transistor (RB-IGBT) is a novel IGBT with bidirectional blocking capability, and two RB-IGBTs are reversely connected in parallel to form a bidirectional switch. Compared with the conventional bidirectional switch which is generally composed of two ordinary IGBTs and two fast recovery diodes, the bidirectional switch composed of RB-IGBTs has fewer elements and lower conduction loss. The conventional RB-IGBT generally adopts a non-punch-through (NPT) structure, which has a long IGBT drift region, and thus has a severe current tail and a large turn-off loss. How to reduce the power loss of the bidirectional switch is one of the current research hotspots.

Silicon carbide, which is one of typical representatives of the third-generation semiconductor materials, has excellent characteristics such as a large forbidden band width, a high electron saturation drift velocity, and a high thermal conductivity. Compared with the IGBT with the same voltage-resistant grade, the silicon carbide MOSFET has lower on-voltage drop and turn-off loss. Therefore, if the silicon carbide MOSFET can realize bidirectional blocking, its performance is much superior to that of the RB-IGBT. Fig. 1 shows a conventional planar silicon carbide MOSFET with a large forward blocking capability and a low on-state voltage drop. However, this structure does not have reverse blocking capability.

Disclosure of Invention

The invention aims to solve the problems of how to enable a planar silicon carbide MOSFET to have large forward and reverse symmetrical voltage resistance and how to reduce the conduction voltage drop of the planar silicon carbide MOSFET. Conventional planar silicon carbide MOSFETs, as shown in fig. 1, do not have reverse blocking capability. The invention provides two technical schemes. Technical solution 1 as shown in fig. 2, in the present technical solution, a silicon carbide substrate in a conventional planar silicon carbide MOSFET structure is removed, a first N-type silicon carbide buffer layer is introduced at a source region side, a second N-type silicon carbide buffer layer is introduced at a drain region side, and a junction barrier schottky diode structure (JBS) is introduced at a drain region side. The device structure enables the planar silicon carbide MOSFET to have reverse blocking capability and obtain lower forward conduction voltage drop. Technical solution 2 as shown in fig. 3, in the technical solution 2, a silicon carbide substrate in a conventional planar silicon carbide MOSFET structure is also removed, a first N-type silicon carbide buffer layer is introduced on a source region side, and a second N-type silicon carbide buffer layer is introduced on a drain region side, which is different from the technical solution 1 in a back structure of the device. The technical scheme also enables the planar silicon carbide MOSFET to have reverse blocking capability and obtain lower forward conduction voltage drop. In addition, the invention also provides a preparation method of the device in the two technical schemes, and the preparation method is simple and controllable in manufacturing process and strong in compatibility with the existing process.

In order to achieve the purpose, the technical scheme of the invention is as follows:

scheme one

A planar silicon carbide reverse-resistance MOSFET device, the cellular structure of which comprises: the back drain metal 1, the second N-type silicon carbide buffer layer 21, the N-type silicon carbide epitaxial layer 3 and the first N-type silicon carbide buffer layer 11 are sequentially stacked from bottom to top; the first N-type silicon carbide buffer layer 11 is provided with a first P-type silicon carbide base region 4 and a second P-type silicon carbide base region 41; the lower part of the first N-type silicon carbide buffer layer 11 is connected with the N-type silicon carbide epitaxial layer 3, and the upper part of the first N-type silicon carbide buffer layer 11 separates the first P-type silicon carbide base region 4 from the second P-type silicon carbide base region 41; the first P-type silicon carbide base region 4 is provided with a first P-type silicon carbide source region 5 and a first N-type silicon carbide source region 7; the first P-type silicon carbide source region 5 is connected with the first N-type silicon carbide source region 7 left and right; the second P-type silicon carbide base region 41 is provided with a second P-type silicon carbide source region 51 and a second N-type silicon carbide source region 71; the second P-type silicon carbide source region 51 is connected with the second N-type silicon carbide source region 71 left and right; a gate dielectric layer 10 is arranged above the first P-type silicon carbide base region 4, the second P-type silicon carbide base region 41 and the first N-type silicon carbide buffer layer 11; a grid electrode 9 is arranged above the grid dielectric layer 10; the first source metal 6 is vertically connected with the first P-type silicon carbide source region 5 and part of the first N-type silicon carbide source region 7 and forms ohmic contact; the second source metal 61 is vertically connected with the second P-type silicon carbide source region 51 and part of the second N-type silicon carbide source region 71, and forms ohmic contact;

the second N-type silicon carbide buffer layer 21 is provided with non-adjacent P-type regions 12; ohmic contact 13 is formed between the lower part of the P-type region 12 and the back drain metal 1; a schottky contact 14 is formed between the second N-type silicon carbide buffer layer 21 and the back drain metal 1.

Preferably, the N-type silicon carbide epitaxial layer 3 is replaced with P pillars 31 and N pillars 32.

Preferably, the first P-type buried layer 15 is provided directly below, below the left, and below the right of the first N-type silicon carbide buffer layer 11.

Preferably, the second P-type buried layer 18 is provided inside the first N-type silicon carbide buffer layer 11.

Preferably, all silicon carbide materials are replaced by gallium nitride, gallium oxide, boron nitride, silicon materials.

The invention also provides a preparation method of the planar silicon carbide reverse resistance MOSFET device, which comprises the following preparation steps:

step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;

and step 3: preparing a first N-type silicon carbide buffer layer 11 on the surface of the N-type silicon carbide epitaxial layer 3 by adopting an epitaxial process;

and 4, step 4: injecting a P-type semiconductor impurity into one end of the first N-type silicon carbide buffer layer 11 to form a first P-type silicon carbide base region 4 and injecting a P-type semiconductor impurity into the other end of the first N-type silicon carbide buffer layer to form a second P-type silicon carbide base region 41 by adopting photoetching and ion injection processes;

and 5: and injecting P-type semiconductor impurities into the first P-type silicon carbide base region 4 to form a first P-type source region 5 and injecting N-type semiconductor impurities to form a first N-type source region 7 by adopting photoetching and ion injection processes. A second P-type source region 51 is formed by implanting P-type semiconductor impurities into the second P-type base region 41, and a second N-type source region 71 is formed by implanting N-type semiconductor impurities.

Step 6: preparing a gate dielectric layer 10 on the surfaces of the first P-type silicon carbide base region 4, the second P-type silicon carbide base region 41 and the first N-type silicon carbide buffer layer 11 by adopting a thermal oxidation process;

and 7: preparing a grid 9 on the surface of the grid dielectric layer 10 by adopting a deposition and etching process;

and 8: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;

and step 9: manufacturing nonadjacent P-type regions 12 in the second N-type silicon carbide buffer layer 21 by adopting photoetching and ion implantation processes;

step 10: preparing a first source metal 6 and a second source metal 61 by adopting an evaporation or sputtering process and an etching process;

step 11: and preparing the back drain metal 1 by adopting an evaporation or sputtering process and an etching process, forming Schottky contact between the back drain metal 1 and the second N-type silicon carbide buffer layer 21, and forming ohmic contact between the back drain metal 1 and the P-type region 12.

Scheme II

A planar silicon carbide reverse-resistance MOSFET device, the cellular structure of which comprises: the back drain metal 1, the second N-type silicon carbide buffer layer 21, the N-type silicon carbide epitaxial layer 3 and the first N-type silicon carbide buffer layer 11 are sequentially stacked from bottom to top; the first N-type silicon carbide buffer layer 11 is provided with a first P-type silicon carbide base region 4 and a second P-type silicon carbide base region 41; the lower part of the first N-type silicon carbide buffer layer 11 is connected with the N-type silicon carbide epitaxial layer 3, and the upper part of the first N-type silicon carbide buffer layer 11 separates the first P-type silicon carbide base region 4 from the second P-type silicon carbide base region 41; the first P-type silicon carbide base region 4 is provided with a first P-type silicon carbide source region 5 and a first N-type silicon carbide source region 7; the first P-type silicon carbide source region 5 is connected with the first N-type silicon carbide source region 7 left and right; the second P-type silicon carbide base region 41 is provided with a second P-type silicon carbide source region 51 and a second N-type silicon carbide source region 71; the second P-type silicon carbide source region 51 is connected with the second N-type silicon carbide source region 71 left and right; a gate dielectric layer 10 is arranged above the first P-type silicon carbide base region 4, the second P-type silicon carbide base region 41 and the first N-type silicon carbide buffer layer 11; a grid electrode 9 is arranged above the grid dielectric layer 10; the first source metal 6 is vertically connected with the first P-type silicon carbide source region 5 and part of the first N-type silicon carbide source region 7 and forms ohmic contact; the second source metal 61 is vertically connected with the second P-type silicon carbide source region 51 and part of the second N-type silicon carbide source region 71, and forms ohmic contact;

the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type floating areas 17; the lower part of the P-type floating empty region 17 is not contacted with the back drain metal 1, and the P-type floating empty region completely floats in the second N-type silicon carbide buffer layer 21; a schottky contact is formed between the second N-type silicon carbide buffer layer 21 and the back drain metal 1.

Preferably, the N-type silicon carbide epitaxial layer 3 is replaced with P pillars 31 and N pillars 32.

Preferably, the first P-type buried layer 15 is provided directly below, below the left, and below the right of the first N-type silicon carbide buffer layer 11.

Preferably, the second P-type buried layer 18 is provided inside the first N-type silicon carbide buffer layer 11.

Preferably, all silicon carbide materials are replaced by gallium nitride, gallium oxide, boron nitride, silicon materials.

The invention also provides a preparation method of the planar silicon carbide reverse resistance MOSFET device, which comprises the following preparation steps:

step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;

and step 3: preparing a first N-type silicon carbide buffer layer 11 on the surface of the N-type silicon carbide epitaxial layer 3 by adopting an epitaxial process;

and 4, step 4: injecting a P-type semiconductor impurity into one end of the first N-type silicon carbide buffer layer 11 to form a first P-type silicon carbide base region 4 and injecting a P-type semiconductor impurity into the other end of the first N-type silicon carbide buffer layer to form a second P-type silicon carbide base region 41 by adopting photoetching and ion injection processes;

and 5: and injecting P-type semiconductor impurities into the first P-type silicon carbide base region 4 to form a first P-type source region 5 and injecting N-type semiconductor impurities to form a first N-type source region 7 by adopting photoetching and ion injection processes. A second P-type source region 51 is formed by implanting P-type semiconductor impurities into the second P-type base region 41, and a second N-type source region 71 is formed by implanting N-type semiconductor impurities.

Step 6: preparing a gate dielectric layer 10 on the surfaces of the first P-type silicon carbide base region 4, the second P-type silicon carbide base region 41 and the first N-type silicon carbide buffer layer 11 by adopting a thermal oxidation process;

and 7: preparing a grid 9 on the surface of the grid dielectric layer 10 by adopting a deposition and etching process;

and 8: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;

and step 9: manufacturing nonadjacent P-type floating empty regions 17 in the second N-type silicon carbide buffer layer 21 by adopting photoetching and ion implantation processes;

step 10: preparing a first source metal 6 and a second source metal 61 by adopting an evaporation or sputtering process and an etching process;

step 11: the back drain metal 1 is prepared by an evaporation or sputtering process and an etching process, and a schottky contact is formed between the back drain metal 1 and the second N-type silicon carbide buffer layer 21.

Further, for simplicity of description, the device structure and the manufacturing method are described by taking an N-channel MOSFET as an example, but the present invention is also applicable to the manufacturing of a P-channel MOSFET device.

The working principle of the invention is as follows:

a conventional planar silicon carbide MOSFET is shown in fig. 1. During forward operation, a positive voltage is applied to the drain electrode, a negative voltage is applied to the source electrode, the device is started by applying a proper forward bias voltage to the grid electrode, when the device needs to be turned off, the forward bias voltage of the grid electrode is removed, a reverse PN junction formed by the P-type base region and the N-type drift region bears a withstand voltage, the depletion region expands towards the direction of the substrate, and the N-type substrate has high doping concentration, so that the further expansion of the depletion region is prevented, the punch-through of the device is prevented, and the forward withstand voltage is ensured. However, when the MOSFET is turned off in the reverse direction, the conventional planar silicon carbide MOSFET cannot form a voltage-withstanding region, and thus does not have a reverse voltage-withstanding capability.

The invention has two technical schemes of a first scheme and a second scheme, and the basic principles of the two technical schemes are similar, so that only the working principle of the first technical scheme is explained. In the first scheme, a silicon carbide substrate in a traditional planar silicon carbide MOSFET structure is removed, a first N-type silicon carbide buffer layer is introduced on one side of a source region, a second N-type silicon carbide buffer layer is introduced on one side of a drain region, and a junction barrier Schottky diode structure (JBS) is introduced on one side of the drain region, so that a voltage-resistant region can be generated when the silicon carbide MOSFET is turned off in a reverse direction, the silicon carbide MOSFET has reverse blocking capability, and a lower forward conduction voltage drop can be obtained. It is noted that in the present invention, the first N-type silicon carbide buffer layer and the second N-type silicon carbide buffer layer are introduced in a concentration higher than the drift region concentration, but lower than the substrate concentration of the conventional planar silicon carbide MOSFET, in a concentration range of 10¹⁵cm^-3To 10¹⁶cm^-3And the order of magnitude ensures that the device can obtain larger symmetrical voltage resistance.

When the MOSFET device structure is normally conducted, because the Schottky barrier is lower than the PN junction barrier, current can flow through a conducting channel of the Schottky barrier at first, and the device is conductive for many photons, when the device works in the forward direction, the JBS structure is equivalent to the SBD structure, because the Schottky barrier is lower than the barrier of ohmic contact, compared with the traditional planar silicon carbide MOSFET, the device structure can obtain lower MOSFET drain contact resistance, and simultaneously, because the concentrations of the introduced first N-type silicon carbide buffer layer and the second N-type silicon carbide buffer layer are higher than the concentration of a drift region, the conduction voltage drop of the device can be further reduced. When a device passes a large surge current, because a large voltage drop is generated in the N-type silicon carbide by a large transverse current above a P-type silicon carbide/N-type silicon carbide PN junction, the P-type silicon carbide/N-type silicon carbide PN junction on the back is conducted, and a large number of holes are injected into the N-type silicon carbide by the P-type silicon carbide on the back to form local conductance modulation, so that the conduction resistance in the N-type silicon carbide is reduced, the loss of the device is obviously reduced, and the through-current capability of the device is improved, so that the surge current resistance of the device is improved, and the device has high surge current bearing capability.

When forward voltage resistance is achieved, firstly, the PN junction formed by the P-type base region and the first N-type silicon carbide buffer layer carries out voltage resistance, the concentration of the introduced first N-type silicon carbide buffer layer is not very high, so that the depletion region can penetrate through the first N-type silicon carbide buffer layer and continuously extends towards the lower part of the drift region, and when the depletion region reaches the second N-type silicon carbide buffer layer, the concentration of the second N-type silicon carbide buffer layer is higher than that of the drift region, so that the extension of the depletion region can be prevented, and larger forward voltage resistance is guaranteed. When the device reaches the first N-type silicon carbide buffer layer, because the concentration of the first N-type silicon carbide buffer layer is higher than that of the drift region, the expansion of the depletion region is stopped, the punch-through of the device is prevented, and the device is ensured to have larger reverse withstand voltage. Therefore, the device structure has larger forward and reverse symmetrical voltage resistance and smaller forward conduction voltage drop.

The beneficial effects of the invention are as follows:

bidirectional switches are the core devices of multilevel inverters and matrix inverters. Two RB-IGBTs are reversely connected in parallel to form a bidirectional switch, a non-punch-through (NPT) structure is usually adopted for the conventional silicon-based RB-IGBT, and the IGBT drift region of the structure is long, so that the current tailing is serious, and the turn-off loss is large. Compared with a silicon-based IGBT with the same voltage-resistant grade, the silicon carbide MOSFET has lower on-voltage drop and turn-off loss. Compared with a bidirectional switch formed by two silicon-based RB-IGBTs, the bidirectional switch formed by two reverse resistance type silicon carbide MOSFETs has lower conduction voltage drop and higher switching speed, so that the power loss of the bidirectional switch in the application of a multi-level inverter and a matrix inverter is effectively reduced.

Drawings

FIG. 1 is a schematic diagram of a conventional planar silicon carbide MOSFET cell structure;

FIG. 2 is a schematic diagram of a cell structure according to embodiment 1 of the present invention;

FIG. 3 is a schematic diagram of a cell structure according to embodiment 2 of the present invention;

FIG. 4 is a schematic view of a cell according to embodiment 3 of the present invention;

FIG. 5 is a schematic diagram of a cell structure according to embodiment 4 of the present invention;

FIG. 6 is a schematic diagram of a cell structure according to embodiment 5 of the present invention;

FIG. 7 is a schematic diagram of a cell structure according to embodiment 6 of the present invention;

FIG. 8 is a schematic diagram of a cell structure according to embodiment 7 of the present invention;

FIG. 9 is a schematic diagram of a cell structure according to embodiment 8 of the present invention;

FIG. 10 is a schematic diagram of a cell structure according to embodiment 9 of the present invention;

fig. 11 is a schematic structural view after a second N-type silicon carbide buffer layer 21 is formed on the surface of the N-type silicon carbide substrate 2 by an epitaxial process in the production process of embodiment 1 of the present invention;

fig. 12 is a schematic structural view after an N-type silicon carbide epitaxial layer 3 is formed on the surface of the second N-type silicon carbide buffer layer 21 by an epitaxial process in the manufacturing process of embodiment 1 of the present invention;

fig. 13 is a schematic structural view after a first N-type silicon carbide buffer layer 11 is epitaxially formed on the N-type silicon carbide epitaxial layer 3 by an epitaxial process in the production process of embodiment 1 of the present invention;

fig. 14 is a schematic structural diagram after forming the first P-type silicon carbide base region 4 and the second P-type silicon carbide base region 41 in the first N-type silicon carbide buffer layer 11 by photolithography and ion implantation in the manufacturing process of embodiment 1 of the present invention;

fig. 15 is a schematic structural diagram after a first P-type source region 5 and a first N-type source region 7 are formed in the first P-type silicon carbide base region 4 by photolithography and ion implantation in the manufacturing process of embodiment 1 of the present invention, and a second P-type source region 51 and a second N-type source region 71 are formed in the second P-type silicon carbide base region 41;

fig. 16 is a schematic structural view after the gate dielectric layer 10 is formed by a thermal oxidation process in the preparation process of embodiment 1 of the present invention;

fig. 17 is a schematic structural diagram of a gate 9 formed on the surface of the gate dielectric layer 10 by deposition and etching in the manufacturing process of embodiment 1 of the present invention;

fig. 18 is a schematic structural view of a reversed silicon wafer in the manufacturing process of embodiment 1 of the present invention, after the N-type silicon carbide substrate 2 is removed by a grinding process;

fig. 19 is a schematic structural view after the P-type region 12 is formed in the second N-type silicon carbide buffer layer 21 by photolithography and ion implantation in the manufacturing process of embodiment 1 of the present invention;

fig. 20 is a schematic structural view after the first source metal 6 and the second source metal 61 are formed by a deposition process in the manufacturing process of embodiment 1 of the present invention;

fig. 21 is a schematic structural diagram of the embodiment 1 after the back drain metal 1 is formed by a deposition process, a schottky contact is formed between the back drain metal 1 and the second N-type silicon carbide buffer layer 21, and an ohmic contact is formed between the back drain metal and the P-type region 12;

in fig. 1 to 10, 1 is a back drain metal, 2 is an N-type silicon carbide substrate, 21 is a second N-type silicon carbide buffer layer, 3 is an N-type silicon carbide epitaxial layer, 31 is a P column, 32 is an N column, 4 is a first P-type silicon carbide base region, 41 is a second P-type silicon carbide base region, 5 is a first P-type source region, 51 is a second P-type source region, 6 is a first source metal, 61 is a second source metal, 7 is a first N-type source region, 71 is a second N-type source region, 9 is a gate electrode, 10 is a gate dielectric layer, 11 is a first N-type silicon carbide buffer layer, 12 is a P-type region, 13 is an ohmic contact, 14 is a schottky contact, 15 is a first P-type buried layer, 17 is a P-type floating region, and 18 is a second P-type buried layer.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Example 1:

a reverse blocking type silicon carbide MOSFET, the cell structure of which is shown in FIG. 2, comprises: the back drain metal 1, the second N-type silicon carbide buffer layer 21, the N-type silicon carbide epitaxial layer 3 and the first N-type silicon carbide buffer layer 11 are sequentially stacked from bottom to top; the first N-type silicon carbide buffer layer 11 is provided with a first P-type silicon carbide base region 4 and a second P-type silicon carbide base region 41; the lower part of the first N-type silicon carbide buffer layer 11 is connected with the N-type silicon carbide epitaxial layer 3, and the upper part of the first N-type silicon carbide buffer layer 11 separates the first P-type silicon carbide base region 4 from the second P-type silicon carbide base region 41; the first P-type silicon carbide base region 4 is provided with a first P-type silicon carbide source region 5 and a first N-type silicon carbide source region 7; the first P-type silicon carbide source region 5 is connected with the first N-type silicon carbide source region 7 left and right; the second P-type silicon carbide base region 41 is provided with a second P-type silicon carbide source region 51 and a second N-type silicon carbide source region 71; the second P-type silicon carbide source region 51 is connected with the second N-type silicon carbide source region 71 left and right; a gate dielectric layer 10 is arranged above the first P-type silicon carbide base region 4, the second P-type silicon carbide base region 41 and the first N-type silicon carbide buffer layer 11; a grid electrode 9 is arranged above the grid dielectric layer 10; the first source metal 6 is vertically connected with the first P-type silicon carbide source region 5 and part of the first N-type silicon carbide source region 7 and forms ohmic contact; the second source metal 61 is vertically connected with the second P-type silicon carbide source region 51 and part of the second N-type silicon carbide source region 71, and forms ohmic contact;

the second N-type silicon carbide buffer layer 21 is provided with non-adjacent P-type regions 12; ohmic contact 13 is formed between the lower part of the P-type region 12 and the back drain metal 1; a schottky contact 14 is formed between the second N-type silicon carbide buffer layer 21 and the back drain metal 1.

Preferably, all silicon carbide materials are replaced by gallium nitride, gallium oxide, boron nitride, silicon materials.

The embodiment also provides a preparation method of the planar silicon carbide reverse-resistance MOSFET device, which comprises the following preparation steps:

step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;

and step 3: preparing a first N-type silicon carbide buffer layer 11 on the surface of the N-type silicon carbide epitaxial layer 3 by adopting an epitaxial process;

and 4, step 4: injecting a P-type semiconductor impurity into one end of the first N-type silicon carbide buffer layer 11 to form a first P-type silicon carbide base region 4 and injecting a P-type semiconductor impurity into the other end of the first N-type silicon carbide buffer layer to form a second P-type silicon carbide base region 41 by adopting photoetching and ion injection processes;

and 5: and injecting P-type semiconductor impurities into the first P-type silicon carbide base region 4 to form a first P-type source region 5 and injecting N-type semiconductor impurities to form a first N-type source region 7 by adopting photoetching and ion injection processes. A second P-type source region 51 is formed by implanting P-type semiconductor impurities into the second P-type base region 41, and a second N-type source region 71 is formed by implanting N-type semiconductor impurities.

Step 6: preparing a gate dielectric layer 10 on the surfaces of the first P-type silicon carbide base region 4, the second P-type silicon carbide base region 41 and the first N-type silicon carbide buffer layer 11 by adopting a thermal oxidation process;

and 7: preparing a grid 9 on the surface of the grid dielectric layer 10 by adopting a deposition and etching process;

and 8: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;

and step 9: manufacturing nonadjacent P-type regions 12 in the second N-type silicon carbide buffer layer 21 by adopting photoetching and ion implantation processes;

step 10: preparing a first source metal 6 and a second source metal 61 by adopting an evaporation or sputtering process and an etching process;

step 11: and preparing the back drain metal 1 by adopting an evaporation or sputtering process and an etching process, forming Schottky contact between the back drain metal 1 and the second N-type silicon carbide buffer layer 21, and forming ohmic contact between the back drain metal 1 and the P-type region 12.

Example 2:

a reverse blocking type silicon carbide MOSFET, the cell structure of which is shown in fig. 3, the present embodiment is different from embodiment 1 in that: the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type floating areas 17; the lower part of the P-type floating empty region 17 is not contacted with the back drain metal 1, and the P-type floating empty region completely floats in the second N-type silicon carbide buffer layer 21; a schottky contact is formed between the second N-type silicon carbide buffer layer 21 and the back drain metal 1.

Preferably, all silicon carbide materials are replaced by gallium nitride, gallium oxide, boron nitride, silicon materials.

The embodiment also provides a preparation method of the planar silicon carbide reverse-resistance MOSFET device, which comprises the following preparation steps:

step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;

step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;

and step 3: preparing a first N-type silicon carbide buffer layer 11 on the surface of the N-type silicon carbide epitaxial layer 3 by adopting an epitaxial process;

and 4, step 4: injecting a P-type semiconductor impurity into one end of the first N-type silicon carbide buffer layer 11 to form a first P-type silicon carbide base region 4 and injecting a P-type semiconductor impurity into the other end of the first N-type silicon carbide buffer layer to form a second P-type silicon carbide base region 41 by adopting photoetching and ion injection processes;

and 5: and injecting P-type semiconductor impurities into the first P-type silicon carbide base region 4 to form a first P-type source region 5 and injecting N-type semiconductor impurities to form a first N-type source region 7 by adopting photoetching and ion injection processes. A second P-type source region 51 is formed by implanting P-type semiconductor impurities into the second P-type base region 41, and a second N-type source region 71 is formed by implanting N-type semiconductor impurities.

Step 6: preparing a gate dielectric layer 10 on the surfaces of the first P-type silicon carbide base region 4, the second P-type silicon carbide base region 41 and the first N-type silicon carbide buffer layer 11 by adopting a thermal oxidation process;

and 7: preparing a grid 9 on the surface of the grid dielectric layer 10 by adopting a deposition and etching process;

and 8: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;

and step 9: manufacturing nonadjacent P-type floating empty regions 17 in the second N-type silicon carbide buffer layer 21 by adopting photoetching and ion implantation processes;

step 10: preparing a first source metal 6 and a second source metal 61 by adopting an evaporation or sputtering process and an etching process;

step 11: the back drain metal 1 is prepared by an evaporation or sputtering process and an etching process, and a schottky contact is formed between the back drain metal 1 and the second N-type silicon carbide buffer layer 21.

Example 3:

the cell structure of a derivative structure of example 1 is shown in FIG. 4. This embodiment replaces the N-type silicon carbide epitaxial layer 3 in embodiment 1 with the P column 31 and the N column 32, and the rest of the structure is the same as that in embodiment 1.

The super junction MOSFET structure is formed by introducing P column 31 and N column 32 in this embodiment. The specific principle is as follows: when the P column 31 and the N column 32 reach charge balance, the entire drift region can be approximately neutral in the non-charge property to the outside, which makes the drift region concentration and the withstand voltage relatively independent. The embodiment can ensure that the conduction voltage drop of the device can be effectively reduced under the same voltage withstanding grade, and the performance of the device is improved.

Example 4:

the cell structure of a derivative structure of example 1 is shown in FIG. 5. This embodiment introduces the first P-type buried layer 15 directly below, below left, and below right of the first N-type silicon carbide buffer layer 11 in embodiment 1, and the rest of the structure is the same as that in embodiment 1.

In the embodiment, the forward voltage withstanding capability of the device is improved by introducing the P-type buried layer 15. The specific principle is as follows: at the time of forward withstand voltage, a part of electric flux lines starting from the first N-type silicon carbide buffer layer 11 may terminate at the P-type buried layer 15, that is, an electric field at a PN junction formed by the P-type base region 5 and the first N-type silicon carbide buffer layer 11 is reduced, thereby increasing the forward withstand voltage.

Example 5:

the cell structure of a derivative structure of example 1 is shown in FIG. 6. This embodiment is an improvement over embodiment 4, in which a second P-type buried layer 18 is introduced into the first N-type silicon carbide buffer layer 11, and the rest of the structure is the same as that of embodiment 4.

In the embodiment, the P-type buried layer 18 is introduced into the first N-type silicon carbide buffer layer 11 to assist in depleting the first N-type silicon carbide buffer layer 11, so that the peak electric field at the PN junction formed by the P-type base region 5 and the first N-type silicon carbide buffer layer 11 is further reduced, and the forward withstand voltage is further improved.

Example 6:

the cell structure of a derivative structure of example 2 is shown in FIG. 7. This embodiment replaces the N-type silicon carbide epitaxial layer 3 in embodiment 2 with the P column 31 and the N column 32, and the rest of the structure is the same as that in embodiment 2.

The super junction MOSFET structure is formed by introducing P column 31 and N column 32 in this embodiment. The specific principle is as follows: when the P column 31 and the N column 32 reach charge balance, the entire drift region can be approximately neutral in the non-charge property to the outside, which makes the drift region concentration and the withstand voltage relatively independent. The embodiment can ensure that the conduction voltage drop of the device can be effectively reduced under the same voltage withstanding grade, and the performance of the device is improved.

Example 7:

the cell structure of a derivative structure of example 2 is shown in FIG. 8. This embodiment introduces the first P-type buried layer 15 directly below, below left, and below right of the first N-type silicon carbide buffer layer 11 in embodiment 2, and the rest of the structure is the same as embodiment 2.

In the embodiment, the first P-type buried layer 15 is introduced, so that the forward voltage endurance capability of the device is improved. The specific principle is as follows: at the time of forward withstand voltage, a part of the electric field lines starting from the first N-type silicon carbide buffer layer 11 may terminate at the first P-type buried layer 15, that is, the electric field at the PN junction formed by the first P-type base region 5 and the first N-type silicon carbide buffer layer 11 is reduced, thereby increasing the forward withstand voltage.

Example 8:

the cell structure of a derivative structure of example 2 is shown in FIG. 9. This embodiment is an improvement over embodiment 7, in which a second P-type buried layer 18 is introduced into the first N-type silicon carbide buffer layer 11, and the rest of the structure is the same as that of embodiment 7.

In this embodiment, the second P-type buried layer 18 is introduced into the first N-type silicon carbide buffer layer 11 to assist in depleting the first N-type silicon carbide buffer layer 11, so that the peak electric field at the PN junction formed by the first P-type base region 5 and the first N-type silicon carbide buffer layer 11 is further reduced, and the forward withstand voltage is further improved.

Example 9:

the cell structure of a derivative structure of example 2 is shown in FIG. 10. This example is an improvement on example 8. In this embodiment, different types of gold half-contacts are formed between the back drain metal 1 and the second N-type silicon carbide buffer layer 21, i.e., the gold half-contact directly under the P-type floating gate region 17 is a schottky contact as shown in fig. 14, and the other region of the interface between the back drain metal 1 and the second N-type silicon carbide buffer layer 21 is an ohmic contact as shown in fig. 13.

The specific principle is as follows: when conducting in the forward direction, current flows through the Schottky contact with lower potential barrier, so that smaller forward conducting voltage drop is obtained. When reverse withstand voltage, the P-type floating space region 17 and the second N-type silicon carbide buffer layer 21 are in a reverse bias state, and with the continuous increase of reverse bias, the potential difference at the PN junction between the P-type floating space region and the second N-type silicon carbide buffer layer is also continuously increased, so that the depletion region is continuously expanded until the schottky interface is wrapped up in an overlapped mode, the schottky barrier is remarkably inhibited from being reduced, and the leakage current is greatly reduced. In this embodiment, since the barrier of the ohmic contact is higher than the schottky barrier, the leakage current through the P-type floating gap is further reduced, and the withstand voltage of the device is further improved.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.