阅读说明：本技术 使用时域和频域的对电力递送系统的距离保护 (Distance protection for power delivery systems using time and frequency domains ) 是由 波格丹·Z·卡兹腾尼 曼加帕斯劳·文卡塔·迈纳姆 查德博·特洛伊·丹尼尔斯 于 2019-05-23 设计创作，主要内容包括：本文公开了电力递送系统的距离保护,其中使用由频域故障检测监督的时域故障检测来检测保护区域内的故障。当时域操作量和时域极化量的实部或虚部均为正或均为负并且频域操作量和频域极化量之间的角度在预定范围内时,可断言距离故障检测有效。可使用电平检查部、符号一致性检查部或干扰检测器来提供附加安全性。(Distance protection for power delivery systems is disclosed herein in which time domain fault detection supervised by frequency domain fault detection is used to detect faults within a protection area. Distance fault detection may be declared valid when the real or imaginary parts of the time domain manipulated variable and the time domain polarization variable are both positive or both negative and the angle between the frequency domain manipulated variable and the frequency domain polarization variable is within a predetermined range. Additional security may be provided using a level check, symbol consistency check, or interference detector.)

1. A system for determining a fault within a protection area of a power delivery system, comprising:

a signal processor for calculating a frequency domain operation amount and a frequency domain polarization amount;

a frequency domain distance fault detector to:

comparing the frequency domain operation quantity with the frequency domain polarization quantity; and

asserting that a frequency domain fault detection signal is valid when the frequency domain operational quantity and the frequency domain polarization quantity are within a predetermined range of each other;

a time domain distance fault detector to:

calculating a time domain operation quantity;

calculating a time domain polarization quantity;

determining a consistency time with the same sign of the time domain operation quantity and the time domain polarization quantity;

asserting that a time domain fault detection signal is valid when the consistency time reaches a predetermined consistency time threshold; and

asserting a distance fault detection signal valid when the frequency domain fault detection signal is asserted valid and the time domain fault detection signal is asserted valid; and

a monitored equipment interface in communication with the power delivery system to implement a protective action in the power delivery system when the distance fault detection signal is asserted to be valid.

2. The system of claim 1, wherein the temporal distance fault detector is further configured to:

calculating a real part of the frequency domain operation quantity;

calculating a real part of the frequency domain polarization quantity;

determining a consistency time when the signs of the real parts of the frequency domain operation quantity and the frequency domain polarization quantity are the same; and

wherein the time domain fault detection signal is asserted when the coincidence time is the same for the real part of the frequency domain operational quantity and the frequency domain polarization quantity.

3. The system of claim 1, wherein the temporal distance fault detector is further configured to:

calculating an imaginary part of the frequency domain operation quantity;

calculating an imaginary part of the frequency domain polarization quantity;

determining a coincidence time in which the signs of the imaginary parts of the frequency-domain manipulated variable and the frequency-domain polarized variable are the same; and

wherein the time-domain fault detection signal is asserted at the coincidence time when the imaginary parts of the frequency-domain operation quantity and the frequency-domain polarization quantity are the same or at the coincidence time when the real parts of the frequency-domain operation quantity and the frequency-domain polarization quantity are the same.

4. The system of claim 1, wherein the predetermined range of frequency domain distance fault detectors comprises 90 degrees.

5. The system of claim 1, wherein the predetermined consistency time threshold comprises a time associated with one-quarter of a power system cycle.

6. The system of claim 1, wherein the temporal distance fault detector comprises an integration timer for determining the coherence time.

7. The system of claim 6, wherein the frequency domain operation quantity comprises a real part of the frequency domain operation quantity;

and the system further comprises a symbol consistency check section to:

determining when the sign of the real part of the frequency domain operation quantity coincides with the sign of the time domain operation signal; and

signaling the integration timer to integrate down when a sign of a real part of the frequency domain operand coincides with a sign of the time domain operand.

8. The system of claim 1, wherein the frequency domain operation quantity comprises a real part of the frequency domain operation quantity;

and the system further comprises a symbol consistency check section to:

asserting a sign consistency operation signal valid if:

the sign of the real part of the frequency domain operation quantity is consistent with that of the time domain operation quantity; and

wherein the distance fault detection signal is asserted only when the symbol consistency operation signal is asserted.

9. The system of claim 6, wherein the temporal distance fault detector further comprises a level check section to:

determining when a magnitude of the time domain operation quantity exceeds a predetermined minimum operation quantity threshold; and

signaling the integration timer to integrate down when the magnitude of the time domain operation quantity exceeds the predetermined minimum operation signal threshold.

10. The system of claim 1, wherein the temporal distance fault detector further comprises a level check section to:

asserting a level check operation signal valid if:

a magnitude of the time domain operand exceeding a predetermined minimum operand threshold; and

wherein the distance fault detection signal is asserted only when the level check operation signal is asserted.

11. The system of claim 1, further comprising an interference detector to detect a power system interference and output an interference signal when the power system interference is detected.

12. The system of claim 11, wherein the time domain distance fault detector comprises an integration timer for determining the coherence time, and the integration timer resets when the interference signal is asserted.

13. The system of claim 1, further comprising a frequency domain timer having a predetermined frequency domain safety time, wherein the fault detection signal is asserted only if the frequency domain fault detection signal is asserted for the predetermined frequency domain safety time.

14. The system of claim 1, wherein the coherence time comprises a time when the signs of the time-domain operands are the same and the frequency-domain fault detection signal is asserted to be valid.

15. A method for determining a fault within a protection area of a power delivery system, comprising:

calculating, by an intelligent electronic device in communication with the power delivery system, a frequency domain operational quantity;

calculating the polarization quantity of the frequency domain;

calculating a time domain operation quantity;

calculating a time domain polarization quantity;

comparing the frequency domain operation quantity with the frequency domain polarization quantity;

comparing the signs of the time-domain operation quantity and the time-domain polarization quantity;

asserting a distance fault detect signal valid when there is a condition within a predetermined coherency time,

the frequency domain operation amount and the frequency domain polarization amount are within a predetermined range; and

the time domain operation quantity and the time domain polarization quantity have the same sign; and

implementing a protective action in the power delivery system when the fault detection signal is asserted to be valid.

16. The method of claim 15, wherein the predetermined consistency time comprises a time associated with one-quarter of a power system cycle.

17. The method of claim 15, wherein the step of asserting that the fault detection signal is valid comprises asserting being valid when the real part of the frequency domain operational quantity and the real part of the frequency domain polarization quantity are within the predetermined range.

18. The method of claim 15, wherein the step of asserting that the fault detection signal is valid comprises asserting being valid when an imaginary part of the frequency domain operational quantity and an imaginary part of the frequency domain polarization quantity are within the predetermined range.

19. The method of claim 15, further comprising:

determining when a magnitude of the time domain operation quantity exceeds a predetermined minimum operation signal threshold; and

integrating the consistency time downward when the magnitude of the temporal operation amount exceeds the predetermined minimum operation amount threshold.

20. The method of claim, further comprising:

calculating a real part of the frequency domain operation quantity;

comparing the sign of the real part of the frequency domain operation quantity with the sign of the time domain operation quantity; and

asserting the range fault detection signal valid only when a sign of a real part of the frequency domain operand coincides with a sign of the time domain operand.

21. The method of claim 15, further comprising:

detecting a disturbance to the power delivery system; and

upon detection of the interference, the distance fault detection signal is continuously asserted to be valid.

Technical Field

The present disclosure relates to distance protection for power delivery systems using time and frequency domains. More particularly, the present disclosure relates to using time domain principles to determine whether a fault is located within a protected distance region, which is protected by using frequency domain principles. The present disclosure also relates to using both time domain and frequency domain principles to improve the speed and security of protection.

Drawings

Non-limiting and non-exhaustive embodiments of the present disclosure, including various embodiments of the present disclosure, are described with reference to the accompanying drawings, in which:

fig. 1 illustrates a single line diagram of a power delivery system including an Intelligent Electronic Device (IED) implementing distance protection according to several embodiments herein.

Fig. 2 illustrates a simplified block diagram of a comparator within a distance element using time domain and frequency domain principles according to several embodiments herein.

Fig. 3A, 3B, and 3C show simplified block diagrams of the logic of a frequency domain distance comparator according to several embodiments herein.

Fig. 4A and 4B illustrate simplified block diagrams of logic for a time-domain distance comparator using real parts of an operating signal and a polarization signal according to several embodiments herein.

Fig. 5A and 5B show simplified block diagrams of the logic of a time domain distance comparator using imaginary parts of an operating signal and a polarization signal according to several embodiments herein.

Fig. 6A, 6B, and 6C illustrate timing diagrams of integration timers that may be used in time domain fault detection according to several embodiments herein.

Fig. 7 illustrates a simplified block diagram of logic of a time-domain distance comparator supervised by a frequency-domain distance comparator according to several embodiments herein.

Fig. 8 illustrates a simplified block diagram of logic for implementing a symbol consistency check section that may be used to supervise a distance comparator, according to several embodiments herein.

Fig. 9 illustrates a simplified block diagram of logic for implementing a level check section that may be used to supervise a distance comparator, according to several embodiments herein.

Fig. 10 illustrates a simplified block diagram of logic of a time domain distance comparator supervised by a frequency domain distance comparator, symbol consistency, and operating signal level according to several embodiments herein.

Fig. 11 shows a simplified block diagram of logic of a time-domain distance comparator controlled by an interference detector according to several embodiments herein.

Fig. 12 illustrates a simplified block diagram of logic for overriding a time-domain distance comparator when the frequency-domain distance comparator asserts active within a delay time according to several embodiments herein.

Fig. 13 illustrates a simplified block diagram of logic for distance comparator detection with supervision and time domain override logic according to several embodiments herein.

Detailed Description

Power delivery systems broadly facilitate the generation, transmission, distribution, and consumption of electrical power. Such systems include various equipment specifically designed for power delivery purposes. Such equipment is sometimes subject to conditions outside of its specified operating parameters, which may result in damage to the equipment, interruption of the generation, delivery, or consumption of power, or similar damage. To alleviate or even avoid such conditions, power delivery equipment and equipment systems are typically monitored using IEDs that collect information from the equipment, determine operating conditions, and take action if the determined operating conditions are outside acceptable parameters.

For example, a three-phase power transmission line of a power delivery system may be used to carry power over a long distance and at a high voltage on separate conductors. The conductors are insulated from each other and from ground. Failure of the insulation can occur for a variety of reasons, resulting in one conductor making electrical contact with another conductor or ground. Such a failure is commonly referred to as a fault. Such fault conditions, if allowed to persist, may cause further damage to the transmission line and its surroundings, including property damage and human and animal life damage. IEDs can be used to monitor such transmission lines by obtaining electrical information from the transmission line (e.g., voltage and current of the transmission line). The IED may obtain electrical information from one end of the transmission line and may be operable to detect a fault condition on a predetermined area of the transmission line. If a fault condition is detected within a protection zone on the transmission line, the IED may command the circuit breaker to open, thereby removing power from the transmission line. Therefore, the IED must use the obtained electrical information and predetermined line parameters to detect the fault, direction to the fault, and ensure that the fault is within a distance or area of protection before commanding the circuit breaker to open. Using protection elements, referred to as "distance elements," such monitoring in the IED can be performed by determining whether a fault is within a distance or region of protection and commanding the circuit breaker to open.

In general, the distance element may comprise several logic conditions (comparators) in combination with an AND gate (AND gate). For example, the quadrilateral distance elements include a reactance comparator, a right blind comparator (right blind comparator), a left blind comparator (optional), a direction comparator, and a phase selection comparator. The mho distance element includes a mho comparator, a phase selection comparator, and a direction comparator. The mho element can be further modified by optionally adding reactive or blind comparators. The performance of all the individual comparators that make up the distance element is important to the performance of the element. Furthermore, the speed and safety of the distance element are influenced in particular by a range-sensitive comparator which is responsible for distinguishing between faults located within the arrival point of the distance element and faults located outside the arrival point. These may be embodied as mho comparators in mho elements, as well as reactance comparators in quadrilateral elements. To some extent, it can also be embodied in a blind comparator (resistance range comparator).

Such IEDs may use the operating signal S_OPAnd a polarization signal S_POLTo determine the fault condition and to conclude that the fault is within the protection zone (between the IED and the distance element arrival point on the transmission line), the operating signal S_OPAnd a polarization signal S_POLThe measured voltage and current and the line impedance may be used for calculation as shown in equations 1 and 2:

S_OP＝I*Z_R-V equation 1

S_POL＝V_POLEquation 2

Wherein:

i is the measured current;

v is the measured voltage;

Z_Ris to measure the impedance between the location of I and V and the expected arrival point; and is

V_POLIs a polarization signal that can be selected from the following values: measured voltage (self-polarisation mho); healthy phase voltage (cross-phase polarization mho); positive sequence voltage (positive sequence polarization mho); or a stored voltage (memory polarization mho).

Can be measured from three phases (V) based on fault type_A、V_B、V_C、I_A、I_B、I_C) Voltage V and current I are selected. The fault type can be determined from the relative phase-to-ground (AG, BG, CG) and relative phase-to-phase (AB, BC, CA) loops. Phase selection logic may be used to determine the type of fault that the phase amount is to be used from the element. For example, the phase selection logic may allow the AG loop to operate during a phase-to-ground fault; and may allow the AB loop to operate during a-to-B phase faults as well as a-to-B phase faults.

In a steady state, the operating signal and the polarization signal of the distance comparator are sine waves. If S is_OPAnd S_POLApproximately in phase, the comparator asserts its output valid, and if S is_OPAnd S_POLThe signals are approximately out of phase, it will cause the output to be asserted noneAnd (5) effect. Typically, the operational threshold is plotted as 90 degrees: if S is_OPAnd S_POLThe angle between is less than 90 degrees in either direction, the comparator asserts valid; and if the angle is greater than 90 degrees, the comparator remains asserted invalid.

The operating signal and the polarization signal may be determined using time domain principles or frequency domain principles. From the time domain principle, equation 3 may be used to determine the operating signal s_OP：

s_OP＝v-Δv_REACHEquation 3

Wherein:

s_OPis an operating signal using time domain principles (note that lower case generally refers to instantaneous values and upper case generally refers to phasor (phaser) values, where appropriate);

v is the instantaneous voltage; and is

Δv_REACHIs the instantaneous voltage drop across a range impedance (reach impedance) that may be calculated using R i + L di/dt, where R and L refer to line resistance and inductance, respectively, according to some embodiments.

The operating signal and the polarization signal may be determined by: using the frequency domain principle, i.e. using a complex mathematical operation to convert the current phasor I to a voltage drop across a range impedance, subtracting it from the voltage phasor, and obtaining a phasor operating signal S_OP. Alternatively, the instantaneous operating signal (using the time domain principle) can be passed through a phasor estimator to provide the frequency domain S directly_OPA signal.

In still other embodiments, the reactance comparator may use the operation signal S according to equation 1_OPAnd the polarization signal calculated according to equation 4:

S_POL＝j*I_POLequation 4

Wherein:

j represents a phase shift of 90 degrees in the frequency domain, or a antipolarization current (I) in the time domain_POL) Di/dt operation of (1).

Similar to the above notation with respect to polarization, the polarization current I can be selected_POLAs loop current (self-polarised reactance) or negative-sequence current (negative-sequence polarised reactance) or zero-sequence currentCurrent (zero sequence polarized reactance), etc.

As described above, operating signals and polarization signals implemented in various protective devices are used to detect faults within a protected area. For example, the electromechanical device may use electromechanical components to compare the operating signal and the polarization signal and send a trip signal to the circuit breaker, if appropriate. In other embodiments, a microprocessor-based IED may be used to calculate phasors and determine fault conditions following one or more of a variety of methods, including, for example: a) directly calculating the angle between the operating signal and the polarization signal and checking it against a 90 degree threshold, b) calculating the torque Re (S)_OP·conj(S_POL) And checking whether it is positive Re (S)_OP·conj(S_POL))>0, or c) calculate the value of m (where m is the per-unit distance to the fault) and check if it is below the per-unit value range setting. The various methods vary in the operations that need to be performed and their computational burden. For example, the m-value method is computationally very efficient when implementing multiple regions having the same settings in addition to the range settings.

When using the time domain, a timer may be used to check the operating signal and the polarization signal s_OPAnd s_POLWith the same polarity. After low-pass filtering, s_OPAnd s_POLThe signal is a sine wave. If they are exactly in phase, then in each half cycle they are identical (have the same polarity) within one half of the cycle. If they are 90 degrees apart, they coincide for one quarter of the cycle in each half cycle. If they are completely out of phase, they do not coincide at all. The rectifier may be used to detect s_OPAnd s_POLThe instantaneous polarity (sign) of the signal. Simple logic including AND and OR gates may be used to detect s_OPAnd s_POLWhether the signals have the same polarity and a timer can be used to check whether the same polarity condition persists for more than a quarter of a cycle. If so, the time domain distance comparator asserts valid.

Embodiments of the present disclosure will be best understood by reference to the drawings, wherein like parts are designated by like numerals throughout. It will be readily understood that the components of the disclosed embodiments, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the systems and methods of the present disclosure is not intended to limit the scope of the disclosure, as claimed, but is merely representative of possible embodiments of the disclosure. Additionally, unless otherwise specified, the steps of a method need not necessarily be performed in any particular order, even sequentially, nor need the steps be performed only once.

In some instances, well-known features, structures, or operations are not shown or described in detail. Furthermore, the described features, structures, or operations may be combined in any suitable manner in one or more embodiments. It will also be readily understood that the components of the embodiments, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations.

Some aspects of the described embodiments may be implemented as software modules or components or elements. As used herein, a software module or component may include any type of computer instruction or computer executable code located within a memory device and/or transmitted as electronic signals over a system bus or wired or wireless network. A software module or component may, for instance, comprise one or more physical or logical blocks of computer instructions, which may be organized as a routine, program, object, component, data structure, etc., that performs one or more tasks or implements particular abstract data types.

In some embodiments, a particular software module or component may include different instructions stored in different locations of a memory device that together implement the described functionality of the module. Indeed, a module or component may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across several memory devices. Some embodiments may be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, software modules or components may be located in local and/or remote memory storage devices. In addition, data bound or presented together in a database record may reside in the same memory device, or on several memory devices, and may be linked together across a network in the record fields of the database.

Embodiments may be provided as a computer program product including a non-transitory computer and/or machine-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process described herein. For example, a non-transitory computer-readable medium may store instructions that, when executed by a processor of a computer system, cause the processor to perform certain methods disclosed herein. The non-transitory computer-readable medium may include, but is not limited to, hard disk drives, floppy disks, optical disks, CD-ROMs, DVD-ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, solid state memory devices, or other types of machine-readable media suitable for storing electronic and/or processor-executable instructions.

Fig. 1 illustrates a single line diagram of a power delivery system 100 monitored by an IED 110 providing distance protection according to several embodiments herein. As discussed above, the IED 110 may include and/or be implemented in connection with a computing device. Accordingly, the IED 110 can include a processor 111, and the processor 111 can include one or more general purpose processors, special purpose processors, application specific integrated circuits, programmable logic elements (e.g., FPGAs), and the like. The IED 110 may also include a non-transitory machine-readable storage medium 112, which storage medium 112 may include one or more disks, solid state storage (e.g., flash memory), optical media, and the like. The IED 110 may be communicatively coupled to one or more networks 160 via one or more communication interfaces 113. Network 160 may include a dedicated network (e.g., a SCADA network, etc.) for monitoring and/or controlling power system 100. Network 160 may also include a general-purpose communication network, such as a TCP/IP network or the like. The communication interface 113 may include a wired and/or wireless communication interface (e.g., serial port, RJ-45, IEEE 802.11 wireless network transceiver, etc.). In some embodiments, the IED 110 may include Human Machine Interface (HMI) components (not shown), such as a display, input devices, and the like.

The IED 110 may include a plurality of protection elements, such as distance elements 120, which may be embodied as instructions stored on a computer-readable medium, such as storage medium 112, that when executed on the processor 111 cause the IED to detect a fault within a protection zone. The distance elements may include instructions for signal processing 130, time domain fault detector 140, and frequency domain fault detector 150. When a fault within the protection zone 162 is detected using the time domain fault detector 140 and the frequency domain fault detector 150, the distance element 120 may include instructions for causing the IED to signal the breaker 102 to open, thereby avoiding feeding power to the fault.

The IED 110 may be communicatively coupled to the power system 100 through a current transformer and a voltage transformer, i.e., it may receive an excitation (stimulus)122 from the power system 100. The excitation 122 may be received directly via the measurement devices described above and/or indirectly via the communication interface 113 (e.g., from another IED or other monitoring device (not shown) in the power system 100). Stimuli 122 may include, but are not limited to: current measurements, voltage measurements, etc.

Additionally, the IED 110 may include a monitored equipment interface 132 in electrical communication with a piece of monitored equipment. As shown, the monitored equipment interface 132 is in communication with the circuit breaker 102. The monitored equipment interface 132 may include hardware for signaling the circuit breaker 102 to open and/or close in response to commands from the IED 110. For example, upon detection of a fault within the protection zone, the distance element 120 may signal the monitored equipment interface 132 to provide an open signal to the circuit breaker 102 to effect a protective action on the power delivery system. In some embodiments, the protective action may be implemented by additional or separate devices. For example, upon detection of a fault, the distance element 120 may signal the communication interface 113, which communication interface 113 signals the fault to other devices (e.g., using the network 160, or directly to another device), which may signal the circuit breaker to open, which would effect protective action on the power delivery system.

The signals obtained from the power delivery system may be used to calculate voltage and current signals for use by the distance elements. It is possible to sample the line current and voltage at a rate suitable for distance protection, such as on the order of kHz. In some embodiments, the sample may be aligned with a time input (not shown). An analog-to-digital converter (ADC)204 may create a digital representation of the input line current and voltage measurements. The output of the ADC can be used for various algorithms. As described above, these voltage and current signals may be used to calculate an operational quantity and a polarization quantity as described herein.

Fig. 2 illustrates a simplified block diagram of a distance element using both time-domain and frequency-domain principles according to several embodiments herein. Typically, the time domain comparator is supervised using frequency domain principles. According to several embodiments of the present disclosure, a filter pair may be used to derive both time domain measurements and frequency domain measurements. For example, the direct filter may be a cosine filter and the matched quadrature filter may be a sine filter. Although separate and specific filters are shown, any pair of quadrature filters may be used. According to several embodiments herein, the group delay of the filter may be compensated such that in steady state, the output from the direct filter is aligned with the input signal. In general, the output of the direct filter may be referred to as the real part, and the output from the quadrature filter may be the imaginary part.

The distance element 200 is shown operating on the signal s in the time domain_OP202 and a time-domain polarization signal s_POL204 begin. The time domain operation signal and the time domain polarization signal s may be calculated according to several embodiments described herein_OP 202、s_POL204. The quadrature filter may be used to operate on the basis of the time domain operating signal and the time domain polarization signal s_OP 202、s_POL204 calculate the real and imaginary parts (frequency domain). That is, the time domain operation signal s_OP202 may be filtered by a direct filter 206 to produce the real part S of the frequency domain operating signal_{OP_RE}252 and time domain operation signal s_OP202 may be filtered by a quadrature filter 208 to produce an imaginary part S of the frequency domain operating signal_{OP_IM}254. Similarly, the time domain polarization signal s_POL204 may be filtered by a direct filter 210 to produce the real part S of the frequency domain polarized signal_{POL_RE}256 and time domain polarization signal s_POL204 may be filtered by a quadrature filter 212 to produce an imaginary part S of the frequency domain polarized signal_{POL_IM} 258。

The time domain comparator 218 for the real part may receive the real part S of the operating signal and the polarization signal_{OP_RE}252 and S_{POL_RE}256 to determine the real part S of the operating signal and the polarization signal_{OP_RE}252 and S_{POL_RE}256 have the same polarity. Comparator 218 asserts signal 282 when the real part of the operating signal and the polarization signal have the same polarity for a predetermined time. Similarly, the time domain comparator for imaginary part 220 may receive the imaginary part S of the steering signal and the polarization signal_{OP_IM}254 and S_{POL_IM}258 to determine the imaginary part S of the operating signal and the polarization signal_{OP_IM}254 and S_{POL_IM}258 have the same polarity. Comparator 220 asserts signal 284 when the imaginary parts of the operating signal and the polarization signal have the same polarity for a predetermined time.

The time domain comparators 218, 220 may be supervised by a symbol consistency check section 214, a level check section 216, and a frequency domain comparator 222. In particular, the frequency-domain comparator 222 may receive the real and imaginary parts S of the frequency-domain operating signal and the frequency-domain polarization signal_{OP_RE} 252、S_{OP_IM} 254、S_{POL_RE}256 and S_{POL_IM}258 and outputs an instruction operation signal S_OPAnd a polarization signal S_POLIn-phase frequency domain fault detection signal 262.

Fig. 3A, 3B, and 3C illustrate block diagrams of frequency domain comparators that may be used in accordance with several embodiments herein. Typically, these comparators will output signal 262 when it is determined that the polarization signal and the operating signal are in phase. The comparator of fig. 3A uses the manipulated variable and the polarization amount S in the direct angle calculator 302_OP、S_POLThe direct angle calculator 302 calculates an operation amount and a polarization amount S_OP、S_POLThe angle therebetween. In some embodiments, operational quantities and polarization quantities S, such as those calculated using equations 1, 2, and 4, may be used_OP、S_POL. The absolute value of the angle is determined 304 and compared to a predetermined angle threshold (e.g., 90 degrees) in comparator 306. When the angle is less than the predetermined threshold, comparator 306 asserts signal 262 active, indicating that the polarization signal and the operational signal are less than 90 degrees apart.

The comparator of fig. 3B uses the operation amount and the polarization amount S in the torque calculator 310_OP、S_POLThe torque calculator 310 determines the operation amount S_OPAnd polarization quantity S_POLThe real part of the product of the complex conjugates of (a). If the calculator output is greater than zero, comparator 312 asserts valid, indicating that the polarization signal and the operation signal are less than 90 degrees apart.

Fig. 3C shows yet another option for a frequency domain comparator, but this time only for a mho comparator, which uses a voltage V, a current I, a range impedance Z_RAnd polarization signal S_POL. As described above, the voltage V and current I signals may be obtained from the power system. The amount of polarization may be any amount of polarization as described above. The per-unit value failure location amount m is calculated using a calculator 314, the calculator 314 using, for example, equation 5:

as described above, the m value represents a per unit value failure location. An m value of one (unity) will be caused by a failure at the arrival point. Thus, if the value of m according to equation 5 is less than one, then the fault is determined to be within the mho comparator protection zone in comparator 318 and signal 262 is asserted valid.

The frequency-domain comparator 222 (as may be embodied using any of the comparators of fig. 3A, 3B, 3C, or other comparators) may operate at any arbitrary processing rate, including very slow rates. The frequency domain comparator may be as slow as four times per power system cycle. Currently, frequency domain comparators are performed at higher rates. The output 262 of the frequency-domain comparator remains asserted as long as the condition is met (e.g., the angles of the calculator 302 are more than 90 degrees apart), even when those signals are constantly changing with the shape of the sine wave.

To improve the frequency domain comparator used according to several embodiments herein, the input voltage and current signals may be filtered. Further, a short output timer may be used on the output (e.g., signal 262) to improve safety.

In several embodiments herein, frequency domain principles may be used for the supervised time domain comparator. Due to this supervision function, the frequency domain comparator does not require an accurate phasor. Conversely, to increase the speed of the frequency domain comparator, the real and imaginary parts on the shortened time scale may be calculated by shortening the data window of the quadrature filter (e.g., filters 206, 208, 210, 212).

Turning now to the time domain comparators 218, 220 of fig. 2, several possible embodiments thereof are described in the following description. In summary, when the real parts of the operation amount and the polarization amount have the same sign (positive or negative) within a predetermined time (coincidence time); alternatively, the time domain comparator asserts active when both the manipulated variable and the imaginary component of the polarization quantity are positive or negative for a predetermined time. Fig. 4A and 4B show simplified logic diagrams of a time domain distance comparator. In particular, FIG. 4A shows a time domain comparator 218, and it uses the real part S of the operating signal and the polarization signal_{OP_RE} 252、S_{POL_RE}256. Since the operating signal and the polarization signal are usually in the form of alternating current waves, they are regularly shifted between positive and negative values. When the real part S of the operating signal and the polarization signal_{OP_RE}252 and S_{POL_RE}256 is positive, positive blocks 402 and 406 will assert valid, respectively. Similarly, when the real part S of the operating signal and the polarization signal_{OP_RE}252 and S_{POL_RE}256 are negative, respectively, negative blocks 404 and 408 will assert valid. When both positive blocks 402, 406 are asserted, the AND block 410 asserts PAVE, which indicates the real part S of the operation signal and the polarization signal_{OP_RE}252 and S_{POL_RE}256 are all positive and the integration timer 414 is started. Similarly, when both negative blocks 404, 408 are asserted, the AND block 412 asserts Nactive, which indicates the real part S of the operation signal and the polarization signal_{OP_RE}252 and S_{POL_RE}256 are all negative and the integration timer 416 is started.

When either the interrupt signal P (from and gate 410) OR N (from and gate 412) is asserted for a predetermined time of the timer, the integration timers 414, 416 may assert that the output to OR 418 is asserted. In one embodiment, the integration timers 414, 416 are set with a predetermined time corresponding to one-quarter of the power system cycle. Thus, the matching polarities of the signals must be consistent for an equivalent duration longer than 90 degrees (one quarter of a power system cycle) to assert that the input to or gate 418 is valid. The OR gate 418 asserts the time domain comparator (real) output 282 active when either the integration timer 414 or 416 is asserted.

Fig. 4B shows another possible embodiment of the time domain comparator 218. According to the illustrated embodiment, AND gates 410 and 412 are asserted directly to OR gate 418, which then asserts a single integration timer 422. The integration timer 422 may operate similarly to the integration timers 414, 416, asserting valid when the positive or negative portions are consistent in polarity for longer than a predetermined time (e.g., a time corresponding to one-quarter of a power system cycle).

FIGS. 5A and 5B show imaginary part S for using an operating signal and a polarization signal_{OP_IM} 254、S_{POL_IM}258 to determine a simplified logic diagram of the time domain comparator output 284. Similar to the previously shown embodiments, when the imaginary part S of the operating signal and the polarization signal_{OP_IM} 254、S_{POL_IM}258 are positive or negative, respectively, positive blocks 502, 506 and negative blocks 504, 508 assert valid. When the imaginary part S of the operating signal and the polarization signal_{OP_IM} 254、S_{POL_IM}258 are both positive, and gate 510 is asserted valid; and when the imaginary part S of the operating signal and the polarization signal_{OP_IM} 254、S_{POL_IM}258 are both negative, and gate 512 asserts valid. When positive or negative and gates 510, 512 are asserted for a predetermined time (e.g., a time associated with one-quarter of a power system cycle), integration timers 514 and 516 are asserted. Assertion of either timer 514, 516 valid will cause or gate 518 to assert the time domain comparator signal 284 valid.

Similarly, as shown in FIG. 5B, AND gates 510 and 512 are asserted directly to OR gate 518, which OR gate 518 is then asserted to a single integration timer 522. The integration timer 522 may operate similar to the integration timers 514, 516, asserting valid when the positive or negative portions are consistent in polarity for longer than a predetermined time (e.g., a time corresponding to one-quarter of a power system cycle).

For speed, several embodiments herein apply coherence timing to both the real and imaginary parts of the operating and polarization signals. Depending on the point on the wave (i.e. when it relates to the fault instant of the peak and zero crossing of the voltage before the fault), the real part of the phasor or the imaginary part of the phasor is generated faster (i.e. the fault condition is tracked faster). In general, when the real part is slow, the imaginary part is fast; and when the imaginary part is slower, the real part is faster. This relationship may be due to the fact that the real part is related to the signal value and the imaginary part is related to the signal derivative. It can be seen that the sine wave has a zero value but a maximum derivative at zero pass, and a maximum value but zero derivative at peak pass.

As shown in fig. 2, the outputs 282, 284 from the real and imaginary parts of the time domain comparators 218, 220 are asserted to the or gate 224, which in turn asserts the distance fault determination 226 (which may be referred to as a distance fault detection signal) when either of the time domain comparators 218, 220 are asserted to be active.

Although the time domain comparators 218, 220 (and as shown in fig. 4A, 4B, 5A, and 5B) are shown using real and imaginary components from the quadrature filters 206, 208, 210, 212, in various embodiments the real time domain comparator 218 may use the instantaneous operating and polarization signals 202, 204 and the imaginary component 220 may be omitted. In addition, the real time domain comparator 218 may use the signal without filtering. An integration timer (e.g., timers 414, 416, 422) may be used to provide security even if the input signal is severely distorted due to, for example, lack of filtering.

The integration timer (e.g., timers 414, 416, 418, 422, 514, 516, 518, 522) may be implemented according to various timing architectures. In one embodiment, as shown in the timing diagram of FIG. 6A, the timer may be implemented to reset momentarily when the input is even temporarily asserted inactive. As shown, the timer's input begins at time 652 and remains asserted for time 602. During time 602, the counter (of the integration timer) starts counting. The counter resets to zero when the input is asserted inactive at time 654, and does not begin counting again until the timer's input is re-asserted active 604 at time 656. The counter begins counting inputs again 606 and once the operational threshold is reached, the timer asserts the output 610 at time 608.

Fig. 6B illustrates another possible implementation of an integration timer that may be used in accordance with several embodiments herein. The illustrated timer uses hold logic, wherein the counter keeps its count until an operational threshold is reached. As shown, it can be seen that the counter starts at a time 652 when the input 602 of the timer is asserted. While the input 602 is asserted inactive at time 654, the counter may remain for a period of time 612 during which the input is asserted inactive. While the input is again asserted at time 656, the counter continues to count until the operational threshold is reached at time 614 and the output of timer 616 is asserted. In some embodiments, the time that the timer keeps counting is limited. For example, the timer logic may include a hold time. The hold time begins when the input signal is asserted inactive at time 654. If the time that the input signal remains asserted inactive exceeds the hold time, the counter will reset to zero, similar to that shown in FIG. 6A.

Fig. 6C illustrates a timing diagram of yet another possible implementation of an integration timer that may be used in accordance with several embodiments herein. The illustrated timer uses downward integration logic when the input is asserted inactive. Specifically, the counter starts counting when the input 602 is asserted at time 652. When the input 602 is asserted inactive at time 654, then the counter begins counting down. When input signal 604 is re-asserted at time 656, the counter again begins counting up 618 until it reaches the operational threshold at time 620. When the operational threshold is reached, output 622 is asserted at time 620.

In each of the timing diagrams shown in fig. 6A, 6B, and 6C, the counter may be incremented at a predetermined rate. Similarly, the rate at which the counter counts down may be predetermined. In some embodiments, this rate matches the rate at which the counter counts up during the time that the input signal 602 is asserted. In other embodiments, the rates may be different. Further, the rate may be dynamic and may vary based on current conditions, such as, but not limited to, in response to the outputs of the level check portion 216 and the symbol consistency check portion 214. For example, asserting that symbol consistency check portion 214 and/or level check portion 216 are active to increase additional security may cause the downward integration rate of the integration timer to be greater than when the signals from level check portion 216 and symbol consistency check portion 214 do not indicate an increase in security.

As shown in fig. 6A, 6B and 6C, embodiments of the timer exhibit different results in terms of safety and reliability. For example, the integration timer associated with the timing diagram shown in FIG. 6A is biased towards security because any temporary loss of input will restart the timer. In this way, false fault determinations are less likely to be made. Alternatively, the instantaneous reset timer associated with the timing diagram shown in fig. 6B is biased towards reliability because a temporary loss would result in holding the integrator and when the input resumes again, the integration would start from where it left off. In this way, the distance elements are less likely to miss a fault. The hybrid timer associated with the timing diagram shown in fig. 6C represents a balance between security and reliability.

As described above, to increase speed, a momentary operating signal may be used in the time domain comparator 218, and to increase safety, an integration timer may be selected. Thus, it is possible to achieve security similar to that of the frequency-based method with less filtering and faster operation. In one embodiment, a sampling/processing rate of 2kHz (0.5ms sampling period) is used. In this embodiment applied to a 60Hz system, the coherence timer would exhibit an angular granularity of 360 x 0.5/16.67-10.8 degrees. This works in place of the desired 4.17ms coherence timing (which is associated with a 90 degree comparator angle), which the logic will perform either 4ms or 4.5ms timing. In some embodiments, this error may be reduced by a higher sampling/processing rate or detecting polarity changes between samples.

In other embodiments, accuracy issues such as those introduced in the above example may be addressed in the following manner: a coherence timer shorter than exactly 90 degrees is used and a frequency domain comparator supervises the time domain comparator. For example, using the above sampling and processing rates, the logic may use 4.0ms (8 times 0.5 time resolution) instead of using the ideal 0.25 × 16.67ms — 4.17 ms. This in turn would undesirably result in a distance shape that is larger than would be expected using the exact 90 degree comparator.

To address this inaccuracy in the shape of the range element, certain embodiments herein use a frequency domain comparator to supervise the time domain comparator. Fig. 7 illustrates a simplified block diagram of logic that may be used to supervise time domain distance protection by frequency domain principles according to several embodiments herein. In particular, and gates 410, 412, 510 and 512 require, in addition to the signals described above, that signal 262 from the frequency domain comparator be asserted in order to assert the appropriate or gate 418, 518 to start the integration timer 422, 522. The signal 262 from the frequency domain comparator may be from any suitable frequency domain comparator, such as those disclosed herein and shown and described in connection with fig. 3A, 3B, and 3C. That is, signal 262 may be provided generally whenever the operating signal and the polarization signal are less than 90 degrees apart. Thus, the time domain comparator is supervised by the frequency domain comparator, since the distance element is constantly active (the integration timer (e.g. 422, 522) cannot be started) until the operating signal and the polarization signal are less than 90 degrees apart; and the real and imaginary parts of the polarization signal and the operation signal are both positive or both negative. In certain embodiments, such as shown, the integration timers 422, 522 may be configured with a time associated with 0.25 power system cycles or less.

If the transient operating signal 202 is only lightly filtered to maintain operating speed, it may exhibit transients (transients) in the input signals 252 and 254 of the time domain comparators 218 and 220. As shown in fig. 2, the distance element may include additional safety measures, including, for example, a symbol consistency check 214 to mitigate such transients. In general, the symbol consistency check section 214 checks the instantaneous operation signal s_OP202 (e.g., instantaneous IZ-V values) and the real part S of the phasor manipulation signal_{OP_RE}252 (e.g., phasor IZ-V operating signals). In various descriptions herein, the transient operation signal may be referred to as the "raw" signal, where the phasor operation signal may be referred to as the "filtered" signalThe "signal of (1).

In the illustrated embodiment, the time domain comparators 218, 220 use the sign consistency check 214 to oversee the outputs 282 and 284. FIG. 8 illustrates a simplified logic diagram of symbol consistency check 214 in accordance with several embodiments. Symbol consistency check unit 214 uses time domain operation signal s_OP202 and the real part S of the frequency domain operating signal_{OP_RE}252. When operating on the real part S of the signal in the frequency domain_{OP_RE}252 and a time domain operation signal s_OP202 are positive, positive blocks 802, 806 assert valid; and operating on the real part S of the signal in the frequency domain_{OP_RE}252 and a time domain operation signal s_OP202 are negative, respectively, negative blocks 804, 808 assert valid. When both positive block 802 and negative block 808 are asserted, AND gate 810 is asserted, indicating the real part S of the frequency domain operation signal_{OP_RE}252 is positive and the time domain operation signal s_OP202 is negative (i.e., both signals have opposite signs at the same time). Similarly, when negative block 804 and positive block 806 are asserted, and gate 812 is asserted, indicating the real part S of the frequency domain operation signal_{OP_RE}252 is negative and the time domain operation signal s_OP202 is positive (i.e., both signals have opposite signs at the same time). In summary, when the sign of the operation signal is opposite, and gate 810 or 812 asserts active. When AND gate 810 or 812 asserts valid, OR gate 814 asserts valid. The output of the or gate is inverted 816 such that when the sign of the operation signal is the same sign, then the sign consistency operation signal 818 is asserted. Otherwise, when the signs are reversed, then signal 820 to apply additional security is asserted. Therefore, the sign coincidence checking section 214 allows normal operation when the signs of the operation signals are not reversed, but requires additional security when the signs are reversed.

The logic of fig. 8 compares the signs of the original signal and the filtered signal with respect to the original signal and the filtered signal. If the signs are consistent (both positive or both negative), the operating signal may be trusted and allowed to operate from normal 818 even if the values of the signals are inconsistent (indicating that a transient may still be present in the signal). In addition, transients that cause symbol inconsistency are considered a potential threat to security and produce a signal 820 that applies additional security.

The normal operation signal 818 may be implemented to allow the integrators (e.g., integration timers 414, 416, 422, 514, 516, 522) to operate normally. The signal 820 for applying additional security can be implemented to assert the input of the integration timer invalid, the effect of which is to instruct them to reset or integrate down-depending on the timing scheme illustrated in fig. 6-to obtain additional security.

Returning now to the additional safety check, the level check portion 216 may check the level of the operation signal to supervise the output of the distance element. Fig. 9 illustrates a simplified block diagram of logic that may be used for a level check section consistent with several embodiments herein. Time domain operation signal s_OP202 must be above a predetermined level to assert the "normal operation" signal active. In principle, for a metal fault at the point of arrival, the operating signal of the distance sensitive distance comparator (mho, reactance) is ideally zero and increases as the fault location is farther from the point of arrival (inside or outside the distance zone). Therefore, the smaller the operating signal, the closer the fault is to the point of arrival, and greater safety is required to determine whether the fault is inside or outside the protected area. If the operating signal is large, it must be located far outside the protected area or far inside the protected area. However, when the operation signal is small, the signal-to-noise ratio becomes poor and higher safety is required. Using the level of the operating signal adds the following advantages: operation is accelerated when the fault is close (operating signal is large) and slowed down to maintain safety in weak systems or when the fault is near the arrival point. It should be noted that the individual levels of the voltage or current signals, respectively, do not comprise much information about the additional safety requirements, but instead the level of the operating signal comprises information about whether the signal-to-noise ratio might be a problem. The noise may be, for example, unfiltered transients from the power system (as opposed to a/D converter noise or noise in the relay electronics).

FIG. 9 illustrates the logic of one embodiment of a level check section that may be used. In the embodiment shown, the level of the operating signal is checked against a predetermined threshold. In particular, a time domain operation is determinedSignal s_OP202 (absolute value 902) and present it to comparator 906. The comparator 906 compares the magnitude with a predetermined threshold V_MIN904 for comparison. In an alternative embodiment, the phase magnitude value (S) may be_{OP_RE}+jS_{OP_IM}) Is compared to a predetermined threshold. When operating signal s_OP202 (or respectively operating phasors) exceeds a predetermined threshold 904, then the comparator asserts valid. While the assertion of the comparator 906 is valid, a level check operation signal ("normal operation") 908 signal is provided by the level check module 216. As described above, the normal operation 908 signal allows the distance element to continue to advance without additional security. Alternatively, when the comparator 906 is not asserted (operation signal s)_OP202 does not exceed the predetermined threshold 904), the signal from the comparator 906 is inverted 910, asserting the additional security signal 912. Since the level of the operating signal is less than the predetermined threshold, the distance element may use an additional security signal 912 to improve security. As with signal 812, the additional security signal 912 may be used by the integration timer to assert an invalid, which may result in counting down (or counting back) when the invalid is asserted to improve security.

FIG. 10 shows a simplified block diagram of logic that may be used to implement security in a range element using a frequency domain comparator, a level check section, and a symbol consistency check section. And gate 902 asserts valid when all of the following conditions exist: 1) a frequency domain comparator signal 262 indicating that the frequency domain range sensitive comparator 222 has detected a fault within the protection zone; 2) a signal 818 of normal operation from the symbol consistency check section 214; and 3) a signal 908 from normal operation of the level check portion 216. In addition to the conditions detailed above for asserting valid, the AND gates 410, 412, 510, 512 are asserted only when the signal from the AND gate 902 is asserted. Thus, in several embodiments, the frequency domain comparator, the level check section and the symbol consistency check section add security to the time domain comparator.

In alternative embodiments, different logic tools may be used for additional or reduced security. For example, and gate 902 may be replaced by an or gate, such that asserting and gate 410, 412, 510, or 512 in addition to the signals from the positive and negative blocks as described above requires one or more of frequency domain comparator signal 262, level check 908, or symbol consistency check signal 818.

In yet another embodiment, a symbol consistency check may be used to assert that two different and parallel integration timers are valid. The normal operation signal 818 may be used in a first integration timer of the time domain comparator to integrate the first operation signal and the signal 820 applying additional security may be used in a second integration timer of the time domain comparator to integrate the second operation signal (all provided that other conditions for starting and running the integration timer are also met). The outputs of the first and second integration timers may be used to determine whether a fault has been detected 262. For example, the second integration timer (associated with the additional safety signal 820) may require a higher operational threshold (longer assertion validity time), thereby adding some additional safety. In this example, if either the first integration timer or the second integration timer asserts its output valid, the output 262 indicating that a fault was detected may be asserted.

In various cases, the comparator may be asserted active prior to the fault. For example, in the case of using a quadrilateral element, the reactance comparator may be asserted to be active prior to a fault. For this reason, the load impedance is typically lower than the reactance setpoint. If so, the load will assert the output of the reactive comparator to be valid. A mho comparator under heavy load conditions may also assert valid (mho distance element does not operate because it is usually prevented by load intrusion logic, but the mho comparator itself may be permanently asserted valid to the load). If the mho comparator or reactive comparator is permanently asserted to be active to the load, its safety margin may be small for subsequent faults outside the distance protection zone. Due to the load before the fault, the integration timers are at a non-zero value, they can integrate up and operate faster than if they were integrating from zero.

To address such pre-fault integration, an interference detector may be used to reset the integration timer. Fig. 11 shows a simplified block diagram of logic for resetting an integration timer using a jammer detector. Specifically, if a glitch 1102 is detected, then at the rising edge 1104 of the glitch (and the loss timer 1110 is not asserted), and gate 1106 asserts signal 1108 to reset the integration timers 422, 522. The loss timer 1110 may be used to prevent a reset during an ongoing power system event until the next power system event.

As described above, when the operation signal is small, the operation of the distance element against a failure within the protection area can be delayed or prevented. Thus, it may be beneficial to allow operation based on only the frequency domain comparator, but to use a sufficiently long time delay for security. Fig. 12 shows a simplified block diagram of logic that may be used to implement a frequency-only solution with a security timer. Similar to the embodiment shown in fig. 10, and gate 1002 asserts valid when all three frequency domain comparators assert valid 262, the sign consistency check asserts valid 818, and the level check asserts valid 908. The security timer 1202 is also started when the frequency domain comparator 262 is asserted to be active. The distance fault detect signal 226 is asserted by the or gate 1204 if the integration timer 422 (or other integration timers such as 414, 416, 514, 516, 522, not specifically shown in this block diagram) or the safety timer 1202. Thus, even if neither of the range sensitive time domain (real or imaginary) comparators 218, 220 detects a fault within the protection zone, the frequency domain comparator may be used to assert the output distance fault detect signal 226 valid when a sufficiently long time delay. The security timer 1202 may include a predetermined time delay to ensure that the frequency domain comparator is asserted for a sufficient amount of time to ensure security. The security timer 1202 may be implemented as an instantaneous reset timer, an integration timer, or a hybrid timer, as described herein.

For completeness, fig. 13 shows a simplified block diagram of logic that may be used to detect faults within the protection zone (asserting the fault detection signal 262 active) using frequency and time domain principles. It should be noted that logic similar to that shown may be applied to various comparators (e.g., mho and reactance distance comparators) to achieve speed and safety benefits. That is, the frequency domain comparator may be replaced by a mho or reactance distance comparator. Similarly, the time domain comparator may be replaced with a matched mho or reactance distance comparator. Further, logic may be used with comparators or elements that are not range sensitive.

The disclosure of embodiments herein may apply a symbol consistency check to the real part of the operating signal, but in various embodiments, not to the imaginary part (e.g., the output from 818 may not flow to and gates 510, 512). This comparison is convenient because of the momentary operating signal s_OPAnd the real part S of the filtered operating signal_{OP_RE}Are coherent in time and therefore the two can be compared directly. For comparing the imaginary part S of the frequency-domain operating signal_{OP_IM}Will need to calculate s_OPThe time derivative of the signal. The time derivative operation adds noise and this noise may lead to false signaling (i.e., asserting the need for higher security when not necessary). However, according to several embodiments herein, symbol consistency checking may be applied to one or both of the real and imaginary time domain comparators 218, 220, or not to either.

In addition, although FIG. 9 illustrates a pair of operation signals (e.g., s as shown)_OP202, or even S_{OP_RE}252 or S_{OP_IM}254) Following the same logic as shown, the polarization signal may also be level checked. That is, similarly to the illustration in fig. 9, the polarization signal s_POL 204、S_{POL_RE}256 or S_{POL_IM}258, all or none of which may be level checked. This check of the polarization signal is particularly useful for reactive comparators that use zero sequence or negative sequence currents for polarization.

While particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the disclosure is not limited to the precise configuration and components disclosed herein. Further, the principles described herein may also be used to protect a power system from over-frequency conditions, where power generation rather than load would be reduced to reduce the impact on the system. Accordingly, many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the disclosure. The scope of the invention should, therefore, be determined only by the following claims.